Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[linux/fpc-iii.git] / drivers / watchdog / lantiq_wdt.c
blob7f43cefa0eae39505c28aebca4aaf9c1dffa3a9d
1 /*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
6 * Copyright (C) 2010 John Crispin <john@phrozen.org>
7 * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
8 * Based on EP93xx wdt driver
9 */
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/module.h>
14 #include <linux/fs.h>
15 #include <linux/miscdevice.h>
16 #include <linux/watchdog.h>
17 #include <linux/of_platform.h>
18 #include <linux/uaccess.h>
19 #include <linux/clk.h>
20 #include <linux/io.h>
21 #include <linux/regmap.h>
22 #include <linux/mfd/syscon.h>
24 #include <lantiq_soc.h>
26 #define LTQ_XRX_RCU_RST_STAT 0x0014
27 #define LTQ_XRX_RCU_RST_STAT_WDT BIT(31)
29 /* CPU0 Reset Source Register */
30 #define LTQ_FALCON_SYS1_CPU0RS 0x0060
31 /* reset cause mask */
32 #define LTQ_FALCON_SYS1_CPU0RS_MASK 0x0007
33 #define LTQ_FALCON_SYS1_CPU0RS_WDT 0x02
36 * Section 3.4 of the datasheet
37 * The password sequence protects the WDT control register from unintended
38 * write actions, which might cause malfunction of the WDT.
40 * essentially the following two magic passwords need to be written to allow
41 * IO access to the WDT core
43 #define LTQ_WDT_PW1 0x00BE0000
44 #define LTQ_WDT_PW2 0x00DC0000
46 #define LTQ_WDT_CR 0x0 /* watchdog control register */
47 #define LTQ_WDT_SR 0x8 /* watchdog status register */
49 #define LTQ_WDT_SR_EN (0x1 << 31) /* enable bit */
50 #define LTQ_WDT_SR_PWD (0x3 << 26) /* turn on power */
51 #define LTQ_WDT_SR_CLKDIV (0x3 << 24) /* turn on clock and set */
52 /* divider to 0x40000 */
53 #define LTQ_WDT_DIVIDER 0x40000
54 #define LTQ_MAX_TIMEOUT ((1 << 16) - 1) /* the reload field is 16 bit */
56 static bool nowayout = WATCHDOG_NOWAYOUT;
58 static void __iomem *ltq_wdt_membase;
59 static unsigned long ltq_io_region_clk_rate;
61 static unsigned long ltq_wdt_bootstatus;
62 static unsigned long ltq_wdt_in_use;
63 static int ltq_wdt_timeout = 30;
64 static int ltq_wdt_ok_to_close;
66 static void
67 ltq_wdt_enable(void)
69 unsigned long int timeout = ltq_wdt_timeout *
70 (ltq_io_region_clk_rate / LTQ_WDT_DIVIDER) + 0x1000;
71 if (timeout > LTQ_MAX_TIMEOUT)
72 timeout = LTQ_MAX_TIMEOUT;
74 /* write the first password magic */
75 ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR);
76 /* write the second magic plus the configuration and new timeout */
77 ltq_w32(LTQ_WDT_SR_EN | LTQ_WDT_SR_PWD | LTQ_WDT_SR_CLKDIV |
78 LTQ_WDT_PW2 | timeout, ltq_wdt_membase + LTQ_WDT_CR);
81 static void
82 ltq_wdt_disable(void)
84 /* write the first password magic */
85 ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR);
87 * write the second password magic with no config
88 * this turns the watchdog off
90 ltq_w32(LTQ_WDT_PW2, ltq_wdt_membase + LTQ_WDT_CR);
93 static ssize_t
94 ltq_wdt_write(struct file *file, const char __user *data,
95 size_t len, loff_t *ppos)
97 if (len) {
98 if (!nowayout) {
99 size_t i;
101 ltq_wdt_ok_to_close = 0;
102 for (i = 0; i != len; i++) {
103 char c;
105 if (get_user(c, data + i))
106 return -EFAULT;
107 if (c == 'V')
108 ltq_wdt_ok_to_close = 1;
109 else
110 ltq_wdt_ok_to_close = 0;
113 ltq_wdt_enable();
116 return len;
119 static struct watchdog_info ident = {
120 .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
121 WDIOF_CARDRESET,
122 .identity = "ltq_wdt",
125 static long
126 ltq_wdt_ioctl(struct file *file,
127 unsigned int cmd, unsigned long arg)
129 int ret = -ENOTTY;
131 switch (cmd) {
132 case WDIOC_GETSUPPORT:
133 ret = copy_to_user((struct watchdog_info __user *)arg, &ident,
134 sizeof(ident)) ? -EFAULT : 0;
135 break;
137 case WDIOC_GETBOOTSTATUS:
138 ret = put_user(ltq_wdt_bootstatus, (int __user *)arg);
139 break;
141 case WDIOC_GETSTATUS:
142 ret = put_user(0, (int __user *)arg);
143 break;
145 case WDIOC_SETTIMEOUT:
146 ret = get_user(ltq_wdt_timeout, (int __user *)arg);
147 if (!ret)
148 ltq_wdt_enable();
149 /* intentional drop through */
150 case WDIOC_GETTIMEOUT:
151 ret = put_user(ltq_wdt_timeout, (int __user *)arg);
152 break;
154 case WDIOC_KEEPALIVE:
155 ltq_wdt_enable();
156 ret = 0;
157 break;
159 return ret;
162 static int
163 ltq_wdt_open(struct inode *inode, struct file *file)
165 if (test_and_set_bit(0, &ltq_wdt_in_use))
166 return -EBUSY;
167 ltq_wdt_in_use = 1;
168 ltq_wdt_enable();
170 return nonseekable_open(inode, file);
173 static int
174 ltq_wdt_release(struct inode *inode, struct file *file)
176 if (ltq_wdt_ok_to_close)
177 ltq_wdt_disable();
178 else
179 pr_err("watchdog closed without warning\n");
180 ltq_wdt_ok_to_close = 0;
181 clear_bit(0, &ltq_wdt_in_use);
183 return 0;
186 static const struct file_operations ltq_wdt_fops = {
187 .owner = THIS_MODULE,
188 .write = ltq_wdt_write,
189 .unlocked_ioctl = ltq_wdt_ioctl,
190 .open = ltq_wdt_open,
191 .release = ltq_wdt_release,
192 .llseek = no_llseek,
195 static struct miscdevice ltq_wdt_miscdev = {
196 .minor = WATCHDOG_MINOR,
197 .name = "watchdog",
198 .fops = &ltq_wdt_fops,
201 typedef int (*ltq_wdt_bootstatus_set)(struct platform_device *pdev);
203 static int ltq_wdt_bootstatus_xrx(struct platform_device *pdev)
205 struct device *dev = &pdev->dev;
206 struct regmap *rcu_regmap;
207 u32 val;
208 int err;
210 rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
211 if (IS_ERR(rcu_regmap))
212 return PTR_ERR(rcu_regmap);
214 err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);
215 if (err)
216 return err;
218 if (val & LTQ_XRX_RCU_RST_STAT_WDT)
219 ltq_wdt_bootstatus = WDIOF_CARDRESET;
221 return 0;
224 static int ltq_wdt_bootstatus_falcon(struct platform_device *pdev)
226 struct device *dev = &pdev->dev;
227 struct regmap *rcu_regmap;
228 u32 val;
229 int err;
231 rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
232 "lantiq,rcu");
233 if (IS_ERR(rcu_regmap))
234 return PTR_ERR(rcu_regmap);
236 err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);
237 if (err)
238 return err;
240 if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)
241 ltq_wdt_bootstatus = WDIOF_CARDRESET;
243 return 0;
246 static int
247 ltq_wdt_probe(struct platform_device *pdev)
249 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
250 struct clk *clk;
251 ltq_wdt_bootstatus_set ltq_wdt_bootstatus_set;
252 int ret;
254 ltq_wdt_membase = devm_ioremap_resource(&pdev->dev, res);
255 if (IS_ERR(ltq_wdt_membase))
256 return PTR_ERR(ltq_wdt_membase);
258 ltq_wdt_bootstatus_set = of_device_get_match_data(&pdev->dev);
259 if (ltq_wdt_bootstatus_set) {
260 ret = ltq_wdt_bootstatus_set(pdev);
261 if (ret)
262 return ret;
265 /* we do not need to enable the clock as it is always running */
266 clk = clk_get_io();
267 if (IS_ERR(clk)) {
268 dev_err(&pdev->dev, "Failed to get clock\n");
269 return -ENOENT;
271 ltq_io_region_clk_rate = clk_get_rate(clk);
272 clk_put(clk);
274 dev_info(&pdev->dev, "Init done\n");
275 return misc_register(&ltq_wdt_miscdev);
278 static int
279 ltq_wdt_remove(struct platform_device *pdev)
281 misc_deregister(&ltq_wdt_miscdev);
283 return 0;
286 static const struct of_device_id ltq_wdt_match[] = {
287 { .compatible = "lantiq,wdt", .data = NULL},
288 { .compatible = "lantiq,xrx100-wdt", .data = ltq_wdt_bootstatus_xrx },
289 { .compatible = "lantiq,falcon-wdt", .data = ltq_wdt_bootstatus_falcon },
292 MODULE_DEVICE_TABLE(of, ltq_wdt_match);
294 static struct platform_driver ltq_wdt_driver = {
295 .probe = ltq_wdt_probe,
296 .remove = ltq_wdt_remove,
297 .driver = {
298 .name = "wdt",
299 .of_match_table = ltq_wdt_match,
303 module_platform_driver(ltq_wdt_driver);
305 module_param(nowayout, bool, 0);
306 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
307 MODULE_AUTHOR("John Crispin <john@phrozen.org>");
308 MODULE_DESCRIPTION("Lantiq SoC Watchdog");
309 MODULE_LICENSE("GPL");