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mm: make wait_on_page_writeback() wait for multiple pending writebacks
[linux/fpc-iii.git] / arch / arm / mach-davinci / dm365.c
blobc1e0d46996e444026eab780262e0c025046a279d
1 /*
2 * TI DaVinci DM365 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/clk-provider.h>
17 #include <linux/clk/davinci.h>
18 #include <linux/clkdev.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dmaengine.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/irqchip/irq-davinci-aintc.h>
24 #include <linux/platform_data/edma.h>
25 #include <linux/platform_data/gpio-davinci.h>
26 #include <linux/platform_data/keyscan-davinci.h>
27 #include <linux/platform_data/spi-davinci.h>
28 #include <linux/platform_device.h>
29 #include <linux/serial_8250.h>
30 #include <linux/spi/spi.h>
31
32 #include <asm/mach/map.h>
33
34 #include <mach/common.h>
35 #include <mach/cputype.h>
36 #include <mach/mux.h>
37 #include <mach/serial.h>
38
39 #include <clocksource/timer-davinci.h>
40
41 #include "asp.h"
42 #include "davinci.h"
43 #include "irqs.h"
44 #include "mux.h"
45
46 #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
47 #define DM365_RTC_BASE 0x01c69000
48 #define DM365_KEYSCAN_BASE 0x01c69400
49 #define DM365_OSD_BASE 0x01c71c00
50 #define DM365_VENC_BASE 0x01c71e00
51 #define DAVINCI_DM365_VC_BASE 0x01d0c000
52 #define DAVINCI_DMA_VC_TX 2
53 #define DAVINCI_DMA_VC_RX 3
54 #define DM365_EMAC_BASE 0x01d07000
55 #define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
56 #define DM365_EMAC_CNTRL_OFFSET 0x0000
57 #define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
58 #define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
59 #define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
60
61 #define INTMUX 0x18
62 #define EVTMUX 0x1c
63
64
65 static const struct mux_config dm365_pins[] = {
66 #ifdef CONFIG_DAVINCI_MUX
67 MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
68
69 MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
70 MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
71 MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
72 MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
73 MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
74 MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
75
76 MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
77 MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
78
79 MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
80 MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
81 MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
82 MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
83 MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
84 MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
85 MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
86 MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
87
88 MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
89 MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
90 MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
91 MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
92 MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
93 MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
94
95 MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
96 MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
97 MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
98 MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
99 MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
100
101 MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
102 MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
103 MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
104 MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
105 MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
106 MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
107
108 MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
109 MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
110 MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
111 MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
112 MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
113 MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
114 MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
115 MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
116 MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
117 MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
118 MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
119 MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
120 MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
121 MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
122 MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
123 MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
124 MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
125
126 MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
127
128 MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
129 MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
130 MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
131 MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
132 MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
133 MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
134 MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
135 MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
136 MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
137 MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
138 MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
139 MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
140
141 MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
142 MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
143 MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
144 MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
145 MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
146
147 MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
148 MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
149 MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
150 MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
151 MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
152
153 MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
154 MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
155 MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
156 MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
157 MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
158
159 MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
160 MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
161 MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
162 MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
163 MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
164
165 MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
166 MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
167 MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
168
169 MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
170 MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
171 MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
172 MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
173 MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
174 MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
175 MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
176
177 MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
178 MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
179 MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
180 MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
181 MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
182 MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
183 MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
184 MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
185 MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
186 MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
187
188 INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
189 INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
190 INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
191 INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
192 INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
193 INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
194 INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
195 INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
196 INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
197 INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
198 INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
199 INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
200 INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
201 INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
202 INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
203 INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
204 INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
205 INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
206
207 EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
208 EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
209 EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
210 EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
211 #endif
212 };
213
214 static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
215
216 static struct davinci_spi_platform_data dm365_spi0_pdata = {
217 .version = SPI_VERSION_1,
218 .num_chipselect = 2,
219 .dma_event_q = EVENTQ_3,
220 .prescaler_limit = 1,
221 };
222
223 static struct resource dm365_spi0_resources[] = {
224 {
225 .start = 0x01c66000,
226 .end = 0x01c667ff,
227 .flags = IORESOURCE_MEM,
228 },
229 {
230 .start = DAVINCI_INTC_IRQ(IRQ_DM365_SPIINT0_0),
231 .flags = IORESOURCE_IRQ,
232 },
233 };
234
235 static struct platform_device dm365_spi0_device = {
236 .name = "spi_davinci",
237 .id = 0,
238 .dev = {
239 .dma_mask = &dm365_spi0_dma_mask,
240 .coherent_dma_mask = DMA_BIT_MASK(32),
241 .platform_data = &dm365_spi0_pdata,
242 },
243 .num_resources = ARRAY_SIZE(dm365_spi0_resources),
244 .resource = dm365_spi0_resources,
245 };
246
247 void __init dm365_init_spi0(unsigned chipselect_mask,
248 const struct spi_board_info *info, unsigned len)
249 {
250 davinci_cfg_reg(DM365_SPI0_SCLK);
251 davinci_cfg_reg(DM365_SPI0_SDI);
252 davinci_cfg_reg(DM365_SPI0_SDO);
253
254 /* not all slaves will be wired up */
255 if (chipselect_mask & BIT(0))
256 davinci_cfg_reg(DM365_SPI0_SDENA0);
257 if (chipselect_mask & BIT(1))
258 davinci_cfg_reg(DM365_SPI0_SDENA1);
259
260 spi_register_board_info(info, len);
261
262 platform_device_register(&dm365_spi0_device);
263 }
264
265 static struct resource dm365_gpio_resources[] = {
266 { /* registers */
267 .start = DAVINCI_GPIO_BASE,
268 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
269 .flags = IORESOURCE_MEM,
270 },
271 { /* interrupt */
272 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
273 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
274 .flags = IORESOURCE_IRQ,
275 },
276 {
277 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
278 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
279 .flags = IORESOURCE_IRQ,
280 },
281 {
282 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
283 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
284 .flags = IORESOURCE_IRQ,
285 },
286 {
287 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
288 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
289 .flags = IORESOURCE_IRQ,
290 },
291 {
292 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
293 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
294 .flags = IORESOURCE_IRQ,
295 },
296 {
297 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
298 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
299 .flags = IORESOURCE_IRQ,
300 },
301 {
302 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
303 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
304 .flags = IORESOURCE_IRQ,
305 },
306 {
307 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
308 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
309 .flags = IORESOURCE_IRQ,
310 },
311 };
312
313 static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
314 .no_auto_base = true,
315 .base = 0,
316 .ngpio = 104,
317 .gpio_unbanked = 8,
318 };
319
320 int __init dm365_gpio_register(void)
321 {
322 return davinci_gpio_register(dm365_gpio_resources,
323 ARRAY_SIZE(dm365_gpio_resources),
324 &dm365_gpio_platform_data);
325 }
326
327 static struct emac_platform_data dm365_emac_pdata = {
328 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
329 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
330 .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
331 .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
332 .version = EMAC_VERSION_2,
333 };
334
335 static struct resource dm365_emac_resources[] = {
336 {
337 .start = DM365_EMAC_BASE,
338 .end = DM365_EMAC_BASE + SZ_16K - 1,
339 .flags = IORESOURCE_MEM,
340 },
341 {
342 .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
343 .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
344 .flags = IORESOURCE_IRQ,
345 },
346 {
347 .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
348 .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
349 .flags = IORESOURCE_IRQ,
350 },
351 {
352 .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
353 .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
354 .flags = IORESOURCE_IRQ,
355 },
356 {
357 .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
358 .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
359 .flags = IORESOURCE_IRQ,
360 },
361 };
362
363 static struct platform_device dm365_emac_device = {
364 .name = "davinci_emac",
365 .id = 1,
366 .dev = {
367 .platform_data = &dm365_emac_pdata,
368 },
369 .num_resources = ARRAY_SIZE(dm365_emac_resources),
370 .resource = dm365_emac_resources,
371 };
372
373 static struct resource dm365_mdio_resources[] = {
374 {
375 .start = DM365_EMAC_MDIO_BASE,
376 .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
377 .flags = IORESOURCE_MEM,
378 },
379 };
380
381 static struct platform_device dm365_mdio_device = {
382 .name = "davinci_mdio",
383 .id = 0,
384 .num_resources = ARRAY_SIZE(dm365_mdio_resources),
385 .resource = dm365_mdio_resources,
386 };
387
388 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
389 [IRQ_VDINT0] = 2,
390 [IRQ_VDINT1] = 6,
391 [IRQ_VDINT2] = 6,
392 [IRQ_HISTINT] = 6,
393 [IRQ_H3AINT] = 6,
394 [IRQ_PRVUINT] = 6,
395 [IRQ_RSZINT] = 6,
396 [IRQ_DM365_INSFINT] = 7,
397 [IRQ_VENCINT] = 6,
398 [IRQ_ASQINT] = 6,
399 [IRQ_IMXINT] = 6,
400 [IRQ_DM365_IMCOPINT] = 4,
401 [IRQ_USBINT] = 4,
402 [IRQ_DM365_RTOINT] = 7,
403 [IRQ_DM365_TINT5] = 7,
404 [IRQ_DM365_TINT6] = 5,
405 [IRQ_CCINT0] = 5,
406 [IRQ_CCERRINT] = 5,
407 [IRQ_TCERRINT0] = 5,
408 [IRQ_TCERRINT] = 7,
409 [IRQ_PSCIN] = 4,
410 [IRQ_DM365_SPINT2_1] = 7,
411 [IRQ_DM365_TINT7] = 7,
412 [IRQ_DM365_SDIOINT0] = 7,
413 [IRQ_MBXINT] = 7,
414 [IRQ_MBRINT] = 7,
415 [IRQ_MMCINT] = 7,
416 [IRQ_DM365_MMCINT1] = 7,
417 [IRQ_DM365_PWMINT3] = 7,
418 [IRQ_AEMIFINT] = 2,
419 [IRQ_DM365_SDIOINT1] = 2,
420 [IRQ_TINT0_TINT12] = 7,
421 [IRQ_TINT0_TINT34] = 7,
422 [IRQ_TINT1_TINT12] = 7,
423 [IRQ_TINT1_TINT34] = 7,
424 [IRQ_PWMINT0] = 7,
425 [IRQ_PWMINT1] = 3,
426 [IRQ_PWMINT2] = 3,
427 [IRQ_I2C] = 3,
428 [IRQ_UARTINT0] = 3,
429 [IRQ_UARTINT1] = 3,
430 [IRQ_DM365_RTCINT] = 3,
431 [IRQ_DM365_SPIINT0_0] = 3,
432 [IRQ_DM365_SPIINT3_0] = 3,
433 [IRQ_DM365_GPIO0] = 3,
434 [IRQ_DM365_GPIO1] = 7,
435 [IRQ_DM365_GPIO2] = 4,
436 [IRQ_DM365_GPIO3] = 4,
437 [IRQ_DM365_GPIO4] = 7,
438 [IRQ_DM365_GPIO5] = 7,
439 [IRQ_DM365_GPIO6] = 7,
440 [IRQ_DM365_GPIO7] = 7,
441 [IRQ_DM365_EMAC_RXTHRESH] = 7,
442 [IRQ_DM365_EMAC_RXPULSE] = 7,
443 [IRQ_DM365_EMAC_TXPULSE] = 7,
444 [IRQ_DM365_EMAC_MISCPULSE] = 7,
445 [IRQ_DM365_GPIO12] = 7,
446 [IRQ_DM365_GPIO13] = 7,
447 [IRQ_DM365_GPIO14] = 7,
448 [IRQ_DM365_GPIO15] = 7,
449 [IRQ_DM365_KEYINT] = 7,
450 [IRQ_DM365_TCERRINT2] = 7,
451 [IRQ_DM365_TCERRINT3] = 7,
452 [IRQ_DM365_EMUINT] = 7,
453 };
454
455 /* Four Transfer Controllers on DM365 */
456 static s8 dm365_queue_priority_mapping[][2] = {
457 /* {event queue no, Priority} */
458 {0, 7},
459 {1, 7},
460 {2, 7},
461 {3, 0},
462 {-1, -1},
463 };
464
465 static const struct dma_slave_map dm365_edma_map[] = {
466 { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
467 { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
468 { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
469 { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
470 { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
471 { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
472 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
473 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
474 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
475 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
476 { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
477 { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
478 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
479 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
480 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
481 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
482 };
483
484 static struct edma_soc_info dm365_edma_pdata = {
485 .queue_priority_mapping = dm365_queue_priority_mapping,
486 .default_queue = EVENTQ_3,
487 .slave_map = dm365_edma_map,
488 .slavecnt = ARRAY_SIZE(dm365_edma_map),
489 };
490
491 static struct resource edma_resources[] = {
492 {
493 .name = "edma3_cc",
494 .start = 0x01c00000,
495 .end = 0x01c00000 + SZ_64K - 1,
496 .flags = IORESOURCE_MEM,
497 },
498 {
499 .name = "edma3_tc0",
500 .start = 0x01c10000,
501 .end = 0x01c10000 + SZ_1K - 1,
502 .flags = IORESOURCE_MEM,
503 },
504 {
505 .name = "edma3_tc1",
506 .start = 0x01c10400,
507 .end = 0x01c10400 + SZ_1K - 1,
508 .flags = IORESOURCE_MEM,
509 },
510 {
511 .name = "edma3_tc2",
512 .start = 0x01c10800,
513 .end = 0x01c10800 + SZ_1K - 1,
514 .flags = IORESOURCE_MEM,
515 },
516 {
517 .name = "edma3_tc3",
518 .start = 0x01c10c00,
519 .end = 0x01c10c00 + SZ_1K - 1,
520 .flags = IORESOURCE_MEM,
521 },
522 {
523 .name = "edma3_ccint",
524 .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
525 .flags = IORESOURCE_IRQ,
526 },
527 {
528 .name = "edma3_ccerrint",
529 .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
530 .flags = IORESOURCE_IRQ,
531 },
532 /* not using TC*_ERR */
533 };
534
535 static const struct platform_device_info dm365_edma_device __initconst = {
536 .name = "edma",
537 .id = 0,
538 .dma_mask = DMA_BIT_MASK(32),
539 .res = edma_resources,
540 .num_res = ARRAY_SIZE(edma_resources),
541 .data = &dm365_edma_pdata,
542 .size_data = sizeof(dm365_edma_pdata),
543 };
544
545 static struct resource dm365_asp_resources[] = {
546 {
547 .name = "mpu",
548 .start = DAVINCI_DM365_ASP0_BASE,
549 .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
550 .flags = IORESOURCE_MEM,
551 },
552 {
553 .start = DAVINCI_DMA_ASP0_TX,
554 .end = DAVINCI_DMA_ASP0_TX,
555 .flags = IORESOURCE_DMA,
556 },
557 {
558 .start = DAVINCI_DMA_ASP0_RX,
559 .end = DAVINCI_DMA_ASP0_RX,
560 .flags = IORESOURCE_DMA,
561 },
562 };
563
564 static struct platform_device dm365_asp_device = {
565 .name = "davinci-mcbsp",
566 .id = -1,
567 .num_resources = ARRAY_SIZE(dm365_asp_resources),
568 .resource = dm365_asp_resources,
569 };
570
571 static struct resource dm365_vc_resources[] = {
572 {
573 .start = DAVINCI_DM365_VC_BASE,
574 .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
575 .flags = IORESOURCE_MEM,
576 },
577 {
578 .start = DAVINCI_DMA_VC_TX,
579 .end = DAVINCI_DMA_VC_TX,
580 .flags = IORESOURCE_DMA,
581 },
582 {
583 .start = DAVINCI_DMA_VC_RX,
584 .end = DAVINCI_DMA_VC_RX,
585 .flags = IORESOURCE_DMA,
586 },
587 };
588
589 static struct platform_device dm365_vc_device = {
590 .name = "davinci_voicecodec",
591 .id = -1,
592 .num_resources = ARRAY_SIZE(dm365_vc_resources),
593 .resource = dm365_vc_resources,
594 };
595
596 static struct resource dm365_rtc_resources[] = {
597 {
598 .start = DM365_RTC_BASE,
599 .end = DM365_RTC_BASE + SZ_1K - 1,
600 .flags = IORESOURCE_MEM,
601 },
602 {
603 .start = DAVINCI_INTC_IRQ(IRQ_DM365_RTCINT),
604 .flags = IORESOURCE_IRQ,
605 },
606 };
607
608 static struct platform_device dm365_rtc_device = {
609 .name = "rtc_davinci",
610 .id = 0,
611 .num_resources = ARRAY_SIZE(dm365_rtc_resources),
612 .resource = dm365_rtc_resources,
613 };
614
615 static struct map_desc dm365_io_desc[] = {
616 {
617 .virtual = IO_VIRT,
618 .pfn = __phys_to_pfn(IO_PHYS),
619 .length = IO_SIZE,
620 .type = MT_DEVICE
621 },
622 };
623
624 static struct resource dm365_ks_resources[] = {
625 {
626 /* registers */
627 .start = DM365_KEYSCAN_BASE,
628 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
629 .flags = IORESOURCE_MEM,
630 },
631 {
632 /* interrupt */
633 .start = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
634 .end = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
635 .flags = IORESOURCE_IRQ,
636 },
637 };
638
639 static struct platform_device dm365_ks_device = {
640 .name = "davinci_keyscan",
641 .id = 0,
642 .num_resources = ARRAY_SIZE(dm365_ks_resources),
643 .resource = dm365_ks_resources,
644 };
645
646 /* Contents of JTAG ID register used to identify exact cpu type */
647 static struct davinci_id dm365_ids[] = {
648 {
649 .variant = 0x0,
650 .part_no = 0xb83e,
651 .manufacturer = 0x017,
652 .cpu_id = DAVINCI_CPU_ID_DM365,
653 .name = "dm365_rev1.1",
654 },
655 {
656 .variant = 0x8,
657 .part_no = 0xb83e,
658 .manufacturer = 0x017,
659 .cpu_id = DAVINCI_CPU_ID_DM365,
660 .name = "dm365_rev1.2",
661 },
662 };
663
664 /*
665 * Bottom half of timer0 is used for clockevent, top half is used for
666 * clocksource.
667 */
668 static const struct davinci_timer_cfg dm365_timer_cfg = {
669 .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_128),
670 .irq = {
671 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
672 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
673 },
674 };
675
676 #define DM365_UART1_BASE (IO_PHYS + 0x106000)
677
678 static struct plat_serial8250_port dm365_serial0_platform_data[] = {
679 {
680 .mapbase = DAVINCI_UART0_BASE,
681 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
682 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
683 UPF_IOREMAP,
684 .iotype = UPIO_MEM,
685 .regshift = 2,
686 },
687 {
688 .flags = 0,
689 }
690 };
691 static struct plat_serial8250_port dm365_serial1_platform_data[] = {
692 {
693 .mapbase = DM365_UART1_BASE,
694 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
695 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
696 UPF_IOREMAP,
697 .iotype = UPIO_MEM,
698 .regshift = 2,
699 },
700 {
701 .flags = 0,
702 }
703 };
704
705 struct platform_device dm365_serial_device[] = {
706 {
707 .name = "serial8250",
708 .id = PLAT8250_DEV_PLATFORM,
709 .dev = {
710 .platform_data = dm365_serial0_platform_data,
711 }
712 },
713 {
714 .name = "serial8250",
715 .id = PLAT8250_DEV_PLATFORM1,
716 .dev = {
717 .platform_data = dm365_serial1_platform_data,
718 }
719 },
720 {
721 }
722 };
723
724 static const struct davinci_soc_info davinci_soc_info_dm365 = {
725 .io_desc = dm365_io_desc,
726 .io_desc_num = ARRAY_SIZE(dm365_io_desc),
727 .jtag_id_reg = 0x01c40028,
728 .ids = dm365_ids,
729 .ids_num = ARRAY_SIZE(dm365_ids),
730 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
731 .pinmux_pins = dm365_pins,
732 .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
733 .emac_pdata = &dm365_emac_pdata,
734 .sram_dma = 0x00010000,
735 .sram_len = SZ_32K,
736 };
737
738 void __init dm365_init_asp(void)
739 {
740 davinci_cfg_reg(DM365_MCBSP0_BDX);
741 davinci_cfg_reg(DM365_MCBSP0_X);
742 davinci_cfg_reg(DM365_MCBSP0_BFSX);
743 davinci_cfg_reg(DM365_MCBSP0_BDR);
744 davinci_cfg_reg(DM365_MCBSP0_R);
745 davinci_cfg_reg(DM365_MCBSP0_BFSR);
746 davinci_cfg_reg(DM365_EVT2_ASP_TX);
747 davinci_cfg_reg(DM365_EVT3_ASP_RX);
748 platform_device_register(&dm365_asp_device);
749 }
750
751 void __init dm365_init_vc(void)
752 {
753 davinci_cfg_reg(DM365_EVT2_VC_TX);
754 davinci_cfg_reg(DM365_EVT3_VC_RX);
755 platform_device_register(&dm365_vc_device);
756 }
757
758 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
759 {
760 dm365_ks_device.dev.platform_data = pdata;
761 platform_device_register(&dm365_ks_device);
762 }
763
764 void __init dm365_init_rtc(void)
765 {
766 davinci_cfg_reg(DM365_INT_PRTCSS);
767 platform_device_register(&dm365_rtc_device);
768 }
769
770 void __init dm365_init(void)
771 {
772 davinci_common_init(&davinci_soc_info_dm365);
773 davinci_map_sysmod();
774 }
775
776 void __init dm365_init_time(void)
777 {
778 void __iomem *pll1, *pll2, *psc;
779 struct clk *clk;
780 int rv;
781
782 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
783
784 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
785 dm365_pll1_init(NULL, pll1, NULL);
786
787 pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K);
788 dm365_pll2_init(NULL, pll2, NULL);
789
790 psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
791 dm365_psc_init(NULL, psc);
792
793 clk = clk_get(NULL, "timer0");
794 if (WARN_ON(IS_ERR(clk))) {
795 pr_err("Unable to get the timer clock\n");
796 return;
797 }
798
799 rv = davinci_timer_register(clk, &dm365_timer_cfg);
800 WARN(rv, "Unable to register the timer: %d\n", rv);
801 }
802
803 void __init dm365_register_clocks(void)
804 {
805 /* all clocks are currently registered in dm365_init_time() */
806 }
807
808 static struct resource dm365_vpss_resources[] = {
809 {
810 /* VPSS ISP5 Base address */
811 .name = "isp5",
812 .start = 0x01c70000,
813 .end = 0x01c70000 + 0xff,
814 .flags = IORESOURCE_MEM,
815 },
816 {
817 /* VPSS CLK Base address */
818 .name = "vpss",
819 .start = 0x01c70200,
820 .end = 0x01c70200 + 0xff,
821 .flags = IORESOURCE_MEM,
822 },
823 };
824
825 static struct platform_device dm365_vpss_device = {
826 .name = "vpss",
827 .id = -1,
828 .dev.platform_data = "dm365_vpss",
829 .num_resources = ARRAY_SIZE(dm365_vpss_resources),
830 .resource = dm365_vpss_resources,
831 };
832
833 static struct resource vpfe_resources[] = {
834 {
835 .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
836 .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
837 .flags = IORESOURCE_IRQ,
838 },
839 {
840 .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
841 .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
842 .flags = IORESOURCE_IRQ,
843 },
844 };
845
846 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
847 static struct platform_device vpfe_capture_dev = {
848 .name = CAPTURE_DRV_NAME,
849 .id = -1,
850 .num_resources = ARRAY_SIZE(vpfe_resources),
851 .resource = vpfe_resources,
852 .dev = {
853 .dma_mask = &vpfe_capture_dma_mask,
854 .coherent_dma_mask = DMA_BIT_MASK(32),
855 },
856 };
857
858 static void dm365_isif_setup_pinmux(void)
859 {
860 davinci_cfg_reg(DM365_VIN_CAM_WEN);
861 davinci_cfg_reg(DM365_VIN_CAM_VD);
862 davinci_cfg_reg(DM365_VIN_CAM_HD);
863 davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
864 davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
865 }
866
867 static struct resource isif_resource[] = {
868 /* ISIF Base address */
869 {
870 .start = 0x01c71000,
871 .end = 0x01c71000 + 0x1ff,
872 .flags = IORESOURCE_MEM,
873 },
874 /* ISIF Linearization table 0 */
875 {
876 .start = 0x1C7C000,
877 .end = 0x1C7C000 + 0x2ff,
878 .flags = IORESOURCE_MEM,
879 },
880 /* ISIF Linearization table 1 */
881 {
882 .start = 0x1C7C400,
883 .end = 0x1C7C400 + 0x2ff,
884 .flags = IORESOURCE_MEM,
885 },
886 };
887 static struct platform_device dm365_isif_dev = {
888 .name = "isif",
889 .id = -1,
890 .num_resources = ARRAY_SIZE(isif_resource),
891 .resource = isif_resource,
892 .dev = {
893 .dma_mask = &vpfe_capture_dma_mask,
894 .coherent_dma_mask = DMA_BIT_MASK(32),
895 .platform_data = dm365_isif_setup_pinmux,
896 },
897 };
898
899 static struct resource dm365_osd_resources[] = {
900 {
901 .start = DM365_OSD_BASE,
902 .end = DM365_OSD_BASE + 0xff,
903 .flags = IORESOURCE_MEM,
904 },
905 };
906
907 static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
908
909 static struct platform_device dm365_osd_dev = {
910 .name = DM365_VPBE_OSD_SUBDEV_NAME,
911 .id = -1,
912 .num_resources = ARRAY_SIZE(dm365_osd_resources),
913 .resource = dm365_osd_resources,
914 .dev = {
915 .dma_mask = &dm365_video_dma_mask,
916 .coherent_dma_mask = DMA_BIT_MASK(32),
917 },
918 };
919
920 static struct resource dm365_venc_resources[] = {
921 {
922 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
923 .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
924 .flags = IORESOURCE_IRQ,
925 },
926 /* venc registers io space */
927 {
928 .start = DM365_VENC_BASE,
929 .end = DM365_VENC_BASE + 0x177,
930 .flags = IORESOURCE_MEM,
931 },
932 /* vdaccfg registers io space */
933 {
934 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
935 .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
936 .flags = IORESOURCE_MEM,
937 },
938 };
939
940 static struct resource dm365_v4l2_disp_resources[] = {
941 {
942 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
943 .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
944 .flags = IORESOURCE_IRQ,
945 },
946 /* venc registers io space */
947 {
948 .start = DM365_VENC_BASE,
949 .end = DM365_VENC_BASE + 0x177,
950 .flags = IORESOURCE_MEM,
951 },
952 };
953
954 static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
955 {
956 switch (if_type) {
957 case MEDIA_BUS_FMT_SGRBG8_1X8:
958 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
959 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
960 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
961 break;
962 case MEDIA_BUS_FMT_YUYV10_1X20:
963 if (field)
964 davinci_cfg_reg(DM365_VOUT_FIELD);
965 else
966 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
967 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
968 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
969 break;
970 default:
971 return -EINVAL;
972 }
973
974 return 0;
975 }
976
977 static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
978 unsigned int pclock)
979 {
980 void __iomem *vpss_clkctl_reg;
981 u32 val;
982
983 vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
984
985 switch (type) {
986 case VPBE_ENC_STD:
987 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
988 break;
989 case VPBE_ENC_DV_TIMINGS:
990 if (pclock <= 27000000) {
991 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
992 } else {
993 /* set sysclk4 to output 74.25 MHz from pll1 */
994 val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
995 VPSS_VENCCLKEN_ENABLE;
996 }
997 break;
998 default:
999 return -EINVAL;
1000 }
1001 writel(val, vpss_clkctl_reg);
1002
1003 return 0;
1004 }
1005
1006 static struct platform_device dm365_vpbe_display = {
1007 .name = "vpbe-v4l2",
1008 .id = -1,
1009 .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources),
1010 .resource = dm365_v4l2_disp_resources,
1011 .dev = {
1012 .dma_mask = &dm365_video_dma_mask,
1013 .coherent_dma_mask = DMA_BIT_MASK(32),
1014 },
1015 };
1016
1017 static struct venc_platform_data dm365_venc_pdata = {
1018 .setup_pinmux = dm365_vpbe_setup_pinmux,
1019 .setup_clock = dm365_venc_setup_clock,
1020 };
1021
1022 static struct platform_device dm365_venc_dev = {
1023 .name = DM365_VPBE_VENC_SUBDEV_NAME,
1024 .id = -1,
1025 .num_resources = ARRAY_SIZE(dm365_venc_resources),
1026 .resource = dm365_venc_resources,
1027 .dev = {
1028 .dma_mask = &dm365_video_dma_mask,
1029 .coherent_dma_mask = DMA_BIT_MASK(32),
1030 .platform_data = (void *)&dm365_venc_pdata,
1031 },
1032 };
1033
1034 static struct platform_device dm365_vpbe_dev = {
1035 .name = "vpbe_controller",
1036 .id = -1,
1037 .dev = {
1038 .dma_mask = &dm365_video_dma_mask,
1039 .coherent_dma_mask = DMA_BIT_MASK(32),
1040 },
1041 };
1042
1043 int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
1044 struct vpbe_config *vpbe_cfg)
1045 {
1046 if (vpfe_cfg || vpbe_cfg)
1047 platform_device_register(&dm365_vpss_device);
1048
1049 if (vpfe_cfg) {
1050 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1051 platform_device_register(&dm365_isif_dev);
1052 platform_device_register(&vpfe_capture_dev);
1053 }
1054 if (vpbe_cfg) {
1055 dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
1056 platform_device_register(&dm365_osd_dev);
1057 platform_device_register(&dm365_venc_dev);
1058 platform_device_register(&dm365_vpbe_dev);
1059 platform_device_register(&dm365_vpbe_display);
1060 }
1061
1062 return 0;
1063 }
1064
1065 static const struct davinci_aintc_config dm365_aintc_config = {
1066 .reg = {
1067 .start = DAVINCI_ARM_INTC_BASE,
1068 .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
1069 .flags = IORESOURCE_MEM,
1070 },
1071 .num_irqs = 64,
1072 .prios = dm365_default_priorities,
1073 };
1074
1075 void __init dm365_init_irq(void)
1076 {
1077 davinci_aintc_init(&dm365_aintc_config);
1078 }
1079
1080 static int __init dm365_init_devices(void)
1081 {
1082 struct platform_device *edma_pdev;
1083 int ret = 0;
1084
1085 if (!cpu_is_davinci_dm365())
1086 return 0;
1087
1088 davinci_cfg_reg(DM365_INT_EDMA_CC);
1089 edma_pdev = platform_device_register_full(&dm365_edma_device);
1090 if (IS_ERR(edma_pdev)) {
1091 pr_warn("%s: Failed to register eDMA\n", __func__);
1092 return PTR_ERR(edma_pdev);
1093 }
1094
1095 platform_device_register(&dm365_mdio_device);
1096 platform_device_register(&dm365_emac_device);
1097
1098 ret = davinci_init_wdt();
1099 if (ret)
1100 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1101
1102 return ret;
1103 }
1104 postcore_initcall(dm365_init_devices);
Linux with added FPC-III support