arch/arm/mach-omap1/dma.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * OMAP1/OMAP7xx - specific DMA driver
   4  *
   5  * Copyright (C) 2003 - 2008 Nokia Corporation
   6  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   7  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   8  * Graphics DMA and LCD DMA graphics tranformations
   9  * by Imre Deak <imre.deak@nokia.com>
  10  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
  14  * Converted DMA library into platform driver
  15  *                   - G, Manjunath Kondaiah <manjugk@ti.com>
  16  */
  17
  18 #include <linux/err.h>
  19 #include <linux/slab.h>
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/device.h>
  23 #include <linux/io.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/dmaengine.h>
  26 #include <linux/omap-dma.h>
  27 #include <mach/tc.h>
  28
  29 #include "soc.h"
  30
  31 #define OMAP1_DMA_BASE                  (0xfffed800)
  32
  33 static u32 enable_1510_mode;
  34
  35 static const struct omap_dma_reg reg_map[] = {
  36         [GCR]           = { 0x0400, 0x00, OMAP_DMA_REG_16BIT },
  37         [GSCR]          = { 0x0404, 0x00, OMAP_DMA_REG_16BIT },
  38         [GRST1]         = { 0x0408, 0x00, OMAP_DMA_REG_16BIT },
  39         [HW_ID]         = { 0x0442, 0x00, OMAP_DMA_REG_16BIT },
  40         [PCH2_ID]       = { 0x0444, 0x00, OMAP_DMA_REG_16BIT },
  41         [PCH0_ID]       = { 0x0446, 0x00, OMAP_DMA_REG_16BIT },
  42         [PCH1_ID]       = { 0x0448, 0x00, OMAP_DMA_REG_16BIT },
  43         [PCHG_ID]       = { 0x044a, 0x00, OMAP_DMA_REG_16BIT },
  44         [PCHD_ID]       = { 0x044c, 0x00, OMAP_DMA_REG_16BIT },
  45         [CAPS_0]        = { 0x044e, 0x00, OMAP_DMA_REG_2X16BIT },
  46         [CAPS_1]        = { 0x0452, 0x00, OMAP_DMA_REG_2X16BIT },
  47         [CAPS_2]        = { 0x0456, 0x00, OMAP_DMA_REG_16BIT },
  48         [CAPS_3]        = { 0x0458, 0x00, OMAP_DMA_REG_16BIT },
  49         [CAPS_4]        = { 0x045a, 0x00, OMAP_DMA_REG_16BIT },
  50         [PCH2_SR]       = { 0x0460, 0x00, OMAP_DMA_REG_16BIT },
  51         [PCH0_SR]       = { 0x0480, 0x00, OMAP_DMA_REG_16BIT },
  52         [PCH1_SR]       = { 0x0482, 0x00, OMAP_DMA_REG_16BIT },
  53         [PCHD_SR]       = { 0x04c0, 0x00, OMAP_DMA_REG_16BIT },
  54
  55         /* Common Registers */
  56         [CSDP]          = { 0x0000, 0x40, OMAP_DMA_REG_16BIT },
  57         [CCR]           = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
  58         [CICR]          = { 0x0004, 0x40, OMAP_DMA_REG_16BIT },
  59         [CSR]           = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
  60         [CEN]           = { 0x0010, 0x40, OMAP_DMA_REG_16BIT },
  61         [CFN]           = { 0x0012, 0x40, OMAP_DMA_REG_16BIT },
  62         [CSFI]          = { 0x0014, 0x40, OMAP_DMA_REG_16BIT },
  63         [CSEI]          = { 0x0016, 0x40, OMAP_DMA_REG_16BIT },
  64         [CPC]           = { 0x0018, 0x40, OMAP_DMA_REG_16BIT }, /* 15xx only */
  65         [CSAC]          = { 0x0018, 0x40, OMAP_DMA_REG_16BIT },
  66         [CDAC]          = { 0x001a, 0x40, OMAP_DMA_REG_16BIT },
  67         [CDEI]          = { 0x001c, 0x40, OMAP_DMA_REG_16BIT },
  68         [CDFI]          = { 0x001e, 0x40, OMAP_DMA_REG_16BIT },
  69         [CLNK_CTRL]     = { 0x0028, 0x40, OMAP_DMA_REG_16BIT },
  70
  71         /* Channel specific register offsets */
  72         [CSSA]          = { 0x0008, 0x40, OMAP_DMA_REG_2X16BIT },
  73         [CDSA]          = { 0x000c, 0x40, OMAP_DMA_REG_2X16BIT },
  74         [COLOR]         = { 0x0020, 0x40, OMAP_DMA_REG_2X16BIT },
  75         [CCR2]          = { 0x0024, 0x40, OMAP_DMA_REG_16BIT },
  76         [LCH_CTRL]      = { 0x002a, 0x40, OMAP_DMA_REG_16BIT },
  77 };
  78
  79 static struct resource res[] __initdata = {
  80         [0] = {
  81                 .start  = OMAP1_DMA_BASE,
  82                 .end    = OMAP1_DMA_BASE + SZ_2K - 1,
  83                 .flags  = IORESOURCE_MEM,
  84         },
  85         [1] = {
  86                 .name   = "0",
  87                 .start  = INT_DMA_CH0_6,
  88                 .flags  = IORESOURCE_IRQ,
  89         },
  90         [2] = {
  91                 .name   = "1",
  92                 .start  = INT_DMA_CH1_7,
  93                 .flags  = IORESOURCE_IRQ,
  94         },
  95         [3] = {
  96                 .name   = "2",
  97                 .start  = INT_DMA_CH2_8,
  98                 .flags  = IORESOURCE_IRQ,
  99         },
 100         [4] = {
 101                 .name   = "3",
 102                 .start  = INT_DMA_CH3,
 103                 .flags  = IORESOURCE_IRQ,
 104         },
 105         [5] = {
 106                 .name   = "4",
 107                 .start  = INT_DMA_CH4,
 108                 .flags  = IORESOURCE_IRQ,
 109         },
 110         [6] = {
 111                 .name   = "5",
 112                 .start  = INT_DMA_CH5,
 113                 .flags  = IORESOURCE_IRQ,
 114         },
 115         /* Handled in lcd_dma.c */
 116         [7] = {
 117                 .name   = "6",
 118                 .start  = INT_1610_DMA_CH6,
 119                 .flags  = IORESOURCE_IRQ,
 120         },
 121         /* irq's for omap16xx and omap7xx */
 122         [8] = {
 123                 .name   = "7",
 124                 .start  = INT_1610_DMA_CH7,
 125                 .flags  = IORESOURCE_IRQ,
 126         },
 127         [9] = {
 128                 .name   = "8",
 129                 .start  = INT_1610_DMA_CH8,
 130                 .flags  = IORESOURCE_IRQ,
 131         },
 132         [10] = {
 133                 .name  = "9",
 134                 .start = INT_1610_DMA_CH9,
 135                 .flags = IORESOURCE_IRQ,
 136         },
 137         [11] = {
 138                 .name  = "10",
 139                 .start = INT_1610_DMA_CH10,
 140                 .flags = IORESOURCE_IRQ,
 141         },
 142         [12] = {
 143                 .name  = "11",
 144                 .start = INT_1610_DMA_CH11,
 145                 .flags = IORESOURCE_IRQ,
 146         },
 147         [13] = {
 148                 .name  = "12",
 149                 .start = INT_1610_DMA_CH12,
 150                 .flags = IORESOURCE_IRQ,
 151         },
 152         [14] = {
 153                 .name  = "13",
 154                 .start = INT_1610_DMA_CH13,
 155                 .flags = IORESOURCE_IRQ,
 156         },
 157         [15] = {
 158                 .name  = "14",
 159                 .start = INT_1610_DMA_CH14,
 160                 .flags = IORESOURCE_IRQ,
 161         },
 162         [16] = {
 163                 .name  = "15",
 164                 .start = INT_1610_DMA_CH15,
 165                 .flags = IORESOURCE_IRQ,
 166         },
 167         [17] = {
 168                 .name  = "16",
 169                 .start = INT_DMA_LCD,
 170                 .flags = IORESOURCE_IRQ,
 171         },
 172 };
 173
 174 static void __iomem *dma_base;
 175 static inline void dma_write(u32 val, int reg, int lch)
 176 {
 177         void __iomem *addr = dma_base;
 178
 179         addr += reg_map[reg].offset;
 180         addr += reg_map[reg].stride * lch;
 181
 182         __raw_writew(val, addr);
 183         if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
 184                 __raw_writew(val >> 16, addr + 2);
 185 }
 186
 187 static inline u32 dma_read(int reg, int lch)
 188 {
 189         void __iomem *addr = dma_base;
 190         uint32_t val;
 191
 192         addr += reg_map[reg].offset;
 193         addr += reg_map[reg].stride * lch;
 194
 195         val = __raw_readw(addr);
 196         if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
 197                 val |= __raw_readw(addr + 2) << 16;
 198
 199         return val;
 200 }
 201
 202 static void omap1_clear_lch_regs(int lch)
 203 {
 204         int i;
 205
 206         for (i = CPC; i <= COLOR; i += 1)
 207                 dma_write(0, i, lch);
 208 }
 209
 210 static void omap1_clear_dma(int lch)
 211 {
 212         u32 l;
 213
 214         l = dma_read(CCR, lch);
 215         l &= ~OMAP_DMA_CCR_EN;
 216         dma_write(l, CCR, lch);
 217
 218         /* Clear pending interrupts */
 219         l = dma_read(CSR, lch);
 220 }
 221
 222 static void omap1_show_dma_caps(void)
 223 {
 224         if (enable_1510_mode) {
 225                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
 226         } else {
 227                 u16 w;
 228                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
 229                                                         dma_read(HW_ID, 0));
 230                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
 231                         dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
 232                         dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
 233                         dma_read(CAPS_4, 0));
 234
 235                 /* Disable OMAP 3.0/3.1 compatibility mode. */
 236                 w = dma_read(GSCR, 0);
 237                 w |= 1 << 3;
 238                 dma_write(w, GSCR, 0);
 239         }
 240 }
 241
 242 static unsigned configure_dma_errata(void)
 243 {
 244         unsigned errata = 0;
 245
 246         /*
 247          * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
 248          * read before the DMA controller finished disabling the channel.
 249          */
 250         if (!cpu_is_omap15xx())
 251                 SET_DMA_ERRATA(DMA_ERRATA_3_3);
 252
 253         return errata;
 254 }
 255
 256 static const struct platform_device_info omap_dma_dev_info = {
 257         .name = "omap-dma-engine",
 258         .id = -1,
 259         .dma_mask = DMA_BIT_MASK(32),
 260         .res = res,
 261         .num_res = 1,
 262 };
 263
 264 /* OMAP730, OMAP850 */
 265 static const struct dma_slave_map omap7xx_sdma_map[] = {
 266         { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) },
 267         { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) },
 268         { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(10) },
 269         { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(11) },
 270         { "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) },
 271         { "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) },
 272         { "omap_udc", "rx0", SDMA_FILTER_PARAM(26) },
 273         { "omap_udc", "rx1", SDMA_FILTER_PARAM(27) },
 274         { "omap_udc", "rx2", SDMA_FILTER_PARAM(28) },
 275         { "omap_udc", "tx0", SDMA_FILTER_PARAM(29) },
 276         { "omap_udc", "tx1", SDMA_FILTER_PARAM(30) },
 277         { "omap_udc", "tx2", SDMA_FILTER_PARAM(31) },
 278 };
 279
 280 /* OMAP1510, OMAP1610*/
 281 static const struct dma_slave_map omap1xxx_sdma_map[] = {
 282         { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) },
 283         { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) },
 284         { "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(10) },
 285         { "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(11) },
 286         { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(16) },
 287         { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(17) },
 288         { "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) },
 289         { "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) },
 290         { "omap_udc", "rx0", SDMA_FILTER_PARAM(26) },
 291         { "omap_udc", "rx1", SDMA_FILTER_PARAM(27) },
 292         { "omap_udc", "rx2", SDMA_FILTER_PARAM(28) },
 293         { "omap_udc", "tx0", SDMA_FILTER_PARAM(29) },
 294         { "omap_udc", "tx1", SDMA_FILTER_PARAM(30) },
 295         { "omap_udc", "tx2", SDMA_FILTER_PARAM(31) },
 296         { "mmci-omap.1", "tx", SDMA_FILTER_PARAM(54) },
 297         { "mmci-omap.1", "rx", SDMA_FILTER_PARAM(55) },
 298 };
 299
 300 static struct omap_system_dma_plat_info dma_plat_info __initdata = {
 301         .reg_map        = reg_map,
 302         .channel_stride = 0x40,
 303         .show_dma_caps  = omap1_show_dma_caps,
 304         .clear_lch_regs = omap1_clear_lch_regs,
 305         .clear_dma      = omap1_clear_dma,
 306         .dma_write      = dma_write,
 307         .dma_read       = dma_read,
 308 };
 309
 310 static int __init omap1_system_dma_init(void)
 311 {
 312         struct omap_system_dma_plat_info        p;
 313         struct omap_dma_dev_attr                *d;
 314         struct platform_device                  *pdev, *dma_pdev;
 315         int ret;
 316
 317         pdev = platform_device_alloc("omap_dma_system", 0);
 318         if (!pdev) {
 319                 pr_err("%s: Unable to device alloc for dma\n",
 320                         __func__);
 321                 return -ENOMEM;
 322         }
 323
 324         dma_base = ioremap(res[0].start, resource_size(&res[0]));
 325         if (!dma_base) {
 326                 pr_err("%s: Unable to ioremap\n", __func__);
 327                 ret = -ENODEV;
 328                 goto exit_device_put;
 329         }
 330
 331         ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
 332         if (ret) {
 333                 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
 334                         __func__, pdev->name, pdev->id);
 335                 goto exit_iounmap;
 336         }
 337
 338         d = kzalloc(sizeof(*d), GFP_KERNEL);
 339         if (!d) {
 340                 ret = -ENOMEM;
 341                 goto exit_iounmap;
 342         }
 343
 344         /* Valid attributes for omap1 plus processors */
 345         if (cpu_is_omap15xx())
 346                 d->dev_caps = ENABLE_1510_MODE;
 347         enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
 348
 349         if (cpu_is_omap16xx())
 350                 d->dev_caps = ENABLE_16XX_MODE;
 351
 352         d->dev_caps             |= SRC_PORT;
 353         d->dev_caps             |= DST_PORT;
 354         d->dev_caps             |= SRC_INDEX;
 355         d->dev_caps             |= DST_INDEX;
 356         d->dev_caps             |= IS_BURST_ONLY4;
 357         d->dev_caps             |= CLEAR_CSR_ON_READ;
 358         d->dev_caps             |= IS_WORD_16;
 359
 360         /* available logical channels */
 361         if (cpu_is_omap15xx()) {
 362                 d->lch_count = 9;
 363         } else {
 364                 if (d->dev_caps & ENABLE_1510_MODE)
 365                         d->lch_count = 9;
 366                 else
 367                         d->lch_count = 16;
 368         }
 369
 370         p = dma_plat_info;
 371         p.dma_attr = d;
 372         p.errata = configure_dma_errata();
 373
 374         if (cpu_is_omap7xx()) {
 375                 p.slave_map = omap7xx_sdma_map;
 376                 p.slavecnt = ARRAY_SIZE(omap7xx_sdma_map);
 377         } else {
 378                 p.slave_map = omap1xxx_sdma_map;
 379                 p.slavecnt = ARRAY_SIZE(omap1xxx_sdma_map);
 380         }
 381
 382         ret = platform_device_add_data(pdev, &p, sizeof(p));
 383         if (ret) {
 384                 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
 385                         __func__, pdev->name, pdev->id);
 386                 goto exit_release_d;
 387         }
 388
 389         ret = platform_device_add(pdev);
 390         if (ret) {
 391                 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
 392                         __func__, pdev->name, pdev->id);
 393                 goto exit_release_d;
 394         }
 395
 396         dma_pdev = platform_device_register_full(&omap_dma_dev_info);
 397         if (IS_ERR(dma_pdev)) {
 398                 ret = PTR_ERR(dma_pdev);
 399                 goto exit_release_pdev;
 400         }
 401
 402         return ret;
 403
 404 exit_release_pdev:
 405         platform_device_del(pdev);
 406 exit_release_d:
 407         kfree(d);
 408 exit_iounmap:
 409         iounmap(dma_base);
 410 exit_device_put:
 411         platform_device_put(pdev);
 412
 413         return ret;
 414 }
 415 arch_initcall(omap1_system_dma_init);