arch/arm/mach-omap1/include/mach/mux.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * arch/arm/plat-omap/include/mach/mux.h
   4  *
   5  * Table of the Omap register configurations for the FUNC_MUX and
   6  * PULL_DWN combinations.
   7  *
   8  * Copyright (C) 2004 - 2008 Texas Instruments Inc.
   9  * Copyright (C) 2003 - 2008 Nokia Corporation
  10  *
  11  * Written by Tony Lindgren
  12  *
  13  * NOTE: Please use the following naming style for new pin entries.
  14  *       For example, W8_1610_MMC2_DAT0, where:
  15  *       - W8        = ball
  16  *       - 1610      = 1510 or 1610, none if common for both 1510 and 1610
  17  *       - MMC2_DAT0 = function
  18  */
  19
  20 #ifndef __ASM_ARCH_MUX_H
  21 #define __ASM_ARCH_MUX_H
  22
  23 #define PU_PD_SEL_NA            0       /* No pu_pd reg available */
  24 #define PULL_DWN_CTRL_NA        0       /* No pull-down control needed */
  25
  26 #ifdef  CONFIG_OMAP_MUX_DEBUG
  27 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
  28                                         .mux_reg = FUNC_MUX_CTRL_##reg, \
  29                                         .mask_offset = mode_offset, \
  30                                         .mask = mode,
  31
  32 #define PULL_REG(reg, bit, status)      .pull_name = "PULL_DWN_CTRL_"#reg, \
  33                                         .pull_reg = PULL_DWN_CTRL_##reg, \
  34                                         .pull_bit = bit, \
  35                                         .pull_val = status,
  36
  37 #define PU_PD_REG(reg, status)          .pu_pd_name = "PU_PD_SEL_"#reg, \
  38                                         .pu_pd_reg = PU_PD_SEL_##reg, \
  39                                         .pu_pd_val = status,
  40
  41 #define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
  42                                         .mux_reg = OMAP7XX_IO_CONF_##reg, \
  43                                         .mask_offset = mode_offset, \
  44                                         .mask = mode,
  45
  46 #define PULL_REG_7XX(reg, bit, status)  .pull_name = "OMAP7XX_IO_CONF_"#reg, \
  47                                         .pull_reg = OMAP7XX_IO_CONF_##reg, \
  48                                         .pull_bit = bit, \
  49                                         .pull_val = status,
  50
  51 #else
  52
  53 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
  54                                         .mask_offset = mode_offset, \
  55                                         .mask = mode,
  56
  57 #define PULL_REG(reg, bit, status)      .pull_reg = PULL_DWN_CTRL_##reg, \
  58                                         .pull_bit = bit, \
  59                                         .pull_val = status,
  60
  61 #define PU_PD_REG(reg, status)          .pu_pd_reg = PU_PD_SEL_##reg, \
  62                                         .pu_pd_val = status,
  63
  64 #define MUX_REG_7XX(reg, mode_offset, mode) \
  65                                         .mux_reg = OMAP7XX_IO_CONF_##reg, \
  66                                         .mask_offset = mode_offset, \
  67                                         .mask = mode,
  68
  69 #define PULL_REG_7XX(reg, bit, status)  .pull_reg = OMAP7XX_IO_CONF_##reg, \
  70                                         .pull_bit = bit, \
  71                                         .pull_val = status,
  72
  73 #endif /* CONFIG_OMAP_MUX_DEBUG */
  74
  75 #define MUX_CFG(desc, mux_reg, mode_offset, mode,       \
  76                 pull_reg, pull_bit, pull_status,        \
  77                 pu_pd_reg, pu_pd_status, debug_status)  \
  78 {                                                       \
  79         .name =  desc,                                  \
  80         .debug = debug_status,                          \
  81         MUX_REG(mux_reg, mode_offset, mode)             \
  82         PULL_REG(pull_reg, pull_bit, pull_status)       \
  83         PU_PD_REG(pu_pd_reg, pu_pd_status)              \
  84 },
  85
  86
  87 /*
  88  * OMAP730/850 has a slightly different config for the pin mux.
  89  * - config regs are the OMAP7XX_IO_CONF_x regs (see omap7xx.h) regs and
  90  *   not the FUNC_MUX_CTRL_x regs from hardware.h
  91  * - for pull-up/down, only has one enable bit which is in the same register
  92  *   as mux config
  93  */
  94 #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode,   \
  95                    pull_bit, pull_status, debug_status)\
  96 {                                                       \
  97         .name =  desc,                                  \
  98         .debug = debug_status,                          \
  99         MUX_REG_7XX(mux_reg, mode_offset, mode)         \
 100         PULL_REG_7XX(mux_reg, pull_bit, pull_status)    \
 101         PU_PD_REG(NA, 0)                \
 102 },
 103
 104 struct pin_config {
 105         char                    *name;
 106         const unsigned int      mux_reg;
 107         unsigned char           debug;
 108
 109         const unsigned char mask_offset;
 110         const unsigned char mask;
 111
 112         const char *pull_name;
 113         const unsigned int pull_reg;
 114         const unsigned char pull_val;
 115         const unsigned char pull_bit;
 116
 117         const char *pu_pd_name;
 118         const unsigned int pu_pd_reg;
 119         const unsigned char pu_pd_val;
 120
 121 #if     defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
 122         const char *mux_reg_name;
 123 #endif
 124
 125 };
 126
 127 enum omap7xx_index {
 128         /* OMAP 730 keyboard */
 129         E2_7XX_KBR0,
 130         J7_7XX_KBR1,
 131         E1_7XX_KBR2,
 132         F3_7XX_KBR3,
 133         D2_7XX_KBR4,
 134         C2_7XX_KBC0,
 135         D3_7XX_KBC1,
 136         E4_7XX_KBC2,
 137         F4_7XX_KBC3,
 138         E3_7XX_KBC4,
 139
 140         /* USB */
 141         AA17_7XX_USB_DM,
 142         W16_7XX_USB_PU_EN,
 143         W17_7XX_USB_VBUSI,
 144         W18_7XX_USB_DMCK_OUT,
 145         W19_7XX_USB_DCRST,
 146
 147         /* MMC */
 148         MMC_7XX_CMD,
 149         MMC_7XX_CLK,
 150         MMC_7XX_DAT0,
 151
 152         /* I2C */
 153         I2C_7XX_SCL,
 154         I2C_7XX_SDA,
 155
 156         /* SPI */
 157         SPI_7XX_1,
 158         SPI_7XX_2,
 159         SPI_7XX_3,
 160         SPI_7XX_4,
 161         SPI_7XX_5,
 162         SPI_7XX_6,
 163
 164         /* UART */
 165         UART_7XX_1,
 166         UART_7XX_2,
 167 };
 168
 169 enum omap1xxx_index {
 170         /* UART1 (BT_UART_GATING)*/
 171         UART1_TX = 0,
 172         UART1_RTS,
 173
 174         /* UART2 (COM_UART_GATING)*/
 175         UART2_TX,
 176         UART2_RX,
 177         UART2_CTS,
 178         UART2_RTS,
 179
 180         /* UART3 (GIGA_UART_GATING) */
 181         UART3_TX,
 182         UART3_RX,
 183         UART3_CTS,
 184         UART3_RTS,
 185         UART3_CLKREQ,
 186         UART3_BCLK,     /* 12MHz clock out */
 187         Y15_1610_UART3_RTS,
 188
 189         /* PWT & PWL */
 190         PWT,
 191         PWL,
 192
 193         /* USB master generic */
 194         R18_USB_VBUS,
 195         R18_1510_USB_GPIO0,
 196         W4_USB_PUEN,
 197         W4_USB_CLKO,
 198         W4_USB_HIGHZ,
 199         W4_GPIO58,
 200
 201         /* USB1 master */
 202         USB1_SUSP,
 203         USB1_SEO,
 204         W13_1610_USB1_SE0,
 205         USB1_TXEN,
 206         USB1_TXD,
 207         USB1_VP,
 208         USB1_VM,
 209         USB1_RCV,
 210         USB1_SPEED,
 211         R13_1610_USB1_SPEED,
 212         R13_1710_USB1_SE0,
 213
 214         /* USB2 master */
 215         USB2_SUSP,
 216         USB2_VP,
 217         USB2_TXEN,
 218         USB2_VM,
 219         USB2_RCV,
 220         USB2_SEO,
 221         USB2_TXD,
 222
 223         /* OMAP-1510 GPIO */
 224         R18_1510_GPIO0,
 225         R19_1510_GPIO1,
 226         M14_1510_GPIO2,
 227
 228         /* OMAP1610 GPIO */
 229         P18_1610_GPIO3,
 230         Y15_1610_GPIO17,
 231
 232         /* OMAP-1710 GPIO */
 233         R18_1710_GPIO0,
 234         V2_1710_GPIO10,
 235         N21_1710_GPIO14,
 236         W15_1710_GPIO40,
 237
 238         /* MPUIO */
 239         MPUIO2,
 240         N15_1610_MPUIO2,
 241         MPUIO4,
 242         MPUIO5,
 243         T20_1610_MPUIO5,
 244         W11_1610_MPUIO6,
 245         V10_1610_MPUIO7,
 246         W11_1610_MPUIO9,
 247         V10_1610_MPUIO10,
 248         W10_1610_MPUIO11,
 249         E20_1610_MPUIO13,
 250         U20_1610_MPUIO14,
 251         E19_1610_MPUIO15,
 252
 253         /* MCBSP2 */
 254         MCBSP2_CLKR,
 255         MCBSP2_CLKX,
 256         MCBSP2_DR,
 257         MCBSP2_DX,
 258         MCBSP2_FSR,
 259         MCBSP2_FSX,
 260
 261         /* MCBSP3 */
 262         MCBSP3_CLKX,
 263
 264         /* Misc ballouts */
 265         BALLOUT_V8_ARMIO3,
 266         N20_HDQ,
 267
 268         /* OMAP-1610 MMC2 */
 269         W8_1610_MMC2_DAT0,
 270         V8_1610_MMC2_DAT1,
 271         W15_1610_MMC2_DAT2,
 272         R10_1610_MMC2_DAT3,
 273         Y10_1610_MMC2_CLK,
 274         Y8_1610_MMC2_CMD,
 275         V9_1610_MMC2_CMDDIR,
 276         V5_1610_MMC2_DATDIR0,
 277         W19_1610_MMC2_DATDIR1,
 278         R18_1610_MMC2_CLKIN,
 279
 280         /* OMAP-1610 External Trace Interface */
 281         M19_1610_ETM_PSTAT0,
 282         L15_1610_ETM_PSTAT1,
 283         L18_1610_ETM_PSTAT2,
 284         L19_1610_ETM_D0,
 285         J19_1610_ETM_D6,
 286         J18_1610_ETM_D7,
 287
 288         /* OMAP16XX GPIO */
 289         P20_1610_GPIO4,
 290         V9_1610_GPIO7,
 291         W8_1610_GPIO9,
 292         N20_1610_GPIO11,
 293         N19_1610_GPIO13,
 294         P10_1610_GPIO22,
 295         V5_1610_GPIO24,
 296         AA20_1610_GPIO_41,
 297         W19_1610_GPIO48,
 298         M7_1610_GPIO62,
 299         V14_16XX_GPIO37,
 300         R9_16XX_GPIO18,
 301         L14_16XX_GPIO49,
 302
 303         /* OMAP-1610 uWire */
 304         V19_1610_UWIRE_SCLK,
 305         U18_1610_UWIRE_SDI,
 306         W21_1610_UWIRE_SDO,
 307         N14_1610_UWIRE_CS0,
 308         P15_1610_UWIRE_CS3,
 309         N15_1610_UWIRE_CS1,
 310
 311         /* OMAP-1610 SPI */
 312         U19_1610_SPIF_SCK,
 313         U18_1610_SPIF_DIN,
 314         P20_1610_SPIF_DIN,
 315         W21_1610_SPIF_DOUT,
 316         R18_1610_SPIF_DOUT,
 317         N14_1610_SPIF_CS0,
 318         N15_1610_SPIF_CS1,
 319         T19_1610_SPIF_CS2,
 320         P15_1610_SPIF_CS3,
 321
 322         /* OMAP-1610 Flash */
 323         L3_1610_FLASH_CS2B_OE,
 324         M8_1610_FLASH_CS2B_WE,
 325
 326         /* First MMC */
 327         MMC_CMD,
 328         MMC_DAT1,
 329         MMC_DAT2,
 330         MMC_DAT0,
 331         MMC_CLK,
 332         MMC_DAT3,
 333
 334         /* OMAP-1710 MMC CMDDIR and DATDIR0 */
 335         M15_1710_MMC_CLKI,
 336         P19_1710_MMC_CMDDIR,
 337         P20_1710_MMC_DATDIR0,
 338
 339         /* OMAP-1610 USB0 alternate pin configuration */
 340         W9_USB0_TXEN,
 341         AA9_USB0_VP,
 342         Y5_USB0_RCV,
 343         R9_USB0_VM,
 344         V6_USB0_TXD,
 345         W5_USB0_SE0,
 346         V9_USB0_SPEED,
 347         V9_USB0_SUSP,
 348
 349         /* USB2 */
 350         W9_USB2_TXEN,
 351         AA9_USB2_VP,
 352         Y5_USB2_RCV,
 353         R9_USB2_VM,
 354         V6_USB2_TXD,
 355         W5_USB2_SE0,
 356
 357         /* 16XX UART */
 358         R13_1610_UART1_TX,
 359         V14_16XX_UART1_RX,
 360         R14_1610_UART1_CTS,
 361         AA15_1610_UART1_RTS,
 362         R9_16XX_UART2_RX,
 363         L14_16XX_UART3_RX,
 364
 365         /* I2C OMAP-1610 */
 366         I2C_SCL,
 367         I2C_SDA,
 368
 369         /* Keypad */
 370         F18_1610_KBC0,
 371         D20_1610_KBC1,
 372         D19_1610_KBC2,
 373         E18_1610_KBC3,
 374         C21_1610_KBC4,
 375         G18_1610_KBR0,
 376         F19_1610_KBR1,
 377         H14_1610_KBR2,
 378         E20_1610_KBR3,
 379         E19_1610_KBR4,
 380         N19_1610_KBR5,
 381
 382         /* Power management */
 383         T20_1610_LOW_PWR,
 384
 385         /* MCLK Settings */
 386         V5_1710_MCLK_ON,
 387         V5_1710_MCLK_OFF,
 388         R10_1610_MCLK_ON,
 389         R10_1610_MCLK_OFF,
 390
 391         /* CompactFlash controller */
 392         P11_1610_CF_CD2,
 393         R11_1610_CF_IOIS16,
 394         V10_1610_CF_IREQ,
 395         W10_1610_CF_RESET,
 396         W11_1610_CF_CD1,
 397
 398         /* parallel camera */
 399         J15_1610_CAM_LCLK,
 400         J18_1610_CAM_D7,
 401         J19_1610_CAM_D6,
 402         J14_1610_CAM_D5,
 403         K18_1610_CAM_D4,
 404         K19_1610_CAM_D3,
 405         K15_1610_CAM_D2,
 406         K14_1610_CAM_D1,
 407         L19_1610_CAM_D0,
 408         L18_1610_CAM_VS,
 409         L15_1610_CAM_HS,
 410         M19_1610_CAM_RSTZ,
 411         Y15_1610_CAM_OUTCLK,
 412
 413         /* serial camera */
 414         H19_1610_CAM_EXCLK,
 415         Y12_1610_CCP_CLKP,
 416         W13_1610_CCP_CLKM,
 417         W14_1610_CCP_DATAP,
 418         Y14_1610_CCP_DATAM,
 419
 420 };
 421
 422 struct omap_mux_cfg {
 423         struct pin_config       *pins;
 424         unsigned long           size;
 425         int                     (*cfg_reg)(const struct pin_config *cfg);
 426 };
 427
 428 #ifdef  CONFIG_OMAP_MUX
 429 /* setup pin muxing in Linux */
 430 extern int omap1_mux_init(void);
 431 extern int omap_mux_register(struct omap_mux_cfg *);
 432 extern int omap_cfg_reg(unsigned long reg_cfg);
 433 #else
 434 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
 435 static inline int omap1_mux_init(void) { return 0; }
 436 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
 437 #endif
 438
 439 extern int omap2_mux_init(void);
 440
 441 #endif