1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap2/io.c
5 * OMAP2 I/O mapping code
7 * Copyright (C) 2005 Nokia Corporation
8 * Copyright (C) 2007-2009 Texas Instruments
11 * Juha Yrjola <juha.yrjola@nokia.com>
12 * Syed Khasim <x0khasim@ti.com>
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
20 #include <linux/clk.h>
23 #include <asm/mach/map.h>
25 #include <linux/omap-dma.h>
27 #include "omap_hwmod.h"
31 #include "powerdomain.h"
32 #include "clockdomain.h"
35 #include "clock2xxx.h"
36 #include "clock3xxx.h"
47 #include "prcm_mpu44xx.h"
48 #include "prminst44xx.h"
54 #include "omap-secure.h"
57 * omap_clk_soc_init: points to a function that does the SoC-specific
58 * clock initializations
60 static int (*omap_clk_soc_init
)(void);
63 * The machine specific code may provide the extra mapping besides the
64 * default mapping provided here.
67 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
68 static struct map_desc omap24xx_io_desc
[] __initdata
= {
70 .virtual = L3_24XX_VIRT
,
71 .pfn
= __phys_to_pfn(L3_24XX_PHYS
),
72 .length
= L3_24XX_SIZE
,
76 .virtual = L4_24XX_VIRT
,
77 .pfn
= __phys_to_pfn(L4_24XX_PHYS
),
78 .length
= L4_24XX_SIZE
,
83 #ifdef CONFIG_SOC_OMAP2420
84 static struct map_desc omap242x_io_desc
[] __initdata
= {
86 .virtual = DSP_MEM_2420_VIRT
,
87 .pfn
= __phys_to_pfn(DSP_MEM_2420_PHYS
),
88 .length
= DSP_MEM_2420_SIZE
,
92 .virtual = DSP_IPI_2420_VIRT
,
93 .pfn
= __phys_to_pfn(DSP_IPI_2420_PHYS
),
94 .length
= DSP_IPI_2420_SIZE
,
98 .virtual = DSP_MMU_2420_VIRT
,
99 .pfn
= __phys_to_pfn(DSP_MMU_2420_PHYS
),
100 .length
= DSP_MMU_2420_SIZE
,
107 #ifdef CONFIG_SOC_OMAP2430
108 static struct map_desc omap243x_io_desc
[] __initdata
= {
110 .virtual = L4_WK_243X_VIRT
,
111 .pfn
= __phys_to_pfn(L4_WK_243X_PHYS
),
112 .length
= L4_WK_243X_SIZE
,
116 .virtual = OMAP243X_GPMC_VIRT
,
117 .pfn
= __phys_to_pfn(OMAP243X_GPMC_PHYS
),
118 .length
= OMAP243X_GPMC_SIZE
,
122 .virtual = OMAP243X_SDRC_VIRT
,
123 .pfn
= __phys_to_pfn(OMAP243X_SDRC_PHYS
),
124 .length
= OMAP243X_SDRC_SIZE
,
128 .virtual = OMAP243X_SMS_VIRT
,
129 .pfn
= __phys_to_pfn(OMAP243X_SMS_PHYS
),
130 .length
= OMAP243X_SMS_SIZE
,
137 #ifdef CONFIG_ARCH_OMAP3
138 static struct map_desc omap34xx_io_desc
[] __initdata
= {
140 .virtual = L3_34XX_VIRT
,
141 .pfn
= __phys_to_pfn(L3_34XX_PHYS
),
142 .length
= L3_34XX_SIZE
,
146 .virtual = L4_34XX_VIRT
,
147 .pfn
= __phys_to_pfn(L4_34XX_PHYS
),
148 .length
= L4_34XX_SIZE
,
152 .virtual = OMAP34XX_GPMC_VIRT
,
153 .pfn
= __phys_to_pfn(OMAP34XX_GPMC_PHYS
),
154 .length
= OMAP34XX_GPMC_SIZE
,
158 .virtual = OMAP343X_SMS_VIRT
,
159 .pfn
= __phys_to_pfn(OMAP343X_SMS_PHYS
),
160 .length
= OMAP343X_SMS_SIZE
,
164 .virtual = OMAP343X_SDRC_VIRT
,
165 .pfn
= __phys_to_pfn(OMAP343X_SDRC_PHYS
),
166 .length
= OMAP343X_SDRC_SIZE
,
170 .virtual = L4_PER_34XX_VIRT
,
171 .pfn
= __phys_to_pfn(L4_PER_34XX_PHYS
),
172 .length
= L4_PER_34XX_SIZE
,
176 .virtual = L4_EMU_34XX_VIRT
,
177 .pfn
= __phys_to_pfn(L4_EMU_34XX_PHYS
),
178 .length
= L4_EMU_34XX_SIZE
,
184 #ifdef CONFIG_SOC_TI81XX
185 static struct map_desc omapti81xx_io_desc
[] __initdata
= {
187 .virtual = L4_34XX_VIRT
,
188 .pfn
= __phys_to_pfn(L4_34XX_PHYS
),
189 .length
= L4_34XX_SIZE
,
195 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
196 static struct map_desc omapam33xx_io_desc
[] __initdata
= {
198 .virtual = L4_34XX_VIRT
,
199 .pfn
= __phys_to_pfn(L4_34XX_PHYS
),
200 .length
= L4_34XX_SIZE
,
204 .virtual = L4_WK_AM33XX_VIRT
,
205 .pfn
= __phys_to_pfn(L4_WK_AM33XX_PHYS
),
206 .length
= L4_WK_AM33XX_SIZE
,
212 #ifdef CONFIG_ARCH_OMAP4
213 static struct map_desc omap44xx_io_desc
[] __initdata
= {
215 .virtual = L3_44XX_VIRT
,
216 .pfn
= __phys_to_pfn(L3_44XX_PHYS
),
217 .length
= L3_44XX_SIZE
,
221 .virtual = L4_44XX_VIRT
,
222 .pfn
= __phys_to_pfn(L4_44XX_PHYS
),
223 .length
= L4_44XX_SIZE
,
227 .virtual = L4_PER_44XX_VIRT
,
228 .pfn
= __phys_to_pfn(L4_PER_44XX_PHYS
),
229 .length
= L4_PER_44XX_SIZE
,
235 #ifdef CONFIG_SOC_OMAP5
236 static struct map_desc omap54xx_io_desc
[] __initdata
= {
238 .virtual = L3_54XX_VIRT
,
239 .pfn
= __phys_to_pfn(L3_54XX_PHYS
),
240 .length
= L3_54XX_SIZE
,
244 .virtual = L4_54XX_VIRT
,
245 .pfn
= __phys_to_pfn(L4_54XX_PHYS
),
246 .length
= L4_54XX_SIZE
,
250 .virtual = L4_WK_54XX_VIRT
,
251 .pfn
= __phys_to_pfn(L4_WK_54XX_PHYS
),
252 .length
= L4_WK_54XX_SIZE
,
256 .virtual = L4_PER_54XX_VIRT
,
257 .pfn
= __phys_to_pfn(L4_PER_54XX_PHYS
),
258 .length
= L4_PER_54XX_SIZE
,
264 #ifdef CONFIG_SOC_DRA7XX
265 static struct map_desc dra7xx_io_desc
[] __initdata
= {
267 .virtual = L4_CFG_MPU_DRA7XX_VIRT
,
268 .pfn
= __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS
),
269 .length
= L4_CFG_MPU_DRA7XX_SIZE
,
273 .virtual = L3_MAIN_SN_DRA7XX_VIRT
,
274 .pfn
= __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS
),
275 .length
= L3_MAIN_SN_DRA7XX_SIZE
,
279 .virtual = L4_PER1_DRA7XX_VIRT
,
280 .pfn
= __phys_to_pfn(L4_PER1_DRA7XX_PHYS
),
281 .length
= L4_PER1_DRA7XX_SIZE
,
285 .virtual = L4_PER2_DRA7XX_VIRT
,
286 .pfn
= __phys_to_pfn(L4_PER2_DRA7XX_PHYS
),
287 .length
= L4_PER2_DRA7XX_SIZE
,
291 .virtual = L4_PER3_DRA7XX_VIRT
,
292 .pfn
= __phys_to_pfn(L4_PER3_DRA7XX_PHYS
),
293 .length
= L4_PER3_DRA7XX_SIZE
,
297 .virtual = L4_CFG_DRA7XX_VIRT
,
298 .pfn
= __phys_to_pfn(L4_CFG_DRA7XX_PHYS
),
299 .length
= L4_CFG_DRA7XX_SIZE
,
303 .virtual = L4_WKUP_DRA7XX_VIRT
,
304 .pfn
= __phys_to_pfn(L4_WKUP_DRA7XX_PHYS
),
305 .length
= L4_WKUP_DRA7XX_SIZE
,
311 #ifdef CONFIG_SOC_OMAP2420
312 void __init
omap242x_map_io(void)
314 iotable_init(omap24xx_io_desc
, ARRAY_SIZE(omap24xx_io_desc
));
315 iotable_init(omap242x_io_desc
, ARRAY_SIZE(omap242x_io_desc
));
319 #ifdef CONFIG_SOC_OMAP2430
320 void __init
omap243x_map_io(void)
322 iotable_init(omap24xx_io_desc
, ARRAY_SIZE(omap24xx_io_desc
));
323 iotable_init(omap243x_io_desc
, ARRAY_SIZE(omap243x_io_desc
));
327 #ifdef CONFIG_ARCH_OMAP3
328 void __init
omap3_map_io(void)
330 iotable_init(omap34xx_io_desc
, ARRAY_SIZE(omap34xx_io_desc
));
334 #ifdef CONFIG_SOC_TI81XX
335 void __init
ti81xx_map_io(void)
337 iotable_init(omapti81xx_io_desc
, ARRAY_SIZE(omapti81xx_io_desc
));
341 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
342 void __init
am33xx_map_io(void)
344 iotable_init(omapam33xx_io_desc
, ARRAY_SIZE(omapam33xx_io_desc
));
348 #ifdef CONFIG_ARCH_OMAP4
349 void __init
omap4_map_io(void)
351 iotable_init(omap44xx_io_desc
, ARRAY_SIZE(omap44xx_io_desc
));
352 omap_barriers_init();
356 #ifdef CONFIG_SOC_OMAP5
357 void __init
omap5_map_io(void)
359 iotable_init(omap54xx_io_desc
, ARRAY_SIZE(omap54xx_io_desc
));
360 omap_barriers_init();
364 #ifdef CONFIG_SOC_DRA7XX
365 void __init
dra7xx_map_io(void)
367 iotable_init(dra7xx_io_desc
, ARRAY_SIZE(dra7xx_io_desc
));
368 omap_barriers_init();
372 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
374 * Sets the CORE DPLL3 M2 divider to the same value that it's at
375 * currently. This has the effect of setting the SDRC SDRAM AC timing
376 * registers to the values currently defined by the kernel. Currently
377 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
378 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
379 * or passes along the return value of clk_set_rate().
381 static int __init
_omap2_init_reprogram_sdrc(void)
383 struct clk
*dpll3_m2_ck
;
387 if (!cpu_is_omap34xx())
390 dpll3_m2_ck
= clk_get(NULL
, "dpll3_m2_ck");
391 if (IS_ERR(dpll3_m2_ck
))
394 rate
= clk_get_rate(dpll3_m2_ck
);
395 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate
);
396 v
= clk_set_rate(dpll3_m2_ck
, rate
);
398 pr_err("dpll3_m2_clk rate change failed: %d\n", v
);
400 clk_put(dpll3_m2_ck
);
405 static int _set_hwmod_postsetup_state(struct omap_hwmod
*oh
, void *data
)
407 return omap_hwmod_set_postsetup_state(oh
, *(u8
*)data
);
410 static void __init __maybe_unused
omap_hwmod_init_postsetup(void)
412 u8 postsetup_state
= _HWMOD_STATE_DEFAULT
;
414 /* Set the default postsetup state for all hwmods */
415 omap_hwmod_for_each(_set_hwmod_postsetup_state
, &postsetup_state
);
418 #ifdef CONFIG_SOC_OMAP2420
419 void __init
omap2420_init_early(void)
421 omap2_set_globals_tap(OMAP242X_CLASS
, OMAP2_L4_IO_ADDRESS(0x48014000));
422 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE
),
423 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE
));
424 omap2_control_base_init();
425 omap2xxx_check_revision();
426 omap2_prcm_base_init();
427 omap2xxx_voltagedomains_init();
428 omap242x_powerdomains_init();
429 omap242x_clockdomains_init();
430 omap2420_hwmod_init();
431 omap_hwmod_init_postsetup();
432 omap_clk_soc_init
= omap2420_dt_clk_init
;
433 rate_table
= omap2420_rate_table
;
436 void __init
omap2420_init_late(void)
438 omap_pm_soc_init
= omap2_pm_init
;
442 #ifdef CONFIG_SOC_OMAP2430
443 void __init
omap2430_init_early(void)
445 omap2_set_globals_tap(OMAP243X_CLASS
, OMAP2_L4_IO_ADDRESS(0x4900a000));
446 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE
),
447 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE
));
448 omap2_control_base_init();
449 omap2xxx_check_revision();
450 omap2_prcm_base_init();
451 omap2xxx_voltagedomains_init();
452 omap243x_powerdomains_init();
453 omap243x_clockdomains_init();
454 omap2430_hwmod_init();
455 omap_hwmod_init_postsetup();
456 omap_clk_soc_init
= omap2430_dt_clk_init
;
457 rate_table
= omap2430_rate_table
;
460 void __init
omap2430_init_late(void)
462 omap_pm_soc_init
= omap2_pm_init
;
467 * Currently only board-omap3beagle.c should call this because of the
468 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
470 #ifdef CONFIG_ARCH_OMAP3
471 void __init
omap3_init_early(void)
473 omap2_set_globals_tap(OMAP343X_CLASS
, OMAP2_L4_IO_ADDRESS(0x4830A000));
474 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE
),
475 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE
));
476 omap2_control_base_init();
477 omap3xxx_check_revision();
478 omap3xxx_check_features();
479 omap2_prcm_base_init();
480 omap3xxx_voltagedomains_init();
481 omap3xxx_powerdomains_init();
482 omap3xxx_clockdomains_init();
483 omap3xxx_hwmod_init();
484 omap_hwmod_init_postsetup();
488 void __init
omap3430_init_early(void)
491 omap_clk_soc_init
= omap3430_dt_clk_init
;
494 void __init
omap35xx_init_early(void)
497 omap_clk_soc_init
= omap3430_dt_clk_init
;
500 void __init
omap3630_init_early(void)
503 omap_clk_soc_init
= omap3630_dt_clk_init
;
506 void __init
am35xx_init_early(void)
509 omap_clk_soc_init
= am35xx_dt_clk_init
;
512 void __init
omap3_init_late(void)
514 omap_pm_soc_init
= omap3_pm_init
;
517 void __init
ti81xx_init_late(void)
519 omap_pm_soc_init
= omap_pm_nop_init
;
523 #ifdef CONFIG_SOC_TI81XX
524 void __init
ti814x_init_early(void)
526 omap2_set_globals_tap(TI814X_CLASS
,
527 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE
));
528 omap2_control_base_init();
529 omap3xxx_check_revision();
530 ti81xx_check_features();
531 omap2_prcm_base_init();
532 omap3xxx_voltagedomains_init();
533 omap3xxx_powerdomains_init();
534 ti814x_clockdomains_init();
536 omap_hwmod_init_postsetup();
537 omap_clk_soc_init
= dm814x_dt_clk_init
;
541 void __init
ti816x_init_early(void)
543 omap2_set_globals_tap(TI816X_CLASS
,
544 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE
));
545 omap2_control_base_init();
546 omap3xxx_check_revision();
547 ti81xx_check_features();
548 omap2_prcm_base_init();
549 omap3xxx_voltagedomains_init();
550 omap3xxx_powerdomains_init();
551 ti816x_clockdomains_init();
553 omap_hwmod_init_postsetup();
554 omap_clk_soc_init
= dm816x_dt_clk_init
;
559 #ifdef CONFIG_SOC_AM33XX
560 void __init
am33xx_init_early(void)
562 omap2_set_globals_tap(AM335X_CLASS
,
563 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE
));
564 omap2_control_base_init();
565 omap3xxx_check_revision();
566 am33xx_check_features();
567 omap2_prcm_base_init();
568 am33xx_powerdomains_init();
569 am33xx_clockdomains_init();
570 omap_clk_soc_init
= am33xx_dt_clk_init
;
574 void __init
am33xx_init_late(void)
576 omap_pm_soc_init
= amx3_common_pm_init
;
580 #ifdef CONFIG_SOC_AM43XX
581 void __init
am43xx_init_early(void)
583 omap2_set_globals_tap(AM335X_CLASS
,
584 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE
));
585 omap2_control_base_init();
586 omap3xxx_check_revision();
587 am33xx_check_features();
588 omap2_prcm_base_init();
589 am43xx_powerdomains_init();
590 am43xx_clockdomains_init();
591 omap_l2_cache_init();
592 omap_clk_soc_init
= am43xx_dt_clk_init
;
596 void __init
am43xx_init_late(void)
598 omap_pm_soc_init
= amx3_common_pm_init
;
602 #ifdef CONFIG_ARCH_OMAP4
603 void __init
omap4430_init_early(void)
605 omap2_set_globals_tap(OMAP443X_CLASS
,
606 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE
));
607 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE
));
608 omap2_control_base_init();
609 omap4xxx_check_revision();
610 omap4xxx_check_features();
611 omap2_prcm_base_init();
612 omap4_sar_ram_init();
613 omap4_mpuss_early_init();
614 omap4_pm_init_early();
615 omap44xx_voltagedomains_init();
616 omap44xx_powerdomains_init();
617 omap44xx_clockdomains_init();
618 omap44xx_hwmod_init();
619 omap_hwmod_init_postsetup();
620 omap_l2_cache_init();
621 omap_clk_soc_init
= omap4xxx_dt_clk_init
;
625 void __init
omap4430_init_late(void)
627 omap_pm_soc_init
= omap4_pm_init
;
631 #ifdef CONFIG_SOC_OMAP5
632 void __init
omap5_init_early(void)
634 omap2_set_globals_tap(OMAP54XX_CLASS
,
635 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE
));
636 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE
));
637 omap2_control_base_init();
638 omap2_prcm_base_init();
639 omap5xxx_check_revision();
640 omap4_sar_ram_init();
641 omap4_mpuss_early_init();
642 omap4_pm_init_early();
643 omap54xx_voltagedomains_init();
644 omap54xx_powerdomains_init();
645 omap54xx_clockdomains_init();
646 omap54xx_hwmod_init();
647 omap_hwmod_init_postsetup();
648 omap_clk_soc_init
= omap5xxx_dt_clk_init
;
652 void __init
omap5_init_late(void)
654 omap_pm_soc_init
= omap4_pm_init
;
658 #ifdef CONFIG_SOC_DRA7XX
659 void __init
dra7xx_init_early(void)
661 omap2_set_globals_tap(DRA7XX_CLASS
,
662 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE
));
663 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE
));
664 omap2_control_base_init();
665 omap4_pm_init_early();
666 omap2_prcm_base_init();
667 dra7xxx_check_revision();
668 dra7xx_powerdomains_init();
669 dra7xx_clockdomains_init();
671 omap_hwmod_init_postsetup();
672 omap_clk_soc_init
= dra7xx_dt_clk_init
;
676 void __init
dra7xx_init_late(void)
678 omap_pm_soc_init
= omap4_pm_init
;
683 void __init
omap_sdrc_init(struct omap_sdrc_params
*sdrc_cs0
,
684 struct omap_sdrc_params
*sdrc_cs1
)
688 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
689 omap2_sdrc_init(sdrc_cs0
, sdrc_cs1
);
690 _omap2_init_reprogram_sdrc();
694 int __init
omap_clk_init(void)
698 if (!omap_clk_soc_init
)
701 ti_clk_init_features();
703 omap2_clk_setup_ll_ops();
705 ret
= omap_control_init();
709 ret
= omap_prcm_init();
715 ti_dt_clk_init_retry_clks();
717 ti_dt_clockdomains_setup();
719 ret
= omap_clk_soc_init();