mm: make wait_on_page_writeback() wait for multiple pending writebacks
[linux/fpc-iii.git] / arch / arm / mach-pxa / palmz72.h
blob40f3f998798318d8482e24aea5dfde6a66f29fa5
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * GPIOs and interrupts for Palm Zire72 Handheld Computer
5 * Authors: Alex Osborne <bobofdoom@gmail.com>
6 * Jan Herman <2hp@seznam.cz>
7 * Sergey Lapin <slapin@ossfans.org>
8 */
10 #ifndef _INCLUDE_PALMZ72_H_
11 #define _INCLUDE_PALMZ72_H_
13 /* Power and control */
14 #define GPIO_NR_PALMZ72_GPIO_RESET 1
15 #define GPIO_NR_PALMZ72_POWER_DETECT 0
17 /* SD/MMC */
18 #define GPIO_NR_PALMZ72_SD_DETECT_N 14
19 #define GPIO_NR_PALMZ72_SD_POWER_N 98
20 #define GPIO_NR_PALMZ72_SD_RO 115
22 /* Touchscreen */
23 #define GPIO_NR_PALMZ72_WM9712_IRQ 27
25 /* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
26 #define GPIO_NR_PALMZ72_IR_DISABLE 49
28 /* USB */
29 #define GPIO_NR_PALMZ72_USB_DETECT_N 15
30 #define GPIO_NR_PALMZ72_USB_PULLUP 95
32 /* LCD/Backlight */
33 #define GPIO_NR_PALMZ72_BL_POWER 20
34 #define GPIO_NR_PALMZ72_LCD_POWER 96
36 /* LED */
37 #define GPIO_NR_PALMZ72_LED_GREEN 88
39 /* Bluetooth */
40 #define GPIO_NR_PALMZ72_BT_POWER 17
41 #define GPIO_NR_PALMZ72_BT_RESET 83
43 /* Camera */
44 #define GPIO_NR_PALMZ72_CAM_PWDN 56
45 #define GPIO_NR_PALMZ72_CAM_RESET 57
46 #define GPIO_NR_PALMZ72_CAM_POWER 91
48 /** Initial values **/
50 /* Battery */
51 #define PALMZ72_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
52 #define PALMZ72_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
53 #define PALMZ72_BAT_MAX_CURRENT 0 /* unknown */
54 #define PALMZ72_BAT_MIN_CURRENT 0 /* unknown */
55 #define PALMZ72_BAT_MAX_CHARGE 1 /* unknown */
56 #define PALMZ72_BAT_MIN_CHARGE 1 /* unknown */
57 #define PALMZ72_MAX_LIFE_MINS 360 /* on-life in minutes */
59 /* Backlight */
60 #define PALMZ72_MAX_INTENSITY 0xFE
61 #define PALMZ72_DEFAULT_INTENSITY 0x7E
62 #define PALMZ72_LIMIT_MASK 0x7F
63 #define PALMZ72_PRESCALER 0x3F
64 #define PALMZ72_PERIOD_NS 3500
66 #ifdef CONFIG_PM
67 struct palmz72_resume_info {
68 u32 magic0; /* 0x0 */
69 u32 magic1; /* 0x4 */
70 u32 resume_addr; /* 0x8 */
71 u32 pad[11]; /* 0xc..0x37 */
72 u32 arm_control; /* 0x38 */
73 u32 aux_control; /* 0x3c */
74 u32 ttb; /* 0x40 */
75 u32 domain_access; /* 0x44 */
76 u32 process_id; /* 0x48 */
78 #endif
79 #endif