1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/plat-pxa/include/plat/mfp.h
5 * Common Multi-Function Pin Definitions
7 * Copyright (C) 2007 Marvell International Ltd.
9 * 2007-8-21: eric miao <eric.miao@marvell.com>
13 #ifndef __ASM_PLAT_MFP_H
14 #define __ASM_PLAT_MFP_H
16 #define mfp_to_gpio(m) ((m) % 256)
18 /* list of all the configurable MFP pins */
216 MFP_PIN_GPIO255
= 255,
243 MFP_PIN_DF_nADV1_ALE
,
248 MFP_PIN_DF_nADV2_ALE
,
277 MFP_PIN_DF_nCS0_SM_nCS2
,
278 MFP_PIN_DF_nCS1_SM_nCS3
,
283 MFP_PIN_DF_CLE_SM_OEn
,
284 MFP_PIN_DF_ALE_SM_WEn
,
308 /* additional pins on PXA930 */
316 /* additional pins on MMP2 */
327 * a possible MFP configuration is represented by a 32-bit integer
329 * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
330 * bit 10..12 - Alternate Function Selection
331 * bit 13..15 - Drive Strength
332 * bit 16..18 - Low Power Mode State
333 * bit 19..20 - Low Power Mode Edge Detection
334 * bit 21..22 - Run Mode Pull State
336 * to facilitate the definition, the following macros are provided
338 * MFP_CFG_DEFAULT - default MFP configuration value, with
339 * alternate function = 0,
340 * drive strength = fast 3mA (MFP_DS03X)
341 * low power mode = default
342 * edge detection = none
344 * MFP_CFG - default MFPR value with alternate function
345 * MFP_CFG_DRV - default MFPR value with alternate function and
347 * MFP_CFG_LPM - default MFPR value with alternate function and
349 * MFP_CFG_X - default MFPR value with alternate function,
350 * pin drive strength and low power mode
353 typedef unsigned long mfp_cfg_t
;
355 #define MFP_PIN(x) ((x) & 0x3ff)
357 #define MFP_AF0 (0x0 << 10)
358 #define MFP_AF1 (0x1 << 10)
359 #define MFP_AF2 (0x2 << 10)
360 #define MFP_AF3 (0x3 << 10)
361 #define MFP_AF4 (0x4 << 10)
362 #define MFP_AF5 (0x5 << 10)
363 #define MFP_AF6 (0x6 << 10)
364 #define MFP_AF7 (0x7 << 10)
365 #define MFP_AF_MASK (0x7 << 10)
366 #define MFP_AF(x) (((x) >> 10) & 0x7)
368 #define MFP_DS01X (0x0 << 13)
369 #define MFP_DS02X (0x1 << 13)
370 #define MFP_DS03X (0x2 << 13)
371 #define MFP_DS04X (0x3 << 13)
372 #define MFP_DS06X (0x4 << 13)
373 #define MFP_DS08X (0x5 << 13)
374 #define MFP_DS10X (0x6 << 13)
375 #define MFP_DS13X (0x7 << 13)
376 #define MFP_DS_MASK (0x7 << 13)
377 #define MFP_DS(x) (((x) >> 13) & 0x7)
379 #define MFP_LPM_DEFAULT (0x0 << 16)
380 #define MFP_LPM_DRIVE_LOW (0x1 << 16)
381 #define MFP_LPM_DRIVE_HIGH (0x2 << 16)
382 #define MFP_LPM_PULL_LOW (0x3 << 16)
383 #define MFP_LPM_PULL_HIGH (0x4 << 16)
384 #define MFP_LPM_FLOAT (0x5 << 16)
385 #define MFP_LPM_INPUT (0x6 << 16)
386 #define MFP_LPM_STATE_MASK (0x7 << 16)
387 #define MFP_LPM_STATE(x) (((x) >> 16) & 0x7)
389 #define MFP_LPM_EDGE_NONE (0x0 << 19)
390 #define MFP_LPM_EDGE_RISE (0x1 << 19)
391 #define MFP_LPM_EDGE_FALL (0x2 << 19)
392 #define MFP_LPM_EDGE_BOTH (0x3 << 19)
393 #define MFP_LPM_EDGE_MASK (0x3 << 19)
394 #define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3)
396 #define MFP_PULL_NONE (0x0 << 21)
397 #define MFP_PULL_LOW (0x1 << 21)
398 #define MFP_PULL_HIGH (0x2 << 21)
399 #define MFP_PULL_BOTH (0x3 << 21)
400 #define MFP_PULL_FLOAT (0x4 << 21)
401 #define MFP_PULL_MASK (0x7 << 21)
402 #define MFP_PULL(x) (((x) >> 21) & 0x7)
404 #define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\
405 MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
407 #define MFP_CFG(pin, af) \
408 ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
409 (MFP_PIN(MFP_PIN_##pin) | MFP_##af))
411 #define MFP_CFG_DRV(pin, af, drv) \
412 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
413 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
415 #define MFP_CFG_LPM(pin, af, lpm) \
416 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
417 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
419 #define MFP_CFG_X(pin, af, drv, lpm) \
420 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
421 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
423 #if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP)
425 * each MFP pin will have a MFPR register, since the offset of the
426 * register varies between processors, the processor specific code
427 * should initialize the pin offsets by mfp_init()
429 * mfp_init_base() - accepts a virtual base for all MFPR registers and
430 * initialize the MFP table to a default state
432 * mfp_init_addr() - accepts a table of "mfp_addr_map" structure, which
433 * represents a range of MFP pins from "start" to "end", with the offset
434 * beginning at "offset", to define a single pin, let "end" = -1.
438 * MFP_ADDR_X() to define a range of pins
439 * MFP_ADDR() to define a single pin
440 * MFP_ADDR_END to signal the end of pin offset definitions
442 struct mfp_addr_map
{
445 unsigned long offset
;
448 #define MFP_ADDR_X(start, end, offset) \
449 { MFP_PIN_##start, MFP_PIN_##end, offset }
451 #define MFP_ADDR(pin, offset) \
452 { MFP_PIN_##pin, -1, offset }
454 #define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
456 void __init
mfp_init_base(void __iomem
*mfpr_base
);
457 void __init
mfp_init_addr(struct mfp_addr_map
*map
);
460 * mfp_{read, write}() - for direct read/write access to the MFPR register
461 * mfp_config() - for configuring a group of MFPR registers
462 * mfp_config_lpm() - configuring all low power MFPR registers for suspend
463 * mfp_config_run() - configuring all run time MFPR registers after resume
465 unsigned long mfp_read(int mfp
);
466 void mfp_write(int mfp
, unsigned long mfpr_val
);
467 void mfp_config(unsigned long *mfp_cfgs
, int num
);
468 void mfp_config_run(void);
469 void mfp_config_lpm(void);
470 #endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */
472 #endif /* __ASM_PLAT_MFP_H */