2 * CE4100 on Falcon Falls
4 * (c) Copyright 2010 Intel Corporation
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License.
12 model = "intel,falconfalls";
13 compatible = "intel,falconfalls";
23 compatible = "intel,ce4100";
32 compatible = "intel,ce4100-cp";
35 ioapic1: interrupt-controller@fec00000 {
36 #interrupt-cells = <2>;
37 compatible = "intel,ce4100-ioapic";
39 reg = <0xfec00000 0x1000>;
43 compatible = "intel,ce4100-hpet";
44 reg = <0xfed00000 0x200>;
47 lapic0: interrupt-controller@fee00000 {
48 compatible = "intel,ce4100-lapic";
49 reg = <0xfee00000 0x1000>;
55 compatible = "intel,ce4100-pci", "pci";
58 ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
59 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
60 0x0000000 0 0x0 0x0 0 0x100>;
62 /* Secondary IO-APIC */
63 ioapic2: interrupt-controller@0,1 {
64 #interrupt-cells = <2>;
65 compatible = "intel,ce4100-ioapic";
67 reg = <0x100 0x0 0x0 0x0 0x0>;
68 assigned-addresses = <0x02000000 0x0 0xbffff000 0x0 0x1000>;
74 compatible = "intel,ce4100-pci", "pci";
77 ranges = <0x2000000 0 0xdffe0000 0x2000000 0 0xdffe0000 0 0x1000>;
79 interrupt-parent = <&ioapic2>;
82 compatible = "pci8086,2e5b.2",
87 reg = <0x11000 0x0 0x0 0x0 0x0>;
92 compatible = "pci8086,2e5c.2",
97 reg = <0x11800 0x0 0x0 0x0 0x0>;
102 compatible = "pci8086,2e5d.2",
107 reg = <0x12000 0x0 0x0 0x0 0x0>;
112 compatible = "pci8086,2e5e.2",
117 reg = <0x12100 0x0 0x0 0x0 0x0>;
122 compatible = "pci8086,2e5f.2",
127 reg = <0x13000 0x0 0x0 0x0 0x0>;
132 compatible = "pci8086,2e5f.2",
137 reg = <0x13100 0x0 0x0 0x0 0x0>;
142 compatible = "pci8086,2e60.2",
147 reg = <0x13200 0x0 0x0 0x0 0x0>;
152 compatible = "pci8086,2e61.2",
157 reg = <0x14000 0x0 0x0 0x0 0x0>;
162 compatible = "pci8086,2e62.2",
167 reg = <0x14100 0x0 0x0 0x0 0x0>;
172 compatible = "pci8086,2e63.2",
177 reg = <0x14200 0x0 0x0 0x0 0x0>;
181 entertainment-encryption@9,0 {
182 compatible = "pci8086,2e64.2",
187 reg = <0x14800 0x0 0x0 0x0 0x0>;
192 compatible = "pci8086,2e65.2",
197 reg = <0x15000 0x0 0x0 0x0 0x0>;
201 compatible = "pci8086,2e66.2",
206 reg = <0x15800 0x0 0x0 0x0 0x0>;
211 compatible = "pci8086,2e67.2",
217 reg = <0x15900 0x0 0x0 0x0 0x0>;
223 #address-cells = <2>;
225 compatible = "pci8086,2e68.2",
230 reg = <0x15a00 0x0 0x0 0x0 0x0>;
232 ranges = <0 0 0x02000000 0 0xdffe0500 0x100
233 1 0 0x02000000 0 0xdffe0600 0x100
234 2 0 0x02000000 0 0xdffe0700 0x100>;
237 #address-cells = <1>;
239 compatible = "intel,ce4100-i2c-controller";
244 #address-cells = <1>;
246 compatible = "intel,ce4100-i2c-controller";
251 compatible = "ti,pcf8575";
258 #address-cells = <1>;
260 compatible = "intel,ce4100-i2c-controller";
265 compatible = "ti,pcf8575";
273 compatible = "pci8086,2e69.2",
278 reg = <0x15b00 0x0 0x0 0x0 0x0>;
283 #address-cells = <1>;
291 reg = <0x15c00 0x0 0x0 0x0 0x0>;
295 compatible = "ti,pcm1755";
297 spi-max-frequency = <115200>;
301 compatible = "ti,pcm1609a";
303 spi-max-frequency = <115200>;
307 compatible = "atmel,at93c46";
309 spi-max-frequency = <115200>;
314 compatible = "pci8086,2e6d.2",
319 reg = <0x15f00 0x0 0x0 0x0 0x0>;
323 compatible = "pci8086,2e6e.2",
328 reg = <0x16000 0x0 0x0 0x0 0x0>;
333 compatible = "pci8086,2e6f.2",
338 reg = <0x16100 0x0 0x0 0x0 0x0>;
343 compatible = "pci8086,2e70.2",
348 reg = <0x16800 0x0 0x0 0x0 0x0>;
353 compatible = "pci8086,2e70.2",
358 reg = <0x16900 0x0 0x0 0x0 0x0>;
363 compatible = "pci8086,2e71.0",
368 reg = <0x17000 0x0 0x0 0x0 0x0>;
373 compatible = "pci8086,701.1",
378 reg = <0x17800 0x0 0x0 0x0 0x0>;
382 entertainment-encryption@10,0 {
383 compatible = "pci8086,702.1",
388 reg = <0x18000 0x0 0x0 0x0 0x0>;
392 compatible = "pci8086,703.1",
397 reg = <0x18800 0x0 0x0 0x0 0x0>;
402 compatible = "pci8086,704.0",
407 reg = <0x19000 0x0 0x0 0x0 0x0>;
412 #address-cells = <2>;
415 ranges = <1 0 0 0 0 0x100>;
418 compatible = "intel,ce4100-rtc", "motorola,mc146818";
420 interrupt-parent = <&ioapic1>;