1 /* -*- linux-c -*- ------------------------------------------------------- *
3 * Copyright (C) 1991, 1992 Linus Torvalds
4 * Copyright 2007 rPath, Inc. - All Rights Reserved
6 * This file is part of the Linux kernel, and is made available under
7 * the terms of the GNU General Public License version 2.
9 * ----------------------------------------------------------------------- */
12 * Check for obligatory CPU features and abort if the features are not
13 * present. This code should be compilable as 16-, 32- or 64-bit
14 * code, so be very careful with types and inline assembly.
16 * This code should not contain any messages; that requires an
19 * As written, this code is not safe for inclusion into the kernel
20 * proper (after FPU initialization, in particular).
27 #include <linux/types.h>
28 #include <asm/cpufeature.h>
29 #include <asm/processor-flags.h>
30 #include <asm/required-features.h>
31 #include <asm/msr-index.h>
33 struct cpu_features cpu
;
34 static u32 cpu_vendor
[3];
35 static u32 err_flags
[NCAPINTS
];
37 static const int req_level
= CONFIG_X86_MINIMUM_CPU_FAMILY
;
39 static const u32 req_flags
[NCAPINTS
] =
51 #define A32(a, b, c, d) (((d) << 24)+((c) << 16)+((b) << 8)+(a))
53 static int is_amd(void)
55 return cpu_vendor
[0] == A32('A', 'u', 't', 'h') &&
56 cpu_vendor
[1] == A32('e', 'n', 't', 'i') &&
57 cpu_vendor
[2] == A32('c', 'A', 'M', 'D');
60 static int is_centaur(void)
62 return cpu_vendor
[0] == A32('C', 'e', 'n', 't') &&
63 cpu_vendor
[1] == A32('a', 'u', 'r', 'H') &&
64 cpu_vendor
[2] == A32('a', 'u', 'l', 's');
67 static int is_transmeta(void)
69 return cpu_vendor
[0] == A32('G', 'e', 'n', 'u') &&
70 cpu_vendor
[1] == A32('i', 'n', 'e', 'T') &&
71 cpu_vendor
[2] == A32('M', 'x', '8', '6');
74 static int has_fpu(void)
76 u16 fcw
= -1, fsw
= -1;
79 asm("movl %%cr0,%0" : "=r" (cr0
));
80 if (cr0
& (X86_CR0_EM
|X86_CR0_TS
)) {
81 cr0
&= ~(X86_CR0_EM
|X86_CR0_TS
);
82 asm volatile("movl %0,%%cr0" : : "r" (cr0
));
85 asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
86 : "+m" (fsw
), "+m" (fcw
));
88 return fsw
== 0 && (fcw
& 0x103f) == 0x003f;
91 static int has_eflag(u32 mask
)
105 : "=&r" (f0
), "=&r" (f1
)
108 return !!((f0
^f1
) & mask
);
111 static void get_flags(void)
113 u32 max_intel_level
, max_amd_level
;
117 set_bit(X86_FEATURE_FPU
, cpu
.flags
);
119 if (has_eflag(X86_EFLAGS_ID
)) {
121 : "=a" (max_intel_level
),
122 "=b" (cpu_vendor
[0]),
123 "=d" (cpu_vendor
[1]),
127 if (max_intel_level
>= 0x00000001 &&
128 max_intel_level
<= 0x0000ffff) {
135 cpu
.level
= (tfms
>> 8) & 15;
136 cpu
.model
= (tfms
>> 4) & 15;
138 cpu
.model
+= ((tfms
>> 16) & 0xf) << 4;
142 : "=a" (max_amd_level
)
144 : "ebx", "ecx", "edx");
146 if (max_amd_level
>= 0x80000001 &&
147 max_amd_level
<= 0x8000ffff) {
148 u32 eax
= 0x80000001;
158 /* Returns a bitmask of which words we have error bits in */
159 static int check_flags(void)
165 for (i
= 0; i
< NCAPINTS
; i
++) {
166 err_flags
[i
] = req_flags
[i
] & ~cpu
.flags
[i
];
175 * Returns -1 on error.
177 * *cpu_level is set to the current CPU level; *req_level to the required
178 * level. x86-64 is considered level 64 for this purpose.
180 * *err_flags_ptr is set to the flags error array if there are flags missing.
182 int check_cpu(int *cpu_level_ptr
, int *req_level_ptr
, u32
**err_flags_ptr
)
186 memset(&cpu
.flags
, 0, sizeof cpu
.flags
);
189 if (has_eflag(X86_EFLAGS_AC
))
195 if (test_bit(X86_FEATURE_LM
, cpu
.flags
))
200 ~((1 << X86_FEATURE_XMM
)|(1 << X86_FEATURE_XMM2
))) &&
202 /* If this is an AMD and we're only missing SSE+SSE2, try to
205 u32 ecx
= MSR_K7_HWCR
;
208 asm("rdmsr" : "=a" (eax
), "=d" (edx
) : "c" (ecx
));
210 asm("wrmsr" : : "a" (eax
), "d" (edx
), "c" (ecx
));
212 get_flags(); /* Make sure it really did something */
214 } else if (err
== 0x01 &&
215 !(err_flags
[0] & ~(1 << X86_FEATURE_CX8
)) &&
216 is_centaur() && cpu
.model
>= 6) {
217 /* If this is a VIA C3, we might have to enable CX8
220 u32 ecx
= MSR_VIA_FCR
;
223 asm("rdmsr" : "=a" (eax
), "=d" (edx
) : "c" (ecx
));
224 eax
|= (1<<1)|(1<<7);
225 asm("wrmsr" : : "a" (eax
), "d" (edx
), "c" (ecx
));
227 set_bit(X86_FEATURE_CX8
, cpu
.flags
);
229 } else if (err
== 0x01 && is_transmeta()) {
230 /* Transmeta might have masked feature bits in word 0 */
232 u32 ecx
= 0x80860004;
236 asm("rdmsr" : "=a" (eax
), "=d" (edx
) : "c" (ecx
));
237 asm("wrmsr" : : "a" (~0), "d" (edx
), "c" (ecx
));
239 : "+a" (level
), "=d" (cpu
.flags
[0])
241 asm("wrmsr" : : "a" (eax
), "d" (edx
), "c" (ecx
));
247 *err_flags_ptr
= err
? err_flags
: NULL
;
249 *cpu_level_ptr
= cpu
.level
;
251 *req_level_ptr
= req_level
;
253 return (cpu
.level
< req_level
|| err
) ? -1 : 0;