2 * arch/arm/mach-at91/pm_slow_clock.S
4 * Copyright (C) 2006 Savin Zlobec
7 * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/linkage.h>
15 #include <linux/clk/at91_pmc.h>
17 #include "generated/at91_pm_data-offsets.h"
19 #define SRAMC_SELF_FRESH_ACTIVE 0x01
20 #define SRAMC_SELF_FRESH_EXIT 0x00
27 * Wait until master clock is ready (after switching master clock source)
30 1: ldr tmp1, [pmc, #AT91_PMC_SR]
31 tst tmp1, #AT91_PMC_MCKRDY
36 * Wait until master oscillator has stabilized.
39 1: ldr tmp1, [pmc, #AT91_PMC_SR]
40 tst tmp1, #AT91_PMC_MOSCS
45 * Wait until PLLA has locked.
48 1: ldr tmp1, [pmc, #AT91_PMC_SR]
49 tst tmp1, #AT91_PMC_LOCKA
54 * Put the processor to enter the idle state
58 #if defined(CONFIG_CPU_V7)
59 mov tmp1, #AT91_PMC_PCK
60 str tmp1, [pmc, #AT91_PMC_SCDR]
64 wfi @ Wait For Interrupt
66 mcr p15, 0, tmp1, c7, c0, 4
76 * void at91_suspend_sram_fn(struct at91_pm_data*)
78 * @r0: base address of struct at91_pm_data
80 /* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
82 ENTRY(at91_pm_suspend_in_sram)
83 /* Save registers on stack */
84 stmfd sp!, {r4 - r12, lr}
86 /* Drain write buffer */
88 mcr p15, 0, tmp1, c7, c10, 4
90 ldr tmp1, [r0, #PM_DATA_PMC]
92 ldr tmp1, [r0, #PM_DATA_RAMC0]
94 ldr tmp1, [r0, #PM_DATA_RAMC1]
95 str tmp1, .sramc1_base
96 ldr tmp1, [r0, #PM_DATA_MEMCTRL]
98 ldr tmp1, [r0, #PM_DATA_MODE]
100 /* Both ldrne below are here to preload their address in the TLB */
101 ldr tmp1, [r0, #PM_DATA_SHDWC]
104 ldrne tmp2, [tmp1, #0]
105 ldr tmp1, [r0, #PM_DATA_SFRBU]
108 ldrne tmp2, [tmp1, #0x10]
110 /* Active the self-refresh mode */
111 mov r0, #SRAMC_SELF_FRESH_ACTIVE
112 bl at91_sramc_self_refresh
115 cmp r0, #AT91_PM_SLOW_CLOCK
117 cmp r0, #AT91_PM_BACKUP
120 /* Wait for interrupt */
133 /* Exit the self-refresh mode */
134 mov r0, #SRAMC_SELF_FRESH_EXIT
135 bl at91_sramc_self_refresh
137 /* Restore registers, and return */
138 ldmfd sp!, {r4 - r12, pc}
139 ENDPROC(at91_pm_suspend_in_sram)
141 ENTRY(at91_backup_mode)
145 str tmp1, [r0, #0x10]
149 mov tmp1, #0xA5000000
152 ENDPROC(at91_backup_mode)
154 ENTRY(at91_slowck_mode)
157 /* Save Master clock setting */
158 ldr tmp1, [pmc, #AT91_PMC_MCKR]
159 str tmp1, .saved_mckr
162 * Set the Master clock source to slow clock
164 bic tmp1, tmp1, #AT91_PMC_CSS
165 str tmp1, [pmc, #AT91_PMC_MCKR]
169 /* Save PLLA setting and disable it */
170 ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
171 str tmp1, .saved_pllar
173 mov tmp1, #AT91_PMC_PLLCOUNT
174 orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
175 str tmp1, [pmc, #AT91_CKGR_PLLAR]
177 /* Turn off the main oscillator */
178 ldr tmp1, [pmc, #AT91_CKGR_MOR]
179 bic tmp1, tmp1, #AT91_PMC_MOSCEN
180 orr tmp1, tmp1, #AT91_PMC_KEY
181 str tmp1, [pmc, #AT91_CKGR_MOR]
183 /* Wait for interrupt */
186 /* Turn on the main oscillator */
187 ldr tmp1, [pmc, #AT91_CKGR_MOR]
188 orr tmp1, tmp1, #AT91_PMC_MOSCEN
189 orr tmp1, tmp1, #AT91_PMC_KEY
190 str tmp1, [pmc, #AT91_CKGR_MOR]
194 /* Restore PLLA setting */
195 ldr tmp1, .saved_pllar
196 str tmp1, [pmc, #AT91_CKGR_PLLAR]
198 tst tmp1, #(AT91_PMC_MUL & 0xff0000)
200 tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
207 * Restore master clock setting
209 ldr tmp1, .saved_mckr
210 str tmp1, [pmc, #AT91_PMC_MCKR]
215 ENDPROC(at91_slowck_mode)
218 * void at91_sramc_self_refresh(unsigned int is_active)
221 * @r0: 1 - active self-refresh mode
222 * 0 - exit self-refresh mode
225 * @r2: base address of the sram controller
228 ENTRY(at91_sramc_self_refresh)
232 cmp r1, #AT91_MEMCTRL_MC
236 * at91rm9200 Memory controller
240 * For exiting the self-refresh mode, do nothing,
241 * automatically exit the self-refresh mode.
243 tst r0, #SRAMC_SELF_FRESH_ACTIVE
246 /* Active SDRAM self-refresh mode */
248 str r3, [r2, #AT91_MC_SDRAMC_SRR]
252 cmp r1, #AT91_MEMCTRL_DDRSDR
256 * DDR Memory controller
258 tst r0, #SRAMC_SELF_FRESH_ACTIVE
261 /* LPDDR1 --> force DDR2 mode during self-refresh */
262 ldr r3, [r2, #AT91_DDRSDRC_MDR]
263 str r3, .saved_sam9_mdr
264 bic r3, r3, #~AT91_DDRSDRC_MD
265 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
266 ldreq r3, [r2, #AT91_DDRSDRC_MDR]
267 biceq r3, r3, #AT91_DDRSDRC_MD
268 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
269 streq r3, [r2, #AT91_DDRSDRC_MDR]
271 /* Active DDRC self-refresh mode */
272 ldr r3, [r2, #AT91_DDRSDRC_LPR]
273 str r3, .saved_sam9_lpr
274 bic r3, r3, #AT91_DDRSDRC_LPCB
275 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
276 str r3, [r2, #AT91_DDRSDRC_LPR]
278 /* If using the 2nd ddr controller */
283 ldr r3, [r2, #AT91_DDRSDRC_MDR]
284 str r3, .saved_sam9_mdr1
285 bic r3, r3, #~AT91_DDRSDRC_MD
286 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
287 ldreq r3, [r2, #AT91_DDRSDRC_MDR]
288 biceq r3, r3, #AT91_DDRSDRC_MD
289 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
290 streq r3, [r2, #AT91_DDRSDRC_MDR]
292 /* Active DDRC self-refresh mode */
293 ldr r3, [r2, #AT91_DDRSDRC_LPR]
294 str r3, .saved_sam9_lpr1
295 bic r3, r3, #AT91_DDRSDRC_LPCB
296 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
297 str r3, [r2, #AT91_DDRSDRC_LPR]
303 /* Restore MDR in case of LPDDR1 */
304 ldr r3, .saved_sam9_mdr
305 str r3, [r2, #AT91_DDRSDRC_MDR]
306 /* Restore LPR on AT91 with DDRAM */
307 ldr r3, .saved_sam9_lpr
308 str r3, [r2, #AT91_DDRSDRC_LPR]
310 /* If using the 2nd ddr controller */
313 ldrne r3, .saved_sam9_mdr1
314 strne r3, [r2, #AT91_DDRSDRC_MDR]
315 ldrne r3, .saved_sam9_lpr1
316 strne r3, [r2, #AT91_DDRSDRC_LPR]
321 * SDRAMC Memory controller
324 tst r0, #SRAMC_SELF_FRESH_ACTIVE
327 /* Active SDRAMC self-refresh mode */
328 ldr r3, [r2, #AT91_SDRAMC_LPR]
329 str r3, .saved_sam9_lpr
330 bic r3, r3, #AT91_SDRAMC_LPCB
331 orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
332 str r3, [r2, #AT91_SDRAMC_LPR]
335 ldr r3, .saved_sam9_lpr
336 str r3, [r2, #AT91_SDRAMC_LPR]
340 ENDPROC(at91_sramc_self_refresh)
369 ENTRY(at91_pm_suspend_in_sram_sz)
370 .word .-at91_pm_suspend_in_sram