arch/arm/mach-imx/mx31.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __MACH_MX31_H__
   3 #define __MACH_MX31_H__
   4
   5 /*
   6  * IRAM
   7  */
   8 #define MX31_IRAM_BASE_ADDR             0x1ffc0000      /* internal ram */
   9 #define MX31_IRAM_SIZE                  SZ_16K
  10
  11 #define MX31_L2CC_BASE_ADDR             0x30000000
  12 #define MX31_L2CC_SIZE                  SZ_1M
  13
  14 #define MX31_AIPS1_BASE_ADDR            0x43f00000
  15 #define MX31_AIPS1_SIZE                 SZ_1M
  16 #define MX31_MAX_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x04000)
  17 #define MX31_EVTMON_BASE_ADDR                   (MX31_AIPS1_BASE_ADDR + 0x08000)
  18 #define MX31_CLKCTL_BASE_ADDR                   (MX31_AIPS1_BASE_ADDR + 0x0c000)
  19 #define MX31_ETB_SLOT4_BASE_ADDR                (MX31_AIPS1_BASE_ADDR + 0x10000)
  20 #define MX31_ETB_SLOT5_BASE_ADDR                (MX31_AIPS1_BASE_ADDR + 0x14000)
  21 #define MX31_ECT_CTIO_BASE_ADDR                 (MX31_AIPS1_BASE_ADDR + 0x18000)
  22 #define MX31_I2C1_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x80000)
  23 #define MX31_I2C3_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x84000)
  24 #define MX31_USB_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x88000)
  25 #define MX31_USB_OTG_BASE_ADDR                  (MX31_USB_BASE_ADDR + 0x0000)
  26 #define MX31_USB_HS1_BASE_ADDR                  (MX31_USB_BASE_ADDR + 0x0200)
  27 #define MX31_USB_HS2_BASE_ADDR                  (MX31_USB_BASE_ADDR + 0x0400)
  28 #define MX31_ATA_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x8c000)
  29 #define MX31_UART1_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x90000)
  30 #define MX31_UART2_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x94000)
  31 #define MX31_I2C2_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x98000)
  32 #define MX31_OWIRE_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x9c000)
  33 #define MX31_SSI1_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0xa0000)
  34 #define MX31_CSPI1_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0xa4000)
  35 #define MX31_KPP_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0xa8000)
  36 #define MX31_IOMUXC_BASE_ADDR                   (MX31_AIPS1_BASE_ADDR + 0xac000)
  37 #define MX31_UART4_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0xb0000)
  38 #define MX31_UART5_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0xb4000)
  39 #define MX31_ECT_IP1_BASE_ADDR                  (MX31_AIPS1_BASE_ADDR + 0xb8000)
  40 #define MX31_ECT_IP2_BASE_ADDR                  (MX31_AIPS1_BASE_ADDR + 0xbc000)
  41
  42 #define MX31_SPBA0_BASE_ADDR            0x50000000
  43 #define MX31_SPBA0_SIZE                 SZ_1M
  44 #define MX31_SDHC1_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x04000)
  45 #define MX31_SDHC2_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x08000)
  46 #define MX31_UART3_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x0c000)
  47 #define MX31_CSPI2_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x10000)
  48 #define MX31_SSI2_BASE_ADDR                     (MX31_SPBA0_BASE_ADDR + 0x14000)
  49 #define MX31_SIM1_BASE_ADDR                     (MX31_SPBA0_BASE_ADDR + 0x18000)
  50 #define MX31_IIM_BASE_ADDR                      (MX31_SPBA0_BASE_ADDR + 0x1c000)
  51 #define MX31_ATA_DMA_BASE_ADDR                  (MX31_SPBA0_BASE_ADDR + 0x20000)
  52 #define MX31_MSHC1_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x24000)
  53 #define MX31_SPBA_CTRL_BASE_ADDR                (MX31_SPBA0_BASE_ADDR + 0x3c000)
  54
  55 #define MX31_AIPS2_BASE_ADDR            0x53f00000
  56 #define MX31_AIPS2_SIZE                 SZ_1M
  57 #define MX31_CCM_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0x80000)
  58 #define MX31_CSPI3_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0x84000)
  59 #define MX31_FIRI_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0x8c000)
  60 #define MX31_GPT1_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0x90000)
  61 #define MX31_EPIT1_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0x94000)
  62 #define MX31_EPIT2_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0x98000)
  63 #define MX31_GPIO3_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0xa4000)
  64 #define MX31_SCC_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xac000)
  65 #define MX31_SCM_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xae000)
  66 #define MX31_SMN_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xaf000)
  67 #define MX31_RNGA_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xb0000)
  68 #define MX31_IPU_CTRL_BASE_ADDR                 (MX31_AIPS2_BASE_ADDR + 0xc0000)
  69 #define MX31_AUDMUX_BASE_ADDR                   (MX31_AIPS2_BASE_ADDR + 0xc4000)
  70 #define MX31_MPEG4_ENC_BASE_ADDR                (MX31_AIPS2_BASE_ADDR + 0xc8000)
  71 #define MX31_GPIO1_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0xcc000)
  72 #define MX31_GPIO2_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0xd0000)
  73 #define MX31_SDMA_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xd4000)
  74 #define MX31_RTC_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xd8000)
  75 #define MX31_WDOG_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xdc000)
  76 #define MX31_PWM_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xe0000)
  77 #define MX31_RTIC_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xec000)
  78
  79 #define MX31_ROMP_BASE_ADDR             0x60000000
  80 #define MX31_ROMP_BASE_ADDR_VIRT        IOMEM(0xfc500000)
  81 #define MX31_ROMP_SIZE                  SZ_1M
  82
  83 #define MX31_AVIC_BASE_ADDR             0x68000000
  84 #define MX31_AVIC_SIZE                  SZ_1M
  85
  86 #define MX31_IPU_MEM_BASE_ADDR          0x70000000
  87 #define MX31_CSD0_BASE_ADDR             0x80000000
  88 #define MX31_CSD1_BASE_ADDR             0x90000000
  89
  90 #define MX31_CS0_BASE_ADDR              0xa0000000
  91 #define MX31_CS1_BASE_ADDR              0xa8000000
  92 #define MX31_CS2_BASE_ADDR              0xb0000000
  93 #define MX31_CS3_BASE_ADDR              0xb2000000
  94
  95 #define MX31_CS4_BASE_ADDR              0xb4000000
  96 #define MX31_CS4_BASE_ADDR_VIRT         IOMEM(0xf6000000)
  97 #define MX31_CS4_SIZE                   SZ_32M
  98
  99 #define MX31_CS5_BASE_ADDR              0xb6000000
 100 #define MX31_CS5_BASE_ADDR_VIRT         IOMEM(0xf8000000)
 101 #define MX31_CS5_SIZE                   SZ_32M
 102
 103 #define MX31_X_MEMC_BASE_ADDR           0xb8000000
 104 #define MX31_X_MEMC_SIZE                SZ_64K
 105 #define MX31_NFC_BASE_ADDR                      (MX31_X_MEMC_BASE_ADDR + 0x0000)
 106 #define MX31_ESDCTL_BASE_ADDR                   (MX31_X_MEMC_BASE_ADDR + 0x1000)
 107 #define MX31_WEIM_BASE_ADDR                     (MX31_X_MEMC_BASE_ADDR + 0x2000)
 108 #define MX31_M3IF_BASE_ADDR                     (MX31_X_MEMC_BASE_ADDR + 0x3000)
 109 #define MX31_EMI_CTL_BASE_ADDR                  (MX31_X_MEMC_BASE_ADDR + 0x4000)
 110 #define MX31_PCMCIA_CTL_BASE_ADDR               MX31_EMI_CTL_BASE_ADDR
 111
 112 #define MX31_WEIM_CSCRx_BASE_ADDR(cs)   (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
 113 #define MX31_WEIM_CSCRxU(cs)                    (MX31_WEIM_CSCRx_BASE_ADDR(cs))
 114 #define MX31_WEIM_CSCRxL(cs)                    (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
 115 #define MX31_WEIM_CSCRxA(cs)                    (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
 116
 117 #define MX31_PCMCIA_MEM_BASE_ADDR       0xbc000000
 118
 119 #define MX31_IO_P2V(x)                  IMX_IO_P2V(x)
 120 #define MX31_IO_ADDRESS(x)              IOMEM(MX31_IO_P2V(x))
 121
 122 /*
 123  * Interrupt numbers
 124  */
 125 #include <asm/irq.h>
 126 #define MX31_INT_I2C3           (NR_IRQS_LEGACY + 3)
 127 #define MX31_INT_I2C2           (NR_IRQS_LEGACY + 4)
 128 #define MX31_INT_MPEG4_ENCODER  (NR_IRQS_LEGACY + 5)
 129 #define MX31_INT_RTIC           (NR_IRQS_LEGACY + 6)
 130 #define MX31_INT_FIRI           (NR_IRQS_LEGACY + 7)
 131 #define MX31_INT_SDHC2          (NR_IRQS_LEGACY + 8)
 132 #define MX31_INT_SDHC1          (NR_IRQS_LEGACY + 9)
 133 #define MX31_INT_I2C1           (NR_IRQS_LEGACY + 10)
 134 #define MX31_INT_SSI2           (NR_IRQS_LEGACY + 11)
 135 #define MX31_INT_SSI1           (NR_IRQS_LEGACY + 12)
 136 #define MX31_INT_CSPI2          (NR_IRQS_LEGACY + 13)
 137 #define MX31_INT_CSPI1          (NR_IRQS_LEGACY + 14)
 138 #define MX31_INT_ATA            (NR_IRQS_LEGACY + 15)
 139 #define MX31_INT_MBX            (NR_IRQS_LEGACY + 16)
 140 #define MX31_INT_CSPI3          (NR_IRQS_LEGACY + 17)
 141 #define MX31_INT_UART3          (NR_IRQS_LEGACY + 18)
 142 #define MX31_INT_IIM            (NR_IRQS_LEGACY + 19)
 143 #define MX31_INT_SIM2           (NR_IRQS_LEGACY + 20)
 144 #define MX31_INT_SIM1           (NR_IRQS_LEGACY + 21)
 145 #define MX31_INT_RNGA           (NR_IRQS_LEGACY + 22)
 146 #define MX31_INT_EVTMON         (NR_IRQS_LEGACY + 23)
 147 #define MX31_INT_KPP            (NR_IRQS_LEGACY + 24)
 148 #define MX31_INT_RTC            (NR_IRQS_LEGACY + 25)
 149 #define MX31_INT_PWM            (NR_IRQS_LEGACY + 26)
 150 #define MX31_INT_EPIT2          (NR_IRQS_LEGACY + 27)
 151 #define MX31_INT_EPIT1          (NR_IRQS_LEGACY + 28)
 152 #define MX31_INT_GPT            (NR_IRQS_LEGACY + 29)
 153 #define MX31_INT_POWER_FAIL     (NR_IRQS_LEGACY + 30)
 154 #define MX31_INT_CCM_DVFS       (NR_IRQS_LEGACY + 31)
 155 #define MX31_INT_UART2          (NR_IRQS_LEGACY + 32)
 156 #define MX31_INT_NFC            (NR_IRQS_LEGACY + 33)
 157 #define MX31_INT_SDMA           (NR_IRQS_LEGACY + 34)
 158 #define MX31_INT_USB_HS1        (NR_IRQS_LEGACY + 35)
 159 #define MX31_INT_USB_HS2        (NR_IRQS_LEGACY + 36)
 160 #define MX31_INT_USB_OTG        (NR_IRQS_LEGACY + 37)
 161 #define MX31_INT_MSHC1          (NR_IRQS_LEGACY + 39)
 162 #define MX31_INT_MSHC2          (NR_IRQS_LEGACY + 40)
 163 #define MX31_INT_IPU_ERR        (NR_IRQS_LEGACY + 41)
 164 #define MX31_INT_IPU_SYN        (NR_IRQS_LEGACY + 42)
 165 #define MX31_INT_UART1          (NR_IRQS_LEGACY + 45)
 166 #define MX31_INT_UART4          (NR_IRQS_LEGACY + 46)
 167 #define MX31_INT_UART5          (NR_IRQS_LEGACY + 47)
 168 #define MX31_INT_ECT            (NR_IRQS_LEGACY + 48)
 169 #define MX31_INT_SCC_SCM        (NR_IRQS_LEGACY + 49)
 170 #define MX31_INT_SCC_SMN        (NR_IRQS_LEGACY + 50)
 171 #define MX31_INT_GPIO2          (NR_IRQS_LEGACY + 51)
 172 #define MX31_INT_GPIO1          (NR_IRQS_LEGACY + 52)
 173 #define MX31_INT_CCM            (NR_IRQS_LEGACY + 53)
 174 #define MX31_INT_PCMCIA         (NR_IRQS_LEGACY + 54)
 175 #define MX31_INT_WDOG           (NR_IRQS_LEGACY + 55)
 176 #define MX31_INT_GPIO3          (NR_IRQS_LEGACY + 56)
 177 #define MX31_INT_EXT_POWER      (NR_IRQS_LEGACY + 58)
 178 #define MX31_INT_EXT_TEMPER     (NR_IRQS_LEGACY + 59)
 179 #define MX31_INT_EXT_SENSOR60   (NR_IRQS_LEGACY + 60)
 180 #define MX31_INT_EXT_SENSOR61   (NR_IRQS_LEGACY + 61)
 181 #define MX31_INT_EXT_WDOG       (NR_IRQS_LEGACY + 62)
 182 #define MX31_INT_EXT_TV         (NR_IRQS_LEGACY + 63)
 183
 184 #define MX31_DMA_REQ_SDHC1      20
 185 #define MX31_DMA_REQ_SDHC2      21
 186 #define MX31_DMA_REQ_SSI2_RX1   22
 187 #define MX31_DMA_REQ_SSI2_TX1   23
 188 #define MX31_DMA_REQ_SSI2_RX0   24
 189 #define MX31_DMA_REQ_SSI2_TX0   25
 190 #define MX31_DMA_REQ_SSI1_RX1   26
 191 #define MX31_DMA_REQ_SSI1_TX1   27
 192 #define MX31_DMA_REQ_SSI1_RX0   28
 193 #define MX31_DMA_REQ_SSI1_TX0   29
 194
 195 #define MX31_PROD_SIGNATURE             0x1     /* For MX31 */
 196
 197 #endif /* ifndef __MACH_MX31_H__ */