2 * linux/arch/arm/mach-mmp/time.c
4 * Support for clocksource and clockevents
6 * Copyright (C) 2008 Marvell International Ltd.
9 * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
10 * 2008-10-08: Bin Yang <bin.yang@marvell.com>
12 * The timers module actually includes three timers, each timer with up to
13 * three match comparators. Timer #0 is used here in free-running mode as
14 * the clock source, and match comparator #1 used as clock event device.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/interrupt.h>
24 #include <linux/clockchips.h>
27 #include <linux/irq.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/sched_clock.h>
32 #include <asm/mach/time.h>
35 #include "regs-timers.h"
36 #include "regs-apbc.h"
41 #ifdef CONFIG_CPU_MMP2
42 #define MMP_CLOCK_FREQ 6500000
44 #define MMP_CLOCK_FREQ 3250000
47 #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
49 #define MAX_DELTA (0xfffffffe)
50 #define MIN_DELTA (16)
52 static void __iomem
*mmp_timer_base
= TIMERS_VIRT_BASE
;
55 * FIXME: the timer needs some delay to stablize the counter capture
57 static inline uint32_t timer_read(void)
61 __raw_writel(1, mmp_timer_base
+ TMR_CVWR(1));
66 return __raw_readl(mmp_timer_base
+ TMR_CVWR(1));
69 static u64 notrace
mmp_read_sched_clock(void)
74 static irqreturn_t
timer_interrupt(int irq
, void *dev_id
)
76 struct clock_event_device
*c
= dev_id
;
79 * Clear pending interrupt status.
81 __raw_writel(0x01, mmp_timer_base
+ TMR_ICR(0));
86 __raw_writel(0x02, mmp_timer_base
+ TMR_CER
);
93 static int timer_set_next_event(unsigned long delta
,
94 struct clock_event_device
*dev
)
98 local_irq_save(flags
);
103 __raw_writel(0x02, mmp_timer_base
+ TMR_CER
);
106 * Clear and enable timer match 0 interrupt.
108 __raw_writel(0x01, mmp_timer_base
+ TMR_ICR(0));
109 __raw_writel(0x01, mmp_timer_base
+ TMR_IER(0));
112 * Setup new clockevent timer value.
114 __raw_writel(delta
- 1, mmp_timer_base
+ TMR_TN_MM(0, 0));
119 __raw_writel(0x03, mmp_timer_base
+ TMR_CER
);
121 local_irq_restore(flags
);
126 static int timer_set_shutdown(struct clock_event_device
*evt
)
130 local_irq_save(flags
);
131 /* disable the matching interrupt */
132 __raw_writel(0x00, mmp_timer_base
+ TMR_IER(0));
133 local_irq_restore(flags
);
138 static struct clock_event_device ckevt
= {
139 .name
= "clockevent",
140 .features
= CLOCK_EVT_FEAT_ONESHOT
,
142 .set_next_event
= timer_set_next_event
,
143 .set_state_shutdown
= timer_set_shutdown
,
144 .set_state_oneshot
= timer_set_shutdown
,
147 static u64
clksrc_read(struct clocksource
*cs
)
152 static struct clocksource cksrc
= {
153 .name
= "clocksource",
156 .mask
= CLOCKSOURCE_MASK(32),
157 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
160 static void __init
timer_config(void)
162 uint32_t ccr
= __raw_readl(mmp_timer_base
+ TMR_CCR
);
164 __raw_writel(0x0, mmp_timer_base
+ TMR_CER
); /* disable */
166 ccr
&= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
167 (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
168 __raw_writel(ccr
, mmp_timer_base
+ TMR_CCR
);
170 /* set timer 0 to periodic mode, and timer 1 to free-running mode */
171 __raw_writel(0x2, mmp_timer_base
+ TMR_CMR
);
173 __raw_writel(0x1, mmp_timer_base
+ TMR_PLCR(0)); /* periodic */
174 __raw_writel(0x7, mmp_timer_base
+ TMR_ICR(0)); /* clear status */
175 __raw_writel(0x0, mmp_timer_base
+ TMR_IER(0));
177 __raw_writel(0x0, mmp_timer_base
+ TMR_PLCR(1)); /* free-running */
178 __raw_writel(0x7, mmp_timer_base
+ TMR_ICR(1)); /* clear status */
179 __raw_writel(0x0, mmp_timer_base
+ TMR_IER(1));
181 /* enable timer 1 counter */
182 __raw_writel(0x2, mmp_timer_base
+ TMR_CER
);
185 static struct irqaction timer_irq
= {
187 .flags
= IRQF_TIMER
| IRQF_IRQPOLL
,
188 .handler
= timer_interrupt
,
192 void __init
timer_init(int irq
)
196 sched_clock_register(mmp_read_sched_clock
, 32, MMP_CLOCK_FREQ
);
198 ckevt
.cpumask
= cpumask_of(0);
200 setup_irq(irq
, &timer_irq
);
202 clocksource_register_hz(&cksrc
, MMP_CLOCK_FREQ
);
203 clockevents_config_and_register(&ckevt
, MMP_CLOCK_FREQ
,
204 MIN_DELTA
, MAX_DELTA
);
208 static const struct of_device_id mmp_timer_dt_ids
[] = {
209 { .compatible
= "mrvl,mmp-timer", },
213 void __init
mmp_dt_init_timer(void)
215 struct device_node
*np
;
218 np
= of_find_matching_node(NULL
, mmp_timer_dt_ids
);
224 irq
= irq_of_parse_and_map(np
, 0);
229 mmp_timer_base
= of_iomap(np
, 0);
230 if (!mmp_timer_base
) {
237 pr_err("Failed to get timer from device tree with error:%d\n", ret
);