arch/arm/mach-omap2/cm-regbits-34xx.h

   1 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
   2 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
   3
   4 /*
   5  * OMAP3430 Clock Management register bits
   6  *
   7  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   8  * Copyright (C) 2007-2008 Nokia Corporation
   9  *
  10  * Written by Paul Walmsley
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK            (1 << 0)
  18 #define OMAP3430_ST_IVA2_SHIFT                          0
  19 #define OMAP3430_CLKTRCTRL_IVA2_MASK                    (0x3 << 0)
  20 #define OMAP3430_CLKACTIVITY_IVA2_MASK                  (1 << 0)
  21 #define OMAP3430_CLKTRCTRL_MPU_MASK                     (0x3 << 0)
  22 #define OMAP3430_ST_AES2_SHIFT                          28
  23 #define OMAP3430_ST_SHA12_SHIFT                         27
  24 #define AM35XX_ST_UART4_SHIFT                           23
  25 #define OMAP3430_ST_HDQ_SHIFT                           22
  26 #define OMAP3430ES2_ST_SSI_IDLE_SHIFT                   8
  27 #define OMAP3430_ST_MAILBOXES_SHIFT                     7
  28 #define OMAP3430_ST_SAD2D_SHIFT                         3
  29 #define OMAP3430_ST_SDMA_SHIFT                          2
  30 #define OMAP3430ES2_ST_USBTLL_SHIFT                     2
  31 #define OMAP3430ES1_CLKTRCTRL_D2D_MASK                  (0x3 << 4)
  32 #define OMAP3430_CLKTRCTRL_L4_MASK                      (0x3 << 2)
  33 #define OMAP3430_CLKTRCTRL_L3_MASK                      (0x3 << 0)
  34 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK                  (0x3 << 0)
  35 #define OMAP3430ES2_CLKTRCTRL_SGX_MASK                  (0x3 << 0)
  36 #define OMAP3430_ST_WDT2_SHIFT                          5
  37 #define OMAP3430_ST_32KSYNC_SHIFT                       2
  38 #define OMAP3430_AUTO_PERIPH_DPLL_MASK                  (0x7 << 3)
  39 #define OMAP3430ES2_ST_DSS_IDLE_SHIFT                   1
  40 #define OMAP3430_CLKTRCTRL_DSS_MASK                     (0x3 << 0)
  41 #define OMAP3430_CLKTRCTRL_CAM_MASK                     (0x3 << 0)
  42 #define OMAP3430_ST_MCBSP4_SHIFT                        2
  43 #define OMAP3430_ST_MCBSP3_SHIFT                        1
  44 #define OMAP3430_ST_MCBSP2_SHIFT                        0
  45 #define OMAP3430_CLKTRCTRL_PER_MASK                     (0x3 << 0)
  46 #define OMAP3430_CLKTRCTRL_EMU_MASK                     (0x3 << 0)
  47 #define OMAP3430_CLKTRCTRL_NEON_MASK                    (0x3 << 0)
  48 #define OMAP3430ES2_EN_USBHOST2_SHIFT                   1
  49 #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT               1
  50 #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK              (3 << 0)
  51 #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO         0x0
  52 #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP          0x1
  53 #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP         0x2
  54 #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO          0x3
  55 #endif