| blob | ec580fd094a6ae4c2f0b98af4e95b55972fcb7d1 |
1 /*
2 * OMAP3xxx CM module functions
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 * Rajendra Nayak <rnayak@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/delay.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
29 };
31 /*
32 *
33 */
36 {
37 u32 v;
43 }
46 {
47 u32 v;
54 }
57 {
59 }
62 {
64 }
67 {
69 }
72 {
74 }
76 /*
77 *
78 */
80 /**
81 * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby
82 * @part: PRCM partition, ignored for OMAP3
83 * @prcm_mod: PRCM module offset
84 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
85 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
86 *
87 * Wait for the PRCM to indicate that the module identified by
88 * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon
89 * success or -EBUSY if the module doesn't enable in time.
90 */
92 u8 idlest_shift)
93 {
95 u8 cm_idlest_reg;
96 u32 mask;
110 }
112 /**
113 * omap3xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
114 * @idlest_reg: CM_IDLEST* virtual address
115 * @prcm_inst: pointer to an s16 to return the PRCM instance offset
116 * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
117 *
118 * XXX This function is only needed until absolute register addresses are
119 * removed from the OMAP struct clk records.
120 */
124 {
126 u8 idlest_offs;
134 }
135 }
145 }
147 /* Clockdomain low-level operations */
151 {
154 OMAP3430_CM_SLEEPDEP);
156 }
160 {
163 OMAP3430_CM_SLEEPDEP);
165 }
169 {
171 OMAP3430_CM_SLEEPDEP,
173 }
176 {
186 }
188 OMAP3430_CM_SLEEPDEP);
190 }
193 {
197 }
200 {
204 }
207 {
213 }
216 {
222 }
225 {
231 /*
232 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
233 * more details on the unpleasant problem this is working
234 * around
235 */
240 }
246 /* Disable HW transitions when we are changing deps */
255 }
258 }
261 {
267 /*
268 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
269 * more details on the unpleasant problem this is working
270 * around
271 */
277 }
283 /* Disable HW transitions when we are changing deps */
292 }
295 }
312 };
314 /*
315 * Context save/restore code - OMAP3 only
316 */
318 u32 iva2_cm_clksel1;
319 u32 iva2_cm_clksel2;
320 u32 cm_sysconfig;
321 u32 sgx_cm_clksel;
322 u32 dss_cm_clksel;
323 u32 cam_cm_clksel;
324 u32 per_cm_clksel;
325 u32 emu_cm_clksel;
326 u32 emu_cm_clkstctrl;
327 u32 pll_cm_autoidle;
328 u32 pll_cm_autoidle2;
329 u32 pll_cm_clksel4;
330 u32 pll_cm_clksel5;
331 u32 pll_cm_clken2;
332 u32 cm_polctrl;
333 u32 iva2_cm_fclken;
334 u32 iva2_cm_clken_pll;
335 u32 core_cm_fclken1;
336 u32 core_cm_fclken3;
337 u32 sgx_cm_fclken;
338 u32 wkup_cm_fclken;
339 u32 dss_cm_fclken;
340 u32 cam_cm_fclken;
341 u32 per_cm_fclken;
342 u32 usbhost_cm_fclken;
343 u32 core_cm_iclken1;
344 u32 core_cm_iclken2;
345 u32 core_cm_iclken3;
346 u32 sgx_cm_iclken;
347 u32 wkup_cm_iclken;
348 u32 dss_cm_iclken;
349 u32 cam_cm_iclken;
350 u32 per_cm_iclken;
351 u32 usbhost_cm_iclken;
352 u32 iva2_cm_autoidle2;
353 u32 mpu_cm_autoidle2;
354 u32 iva2_cm_clkstctrl;
355 u32 mpu_cm_clkstctrl;
356 u32 core_cm_clkstctrl;
357 u32 sgx_cm_clkstctrl;
358 u32 dss_cm_clkstctrl;
359 u32 cam_cm_clkstctrl;
360 u32 per_cm_clkstctrl;
361 u32 neon_cm_clkstctrl;
362 u32 usbhost_cm_clkstctrl;
363 u32 core_cm_autoidle1;
364 u32 core_cm_autoidle2;
365 u32 core_cm_autoidle3;
366 u32 wkup_cm_autoidle;
367 u32 dss_cm_autoidle;
368 u32 cam_cm_autoidle;
369 u32 per_cm_autoidle;
370 u32 usbhost_cm_autoidle;
371 u32 sgx_cm_sleepdep;
372 u32 dss_cm_sleepdep;
373 u32 cam_cm_sleepdep;
374 u32 per_cm_sleepdep;
375 u32 usbhost_cm_sleepdep;
376 u32 cm_clkout_ctrl;
377 };
382 {
401 /*
402 * As per erratum i671, ROM code does not respect the PER DPLL
403 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
404 * In this case, even though this register has been saved in
405 * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
406 * by ourselves. So, we need to save it anyway.
407 */
480 OMAP2_CM_CLKSTCTRL);
499 OMAP3430_CM_SLEEPDEP);
508 OMAP3430_CM_SLEEPDEP);
511 OMAP3_CM_CLKOUT_CTRL_OFFSET);
512 }
515 {
517 CM_CLKSEL1);
519 CM_CLKSEL2);
521 OMAP3430_CM_SYSCONFIG);
523 CM_CLKSEL);
525 CM_CLKSEL);
527 CM_CLKSEL);
529 CM_CLKSEL);
531 CM_CLKSEL1);
533 OMAP2_CM_CLKSTCTRL);
534 /*
535 * As per erratum i671, ROM code does not respect the PER DPLL
536 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
537 * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
538 */
540 CM_AUTOIDLE);
542 CM_AUTOIDLE2);
544 OMAP3430ES2_CM_CLKSEL4);
546 OMAP3430ES2_CM_CLKSEL5);
548 OMAP3430ES2_CM_CLKEN2);
550 OMAP3430_CM_POLCTRL);
552 CM_FCLKEN);
554 OMAP3430_CM_CLKEN_PLL);
556 CM_FCLKEN1);
558 OMAP3430ES2_CM_FCLKEN3);
560 CM_FCLKEN);
563 CM_FCLKEN);
565 CM_FCLKEN);
567 CM_FCLKEN);
571 CM_ICLKEN1);
573 CM_ICLKEN2);
575 CM_ICLKEN3);
577 CM_ICLKEN);
580 CM_ICLKEN);
582 CM_ICLKEN);
584 CM_ICLKEN);
588 CM_AUTOIDLE2);
590 CM_AUTOIDLE2);
592 OMAP2_CM_CLKSTCTRL);
594 OMAP2_CM_CLKSTCTRL);
596 OMAP2_CM_CLKSTCTRL);
598 OMAP2_CM_CLKSTCTRL);
600 OMAP2_CM_CLKSTCTRL);
602 OMAP2_CM_CLKSTCTRL);
604 OMAP2_CM_CLKSTCTRL);
606 OMAP2_CM_CLKSTCTRL);
610 CM_AUTOIDLE1);
612 CM_AUTOIDLE2);
614 CM_AUTOIDLE3);
616 CM_AUTOIDLE);
618 CM_AUTOIDLE);
620 CM_AUTOIDLE);
622 CM_AUTOIDLE);
626 OMAP3430_CM_SLEEPDEP);
628 OMAP3430_CM_SLEEPDEP);
630 OMAP3430_CM_SLEEPDEP);
632 OMAP3430_CM_SLEEPDEP);
636 OMAP3_CM_CLKOUT_CTRL_OFFSET);
637 }
640 {
645 /*
646 * As per erratum i671, ROM code does not respect the PER DPLL
647 * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
648 * Then, in any case, clear these bits to avoid extra latencies.
649 */
659 }
661 /*
662 *
663 */
668 };
671 {
673 OMAP3430_IVA2_MOD);
675 }
678 {
680 }