arch/arm/mach-ux500/platsmp.c

   1 /*
   2  * Copyright (C) 2002 ARM Ltd.
   3  * Copyright (C) 2008 STMicroelctronics.
   4  * Copyright (C) 2009 ST-Ericsson.
   5  * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
   6  *
   7  * This file is based on arm realview platform
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/errno.h>
  15 #include <linux/delay.h>
  16 #include <linux/device.h>
  17 #include <linux/smp.h>
  18 #include <linux/io.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21
  22 #include <asm/cacheflush.h>
  23 #include <asm/smp_plat.h>
  24 #include <asm/smp_scu.h>
  25
  26 #include "db8500-regs.h"
  27
  28 /* Magic triggers in backup RAM */
  29 #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
  30 #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
  31
  32 static void __iomem *backupram;
  33
  34 static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
  35 {
  36         struct device_node *np;
  37         static void __iomem *scu_base;
  38         unsigned int ncores;
  39         int i;
  40
  41         np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram");
  42         if (!np) {
  43                 pr_err("No backupram base address\n");
  44                 return;
  45         }
  46         backupram = of_iomap(np, 0);
  47         of_node_put(np);
  48         if (!backupram) {
  49                 pr_err("No backupram remap\n");
  50                 return;
  51         }
  52
  53         np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
  54         if (!np) {
  55                 pr_err("No SCU base address\n");
  56                 return;
  57         }
  58         scu_base = of_iomap(np, 0);
  59         of_node_put(np);
  60         if (!scu_base) {
  61                 pr_err("No SCU remap\n");
  62                 return;
  63         }
  64
  65         scu_enable(scu_base);
  66         ncores = scu_get_core_count(scu_base);
  67         for (i = 0; i < ncores; i++)
  68                 set_cpu_possible(i, true);
  69         iounmap(scu_base);
  70 }
  71
  72 static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
  73 {
  74         /*
  75          * write the address of secondary startup into the backup ram register
  76          * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
  77          * backup ram register at offset 0x1FF0, which is what boot rom code
  78          * is waiting for. This will wake up the secondary core from WFE.
  79          */
  80         writel(__pa_symbol(secondary_startup),
  81                backupram + UX500_CPU1_JUMPADDR_OFFSET);
  82         writel(0xA1FEED01,
  83                backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
  84
  85         /* make sure write buffer is drained */
  86         mb();
  87         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
  88         return 0;
  89 }
  90
  91 #ifdef CONFIG_HOTPLUG_CPU
  92 void ux500_cpu_die(unsigned int cpu)
  93 {
  94         wfi();
  95 }
  96 #endif
  97
  98 static const struct smp_operations ux500_smp_ops __initconst = {
  99         .smp_prepare_cpus       = ux500_smp_prepare_cpus,
 100         .smp_boot_secondary     = ux500_boot_secondary,
 101 #ifdef CONFIG_HOTPLUG_CPU
 102         .cpu_die                = ux500_cpu_die,
 103 #endif
 104 };
 105 CPU_METHOD_OF_DECLARE(ux500_smp, "ste,dbx500-smp", &ux500_smp_ops);