| blob | 30398dbc940a2218a2e9d792cb10b463a2d194c0 |
1 config ARM64
2 def_bool y
3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ACPI_MCFG if ACPI
7 select ACPI_SPCR_TABLE if ACPI
8 select ARCH_CLOCKSOURCE_DATA
9 select ARCH_HAS_DEVMEM_IS_ALLOWED
10 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
11 select ARCH_HAS_ELF_RANDOMIZE
12 select ARCH_HAS_GCOV_PROFILE_ALL
13 select ARCH_HAS_GIGANTIC_PAGE
14 select ARCH_HAS_KCOV
15 select ARCH_HAS_SG_CHAIN
16 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
17 select ARCH_USE_CMPXCHG_LOCKREF
18 select ARCH_SUPPORTS_ATOMIC_RMW
19 select ARCH_SUPPORTS_NUMA_BALANCING
20 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
21 select ARCH_WANT_FRAME_POINTERS
22 select ARCH_HAS_UBSAN_SANITIZE_ALL
23 select ARM_AMBA
24 select ARM_ARCH_TIMER
25 select ARM_GIC
26 select AUDIT_ARCH_COMPAT_GENERIC
27 select ARM_GIC_V2M if PCI
28 select ARM_GIC_V3
29 select ARM_GIC_V3_ITS if PCI
30 select ARM_PSCI_FW
31 select BUILDTIME_EXTABLE_SORT
32 select CLONE_BACKWARDS
33 select COMMON_CLK
34 select CPU_PM if (SUSPEND || CPU_IDLE)
35 select DCACHE_WORD_ACCESS
36 select EDAC_SUPPORT
37 select FRAME_POINTER
38 select GENERIC_ALLOCATOR
39 select GENERIC_CLOCKEVENTS
40 select GENERIC_CLOCKEVENTS_BROADCAST
41 select GENERIC_CPU_AUTOPROBE
42 select GENERIC_EARLY_IOREMAP
43 select GENERIC_IDLE_POLL_SETUP
44 select GENERIC_IRQ_PROBE
45 select GENERIC_IRQ_SHOW
46 select GENERIC_IRQ_SHOW_LEVEL
47 select GENERIC_PCI_IOMAP
48 select GENERIC_SCHED_CLOCK
49 select GENERIC_SMP_IDLE_THREAD
50 select GENERIC_STRNCPY_FROM_USER
51 select GENERIC_STRNLEN_USER
52 select GENERIC_TIME_VSYSCALL
53 select HANDLE_DOMAIN_IRQ
54 select HARDIRQS_SW_RESEND
55 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
56 select HAVE_ARCH_AUDITSYSCALL
57 select HAVE_ARCH_BITREVERSE
58 select HAVE_ARCH_HARDENED_USERCOPY
59 select HAVE_ARCH_HUGE_VMAP
60 select HAVE_ARCH_JUMP_LABEL
61 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
62 select HAVE_ARCH_KGDB
63 select HAVE_ARCH_MMAP_RND_BITS
64 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
65 select HAVE_ARCH_SECCOMP_FILTER
66 select HAVE_ARCH_TRACEHOOK
67 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
68 select HAVE_ARM_SMCCC
69 select HAVE_EBPF_JIT
70 select HAVE_C_RECORDMCOUNT
71 select HAVE_CC_STACKPROTECTOR
72 select HAVE_CMPXCHG_DOUBLE
73 select HAVE_CMPXCHG_LOCAL
74 select HAVE_CONTEXT_TRACKING
75 select HAVE_DEBUG_BUGVERBOSE
76 select HAVE_DEBUG_KMEMLEAK
77 select HAVE_DMA_API_DEBUG
78 select HAVE_DMA_CONTIGUOUS
79 select HAVE_DYNAMIC_FTRACE
80 select HAVE_EFFICIENT_UNALIGNED_ACCESS
81 select HAVE_FTRACE_MCOUNT_RECORD
82 select HAVE_FUNCTION_TRACER
83 select HAVE_FUNCTION_GRAPH_TRACER
84 select HAVE_GCC_PLUGINS
85 select HAVE_GENERIC_DMA_COHERENT
86 select HAVE_HW_BREAKPOINT if PERF_EVENTS
87 select HAVE_IRQ_TIME_ACCOUNTING
88 select HAVE_MEMBLOCK
89 select HAVE_MEMBLOCK_NODE_MAP if NUMA
90 select HAVE_PATA_PLATFORM
91 select HAVE_PERF_EVENTS
92 select HAVE_PERF_REGS
93 select HAVE_PERF_USER_STACK_DUMP
94 select HAVE_REGS_AND_STACK_ACCESS_API
95 select HAVE_RCU_TABLE_FREE
96 select HAVE_SYSCALL_TRACEPOINTS
97 select HAVE_KPROBES
98 select HAVE_KRETPROBES if HAVE_KPROBES
99 select IOMMU_DMA if IOMMU_SUPPORT
100 select IRQ_DOMAIN
101 select IRQ_FORCED_THREADING
102 select MODULES_USE_ELF_RELA
103 select NO_BOOTMEM
104 select OF
105 select OF_EARLY_FLATTREE
106 select OF_RESERVED_MEM
107 select PCI_ECAM if ACPI
108 select POWER_RESET
109 select POWER_SUPPLY
110 select SPARSE_IRQ
111 select SYSCTL_EXCEPTION_TRACE
112 help
113 ARM 64-bit (AArch64) Linux support.
115 config 64BIT
116 def_bool y
118 config ARCH_PHYS_ADDR_T_64BIT
119 def_bool y
121 config MMU
122 def_bool y
124 config DEBUG_RODATA
125 def_bool y
127 config ARM64_PAGE_SHIFT
128 int
129 default 16 if ARM64_64K_PAGES
130 default 14 if ARM64_16K_PAGES
131 default 12
133 config ARM64_CONT_SHIFT
134 int
135 default 5 if ARM64_64K_PAGES
136 default 7 if ARM64_16K_PAGES
137 default 4
139 config ARCH_MMAP_RND_BITS_MIN
140 default 14 if ARM64_64K_PAGES
141 default 16 if ARM64_16K_PAGES
142 default 18
144 # max bits determined by the following formula:
145 # VA_BITS - PAGE_SHIFT - 3
146 config ARCH_MMAP_RND_BITS_MAX
147 default 19 if ARM64_VA_BITS=36
148 default 24 if ARM64_VA_BITS=39
149 default 27 if ARM64_VA_BITS=42
150 default 30 if ARM64_VA_BITS=47
151 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
152 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
153 default 33 if ARM64_VA_BITS=48
154 default 14 if ARM64_64K_PAGES
155 default 16 if ARM64_16K_PAGES
156 default 18
158 config ARCH_MMAP_RND_COMPAT_BITS_MIN
159 default 7 if ARM64_64K_PAGES
160 default 9 if ARM64_16K_PAGES
161 default 11
163 config ARCH_MMAP_RND_COMPAT_BITS_MAX
164 default 16
166 config NO_IOPORT_MAP
167 def_bool y if !PCI
169 config STACKTRACE_SUPPORT
170 def_bool y
172 config ILLEGAL_POINTER_VALUE
173 hex
174 default 0xdead000000000000
176 config LOCKDEP_SUPPORT
177 def_bool y
179 config TRACE_IRQFLAGS_SUPPORT
180 def_bool y
182 config RWSEM_XCHGADD_ALGORITHM
183 def_bool y
185 config GENERIC_BUG
186 def_bool y
187 depends on BUG
189 config GENERIC_BUG_RELATIVE_POINTERS
190 def_bool y
191 depends on GENERIC_BUG
193 config GENERIC_HWEIGHT
194 def_bool y
196 config GENERIC_CSUM
197 def_bool y
199 config GENERIC_CALIBRATE_DELAY
200 def_bool y
202 config ZONE_DMA
203 def_bool y
205 config HAVE_GENERIC_RCU_GUP
206 def_bool y
208 config ARCH_DMA_ADDR_T_64BIT
209 def_bool y
211 config NEED_DMA_MAP_STATE
212 def_bool y
214 config NEED_SG_DMA_LENGTH
215 def_bool y
217 config SMP
218 def_bool y
220 config SWIOTLB
221 def_bool y
223 config IOMMU_HELPER
224 def_bool SWIOTLB
226 config KERNEL_MODE_NEON
227 def_bool y
229 config FIX_EARLYCON_MEM
230 def_bool y
232 config PGTABLE_LEVELS
233 int
234 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
235 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
236 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
237 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
238 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
239 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
241 source "init/Kconfig"
243 source "kernel/Kconfig.freezer"
245 source "arch/arm64/Kconfig.platforms"
247 menu "Bus support"
249 config PCI
250 bool "PCI support"
251 help
252 This feature enables support for PCI bus system. If you say Y
253 here, the kernel will include drivers and infrastructure code
254 to support PCI bus devices.
256 config PCI_DOMAINS
257 def_bool PCI
259 config PCI_DOMAINS_GENERIC
260 def_bool PCI
262 config PCI_SYSCALL
263 def_bool PCI
265 source "drivers/pci/Kconfig"
267 endmenu
269 menu "Kernel Features"
271 menu "ARM errata workarounds via the alternatives framework"
273 config ARM64_ERRATUM_826319
274 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
275 default y
276 help
277 This option adds an alternative code sequence to work around ARM
278 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
279 AXI master interface and an L2 cache.
281 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
282 and is unable to accept a certain write via this interface, it will
283 not progress on read data presented on the read data channel and the
284 system can deadlock.
286 The workaround promotes data cache clean instructions to
287 data cache clean-and-invalidate.
288 Please note that this does not necessarily enable the workaround,
289 as it depends on the alternative framework, which will only patch
290 the kernel if an affected CPU is detected.
292 If unsure, say Y.
294 config ARM64_ERRATUM_827319
295 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
296 default y
297 help
298 This option adds an alternative code sequence to work around ARM
299 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
300 master interface and an L2 cache.
302 Under certain conditions this erratum can cause a clean line eviction
303 to occur at the same time as another transaction to the same address
304 on the AMBA 5 CHI interface, which can cause data corruption if the
305 interconnect reorders the two transactions.
307 The workaround promotes data cache clean instructions to
308 data cache clean-and-invalidate.
309 Please note that this does not necessarily enable the workaround,
310 as it depends on the alternative framework, which will only patch
311 the kernel if an affected CPU is detected.
313 If unsure, say Y.
315 config ARM64_ERRATUM_824069
316 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
317 default y
318 help
319 This option adds an alternative code sequence to work around ARM
320 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
321 to a coherent interconnect.
323 If a Cortex-A53 processor is executing a store or prefetch for
324 write instruction at the same time as a processor in another
325 cluster is executing a cache maintenance operation to the same
326 address, then this erratum might cause a clean cache line to be
327 incorrectly marked as dirty.
329 The workaround promotes data cache clean instructions to
330 data cache clean-and-invalidate.
331 Please note that this option does not necessarily enable the
332 workaround, as it depends on the alternative framework, which will
333 only patch the kernel if an affected CPU is detected.
335 If unsure, say Y.
337 config ARM64_ERRATUM_819472
338 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
339 default y
340 help
341 This option adds an alternative code sequence to work around ARM
342 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
343 present when it is connected to a coherent interconnect.
345 If the processor is executing a load and store exclusive sequence at
346 the same time as a processor in another cluster is executing a cache
347 maintenance operation to the same address, then this erratum might
348 cause data corruption.
350 The workaround promotes data cache clean instructions to
351 data cache clean-and-invalidate.
352 Please note that this does not necessarily enable the workaround,
353 as it depends on the alternative framework, which will only patch
354 the kernel if an affected CPU is detected.
356 If unsure, say Y.
358 config ARM64_ERRATUM_832075
359 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
360 default y
361 help
362 This option adds an alternative code sequence to work around ARM
363 erratum 832075 on Cortex-A57 parts up to r1p2.
365 Affected Cortex-A57 parts might deadlock when exclusive load/store
366 instructions to Write-Back memory are mixed with Device loads.
368 The workaround is to promote device loads to use Load-Acquire
369 semantics.
370 Please note that this does not necessarily enable the workaround,
371 as it depends on the alternative framework, which will only patch
372 the kernel if an affected CPU is detected.
374 If unsure, say Y.
376 config ARM64_ERRATUM_834220
377 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
378 depends on KVM
379 default y
380 help
381 This option adds an alternative code sequence to work around ARM
382 erratum 834220 on Cortex-A57 parts up to r1p2.
384 Affected Cortex-A57 parts might report a Stage 2 translation
385 fault as the result of a Stage 1 fault for load crossing a
386 page boundary when there is a permission or device memory
387 alignment fault at Stage 1 and a translation fault at Stage 2.
389 The workaround is to verify that the Stage 1 translation
390 doesn't generate a fault before handling the Stage 2 fault.
391 Please note that this does not necessarily enable the workaround,
392 as it depends on the alternative framework, which will only patch
393 the kernel if an affected CPU is detected.
395 If unsure, say Y.
397 config ARM64_ERRATUM_845719
398 bool "Cortex-A53: 845719: a load might read incorrect data"
399 depends on COMPAT
400 default y
401 help
402 This option adds an alternative code sequence to work around ARM
403 erratum 845719 on Cortex-A53 parts up to r0p4.
405 When running a compat (AArch32) userspace on an affected Cortex-A53
406 part, a load at EL0 from a virtual address that matches the bottom 32
407 bits of the virtual address used by a recent load at (AArch64) EL1
408 might return incorrect data.
410 The workaround is to write the contextidr_el1 register on exception
411 return to a 32-bit task.
412 Please note that this does not necessarily enable the workaround,
413 as it depends on the alternative framework, which will only patch
414 the kernel if an affected CPU is detected.
416 If unsure, say Y.
418 config ARM64_ERRATUM_843419
419 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
420 default y
421 select ARM64_MODULE_CMODEL_LARGE if MODULES
422 help
423 This option links the kernel with '--fix-cortex-a53-843419' and
424 builds modules using the large memory model in order to avoid the use
425 of the ADRP instruction, which can cause a subsequent memory access
426 to use an incorrect address on Cortex-A53 parts up to r0p4.
428 If unsure, say Y.
430 config CAVIUM_ERRATUM_22375
431 bool "Cavium erratum 22375, 24313"
432 default y
433 help
434 Enable workaround for erratum 22375, 24313.
436 This implements two gicv3-its errata workarounds for ThunderX. Both
437 with small impact affecting only ITS table allocation.
439 erratum 22375: only alloc 8MB table size
440 erratum 24313: ignore memory access type
442 The fixes are in ITS initialization and basically ignore memory access
443 type and table size provided by the TYPER and BASER registers.
445 If unsure, say Y.
447 config CAVIUM_ERRATUM_23144
448 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
449 depends on NUMA
450 default y
451 help
452 ITS SYNC command hang for cross node io and collections/cpu mapping.
454 If unsure, say Y.
456 config CAVIUM_ERRATUM_23154
457 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
458 default y
459 help
460 The gicv3 of ThunderX requires a modified version for
461 reading the IAR status to ensure data synchronization
462 (access to icc_iar1_el1 is not sync'ed before and after).
464 If unsure, say Y.
466 config CAVIUM_ERRATUM_27456
467 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
468 default y
469 help
470 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
471 instructions may cause the icache to become corrupted if it
472 contains data for a non-current ASID. The fix is to
473 invalidate the icache when changing the mm context.
475 If unsure, say Y.
477 endmenu
480 choice
481 prompt "Page size"
482 default ARM64_4K_PAGES
483 help
484 Page size (translation granule) configuration.
486 config ARM64_4K_PAGES
487 bool "4KB"
488 help
489 This feature enables 4KB pages support.
491 config ARM64_16K_PAGES
492 bool "16KB"
493 help
494 The system will use 16KB pages support. AArch32 emulation
495 requires applications compiled with 16K (or a multiple of 16K)
496 aligned segments.
498 config ARM64_64K_PAGES
499 bool "64KB"
500 help
501 This feature enables 64KB pages support (4KB by default)
502 allowing only two levels of page tables and faster TLB
503 look-up. AArch32 emulation requires applications compiled
504 with 64K aligned segments.
506 endchoice
508 choice
509 prompt "Virtual address space size"
510 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
511 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
512 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
513 help
514 Allows choosing one of multiple possible virtual address
515 space sizes. The level of translation table is determined by
516 a combination of page size and virtual address space size.
518 config ARM64_VA_BITS_36
519 bool "36-bit" if EXPERT
520 depends on ARM64_16K_PAGES
522 config ARM64_VA_BITS_39
523 bool "39-bit"
524 depends on ARM64_4K_PAGES
526 config ARM64_VA_BITS_42
527 bool "42-bit"
528 depends on ARM64_64K_PAGES
530 config ARM64_VA_BITS_47
531 bool "47-bit"
532 depends on ARM64_16K_PAGES
534 config ARM64_VA_BITS_48
535 bool "48-bit"
537 endchoice
539 config ARM64_VA_BITS
540 int
541 default 36 if ARM64_VA_BITS_36
542 default 39 if ARM64_VA_BITS_39
543 default 42 if ARM64_VA_BITS_42
544 default 47 if ARM64_VA_BITS_47
545 default 48 if ARM64_VA_BITS_48
547 config CPU_BIG_ENDIAN
548 bool "Build big-endian kernel"
549 help
550 Say Y if you plan on running a kernel in big-endian mode.
552 config SCHED_MC
553 bool "Multi-core scheduler support"
554 help
555 Multi-core scheduler support improves the CPU scheduler's decision
556 making when dealing with multi-core CPU chips at a cost of slightly
557 increased overhead in some places. If unsure say N here.
559 config SCHED_SMT
560 bool "SMT scheduler support"
561 help
562 Improves the CPU scheduler's decision making when dealing with
563 MultiThreading at a cost of slightly increased overhead in some
564 places. If unsure say N here.
566 config NR_CPUS
567 int "Maximum number of CPUs (2-4096)"
568 range 2 4096
569 # These have to remain sorted largest to smallest
570 default "64"
572 config HOTPLUG_CPU
573 bool "Support for hot-pluggable CPUs"
574 select GENERIC_IRQ_MIGRATION
575 help
576 Say Y here to experiment with turning CPUs off and on. CPUs
577 can be controlled through /sys/devices/system/cpu.
579 # Common NUMA Features
580 config NUMA
581 bool "Numa Memory Allocation and Scheduler Support"
582 select ACPI_NUMA if ACPI
583 select OF_NUMA
584 help
585 Enable NUMA (Non Uniform Memory Access) support.
587 The kernel will try to allocate memory used by a CPU on the
588 local memory of the CPU and add some more
589 NUMA awareness to the kernel.
591 config NODES_SHIFT
592 int "Maximum NUMA Nodes (as a power of 2)"
593 range 1 10
594 default "2"
595 depends on NEED_MULTIPLE_NODES
596 help
597 Specify the maximum number of NUMA Nodes available on the target
598 system. Increases memory reserved to accommodate various tables.
600 config USE_PERCPU_NUMA_NODE_ID
601 def_bool y
602 depends on NUMA
604 config HAVE_SETUP_PER_CPU_AREA
605 def_bool y
606 depends on NUMA
608 config NEED_PER_CPU_EMBED_FIRST_CHUNK
609 def_bool y
610 depends on NUMA
612 source kernel/Kconfig.preempt
613 source kernel/Kconfig.hz
615 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
616 def_bool y
618 config ARCH_HAS_HOLES_MEMORYMODEL
619 def_bool y if SPARSEMEM
621 config ARCH_SPARSEMEM_ENABLE
622 def_bool y
623 select SPARSEMEM_VMEMMAP_ENABLE
625 config ARCH_SPARSEMEM_DEFAULT
626 def_bool ARCH_SPARSEMEM_ENABLE
628 config ARCH_SELECT_MEMORY_MODEL
629 def_bool ARCH_SPARSEMEM_ENABLE
631 config HAVE_ARCH_PFN_VALID
632 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
634 config HW_PERF_EVENTS
635 def_bool y
636 depends on ARM_PMU
638 config SYS_SUPPORTS_HUGETLBFS
639 def_bool y
641 config ARCH_WANT_HUGE_PMD_SHARE
642 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
644 config ARCH_HAS_CACHE_LINE_SIZE
645 def_bool y
647 source "mm/Kconfig"
649 config SECCOMP
650 bool "Enable seccomp to safely compute untrusted bytecode"
651 ---help---
652 This kernel feature is useful for number crunching applications
653 that may need to compute untrusted bytecode during their
654 execution. By using pipes or other transports made available to
655 the process as file descriptors supporting the read/write
656 syscalls, it's possible to isolate those applications in
657 their own address space using seccomp. Once seccomp is
658 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
659 and the task is only allowed to execute a few safe syscalls
660 defined by each seccomp mode.
662 config PARAVIRT
663 bool "Enable paravirtualization code"
664 help
665 This changes the kernel so it can modify itself when it is run
666 under a hypervisor, potentially improving performance significantly
667 over full virtualization.
669 config PARAVIRT_TIME_ACCOUNTING
670 bool "Paravirtual steal time accounting"
671 select PARAVIRT
672 default n
673 help
674 Select this option to enable fine granularity task steal time
675 accounting. Time spent executing other tasks in parallel with
676 the current vCPU is discounted from the vCPU power. To account for
677 that, there can be a small performance impact.
679 If in doubt, say N here.
681 config KEXEC
682 depends on PM_SLEEP_SMP
683 select KEXEC_CORE
684 bool "kexec system call"
685 ---help---
686 kexec is a system call that implements the ability to shutdown your
687 current kernel, and to start another kernel. It is like a reboot
688 but it is independent of the system firmware. And like a reboot
689 you can start any kernel with it, not just Linux.
691 config XEN_DOM0
692 def_bool y
693 depends on XEN
695 config XEN
696 bool "Xen guest support on ARM64"
697 depends on ARM64 && OF
698 select SWIOTLB_XEN
699 select PARAVIRT
700 help
701 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
703 config FORCE_MAX_ZONEORDER
704 int
705 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
706 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
707 default "11"
708 help
709 The kernel memory allocator divides physically contiguous memory
710 blocks into "zones", where each zone is a power of two number of
711 pages. This option selects the largest power of two that the kernel
712 keeps in the memory allocator. If you need to allocate very large
713 blocks of physically contiguous memory, then you may need to
714 increase this value.
716 This config option is actually maximum order plus one. For example,
717 a value of 11 means that the largest free memory block is 2^10 pages.
719 We make sure that we can allocate upto a HugePage size for each configuration.
720 Hence we have :
721 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
723 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
724 4M allocations matching the default size used by generic code.
726 menuconfig ARMV8_DEPRECATED
727 bool "Emulate deprecated/obsolete ARMv8 instructions"
728 depends on COMPAT
729 help
730 Legacy software support may require certain instructions
731 that have been deprecated or obsoleted in the architecture.
733 Enable this config to enable selective emulation of these
734 features.
736 If unsure, say Y
738 if ARMV8_DEPRECATED
740 config SWP_EMULATION
741 bool "Emulate SWP/SWPB instructions"
742 help
743 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
744 they are always undefined. Say Y here to enable software
745 emulation of these instructions for userspace using LDXR/STXR.
747 In some older versions of glibc [<=2.8] SWP is used during futex
748 trylock() operations with the assumption that the code will not
749 be preempted. This invalid assumption may be more likely to fail
750 with SWP emulation enabled, leading to deadlock of the user
751 application.
753 NOTE: when accessing uncached shared regions, LDXR/STXR rely
754 on an external transaction monitoring block called a global
755 monitor to maintain update atomicity. If your system does not
756 implement a global monitor, this option can cause programs that
757 perform SWP operations to uncached memory to deadlock.
759 If unsure, say Y
761 config CP15_BARRIER_EMULATION
762 bool "Emulate CP15 Barrier instructions"
763 help
764 The CP15 barrier instructions - CP15ISB, CP15DSB, and
765 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
766 strongly recommended to use the ISB, DSB, and DMB
767 instructions instead.
769 Say Y here to enable software emulation of these
770 instructions for AArch32 userspace code. When this option is
771 enabled, CP15 barrier usage is traced which can help
772 identify software that needs updating.
774 If unsure, say Y
776 config SETEND_EMULATION
777 bool "Emulate SETEND instruction"
778 help
779 The SETEND instruction alters the data-endianness of the
780 AArch32 EL0, and is deprecated in ARMv8.
782 Say Y here to enable software emulation of the instruction
783 for AArch32 userspace code.
785 Note: All the cpus on the system must have mixed endian support at EL0
786 for this feature to be enabled. If a new CPU - which doesn't support mixed
787 endian - is hotplugged in after this feature has been enabled, there could
788 be unexpected results in the applications.
790 If unsure, say Y
791 endif
793 menu "ARMv8.1 architectural features"
795 config ARM64_HW_AFDBM
796 bool "Support for hardware updates of the Access and Dirty page flags"
797 default y
798 help
799 The ARMv8.1 architecture extensions introduce support for
800 hardware updates of the access and dirty information in page
801 table entries. When enabled in TCR_EL1 (HA and HD bits) on
802 capable processors, accesses to pages with PTE_AF cleared will
803 set this bit instead of raising an access flag fault.
804 Similarly, writes to read-only pages with the DBM bit set will
805 clear the read-only bit (AP[2]) instead of raising a
806 permission fault.
808 Kernels built with this configuration option enabled continue
809 to work on pre-ARMv8.1 hardware and the performance impact is
810 minimal. If unsure, say Y.
812 config ARM64_PAN
813 bool "Enable support for Privileged Access Never (PAN)"
814 default y
815 help
816 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
817 prevents the kernel or hypervisor from accessing user-space (EL0)
818 memory directly.
820 Choosing this option will cause any unprotected (not using
821 copy_to_user et al) memory access to fail with a permission fault.
823 The feature is detected at runtime, and will remain as a 'nop'
824 instruction if the cpu does not implement the feature.
826 config ARM64_LSE_ATOMICS
827 bool "Atomic instructions"
828 help
829 As part of the Large System Extensions, ARMv8.1 introduces new
830 atomic instructions that are designed specifically to scale in
831 very large systems.
833 Say Y here to make use of these instructions for the in-kernel
834 atomic routines. This incurs a small overhead on CPUs that do
835 not support these instructions and requires the kernel to be
836 built with binutils >= 2.25.
838 config ARM64_VHE
839 bool "Enable support for Virtualization Host Extensions (VHE)"
840 default y
841 help
842 Virtualization Host Extensions (VHE) allow the kernel to run
843 directly at EL2 (instead of EL1) on processors that support
844 it. This leads to better performance for KVM, as they reduce
845 the cost of the world switch.
847 Selecting this option allows the VHE feature to be detected
848 at runtime, and does not affect processors that do not
849 implement this feature.
851 endmenu
853 menu "ARMv8.2 architectural features"
855 config ARM64_UAO
856 bool "Enable support for User Access Override (UAO)"
857 default y
858 help
859 User Access Override (UAO; part of the ARMv8.2 Extensions)
860 causes the 'unprivileged' variant of the load/store instructions to
861 be overriden to be privileged.
863 This option changes get_user() and friends to use the 'unprivileged'
864 variant of the load/store instructions. This ensures that user-space
865 really did have access to the supplied memory. When addr_limit is
866 set to kernel memory the UAO bit will be set, allowing privileged
867 access to kernel memory.
869 Choosing this option will cause copy_to_user() et al to use user-space
870 memory permissions.
872 The feature is detected at runtime, the kernel will use the
873 regular load/store instructions if the cpu does not implement the
874 feature.
876 endmenu
878 config ARM64_MODULE_CMODEL_LARGE
879 bool
881 config ARM64_MODULE_PLTS
882 bool
883 select ARM64_MODULE_CMODEL_LARGE
884 select HAVE_MOD_ARCH_SPECIFIC
886 config RELOCATABLE
887 bool
888 help
889 This builds the kernel as a Position Independent Executable (PIE),
890 which retains all relocation metadata required to relocate the
891 kernel binary at runtime to a different virtual address than the
892 address it was linked at.
893 Since AArch64 uses the RELA relocation format, this requires a
894 relocation pass at runtime even if the kernel is loaded at the
895 same address it was linked at.
897 config RANDOMIZE_BASE
898 bool "Randomize the address of the kernel image"
899 select ARM64_MODULE_PLTS if MODULES
900 select RELOCATABLE
901 help
902 Randomizes the virtual address at which the kernel image is
903 loaded, as a security feature that deters exploit attempts
904 relying on knowledge of the location of kernel internals.
906 It is the bootloader's job to provide entropy, by passing a
907 random u64 value in /chosen/kaslr-seed at kernel entry.
909 When booting via the UEFI stub, it will invoke the firmware's
910 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
911 to the kernel proper. In addition, it will randomise the physical
912 location of the kernel Image as well.
914 If unsure, say N.
916 config RANDOMIZE_MODULE_REGION_FULL
917 bool "Randomize the module region independently from the core kernel"
918 depends on RANDOMIZE_BASE
919 default y
920 help
921 Randomizes the location of the module region without considering the
922 location of the core kernel. This way, it is impossible for modules
923 to leak information about the location of core kernel data structures
924 but it does imply that function calls between modules and the core
925 kernel will need to be resolved via veneers in the module PLT.
927 When this option is not set, the module region will be randomized over
928 a limited range that contains the [_stext, _etext] interval of the
929 core kernel, so branch relocations are always in range.
931 endmenu
933 menu "Boot options"
935 config ARM64_ACPI_PARKING_PROTOCOL
936 bool "Enable support for the ARM64 ACPI parking protocol"
937 depends on ACPI
938 help
939 Enable support for the ARM64 ACPI parking protocol. If disabled
940 the kernel will not allow booting through the ARM64 ACPI parking
941 protocol even if the corresponding data is present in the ACPI
942 MADT table.
944 config CMDLINE
945 string "Default kernel command string"
946 default ""
947 help
948 Provide a set of default command-line options at build time by
949 entering them here. As a minimum, you should specify the the
950 root device (e.g. root=/dev/nfs).
952 config CMDLINE_FORCE
953 bool "Always use the default kernel command string"
954 help
955 Always use the default kernel command string, even if the boot
956 loader passes other arguments to the kernel.
957 This is useful if you cannot or don't want to change the
958 command-line options your boot loader passes to the kernel.
960 config EFI_STUB
961 bool
963 config EFI
964 bool "UEFI runtime support"
965 depends on OF && !CPU_BIG_ENDIAN
966 select LIBFDT
967 select UCS2_STRING
968 select EFI_PARAMS_FROM_FDT
969 select EFI_RUNTIME_WRAPPERS
970 select EFI_STUB
971 select EFI_ARMSTUB
972 default y
973 help
974 This option provides support for runtime services provided
975 by UEFI firmware (such as non-volatile variables, realtime
976 clock, and platform reset). A UEFI stub is also provided to
977 allow the kernel to be booted as an EFI application. This
978 is only useful on systems that have UEFI firmware.
980 config DMI
981 bool "Enable support for SMBIOS (DMI) tables"
982 depends on EFI
983 default y
984 help
985 This enables SMBIOS/DMI feature for systems.
987 This option is only useful on systems that have UEFI firmware.
988 However, even with this option, the resultant kernel should
989 continue to boot on existing non-UEFI platforms.
991 endmenu
993 menu "Userspace binary formats"
995 source "fs/Kconfig.binfmt"
997 config COMPAT
998 bool "Kernel support for 32-bit EL0"
999 depends on ARM64_4K_PAGES || EXPERT
1000 select COMPAT_BINFMT_ELF
1001 select HAVE_UID16
1002 select OLD_SIGSUSPEND3
1003 select COMPAT_OLD_SIGACTION
1004 help
1005 This option enables support for a 32-bit EL0 running under a 64-bit
1006 kernel at EL1. AArch32-specific components such as system calls,
1007 the user helper functions, VFP support and the ptrace interface are
1008 handled appropriately by the kernel.
1010 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1011 that you will only be able to execute AArch32 binaries that were compiled
1012 with page size aligned segments.
1014 If you want to execute 32-bit userspace applications, say Y.
1016 config SYSVIPC_COMPAT
1017 def_bool y
1018 depends on COMPAT && SYSVIPC
1020 endmenu
1022 menu "Power management options"
1024 source "kernel/power/Kconfig"
1026 config ARCH_HIBERNATION_POSSIBLE
1027 def_bool y
1028 depends on CPU_PM
1030 config ARCH_HIBERNATION_HEADER
1031 def_bool y
1032 depends on HIBERNATION
1034 config ARCH_SUSPEND_POSSIBLE
1035 def_bool y
1037 endmenu
1039 menu "CPU Power Management"
1041 source "drivers/cpuidle/Kconfig"
1043 source "drivers/cpufreq/Kconfig"
1045 endmenu
1047 source "net/Kconfig"
1049 source "drivers/Kconfig"
1051 source "drivers/firmware/Kconfig"
1053 source "drivers/acpi/Kconfig"
1055 source "fs/Kconfig"
1057 source "arch/arm64/kvm/Kconfig"
1059 source "arch/arm64/Kconfig.debug"
1061 source "security/Kconfig"
1063 source "crypto/Kconfig"
1064 if CRYPTO
1065 source "arch/arm64/crypto/Kconfig"
1066 endif
1068 source "lib/Kconfig"