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MIPS: Add DINSM to uasm.
[linux/fpc-iii.git] / arch / mips / mm / uasm.c
blob99f0347e82d23c067e35537d14e5036d62f6dcbd
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
9 *
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/init.h>
18
19 #include <asm/inst.h>
20 #include <asm/elf.h>
21 #include <asm/bugs.h>
22 #include <asm/uasm.h>
23
24 enum fields {
25 RS = 0x001,
26 RT = 0x002,
27 RD = 0x004,
28 RE = 0x008,
29 SIMM = 0x010,
30 UIMM = 0x020,
31 BIMM = 0x040,
32 JIMM = 0x080,
33 FUNC = 0x100,
34 SET = 0x200,
35 SCIMM = 0x400
36 };
37
38 #define OP_MASK 0x3f
39 #define OP_SH 26
40 #define RS_MASK 0x1f
41 #define RS_SH 21
42 #define RT_MASK 0x1f
43 #define RT_SH 16
44 #define RD_MASK 0x1f
45 #define RD_SH 11
46 #define RE_MASK 0x1f
47 #define RE_SH 6
48 #define IMM_MASK 0xffff
49 #define IMM_SH 0
50 #define JIMM_MASK 0x3ffffff
51 #define JIMM_SH 0
52 #define FUNC_MASK 0x3f
53 #define FUNC_SH 0
54 #define SET_MASK 0x7
55 #define SET_SH 0
56 #define SCIMM_MASK 0xfffff
57 #define SCIMM_SH 6
58
59 enum opcode {
60 insn_invalid,
61 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
62 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
63 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
64 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
65 insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret,
66 insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld,
67 insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori,
68 insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
69 insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp,
70 insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
71 insn_dins, insn_dinsm, insn_syscall, insn_bbit0, insn_bbit1
72 };
73
74 struct insn {
75 enum opcode opcode;
76 u32 match;
77 enum fields fields;
78 };
79
80 /* This macro sets the non-variable bits of an instruction. */
81 #define M(a, b, c, d, e, f) \
82 ((a) << OP_SH \
83 | (b) << RS_SH \
84 | (c) << RT_SH \
85 | (d) << RD_SH \
86 | (e) << RE_SH \
87 | (f) << FUNC_SH)
88
89 static struct insn insn_table[] __uasminitdata = {
90 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
91 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
92 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
93 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
94 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
95 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
96 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
97 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
98 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
99 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
100 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
101 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
102 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
103 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
104 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
105 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
106 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
107 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
108 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
109 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
110 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
111 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
112 { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
113 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
114 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
115 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
116 { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
117 { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
118 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
119 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
120 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
121 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
122 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
123 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
124 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
125 { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
126 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
127 { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
128 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
129 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
130 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
131 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
132 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
133 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
134 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
135 { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
136 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
137 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
138 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
139 { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 },
140 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
141 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
142 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
143 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
144 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
145 { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
146 { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
147 { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
148 { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
149 { insn_invalid, 0, 0 }
150 };
151
152 #undef M
153
154 static inline __uasminit u32 build_rs(u32 arg)
155 {
156 if (arg & ~RS_MASK)
157 printk(KERN_WARNING "Micro-assembler field overflow\n");
158
159 return (arg & RS_MASK) << RS_SH;
160 }
161
162 static inline __uasminit u32 build_rt(u32 arg)
163 {
164 if (arg & ~RT_MASK)
165 printk(KERN_WARNING "Micro-assembler field overflow\n");
166
167 return (arg & RT_MASK) << RT_SH;
168 }
169
170 static inline __uasminit u32 build_rd(u32 arg)
171 {
172 if (arg & ~RD_MASK)
173 printk(KERN_WARNING "Micro-assembler field overflow\n");
174
175 return (arg & RD_MASK) << RD_SH;
176 }
177
178 static inline __uasminit u32 build_re(u32 arg)
179 {
180 if (arg & ~RE_MASK)
181 printk(KERN_WARNING "Micro-assembler field overflow\n");
182
183 return (arg & RE_MASK) << RE_SH;
184 }
185
186 static inline __uasminit u32 build_simm(s32 arg)
187 {
188 if (arg > 0x7fff || arg < -0x8000)
189 printk(KERN_WARNING "Micro-assembler field overflow\n");
190
191 return arg & 0xffff;
192 }
193
194 static inline __uasminit u32 build_uimm(u32 arg)
195 {
196 if (arg & ~IMM_MASK)
197 printk(KERN_WARNING "Micro-assembler field overflow\n");
198
199 return arg & IMM_MASK;
200 }
201
202 static inline __uasminit u32 build_bimm(s32 arg)
203 {
204 if (arg > 0x1ffff || arg < -0x20000)
205 printk(KERN_WARNING "Micro-assembler field overflow\n");
206
207 if (arg & 0x3)
208 printk(KERN_WARNING "Invalid micro-assembler branch target\n");
209
210 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
211 }
212
213 static inline __uasminit u32 build_jimm(u32 arg)
214 {
215 if (arg & ~((JIMM_MASK) << 2))
216 printk(KERN_WARNING "Micro-assembler field overflow\n");
217
218 return (arg >> 2) & JIMM_MASK;
219 }
220
221 static inline __uasminit u32 build_scimm(u32 arg)
222 {
223 if (arg & ~SCIMM_MASK)
224 printk(KERN_WARNING "Micro-assembler field overflow\n");
225
226 return (arg & SCIMM_MASK) << SCIMM_SH;
227 }
228
229 static inline __uasminit u32 build_func(u32 arg)
230 {
231 if (arg & ~FUNC_MASK)
232 printk(KERN_WARNING "Micro-assembler field overflow\n");
233
234 return arg & FUNC_MASK;
235 }
236
237 static inline __uasminit u32 build_set(u32 arg)
238 {
239 if (arg & ~SET_MASK)
240 printk(KERN_WARNING "Micro-assembler field overflow\n");
241
242 return arg & SET_MASK;
243 }
244
245 /*
246 * The order of opcode arguments is implicitly left to right,
247 * starting with RS and ending with FUNC or IMM.
248 */
249 static void __uasminit build_insn(u32 **buf, enum opcode opc, ...)
250 {
251 struct insn *ip = NULL;
252 unsigned int i;
253 va_list ap;
254 u32 op;
255
256 for (i = 0; insn_table[i].opcode != insn_invalid; i++)
257 if (insn_table[i].opcode == opc) {
258 ip = &insn_table[i];
259 break;
260 }
261
262 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
263 panic("Unsupported Micro-assembler instruction %d", opc);
264
265 op = ip->match;
266 va_start(ap, opc);
267 if (ip->fields & RS)
268 op |= build_rs(va_arg(ap, u32));
269 if (ip->fields & RT)
270 op |= build_rt(va_arg(ap, u32));
271 if (ip->fields & RD)
272 op |= build_rd(va_arg(ap, u32));
273 if (ip->fields & RE)
274 op |= build_re(va_arg(ap, u32));
275 if (ip->fields & SIMM)
276 op |= build_simm(va_arg(ap, s32));
277 if (ip->fields & UIMM)
278 op |= build_uimm(va_arg(ap, u32));
279 if (ip->fields & BIMM)
280 op |= build_bimm(va_arg(ap, s32));
281 if (ip->fields & JIMM)
282 op |= build_jimm(va_arg(ap, u32));
283 if (ip->fields & FUNC)
284 op |= build_func(va_arg(ap, u32));
285 if (ip->fields & SET)
286 op |= build_set(va_arg(ap, u32));
287 if (ip->fields & SCIMM)
288 op |= build_scimm(va_arg(ap, u32));
289 va_end(ap);
290
291 **buf = op;
292 (*buf)++;
293 }
294
295 #define I_u1u2u3(op) \
296 Ip_u1u2u3(op) \
297 { \
298 build_insn(buf, insn##op, a, b, c); \
299 } \
300 UASM_EXPORT_SYMBOL(uasm_i##op);
301
302 #define I_u2u1u3(op) \
303 Ip_u2u1u3(op) \
304 { \
305 build_insn(buf, insn##op, b, a, c); \
306 } \
307 UASM_EXPORT_SYMBOL(uasm_i##op);
308
309 #define I_u3u1u2(op) \
310 Ip_u3u1u2(op) \
311 { \
312 build_insn(buf, insn##op, b, c, a); \
313 } \
314 UASM_EXPORT_SYMBOL(uasm_i##op);
315
316 #define I_u1u2s3(op) \
317 Ip_u1u2s3(op) \
318 { \
319 build_insn(buf, insn##op, a, b, c); \
320 } \
321 UASM_EXPORT_SYMBOL(uasm_i##op);
322
323 #define I_u2s3u1(op) \
324 Ip_u2s3u1(op) \
325 { \
326 build_insn(buf, insn##op, c, a, b); \
327 } \
328 UASM_EXPORT_SYMBOL(uasm_i##op);
329
330 #define I_u2u1s3(op) \
331 Ip_u2u1s3(op) \
332 { \
333 build_insn(buf, insn##op, b, a, c); \
334 } \
335 UASM_EXPORT_SYMBOL(uasm_i##op);
336
337 #define I_u2u1msbu3(op) \
338 Ip_u2u1msbu3(op) \
339 { \
340 build_insn(buf, insn##op, b, a, c+d-1, c); \
341 } \
342 UASM_EXPORT_SYMBOL(uasm_i##op);
343
344 #define I_u2u1msb32u3(op) \
345 Ip_u2u1msbu3(op) \
346 { \
347 build_insn(buf, insn##op, b, a, c+d-33, c); \
348 } \
349 UASM_EXPORT_SYMBOL(uasm_i##op);
350
351 #define I_u1u2(op) \
352 Ip_u1u2(op) \
353 { \
354 build_insn(buf, insn##op, a, b); \
355 } \
356 UASM_EXPORT_SYMBOL(uasm_i##op);
357
358 #define I_u1s2(op) \
359 Ip_u1s2(op) \
360 { \
361 build_insn(buf, insn##op, a, b); \
362 } \
363 UASM_EXPORT_SYMBOL(uasm_i##op);
364
365 #define I_u1(op) \
366 Ip_u1(op) \
367 { \
368 build_insn(buf, insn##op, a); \
369 } \
370 UASM_EXPORT_SYMBOL(uasm_i##op);
371
372 #define I_0(op) \
373 Ip_0(op) \
374 { \
375 build_insn(buf, insn##op); \
376 } \
377 UASM_EXPORT_SYMBOL(uasm_i##op);
378
379 I_u2u1s3(_addiu)
380 I_u3u1u2(_addu)
381 I_u2u1u3(_andi)
382 I_u3u1u2(_and)
383 I_u1u2s3(_beq)
384 I_u1u2s3(_beql)
385 I_u1s2(_bgez)
386 I_u1s2(_bgezl)
387 I_u1s2(_bltz)
388 I_u1s2(_bltzl)
389 I_u1u2s3(_bne)
390 I_u2s3u1(_cache)
391 I_u1u2u3(_dmfc0)
392 I_u1u2u3(_dmtc0)
393 I_u2u1s3(_daddiu)
394 I_u3u1u2(_daddu)
395 I_u2u1u3(_dsll)
396 I_u2u1u3(_dsll32)
397 I_u2u1u3(_dsra)
398 I_u2u1u3(_dsrl)
399 I_u2u1u3(_dsrl32)
400 I_u2u1u3(_drotr)
401 I_u2u1u3(_drotr32)
402 I_u3u1u2(_dsubu)
403 I_0(_eret)
404 I_u1(_j)
405 I_u1(_jal)
406 I_u1(_jr)
407 I_u2s3u1(_ld)
408 I_u2s3u1(_ll)
409 I_u2s3u1(_lld)
410 I_u1s2(_lui)
411 I_u2s3u1(_lw)
412 I_u1u2u3(_mfc0)
413 I_u1u2u3(_mtc0)
414 I_u2u1u3(_ori)
415 I_u3u1u2(_or)
416 I_0(_rfe)
417 I_u2s3u1(_sc)
418 I_u2s3u1(_scd)
419 I_u2s3u1(_sd)
420 I_u2u1u3(_sll)
421 I_u2u1u3(_sra)
422 I_u2u1u3(_srl)
423 I_u2u1u3(_rotr)
424 I_u3u1u2(_subu)
425 I_u2s3u1(_sw)
426 I_0(_tlbp)
427 I_0(_tlbr)
428 I_0(_tlbwi)
429 I_0(_tlbwr)
430 I_u3u1u2(_xor)
431 I_u2u1u3(_xori)
432 I_u2u1msbu3(_dins);
433 I_u2u1msb32u3(_dinsm);
434 I_u1(_syscall);
435 I_u1u2s3(_bbit0);
436 I_u1u2s3(_bbit1);
437
438 #ifdef CONFIG_CPU_CAVIUM_OCTEON
439 #include <asm/octeon/octeon.h>
440 void __uasminit uasm_i_pref(u32 **buf, unsigned int a, signed int b,
441 unsigned int c)
442 {
443 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
444 /*
445 * As per erratum Core-14449, replace prefetches 0-4,
446 * 6-24 with 'pref 28'.
447 */
448 build_insn(buf, insn_pref, c, 28, b);
449 else
450 build_insn(buf, insn_pref, c, a, b);
451 }
452 UASM_EXPORT_SYMBOL(uasm_i_pref);
453 #else
454 I_u2s3u1(_pref)
455 #endif
456
457 /* Handle labels. */
458 void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
459 {
460 (*lab)->addr = addr;
461 (*lab)->lab = lid;
462 (*lab)++;
463 }
464 UASM_EXPORT_SYMBOL(uasm_build_label);
465
466 int __uasminit uasm_in_compat_space_p(long addr)
467 {
468 /* Is this address in 32bit compat space? */
469 #ifdef CONFIG_64BIT
470 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
471 #else
472 return 1;
473 #endif
474 }
475 UASM_EXPORT_SYMBOL(uasm_in_compat_space_p);
476
477 static int __uasminit uasm_rel_highest(long val)
478 {
479 #ifdef CONFIG_64BIT
480 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
481 #else
482 return 0;
483 #endif
484 }
485
486 static int __uasminit uasm_rel_higher(long val)
487 {
488 #ifdef CONFIG_64BIT
489 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
490 #else
491 return 0;
492 #endif
493 }
494
495 int __uasminit uasm_rel_hi(long val)
496 {
497 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
498 }
499 UASM_EXPORT_SYMBOL(uasm_rel_hi);
500
501 int __uasminit uasm_rel_lo(long val)
502 {
503 return ((val & 0xffff) ^ 0x8000) - 0x8000;
504 }
505 UASM_EXPORT_SYMBOL(uasm_rel_lo);
506
507 void __uasminit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
508 {
509 if (!uasm_in_compat_space_p(addr)) {
510 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
511 if (uasm_rel_higher(addr))
512 uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
513 if (uasm_rel_hi(addr)) {
514 uasm_i_dsll(buf, rs, rs, 16);
515 uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr));
516 uasm_i_dsll(buf, rs, rs, 16);
517 } else
518 uasm_i_dsll32(buf, rs, rs, 0);
519 } else
520 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
521 }
522 UASM_EXPORT_SYMBOL(UASM_i_LA_mostly);
523
524 void __uasminit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
525 {
526 UASM_i_LA_mostly(buf, rs, addr);
527 if (uasm_rel_lo(addr)) {
528 if (!uasm_in_compat_space_p(addr))
529 uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr));
530 else
531 uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
532 }
533 }
534 UASM_EXPORT_SYMBOL(UASM_i_LA);
535
536 /* Handle relocations. */
537 void __uasminit
538 uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
539 {
540 (*rel)->addr = addr;
541 (*rel)->type = R_MIPS_PC16;
542 (*rel)->lab = lid;
543 (*rel)++;
544 }
545 UASM_EXPORT_SYMBOL(uasm_r_mips_pc16);
546
547 static inline void __uasminit
548 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
549 {
550 long laddr = (long)lab->addr;
551 long raddr = (long)rel->addr;
552
553 switch (rel->type) {
554 case R_MIPS_PC16:
555 *rel->addr |= build_bimm(laddr - (raddr + 4));
556 break;
557
558 default:
559 panic("Unsupported Micro-assembler relocation %d",
560 rel->type);
561 }
562 }
563
564 void __uasminit
565 uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
566 {
567 struct uasm_label *l;
568
569 for (; rel->lab != UASM_LABEL_INVALID; rel++)
570 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
571 if (rel->lab == l->lab)
572 __resolve_relocs(rel, l);
573 }
574 UASM_EXPORT_SYMBOL(uasm_resolve_relocs);
575
576 void __uasminit
577 uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
578 {
579 for (; rel->lab != UASM_LABEL_INVALID; rel++)
580 if (rel->addr >= first && rel->addr < end)
581 rel->addr += off;
582 }
583 UASM_EXPORT_SYMBOL(uasm_move_relocs);
584
585 void __uasminit
586 uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
587 {
588 for (; lab->lab != UASM_LABEL_INVALID; lab++)
589 if (lab->addr >= first && lab->addr < end)
590 lab->addr += off;
591 }
592 UASM_EXPORT_SYMBOL(uasm_move_labels);
593
594 void __uasminit
595 uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
596 u32 *end, u32 *target)
597 {
598 long off = (long)(target - first);
599
600 memcpy(target, first, (end - first) * sizeof(u32));
601
602 uasm_move_relocs(rel, first, end, off);
603 uasm_move_labels(lab, first, end, off);
604 }
605 UASM_EXPORT_SYMBOL(uasm_copy_handler);
606
607 int __uasminit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
608 {
609 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
610 if (rel->addr == addr
611 && (rel->type == R_MIPS_PC16
612 || rel->type == R_MIPS_26))
613 return 1;
614 }
615
616 return 0;
617 }
618 UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay);
619
620 /* Convenience functions for labeled branches. */
621 void __uasminit
622 uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
623 {
624 uasm_r_mips_pc16(r, *p, lid);
625 uasm_i_bltz(p, reg, 0);
626 }
627 UASM_EXPORT_SYMBOL(uasm_il_bltz);
628
629 void __uasminit
630 uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
631 {
632 uasm_r_mips_pc16(r, *p, lid);
633 uasm_i_b(p, 0);
634 }
635 UASM_EXPORT_SYMBOL(uasm_il_b);
636
637 void __uasminit
638 uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
639 {
640 uasm_r_mips_pc16(r, *p, lid);
641 uasm_i_beqz(p, reg, 0);
642 }
643 UASM_EXPORT_SYMBOL(uasm_il_beqz);
644
645 void __uasminit
646 uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
647 {
648 uasm_r_mips_pc16(r, *p, lid);
649 uasm_i_beqzl(p, reg, 0);
650 }
651 UASM_EXPORT_SYMBOL(uasm_il_beqzl);
652
653 void __uasminit
654 uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
655 unsigned int reg2, int lid)
656 {
657 uasm_r_mips_pc16(r, *p, lid);
658 uasm_i_bne(p, reg1, reg2, 0);
659 }
660 UASM_EXPORT_SYMBOL(uasm_il_bne);
661
662 void __uasminit
663 uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
664 {
665 uasm_r_mips_pc16(r, *p, lid);
666 uasm_i_bnez(p, reg, 0);
667 }
668 UASM_EXPORT_SYMBOL(uasm_il_bnez);
669
670 void __uasminit
671 uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
672 {
673 uasm_r_mips_pc16(r, *p, lid);
674 uasm_i_bgezl(p, reg, 0);
675 }
676 UASM_EXPORT_SYMBOL(uasm_il_bgezl);
677
678 void __uasminit
679 uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
680 {
681 uasm_r_mips_pc16(r, *p, lid);
682 uasm_i_bgez(p, reg, 0);
683 }
684 UASM_EXPORT_SYMBOL(uasm_il_bgez);
685
686 void __uasminit
687 uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
688 unsigned int bit, int lid)
689 {
690 uasm_r_mips_pc16(r, *p, lid);
691 uasm_i_bbit0(p, reg, bit, 0);
692 }
693 UASM_EXPORT_SYMBOL(uasm_il_bbit0);
694
695 void __uasminit
696 uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
697 unsigned int bit, int lid)
698 {
699 uasm_r_mips_pc16(r, *p, lid);
700 uasm_i_bbit1(p, reg, bit, 0);
701 }
702 UASM_EXPORT_SYMBOL(uasm_il_bbit1);
Linux with added FPC-III support