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x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / arch / x86 / kernel / amd_iommu.c
blob8c38f0085403fc6c8f6ceaf95db13b0532e92b15
1 /*
2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
30 #include <asm/gart.h>
31 #include <asm/amd_iommu_proto.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
34
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36
37 #define EXIT_LOOP_COUNT 10000000
38
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
44
45 /*
46 * Domain for untranslated devices - only allocated
47 * if iommu=pt passed on kernel cmd line.
48 */
49 static struct protection_domain *pt_domain;
50
51 static struct iommu_ops amd_iommu_ops;
52
53 /*
54 * general struct to manage commands send to an IOMMU
55 */
56 struct iommu_cmd {
57 u32 data[4];
58 };
59
60 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
61 struct unity_map_entry *e);
62 static struct dma_ops_domain *find_protection_domain(u16 devid);
63 static u64 *alloc_pte(struct protection_domain *domain,
64 unsigned long address, int end_lvl,
65 u64 **pte_page, gfp_t gfp);
66 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
67 unsigned long start_page,
68 unsigned int pages);
69 static void reset_iommu_command_buffer(struct amd_iommu *iommu);
70 static u64 *fetch_pte(struct protection_domain *domain,
71 unsigned long address, int map_size);
72 static void update_domain(struct protection_domain *domain);
73
74 #ifdef CONFIG_AMD_IOMMU_STATS
75
76 /*
77 * Initialization code for statistics collection
78 */
79
80 DECLARE_STATS_COUNTER(compl_wait);
81 DECLARE_STATS_COUNTER(cnt_map_single);
82 DECLARE_STATS_COUNTER(cnt_unmap_single);
83 DECLARE_STATS_COUNTER(cnt_map_sg);
84 DECLARE_STATS_COUNTER(cnt_unmap_sg);
85 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
86 DECLARE_STATS_COUNTER(cnt_free_coherent);
87 DECLARE_STATS_COUNTER(cross_page);
88 DECLARE_STATS_COUNTER(domain_flush_single);
89 DECLARE_STATS_COUNTER(domain_flush_all);
90 DECLARE_STATS_COUNTER(alloced_io_mem);
91 DECLARE_STATS_COUNTER(total_map_requests);
92
93 static struct dentry *stats_dir;
94 static struct dentry *de_isolate;
95 static struct dentry *de_fflush;
96
97 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
98 {
99 if (stats_dir == NULL)
100 return;
101
102 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
103 &cnt->value);
104 }
105
106 static void amd_iommu_stats_init(void)
107 {
108 stats_dir = debugfs_create_dir("amd-iommu", NULL);
109 if (stats_dir == NULL)
110 return;
111
112 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
113 (u32 *)&amd_iommu_isolate);
114
115 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
116 (u32 *)&amd_iommu_unmap_flush);
117
118 amd_iommu_stats_add(&compl_wait);
119 amd_iommu_stats_add(&cnt_map_single);
120 amd_iommu_stats_add(&cnt_unmap_single);
121 amd_iommu_stats_add(&cnt_map_sg);
122 amd_iommu_stats_add(&cnt_unmap_sg);
123 amd_iommu_stats_add(&cnt_alloc_coherent);
124 amd_iommu_stats_add(&cnt_free_coherent);
125 amd_iommu_stats_add(&cross_page);
126 amd_iommu_stats_add(&domain_flush_single);
127 amd_iommu_stats_add(&domain_flush_all);
128 amd_iommu_stats_add(&alloced_io_mem);
129 amd_iommu_stats_add(&total_map_requests);
130 }
131
132 #endif
133
134 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
135 static int iommu_has_npcache(struct amd_iommu *iommu)
136 {
137 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
138 }
139
140 /****************************************************************************
141 *
142 * Interrupt handling functions
143 *
144 ****************************************************************************/
145
146 static void dump_dte_entry(u16 devid)
147 {
148 int i;
149
150 for (i = 0; i < 8; ++i)
151 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
152 amd_iommu_dev_table[devid].data[i]);
153 }
154
155 static void dump_command(unsigned long phys_addr)
156 {
157 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
158 int i;
159
160 for (i = 0; i < 4; ++i)
161 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
162 }
163
164 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
165 {
166 u32 *event = __evt;
167 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
168 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
169 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
170 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
171 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
172
173 printk(KERN_ERR "AMD-Vi: Event logged [");
174
175 switch (type) {
176 case EVENT_TYPE_ILL_DEV:
177 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
178 "address=0x%016llx flags=0x%04x]\n",
179 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
180 address, flags);
181 dump_dte_entry(devid);
182 break;
183 case EVENT_TYPE_IO_FAULT:
184 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
185 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
186 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
187 domid, address, flags);
188 break;
189 case EVENT_TYPE_DEV_TAB_ERR:
190 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
191 "address=0x%016llx flags=0x%04x]\n",
192 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
193 address, flags);
194 break;
195 case EVENT_TYPE_PAGE_TAB_ERR:
196 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
197 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
198 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
199 domid, address, flags);
200 break;
201 case EVENT_TYPE_ILL_CMD:
202 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
203 reset_iommu_command_buffer(iommu);
204 dump_command(address);
205 break;
206 case EVENT_TYPE_CMD_HARD_ERR:
207 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
208 "flags=0x%04x]\n", address, flags);
209 break;
210 case EVENT_TYPE_IOTLB_INV_TO:
211 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
212 "address=0x%016llx]\n",
213 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
214 address);
215 break;
216 case EVENT_TYPE_INV_DEV_REQ:
217 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
218 "address=0x%016llx flags=0x%04x]\n",
219 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
220 address, flags);
221 break;
222 default:
223 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
224 }
225 }
226
227 static void iommu_poll_events(struct amd_iommu *iommu)
228 {
229 u32 head, tail;
230 unsigned long flags;
231
232 spin_lock_irqsave(&iommu->lock, flags);
233
234 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
235 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
236
237 while (head != tail) {
238 iommu_print_event(iommu, iommu->evt_buf + head);
239 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
240 }
241
242 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
243
244 spin_unlock_irqrestore(&iommu->lock, flags);
245 }
246
247 irqreturn_t amd_iommu_int_handler(int irq, void *data)
248 {
249 struct amd_iommu *iommu;
250
251 for_each_iommu(iommu)
252 iommu_poll_events(iommu);
253
254 return IRQ_HANDLED;
255 }
256
257 /****************************************************************************
258 *
259 * IOMMU command queuing functions
260 *
261 ****************************************************************************/
262
263 /*
264 * Writes the command to the IOMMUs command buffer and informs the
265 * hardware about the new command. Must be called with iommu->lock held.
266 */
267 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
268 {
269 u32 tail, head;
270 u8 *target;
271
272 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
273 target = iommu->cmd_buf + tail;
274 memcpy_toio(target, cmd, sizeof(*cmd));
275 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
276 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
277 if (tail == head)
278 return -ENOMEM;
279 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
280
281 return 0;
282 }
283
284 /*
285 * General queuing function for commands. Takes iommu->lock and calls
286 * __iommu_queue_command().
287 */
288 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
289 {
290 unsigned long flags;
291 int ret;
292
293 spin_lock_irqsave(&iommu->lock, flags);
294 ret = __iommu_queue_command(iommu, cmd);
295 if (!ret)
296 iommu->need_sync = true;
297 spin_unlock_irqrestore(&iommu->lock, flags);
298
299 return ret;
300 }
301
302 /*
303 * This function waits until an IOMMU has completed a completion
304 * wait command
305 */
306 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
307 {
308 int ready = 0;
309 unsigned status = 0;
310 unsigned long i = 0;
311
312 INC_STATS_COUNTER(compl_wait);
313
314 while (!ready && (i < EXIT_LOOP_COUNT)) {
315 ++i;
316 /* wait for the bit to become one */
317 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
318 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
319 }
320
321 /* set bit back to zero */
322 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
323 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
324
325 if (unlikely(i == EXIT_LOOP_COUNT)) {
326 spin_unlock(&iommu->lock);
327 reset_iommu_command_buffer(iommu);
328 spin_lock(&iommu->lock);
329 }
330 }
331
332 /*
333 * This function queues a completion wait command into the command
334 * buffer of an IOMMU
335 */
336 static int __iommu_completion_wait(struct amd_iommu *iommu)
337 {
338 struct iommu_cmd cmd;
339
340 memset(&cmd, 0, sizeof(cmd));
341 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
342 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
343
344 return __iommu_queue_command(iommu, &cmd);
345 }
346
347 /*
348 * This function is called whenever we need to ensure that the IOMMU has
349 * completed execution of all commands we sent. It sends a
350 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
351 * us about that by writing a value to a physical address we pass with
352 * the command.
353 */
354 static int iommu_completion_wait(struct amd_iommu *iommu)
355 {
356 int ret = 0;
357 unsigned long flags;
358
359 spin_lock_irqsave(&iommu->lock, flags);
360
361 if (!iommu->need_sync)
362 goto out;
363
364 ret = __iommu_completion_wait(iommu);
365
366 iommu->need_sync = false;
367
368 if (ret)
369 goto out;
370
371 __iommu_wait_for_completion(iommu);
372
373 out:
374 spin_unlock_irqrestore(&iommu->lock, flags);
375
376 return 0;
377 }
378
379 /*
380 * Command send function for invalidating a device table entry
381 */
382 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
383 {
384 struct iommu_cmd cmd;
385 int ret;
386
387 BUG_ON(iommu == NULL);
388
389 memset(&cmd, 0, sizeof(cmd));
390 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
391 cmd.data[0] = devid;
392
393 ret = iommu_queue_command(iommu, &cmd);
394
395 return ret;
396 }
397
398 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
399 u16 domid, int pde, int s)
400 {
401 memset(cmd, 0, sizeof(*cmd));
402 address &= PAGE_MASK;
403 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
404 cmd->data[1] |= domid;
405 cmd->data[2] = lower_32_bits(address);
406 cmd->data[3] = upper_32_bits(address);
407 if (s) /* size bit - we flush more than one 4kb page */
408 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
409 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
410 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
411 }
412
413 /*
414 * Generic command send function for invalidaing TLB entries
415 */
416 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
417 u64 address, u16 domid, int pde, int s)
418 {
419 struct iommu_cmd cmd;
420 int ret;
421
422 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
423
424 ret = iommu_queue_command(iommu, &cmd);
425
426 return ret;
427 }
428
429 /*
430 * TLB invalidation function which is called from the mapping functions.
431 * It invalidates a single PTE if the range to flush is within a single
432 * page. Otherwise it flushes the whole TLB of the IOMMU.
433 */
434 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
435 u64 address, size_t size)
436 {
437 int s = 0;
438 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
439
440 address &= PAGE_MASK;
441
442 if (pages > 1) {
443 /*
444 * If we have to flush more than one page, flush all
445 * TLB entries for this domain
446 */
447 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
448 s = 1;
449 }
450
451 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
452
453 return 0;
454 }
455
456 /* Flush the whole IO/TLB for a given protection domain */
457 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
458 {
459 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
460
461 INC_STATS_COUNTER(domain_flush_single);
462
463 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
464 }
465
466 /* Flush the whole IO/TLB for a given protection domain - including PDE */
467 static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid)
468 {
469 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
470
471 INC_STATS_COUNTER(domain_flush_single);
472
473 iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1);
474 }
475
476 /*
477 * This function flushes one domain on one IOMMU
478 */
479 static void flush_domain_on_iommu(struct amd_iommu *iommu, u16 domid)
480 {
481 struct iommu_cmd cmd;
482 unsigned long flags;
483
484 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
485 domid, 1, 1);
486
487 spin_lock_irqsave(&iommu->lock, flags);
488 __iommu_queue_command(iommu, &cmd);
489 __iommu_completion_wait(iommu);
490 __iommu_wait_for_completion(iommu);
491 spin_unlock_irqrestore(&iommu->lock, flags);
492 }
493
494 static void flush_all_domains_on_iommu(struct amd_iommu *iommu)
495 {
496 int i;
497
498 for (i = 1; i < MAX_DOMAIN_ID; ++i) {
499 if (!test_bit(i, amd_iommu_pd_alloc_bitmap))
500 continue;
501 flush_domain_on_iommu(iommu, i);
502 }
503
504 }
505
506 /*
507 * This function is used to flush the IO/TLB for a given protection domain
508 * on every IOMMU in the system
509 */
510 static void iommu_flush_domain(u16 domid)
511 {
512 struct amd_iommu *iommu;
513
514 INC_STATS_COUNTER(domain_flush_all);
515
516 for_each_iommu(iommu)
517 flush_domain_on_iommu(iommu, domid);
518 }
519
520 void amd_iommu_flush_all_domains(void)
521 {
522 struct amd_iommu *iommu;
523
524 for_each_iommu(iommu)
525 flush_all_domains_on_iommu(iommu);
526 }
527
528 static void flush_all_devices_for_iommu(struct amd_iommu *iommu)
529 {
530 int i;
531
532 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
533 if (iommu != amd_iommu_rlookup_table[i])
534 continue;
535
536 iommu_queue_inv_dev_entry(iommu, i);
537 iommu_completion_wait(iommu);
538 }
539 }
540
541 static void flush_devices_by_domain(struct protection_domain *domain)
542 {
543 struct amd_iommu *iommu;
544 int i;
545
546 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
547 if ((domain == NULL && amd_iommu_pd_table[i] == NULL) ||
548 (amd_iommu_pd_table[i] != domain))
549 continue;
550
551 iommu = amd_iommu_rlookup_table[i];
552 if (!iommu)
553 continue;
554
555 iommu_queue_inv_dev_entry(iommu, i);
556 iommu_completion_wait(iommu);
557 }
558 }
559
560 static void reset_iommu_command_buffer(struct amd_iommu *iommu)
561 {
562 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
563
564 if (iommu->reset_in_progress)
565 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
566
567 iommu->reset_in_progress = true;
568
569 amd_iommu_reset_cmd_buffer(iommu);
570 flush_all_devices_for_iommu(iommu);
571 flush_all_domains_on_iommu(iommu);
572
573 iommu->reset_in_progress = false;
574 }
575
576 void amd_iommu_flush_all_devices(void)
577 {
578 flush_devices_by_domain(NULL);
579 }
580
581 /****************************************************************************
582 *
583 * The functions below are used the create the page table mappings for
584 * unity mapped regions.
585 *
586 ****************************************************************************/
587
588 /*
589 * Generic mapping functions. It maps a physical address into a DMA
590 * address space. It allocates the page table pages if necessary.
591 * In the future it can be extended to a generic mapping function
592 * supporting all features of AMD IOMMU page tables like level skipping
593 * and full 64 bit address spaces.
594 */
595 static int iommu_map_page(struct protection_domain *dom,
596 unsigned long bus_addr,
597 unsigned long phys_addr,
598 int prot,
599 int map_size)
600 {
601 u64 __pte, *pte;
602
603 bus_addr = PAGE_ALIGN(bus_addr);
604 phys_addr = PAGE_ALIGN(phys_addr);
605
606 BUG_ON(!PM_ALIGNED(map_size, bus_addr));
607 BUG_ON(!PM_ALIGNED(map_size, phys_addr));
608
609 if (!(prot & IOMMU_PROT_MASK))
610 return -EINVAL;
611
612 pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL);
613
614 if (IOMMU_PTE_PRESENT(*pte))
615 return -EBUSY;
616
617 __pte = phys_addr | IOMMU_PTE_P;
618 if (prot & IOMMU_PROT_IR)
619 __pte |= IOMMU_PTE_IR;
620 if (prot & IOMMU_PROT_IW)
621 __pte |= IOMMU_PTE_IW;
622
623 *pte = __pte;
624
625 update_domain(dom);
626
627 return 0;
628 }
629
630 static void iommu_unmap_page(struct protection_domain *dom,
631 unsigned long bus_addr, int map_size)
632 {
633 u64 *pte = fetch_pte(dom, bus_addr, map_size);
634
635 if (pte)
636 *pte = 0;
637 }
638
639 /*
640 * This function checks if a specific unity mapping entry is needed for
641 * this specific IOMMU.
642 */
643 static int iommu_for_unity_map(struct amd_iommu *iommu,
644 struct unity_map_entry *entry)
645 {
646 u16 bdf, i;
647
648 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
649 bdf = amd_iommu_alias_table[i];
650 if (amd_iommu_rlookup_table[bdf] == iommu)
651 return 1;
652 }
653
654 return 0;
655 }
656
657 /*
658 * Init the unity mappings for a specific IOMMU in the system
659 *
660 * Basically iterates over all unity mapping entries and applies them to
661 * the default domain DMA of that IOMMU if necessary.
662 */
663 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
664 {
665 struct unity_map_entry *entry;
666 int ret;
667
668 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
669 if (!iommu_for_unity_map(iommu, entry))
670 continue;
671 ret = dma_ops_unity_map(iommu->default_dom, entry);
672 if (ret)
673 return ret;
674 }
675
676 return 0;
677 }
678
679 /*
680 * This function actually applies the mapping to the page table of the
681 * dma_ops domain.
682 */
683 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
684 struct unity_map_entry *e)
685 {
686 u64 addr;
687 int ret;
688
689 for (addr = e->address_start; addr < e->address_end;
690 addr += PAGE_SIZE) {
691 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
692 PM_MAP_4k);
693 if (ret)
694 return ret;
695 /*
696 * if unity mapping is in aperture range mark the page
697 * as allocated in the aperture
698 */
699 if (addr < dma_dom->aperture_size)
700 __set_bit(addr >> PAGE_SHIFT,
701 dma_dom->aperture[0]->bitmap);
702 }
703
704 return 0;
705 }
706
707 /*
708 * Inits the unity mappings required for a specific device
709 */
710 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
711 u16 devid)
712 {
713 struct unity_map_entry *e;
714 int ret;
715
716 list_for_each_entry(e, &amd_iommu_unity_map, list) {
717 if (!(devid >= e->devid_start && devid <= e->devid_end))
718 continue;
719 ret = dma_ops_unity_map(dma_dom, e);
720 if (ret)
721 return ret;
722 }
723
724 return 0;
725 }
726
727 /****************************************************************************
728 *
729 * The next functions belong to the address allocator for the dma_ops
730 * interface functions. They work like the allocators in the other IOMMU
731 * drivers. Its basically a bitmap which marks the allocated pages in
732 * the aperture. Maybe it could be enhanced in the future to a more
733 * efficient allocator.
734 *
735 ****************************************************************************/
736
737 /*
738 * The address allocator core functions.
739 *
740 * called with domain->lock held
741 */
742
743 /*
744 * This function checks if there is a PTE for a given dma address. If
745 * there is one, it returns the pointer to it.
746 */
747 static u64 *fetch_pte(struct protection_domain *domain,
748 unsigned long address, int map_size)
749 {
750 int level;
751 u64 *pte;
752
753 level = domain->mode - 1;
754 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
755
756 while (level > map_size) {
757 if (!IOMMU_PTE_PRESENT(*pte))
758 return NULL;
759
760 level -= 1;
761
762 pte = IOMMU_PTE_PAGE(*pte);
763 pte = &pte[PM_LEVEL_INDEX(level, address)];
764
765 if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) {
766 pte = NULL;
767 break;
768 }
769 }
770
771 return pte;
772 }
773
774 /*
775 * This function is used to add a new aperture range to an existing
776 * aperture in case of dma_ops domain allocation or address allocation
777 * failure.
778 */
779 static int alloc_new_range(struct amd_iommu *iommu,
780 struct dma_ops_domain *dma_dom,
781 bool populate, gfp_t gfp)
782 {
783 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
784 int i;
785
786 #ifdef CONFIG_IOMMU_STRESS
787 populate = false;
788 #endif
789
790 if (index >= APERTURE_MAX_RANGES)
791 return -ENOMEM;
792
793 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
794 if (!dma_dom->aperture[index])
795 return -ENOMEM;
796
797 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
798 if (!dma_dom->aperture[index]->bitmap)
799 goto out_free;
800
801 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
802
803 if (populate) {
804 unsigned long address = dma_dom->aperture_size;
805 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
806 u64 *pte, *pte_page;
807
808 for (i = 0; i < num_ptes; ++i) {
809 pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k,
810 &pte_page, gfp);
811 if (!pte)
812 goto out_free;
813
814 dma_dom->aperture[index]->pte_pages[i] = pte_page;
815
816 address += APERTURE_RANGE_SIZE / 64;
817 }
818 }
819
820 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
821
822 /* Intialize the exclusion range if necessary */
823 if (iommu->exclusion_start &&
824 iommu->exclusion_start >= dma_dom->aperture[index]->offset &&
825 iommu->exclusion_start < dma_dom->aperture_size) {
826 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
827 int pages = iommu_num_pages(iommu->exclusion_start,
828 iommu->exclusion_length,
829 PAGE_SIZE);
830 dma_ops_reserve_addresses(dma_dom, startpage, pages);
831 }
832
833 /*
834 * Check for areas already mapped as present in the new aperture
835 * range and mark those pages as reserved in the allocator. Such
836 * mappings may already exist as a result of requested unity
837 * mappings for devices.
838 */
839 for (i = dma_dom->aperture[index]->offset;
840 i < dma_dom->aperture_size;
841 i += PAGE_SIZE) {
842 u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k);
843 if (!pte || !IOMMU_PTE_PRESENT(*pte))
844 continue;
845
846 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
847 }
848
849 update_domain(&dma_dom->domain);
850
851 return 0;
852
853 out_free:
854 update_domain(&dma_dom->domain);
855
856 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
857
858 kfree(dma_dom->aperture[index]);
859 dma_dom->aperture[index] = NULL;
860
861 return -ENOMEM;
862 }
863
864 static unsigned long dma_ops_area_alloc(struct device *dev,
865 struct dma_ops_domain *dom,
866 unsigned int pages,
867 unsigned long align_mask,
868 u64 dma_mask,
869 unsigned long start)
870 {
871 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
872 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
873 int i = start >> APERTURE_RANGE_SHIFT;
874 unsigned long boundary_size;
875 unsigned long address = -1;
876 unsigned long limit;
877
878 next_bit >>= PAGE_SHIFT;
879
880 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
881 PAGE_SIZE) >> PAGE_SHIFT;
882
883 for (;i < max_index; ++i) {
884 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
885
886 if (dom->aperture[i]->offset >= dma_mask)
887 break;
888
889 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
890 dma_mask >> PAGE_SHIFT);
891
892 address = iommu_area_alloc(dom->aperture[i]->bitmap,
893 limit, next_bit, pages, 0,
894 boundary_size, align_mask);
895 if (address != -1) {
896 address = dom->aperture[i]->offset +
897 (address << PAGE_SHIFT);
898 dom->next_address = address + (pages << PAGE_SHIFT);
899 break;
900 }
901
902 next_bit = 0;
903 }
904
905 return address;
906 }
907
908 static unsigned long dma_ops_alloc_addresses(struct device *dev,
909 struct dma_ops_domain *dom,
910 unsigned int pages,
911 unsigned long align_mask,
912 u64 dma_mask)
913 {
914 unsigned long address;
915
916 #ifdef CONFIG_IOMMU_STRESS
917 dom->next_address = 0;
918 dom->need_flush = true;
919 #endif
920
921 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
922 dma_mask, dom->next_address);
923
924 if (address == -1) {
925 dom->next_address = 0;
926 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
927 dma_mask, 0);
928 dom->need_flush = true;
929 }
930
931 if (unlikely(address == -1))
932 address = DMA_ERROR_CODE;
933
934 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
935
936 return address;
937 }
938
939 /*
940 * The address free function.
941 *
942 * called with domain->lock held
943 */
944 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
945 unsigned long address,
946 unsigned int pages)
947 {
948 unsigned i = address >> APERTURE_RANGE_SHIFT;
949 struct aperture_range *range = dom->aperture[i];
950
951 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
952
953 #ifdef CONFIG_IOMMU_STRESS
954 if (i < 4)
955 return;
956 #endif
957
958 if (address >= dom->next_address)
959 dom->need_flush = true;
960
961 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
962
963 iommu_area_free(range->bitmap, address, pages);
964
965 }
966
967 /****************************************************************************
968 *
969 * The next functions belong to the domain allocation. A domain is
970 * allocated for every IOMMU as the default domain. If device isolation
971 * is enabled, every device get its own domain. The most important thing
972 * about domains is the page table mapping the DMA address space they
973 * contain.
974 *
975 ****************************************************************************/
976
977 static u16 domain_id_alloc(void)
978 {
979 unsigned long flags;
980 int id;
981
982 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
983 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
984 BUG_ON(id == 0);
985 if (id > 0 && id < MAX_DOMAIN_ID)
986 __set_bit(id, amd_iommu_pd_alloc_bitmap);
987 else
988 id = 0;
989 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
990
991 return id;
992 }
993
994 static void domain_id_free(int id)
995 {
996 unsigned long flags;
997
998 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
999 if (id > 0 && id < MAX_DOMAIN_ID)
1000 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1001 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1002 }
1003
1004 /*
1005 * Used to reserve address ranges in the aperture (e.g. for exclusion
1006 * ranges.
1007 */
1008 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1009 unsigned long start_page,
1010 unsigned int pages)
1011 {
1012 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1013
1014 if (start_page + pages > last_page)
1015 pages = last_page - start_page;
1016
1017 for (i = start_page; i < start_page + pages; ++i) {
1018 int index = i / APERTURE_RANGE_PAGES;
1019 int page = i % APERTURE_RANGE_PAGES;
1020 __set_bit(page, dom->aperture[index]->bitmap);
1021 }
1022 }
1023
1024 static void free_pagetable(struct protection_domain *domain)
1025 {
1026 int i, j;
1027 u64 *p1, *p2, *p3;
1028
1029 p1 = domain->pt_root;
1030
1031 if (!p1)
1032 return;
1033
1034 for (i = 0; i < 512; ++i) {
1035 if (!IOMMU_PTE_PRESENT(p1[i]))
1036 continue;
1037
1038 p2 = IOMMU_PTE_PAGE(p1[i]);
1039 for (j = 0; j < 512; ++j) {
1040 if (!IOMMU_PTE_PRESENT(p2[j]))
1041 continue;
1042 p3 = IOMMU_PTE_PAGE(p2[j]);
1043 free_page((unsigned long)p3);
1044 }
1045
1046 free_page((unsigned long)p2);
1047 }
1048
1049 free_page((unsigned long)p1);
1050
1051 domain->pt_root = NULL;
1052 }
1053
1054 /*
1055 * Free a domain, only used if something went wrong in the
1056 * allocation path and we need to free an already allocated page table
1057 */
1058 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1059 {
1060 int i;
1061
1062 if (!dom)
1063 return;
1064
1065 free_pagetable(&dom->domain);
1066
1067 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1068 if (!dom->aperture[i])
1069 continue;
1070 free_page((unsigned long)dom->aperture[i]->bitmap);
1071 kfree(dom->aperture[i]);
1072 }
1073
1074 kfree(dom);
1075 }
1076
1077 /*
1078 * Allocates a new protection domain usable for the dma_ops functions.
1079 * It also intializes the page table and the address allocator data
1080 * structures required for the dma_ops interface
1081 */
1082 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu)
1083 {
1084 struct dma_ops_domain *dma_dom;
1085
1086 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1087 if (!dma_dom)
1088 return NULL;
1089
1090 spin_lock_init(&dma_dom->domain.lock);
1091
1092 dma_dom->domain.id = domain_id_alloc();
1093 if (dma_dom->domain.id == 0)
1094 goto free_dma_dom;
1095 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1096 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1097 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1098 dma_dom->domain.priv = dma_dom;
1099 if (!dma_dom->domain.pt_root)
1100 goto free_dma_dom;
1101
1102 dma_dom->need_flush = false;
1103 dma_dom->target_dev = 0xffff;
1104
1105 if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL))
1106 goto free_dma_dom;
1107
1108 /*
1109 * mark the first page as allocated so we never return 0 as
1110 * a valid dma-address. So we can use 0 as error value
1111 */
1112 dma_dom->aperture[0]->bitmap[0] = 1;
1113 dma_dom->next_address = 0;
1114
1115
1116 return dma_dom;
1117
1118 free_dma_dom:
1119 dma_ops_domain_free(dma_dom);
1120
1121 return NULL;
1122 }
1123
1124 /*
1125 * little helper function to check whether a given protection domain is a
1126 * dma_ops domain
1127 */
1128 static bool dma_ops_domain(struct protection_domain *domain)
1129 {
1130 return domain->flags & PD_DMA_OPS_MASK;
1131 }
1132
1133 /*
1134 * Find out the protection domain structure for a given PCI device. This
1135 * will give us the pointer to the page table root for example.
1136 */
1137 static struct protection_domain *domain_for_device(u16 devid)
1138 {
1139 struct protection_domain *dom;
1140 unsigned long flags;
1141
1142 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1143 dom = amd_iommu_pd_table[devid];
1144 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1145
1146 return dom;
1147 }
1148
1149 static void set_dte_entry(u16 devid, struct protection_domain *domain)
1150 {
1151 u64 pte_root = virt_to_phys(domain->pt_root);
1152
1153 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1154 << DEV_ENTRY_MODE_SHIFT;
1155 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1156
1157 amd_iommu_dev_table[devid].data[2] = domain->id;
1158 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1159 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1160
1161 amd_iommu_pd_table[devid] = domain;
1162 }
1163
1164 /*
1165 * If a device is not yet associated with a domain, this function does
1166 * assigns it visible for the hardware
1167 */
1168 static void __attach_device(struct amd_iommu *iommu,
1169 struct protection_domain *domain,
1170 u16 devid)
1171 {
1172 /* lock domain */
1173 spin_lock(&domain->lock);
1174
1175 /* update DTE entry */
1176 set_dte_entry(devid, domain);
1177
1178 /* Do reference counting */
1179 domain->dev_iommu[iommu->index] += 1;
1180 domain->dev_cnt += 1;
1181
1182 /* ready */
1183 spin_unlock(&domain->lock);
1184 }
1185
1186 /*
1187 * If a device is not yet associated with a domain, this function does
1188 * assigns it visible for the hardware
1189 */
1190 static void attach_device(struct amd_iommu *iommu,
1191 struct protection_domain *domain,
1192 u16 devid)
1193 {
1194 unsigned long flags;
1195
1196 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1197 __attach_device(iommu, domain, devid);
1198 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1199
1200 /*
1201 * We might boot into a crash-kernel here. The crashed kernel
1202 * left the caches in the IOMMU dirty. So we have to flush
1203 * here to evict all dirty stuff.
1204 */
1205 iommu_queue_inv_dev_entry(iommu, devid);
1206 iommu_flush_tlb_pde(iommu, domain->id);
1207 }
1208
1209 /*
1210 * Removes a device from a protection domain (unlocked)
1211 */
1212 static void __detach_device(struct protection_domain *domain, u16 devid)
1213 {
1214 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1215
1216 BUG_ON(!iommu);
1217
1218 /* lock domain */
1219 spin_lock(&domain->lock);
1220
1221 /* remove domain from the lookup table */
1222 amd_iommu_pd_table[devid] = NULL;
1223
1224 /* remove entry from the device table seen by the hardware */
1225 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1226 amd_iommu_dev_table[devid].data[1] = 0;
1227 amd_iommu_dev_table[devid].data[2] = 0;
1228
1229 amd_iommu_apply_erratum_63(devid);
1230
1231 /* decrease reference counters */
1232 domain->dev_iommu[iommu->index] -= 1;
1233 domain->dev_cnt -= 1;
1234
1235 /* ready */
1236 spin_unlock(&domain->lock);
1237
1238 /*
1239 * If we run in passthrough mode the device must be assigned to the
1240 * passthrough domain if it is detached from any other domain
1241 */
1242 if (iommu_pass_through) {
1243 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1244 __attach_device(iommu, pt_domain, devid);
1245 }
1246 }
1247
1248 /*
1249 * Removes a device from a protection domain (with devtable_lock held)
1250 */
1251 static void detach_device(struct protection_domain *domain, u16 devid)
1252 {
1253 unsigned long flags;
1254
1255 /* lock device table */
1256 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1257 __detach_device(domain, devid);
1258 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1259 }
1260
1261 static int device_change_notifier(struct notifier_block *nb,
1262 unsigned long action, void *data)
1263 {
1264 struct device *dev = data;
1265 struct pci_dev *pdev = to_pci_dev(dev);
1266 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
1267 struct protection_domain *domain;
1268 struct dma_ops_domain *dma_domain;
1269 struct amd_iommu *iommu;
1270 unsigned long flags;
1271
1272 if (devid > amd_iommu_last_bdf)
1273 goto out;
1274
1275 devid = amd_iommu_alias_table[devid];
1276
1277 iommu = amd_iommu_rlookup_table[devid];
1278 if (iommu == NULL)
1279 goto out;
1280
1281 domain = domain_for_device(devid);
1282
1283 if (domain && !dma_ops_domain(domain))
1284 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1285 "to a non-dma-ops domain\n", dev_name(dev));
1286
1287 switch (action) {
1288 case BUS_NOTIFY_UNBOUND_DRIVER:
1289 if (!domain)
1290 goto out;
1291 if (iommu_pass_through)
1292 break;
1293 detach_device(domain, devid);
1294 break;
1295 case BUS_NOTIFY_ADD_DEVICE:
1296 /* allocate a protection domain if a device is added */
1297 dma_domain = find_protection_domain(devid);
1298 if (dma_domain)
1299 goto out;
1300 dma_domain = dma_ops_domain_alloc(iommu);
1301 if (!dma_domain)
1302 goto out;
1303 dma_domain->target_dev = devid;
1304
1305 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1306 list_add_tail(&dma_domain->list, &iommu_pd_list);
1307 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1308
1309 break;
1310 default:
1311 goto out;
1312 }
1313
1314 iommu_queue_inv_dev_entry(iommu, devid);
1315 iommu_completion_wait(iommu);
1316
1317 out:
1318 return 0;
1319 }
1320
1321 static struct notifier_block device_nb = {
1322 .notifier_call = device_change_notifier,
1323 };
1324
1325 /*****************************************************************************
1326 *
1327 * The next functions belong to the dma_ops mapping/unmapping code.
1328 *
1329 *****************************************************************************/
1330
1331 /*
1332 * This function checks if the driver got a valid device from the caller to
1333 * avoid dereferencing invalid pointers.
1334 */
1335 static bool check_device(struct device *dev)
1336 {
1337 if (!dev || !dev->dma_mask)
1338 return false;
1339
1340 return true;
1341 }
1342
1343 /*
1344 * In this function the list of preallocated protection domains is traversed to
1345 * find the domain for a specific device
1346 */
1347 static struct dma_ops_domain *find_protection_domain(u16 devid)
1348 {
1349 struct dma_ops_domain *entry, *ret = NULL;
1350 unsigned long flags;
1351
1352 if (list_empty(&iommu_pd_list))
1353 return NULL;
1354
1355 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1356
1357 list_for_each_entry(entry, &iommu_pd_list, list) {
1358 if (entry->target_dev == devid) {
1359 ret = entry;
1360 break;
1361 }
1362 }
1363
1364 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1365
1366 return ret;
1367 }
1368
1369 /*
1370 * In the dma_ops path we only have the struct device. This function
1371 * finds the corresponding IOMMU, the protection domain and the
1372 * requestor id for a given device.
1373 * If the device is not yet associated with a domain this is also done
1374 * in this function.
1375 */
1376 static int get_device_resources(struct device *dev,
1377 struct amd_iommu **iommu,
1378 struct protection_domain **domain,
1379 u16 *bdf)
1380 {
1381 struct dma_ops_domain *dma_dom;
1382 struct pci_dev *pcidev;
1383 u16 _bdf;
1384
1385 *iommu = NULL;
1386 *domain = NULL;
1387 *bdf = 0xffff;
1388
1389 if (dev->bus != &pci_bus_type)
1390 return 0;
1391
1392 pcidev = to_pci_dev(dev);
1393 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1394
1395 /* device not translated by any IOMMU in the system? */
1396 if (_bdf > amd_iommu_last_bdf)
1397 return 0;
1398
1399 *bdf = amd_iommu_alias_table[_bdf];
1400
1401 *iommu = amd_iommu_rlookup_table[*bdf];
1402 if (*iommu == NULL)
1403 return 0;
1404 *domain = domain_for_device(*bdf);
1405 if (*domain == NULL) {
1406 dma_dom = find_protection_domain(*bdf);
1407 if (!dma_dom)
1408 dma_dom = (*iommu)->default_dom;
1409 *domain = &dma_dom->domain;
1410 attach_device(*iommu, *domain, *bdf);
1411 DUMP_printk("Using protection domain %d for device %s\n",
1412 (*domain)->id, dev_name(dev));
1413 }
1414
1415 if (domain_for_device(_bdf) == NULL)
1416 attach_device(*iommu, *domain, _bdf);
1417
1418 return 1;
1419 }
1420
1421 static void update_device_table(struct protection_domain *domain)
1422 {
1423 unsigned long flags;
1424 int i;
1425
1426 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
1427 if (amd_iommu_pd_table[i] != domain)
1428 continue;
1429 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1430 set_dte_entry(i, domain);
1431 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1432 }
1433 }
1434
1435 static void update_domain(struct protection_domain *domain)
1436 {
1437 if (!domain->updated)
1438 return;
1439
1440 update_device_table(domain);
1441 flush_devices_by_domain(domain);
1442 iommu_flush_domain(domain->id);
1443
1444 domain->updated = false;
1445 }
1446
1447 /*
1448 * This function is used to add another level to an IO page table. Adding
1449 * another level increases the size of the address space by 9 bits to a size up
1450 * to 64 bits.
1451 */
1452 static bool increase_address_space(struct protection_domain *domain,
1453 gfp_t gfp)
1454 {
1455 u64 *pte;
1456
1457 if (domain->mode == PAGE_MODE_6_LEVEL)
1458 /* address space already 64 bit large */
1459 return false;
1460
1461 pte = (void *)get_zeroed_page(gfp);
1462 if (!pte)
1463 return false;
1464
1465 *pte = PM_LEVEL_PDE(domain->mode,
1466 virt_to_phys(domain->pt_root));
1467 domain->pt_root = pte;
1468 domain->mode += 1;
1469 domain->updated = true;
1470
1471 return true;
1472 }
1473
1474 static u64 *alloc_pte(struct protection_domain *domain,
1475 unsigned long address,
1476 int end_lvl,
1477 u64 **pte_page,
1478 gfp_t gfp)
1479 {
1480 u64 *pte, *page;
1481 int level;
1482
1483 while (address > PM_LEVEL_SIZE(domain->mode))
1484 increase_address_space(domain, gfp);
1485
1486 level = domain->mode - 1;
1487 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1488
1489 while (level > end_lvl) {
1490 if (!IOMMU_PTE_PRESENT(*pte)) {
1491 page = (u64 *)get_zeroed_page(gfp);
1492 if (!page)
1493 return NULL;
1494 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1495 }
1496
1497 level -= 1;
1498
1499 pte = IOMMU_PTE_PAGE(*pte);
1500
1501 if (pte_page && level == end_lvl)
1502 *pte_page = pte;
1503
1504 pte = &pte[PM_LEVEL_INDEX(level, address)];
1505 }
1506
1507 return pte;
1508 }
1509
1510 /*
1511 * This function fetches the PTE for a given address in the aperture
1512 */
1513 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1514 unsigned long address)
1515 {
1516 struct aperture_range *aperture;
1517 u64 *pte, *pte_page;
1518
1519 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1520 if (!aperture)
1521 return NULL;
1522
1523 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1524 if (!pte) {
1525 pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page,
1526 GFP_ATOMIC);
1527 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1528 } else
1529 pte += PM_LEVEL_INDEX(0, address);
1530
1531 update_domain(&dom->domain);
1532
1533 return pte;
1534 }
1535
1536 /*
1537 * This is the generic map function. It maps one 4kb page at paddr to
1538 * the given address in the DMA address space for the domain.
1539 */
1540 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1541 struct dma_ops_domain *dom,
1542 unsigned long address,
1543 phys_addr_t paddr,
1544 int direction)
1545 {
1546 u64 *pte, __pte;
1547
1548 WARN_ON(address > dom->aperture_size);
1549
1550 paddr &= PAGE_MASK;
1551
1552 pte = dma_ops_get_pte(dom, address);
1553 if (!pte)
1554 return DMA_ERROR_CODE;
1555
1556 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1557
1558 if (direction == DMA_TO_DEVICE)
1559 __pte |= IOMMU_PTE_IR;
1560 else if (direction == DMA_FROM_DEVICE)
1561 __pte |= IOMMU_PTE_IW;
1562 else if (direction == DMA_BIDIRECTIONAL)
1563 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1564
1565 WARN_ON(*pte);
1566
1567 *pte = __pte;
1568
1569 return (dma_addr_t)address;
1570 }
1571
1572 /*
1573 * The generic unmapping function for on page in the DMA address space.
1574 */
1575 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1576 struct dma_ops_domain *dom,
1577 unsigned long address)
1578 {
1579 struct aperture_range *aperture;
1580 u64 *pte;
1581
1582 if (address >= dom->aperture_size)
1583 return;
1584
1585 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1586 if (!aperture)
1587 return;
1588
1589 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1590 if (!pte)
1591 return;
1592
1593 pte += PM_LEVEL_INDEX(0, address);
1594
1595 WARN_ON(!*pte);
1596
1597 *pte = 0ULL;
1598 }
1599
1600 /*
1601 * This function contains common code for mapping of a physically
1602 * contiguous memory region into DMA address space. It is used by all
1603 * mapping functions provided with this IOMMU driver.
1604 * Must be called with the domain lock held.
1605 */
1606 static dma_addr_t __map_single(struct device *dev,
1607 struct amd_iommu *iommu,
1608 struct dma_ops_domain *dma_dom,
1609 phys_addr_t paddr,
1610 size_t size,
1611 int dir,
1612 bool align,
1613 u64 dma_mask)
1614 {
1615 dma_addr_t offset = paddr & ~PAGE_MASK;
1616 dma_addr_t address, start, ret;
1617 unsigned int pages;
1618 unsigned long align_mask = 0;
1619 int i;
1620
1621 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1622 paddr &= PAGE_MASK;
1623
1624 INC_STATS_COUNTER(total_map_requests);
1625
1626 if (pages > 1)
1627 INC_STATS_COUNTER(cross_page);
1628
1629 if (align)
1630 align_mask = (1UL << get_order(size)) - 1;
1631
1632 retry:
1633 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1634 dma_mask);
1635 if (unlikely(address == DMA_ERROR_CODE)) {
1636 /*
1637 * setting next_address here will let the address
1638 * allocator only scan the new allocated range in the
1639 * first run. This is a small optimization.
1640 */
1641 dma_dom->next_address = dma_dom->aperture_size;
1642
1643 if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC))
1644 goto out;
1645
1646 /*
1647 * aperture was sucessfully enlarged by 128 MB, try
1648 * allocation again
1649 */
1650 goto retry;
1651 }
1652
1653 start = address;
1654 for (i = 0; i < pages; ++i) {
1655 ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1656 if (ret == DMA_ERROR_CODE)
1657 goto out_unmap;
1658
1659 paddr += PAGE_SIZE;
1660 start += PAGE_SIZE;
1661 }
1662 address += offset;
1663
1664 ADD_STATS_COUNTER(alloced_io_mem, size);
1665
1666 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1667 iommu_flush_tlb(iommu, dma_dom->domain.id);
1668 dma_dom->need_flush = false;
1669 } else if (unlikely(iommu_has_npcache(iommu)))
1670 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1671
1672 out:
1673 return address;
1674
1675 out_unmap:
1676
1677 for (--i; i >= 0; --i) {
1678 start -= PAGE_SIZE;
1679 dma_ops_domain_unmap(iommu, dma_dom, start);
1680 }
1681
1682 dma_ops_free_addresses(dma_dom, address, pages);
1683
1684 return DMA_ERROR_CODE;
1685 }
1686
1687 /*
1688 * Does the reverse of the __map_single function. Must be called with
1689 * the domain lock held too
1690 */
1691 static void __unmap_single(struct amd_iommu *iommu,
1692 struct dma_ops_domain *dma_dom,
1693 dma_addr_t dma_addr,
1694 size_t size,
1695 int dir)
1696 {
1697 dma_addr_t i, start;
1698 unsigned int pages;
1699
1700 if ((dma_addr == DMA_ERROR_CODE) ||
1701 (dma_addr + size > dma_dom->aperture_size))
1702 return;
1703
1704 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1705 dma_addr &= PAGE_MASK;
1706 start = dma_addr;
1707
1708 for (i = 0; i < pages; ++i) {
1709 dma_ops_domain_unmap(iommu, dma_dom, start);
1710 start += PAGE_SIZE;
1711 }
1712
1713 SUB_STATS_COUNTER(alloced_io_mem, size);
1714
1715 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1716
1717 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1718 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1719 dma_dom->need_flush = false;
1720 }
1721 }
1722
1723 /*
1724 * The exported map_single function for dma_ops.
1725 */
1726 static dma_addr_t map_page(struct device *dev, struct page *page,
1727 unsigned long offset, size_t size,
1728 enum dma_data_direction dir,
1729 struct dma_attrs *attrs)
1730 {
1731 unsigned long flags;
1732 struct amd_iommu *iommu;
1733 struct protection_domain *domain;
1734 u16 devid;
1735 dma_addr_t addr;
1736 u64 dma_mask;
1737 phys_addr_t paddr = page_to_phys(page) + offset;
1738
1739 INC_STATS_COUNTER(cnt_map_single);
1740
1741 if (!check_device(dev))
1742 return DMA_ERROR_CODE;
1743
1744 dma_mask = *dev->dma_mask;
1745
1746 get_device_resources(dev, &iommu, &domain, &devid);
1747
1748 if (iommu == NULL || domain == NULL)
1749 /* device not handled by any AMD IOMMU */
1750 return (dma_addr_t)paddr;
1751
1752 if (!dma_ops_domain(domain))
1753 return DMA_ERROR_CODE;
1754
1755 spin_lock_irqsave(&domain->lock, flags);
1756 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1757 dma_mask);
1758 if (addr == DMA_ERROR_CODE)
1759 goto out;
1760
1761 iommu_completion_wait(iommu);
1762
1763 out:
1764 spin_unlock_irqrestore(&domain->lock, flags);
1765
1766 return addr;
1767 }
1768
1769 /*
1770 * The exported unmap_single function for dma_ops.
1771 */
1772 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1773 enum dma_data_direction dir, struct dma_attrs *attrs)
1774 {
1775 unsigned long flags;
1776 struct amd_iommu *iommu;
1777 struct protection_domain *domain;
1778 u16 devid;
1779
1780 INC_STATS_COUNTER(cnt_unmap_single);
1781
1782 if (!check_device(dev) ||
1783 !get_device_resources(dev, &iommu, &domain, &devid))
1784 /* device not handled by any AMD IOMMU */
1785 return;
1786
1787 if (!dma_ops_domain(domain))
1788 return;
1789
1790 spin_lock_irqsave(&domain->lock, flags);
1791
1792 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1793
1794 iommu_completion_wait(iommu);
1795
1796 spin_unlock_irqrestore(&domain->lock, flags);
1797 }
1798
1799 /*
1800 * This is a special map_sg function which is used if we should map a
1801 * device which is not handled by an AMD IOMMU in the system.
1802 */
1803 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1804 int nelems, int dir)
1805 {
1806 struct scatterlist *s;
1807 int i;
1808
1809 for_each_sg(sglist, s, nelems, i) {
1810 s->dma_address = (dma_addr_t)sg_phys(s);
1811 s->dma_length = s->length;
1812 }
1813
1814 return nelems;
1815 }
1816
1817 /*
1818 * The exported map_sg function for dma_ops (handles scatter-gather
1819 * lists).
1820 */
1821 static int map_sg(struct device *dev, struct scatterlist *sglist,
1822 int nelems, enum dma_data_direction dir,
1823 struct dma_attrs *attrs)
1824 {
1825 unsigned long flags;
1826 struct amd_iommu *iommu;
1827 struct protection_domain *domain;
1828 u16 devid;
1829 int i;
1830 struct scatterlist *s;
1831 phys_addr_t paddr;
1832 int mapped_elems = 0;
1833 u64 dma_mask;
1834
1835 INC_STATS_COUNTER(cnt_map_sg);
1836
1837 if (!check_device(dev))
1838 return 0;
1839
1840 dma_mask = *dev->dma_mask;
1841
1842 get_device_resources(dev, &iommu, &domain, &devid);
1843
1844 if (!iommu || !domain)
1845 return map_sg_no_iommu(dev, sglist, nelems, dir);
1846
1847 if (!dma_ops_domain(domain))
1848 return 0;
1849
1850 spin_lock_irqsave(&domain->lock, flags);
1851
1852 for_each_sg(sglist, s, nelems, i) {
1853 paddr = sg_phys(s);
1854
1855 s->dma_address = __map_single(dev, iommu, domain->priv,
1856 paddr, s->length, dir, false,
1857 dma_mask);
1858
1859 if (s->dma_address) {
1860 s->dma_length = s->length;
1861 mapped_elems++;
1862 } else
1863 goto unmap;
1864 }
1865
1866 iommu_completion_wait(iommu);
1867
1868 out:
1869 spin_unlock_irqrestore(&domain->lock, flags);
1870
1871 return mapped_elems;
1872 unmap:
1873 for_each_sg(sglist, s, mapped_elems, i) {
1874 if (s->dma_address)
1875 __unmap_single(iommu, domain->priv, s->dma_address,
1876 s->dma_length, dir);
1877 s->dma_address = s->dma_length = 0;
1878 }
1879
1880 mapped_elems = 0;
1881
1882 goto out;
1883 }
1884
1885 /*
1886 * The exported map_sg function for dma_ops (handles scatter-gather
1887 * lists).
1888 */
1889 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1890 int nelems, enum dma_data_direction dir,
1891 struct dma_attrs *attrs)
1892 {
1893 unsigned long flags;
1894 struct amd_iommu *iommu;
1895 struct protection_domain *domain;
1896 struct scatterlist *s;
1897 u16 devid;
1898 int i;
1899
1900 INC_STATS_COUNTER(cnt_unmap_sg);
1901
1902 if (!check_device(dev) ||
1903 !get_device_resources(dev, &iommu, &domain, &devid))
1904 return;
1905
1906 if (!dma_ops_domain(domain))
1907 return;
1908
1909 spin_lock_irqsave(&domain->lock, flags);
1910
1911 for_each_sg(sglist, s, nelems, i) {
1912 __unmap_single(iommu, domain->priv, s->dma_address,
1913 s->dma_length, dir);
1914 s->dma_address = s->dma_length = 0;
1915 }
1916
1917 iommu_completion_wait(iommu);
1918
1919 spin_unlock_irqrestore(&domain->lock, flags);
1920 }
1921
1922 /*
1923 * The exported alloc_coherent function for dma_ops.
1924 */
1925 static void *alloc_coherent(struct device *dev, size_t size,
1926 dma_addr_t *dma_addr, gfp_t flag)
1927 {
1928 unsigned long flags;
1929 void *virt_addr;
1930 struct amd_iommu *iommu;
1931 struct protection_domain *domain;
1932 u16 devid;
1933 phys_addr_t paddr;
1934 u64 dma_mask = dev->coherent_dma_mask;
1935
1936 INC_STATS_COUNTER(cnt_alloc_coherent);
1937
1938 if (!check_device(dev))
1939 return NULL;
1940
1941 if (!get_device_resources(dev, &iommu, &domain, &devid))
1942 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1943
1944 flag |= __GFP_ZERO;
1945 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1946 if (!virt_addr)
1947 return NULL;
1948
1949 paddr = virt_to_phys(virt_addr);
1950
1951 if (!iommu || !domain) {
1952 *dma_addr = (dma_addr_t)paddr;
1953 return virt_addr;
1954 }
1955
1956 if (!dma_ops_domain(domain))
1957 goto out_free;
1958
1959 if (!dma_mask)
1960 dma_mask = *dev->dma_mask;
1961
1962 spin_lock_irqsave(&domain->lock, flags);
1963
1964 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1965 size, DMA_BIDIRECTIONAL, true, dma_mask);
1966
1967 if (*dma_addr == DMA_ERROR_CODE) {
1968 spin_unlock_irqrestore(&domain->lock, flags);
1969 goto out_free;
1970 }
1971
1972 iommu_completion_wait(iommu);
1973
1974 spin_unlock_irqrestore(&domain->lock, flags);
1975
1976 return virt_addr;
1977
1978 out_free:
1979
1980 free_pages((unsigned long)virt_addr, get_order(size));
1981
1982 return NULL;
1983 }
1984
1985 /*
1986 * The exported free_coherent function for dma_ops.
1987 */
1988 static void free_coherent(struct device *dev, size_t size,
1989 void *virt_addr, dma_addr_t dma_addr)
1990 {
1991 unsigned long flags;
1992 struct amd_iommu *iommu;
1993 struct protection_domain *domain;
1994 u16 devid;
1995
1996 INC_STATS_COUNTER(cnt_free_coherent);
1997
1998 if (!check_device(dev))
1999 return;
2000
2001 get_device_resources(dev, &iommu, &domain, &devid);
2002
2003 if (!iommu || !domain)
2004 goto free_mem;
2005
2006 if (!dma_ops_domain(domain))
2007 goto free_mem;
2008
2009 spin_lock_irqsave(&domain->lock, flags);
2010
2011 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2012
2013 iommu_completion_wait(iommu);
2014
2015 spin_unlock_irqrestore(&domain->lock, flags);
2016
2017 free_mem:
2018 free_pages((unsigned long)virt_addr, get_order(size));
2019 }
2020
2021 /*
2022 * This function is called by the DMA layer to find out if we can handle a
2023 * particular device. It is part of the dma_ops.
2024 */
2025 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2026 {
2027 u16 bdf;
2028 struct pci_dev *pcidev;
2029
2030 /* No device or no PCI device */
2031 if (!dev || dev->bus != &pci_bus_type)
2032 return 0;
2033
2034 pcidev = to_pci_dev(dev);
2035
2036 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
2037
2038 /* Out of our scope? */
2039 if (bdf > amd_iommu_last_bdf)
2040 return 0;
2041
2042 return 1;
2043 }
2044
2045 /*
2046 * The function for pre-allocating protection domains.
2047 *
2048 * If the driver core informs the DMA layer if a driver grabs a device
2049 * we don't need to preallocate the protection domains anymore.
2050 * For now we have to.
2051 */
2052 static void prealloc_protection_domains(void)
2053 {
2054 struct pci_dev *dev = NULL;
2055 struct dma_ops_domain *dma_dom;
2056 struct amd_iommu *iommu;
2057 u16 devid, __devid;
2058
2059 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2060 __devid = devid = calc_devid(dev->bus->number, dev->devfn);
2061 if (devid > amd_iommu_last_bdf)
2062 continue;
2063 devid = amd_iommu_alias_table[devid];
2064 if (domain_for_device(devid))
2065 continue;
2066 iommu = amd_iommu_rlookup_table[devid];
2067 if (!iommu)
2068 continue;
2069 dma_dom = dma_ops_domain_alloc(iommu);
2070 if (!dma_dom)
2071 continue;
2072 init_unity_mappings_for_device(dma_dom, devid);
2073 dma_dom->target_dev = devid;
2074
2075 attach_device(iommu, &dma_dom->domain, devid);
2076 if (__devid != devid)
2077 attach_device(iommu, &dma_dom->domain, __devid);
2078
2079 list_add_tail(&dma_dom->list, &iommu_pd_list);
2080 }
2081 }
2082
2083 static struct dma_map_ops amd_iommu_dma_ops = {
2084 .alloc_coherent = alloc_coherent,
2085 .free_coherent = free_coherent,
2086 .map_page = map_page,
2087 .unmap_page = unmap_page,
2088 .map_sg = map_sg,
2089 .unmap_sg = unmap_sg,
2090 .dma_supported = amd_iommu_dma_supported,
2091 };
2092
2093 /*
2094 * The function which clues the AMD IOMMU driver into dma_ops.
2095 */
2096 int __init amd_iommu_init_dma_ops(void)
2097 {
2098 struct amd_iommu *iommu;
2099 int ret;
2100
2101 /*
2102 * first allocate a default protection domain for every IOMMU we
2103 * found in the system. Devices not assigned to any other
2104 * protection domain will be assigned to the default one.
2105 */
2106 for_each_iommu(iommu) {
2107 iommu->default_dom = dma_ops_domain_alloc(iommu);
2108 if (iommu->default_dom == NULL)
2109 return -ENOMEM;
2110 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2111 ret = iommu_init_unity_mappings(iommu);
2112 if (ret)
2113 goto free_domains;
2114 }
2115
2116 /*
2117 * If device isolation is enabled, pre-allocate the protection
2118 * domains for each device.
2119 */
2120 if (amd_iommu_isolate)
2121 prealloc_protection_domains();
2122
2123 iommu_detected = 1;
2124 swiotlb = 0;
2125 #ifdef CONFIG_GART_IOMMU
2126 gart_iommu_aperture_disabled = 1;
2127 gart_iommu_aperture = 0;
2128 #endif
2129
2130 /* Make the driver finally visible to the drivers */
2131 dma_ops = &amd_iommu_dma_ops;
2132
2133 register_iommu(&amd_iommu_ops);
2134
2135 bus_register_notifier(&pci_bus_type, &device_nb);
2136
2137 amd_iommu_stats_init();
2138
2139 return 0;
2140
2141 free_domains:
2142
2143 for_each_iommu(iommu) {
2144 if (iommu->default_dom)
2145 dma_ops_domain_free(iommu->default_dom);
2146 }
2147
2148 return ret;
2149 }
2150
2151 /*****************************************************************************
2152 *
2153 * The following functions belong to the exported interface of AMD IOMMU
2154 *
2155 * This interface allows access to lower level functions of the IOMMU
2156 * like protection domain handling and assignement of devices to domains
2157 * which is not possible with the dma_ops interface.
2158 *
2159 *****************************************************************************/
2160
2161 static void cleanup_domain(struct protection_domain *domain)
2162 {
2163 unsigned long flags;
2164 u16 devid;
2165
2166 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2167
2168 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2169 if (amd_iommu_pd_table[devid] == domain)
2170 __detach_device(domain, devid);
2171
2172 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2173 }
2174
2175 static void protection_domain_free(struct protection_domain *domain)
2176 {
2177 if (!domain)
2178 return;
2179
2180 if (domain->id)
2181 domain_id_free(domain->id);
2182
2183 kfree(domain);
2184 }
2185
2186 static struct protection_domain *protection_domain_alloc(void)
2187 {
2188 struct protection_domain *domain;
2189
2190 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2191 if (!domain)
2192 return NULL;
2193
2194 spin_lock_init(&domain->lock);
2195 domain->id = domain_id_alloc();
2196 if (!domain->id)
2197 goto out_err;
2198
2199 return domain;
2200
2201 out_err:
2202 kfree(domain);
2203
2204 return NULL;
2205 }
2206
2207 static int amd_iommu_domain_init(struct iommu_domain *dom)
2208 {
2209 struct protection_domain *domain;
2210
2211 domain = protection_domain_alloc();
2212 if (!domain)
2213 goto out_free;
2214
2215 domain->mode = PAGE_MODE_3_LEVEL;
2216 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2217 if (!domain->pt_root)
2218 goto out_free;
2219
2220 dom->priv = domain;
2221
2222 return 0;
2223
2224 out_free:
2225 protection_domain_free(domain);
2226
2227 return -ENOMEM;
2228 }
2229
2230 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2231 {
2232 struct protection_domain *domain = dom->priv;
2233
2234 if (!domain)
2235 return;
2236
2237 if (domain->dev_cnt > 0)
2238 cleanup_domain(domain);
2239
2240 BUG_ON(domain->dev_cnt != 0);
2241
2242 free_pagetable(domain);
2243
2244 domain_id_free(domain->id);
2245
2246 kfree(domain);
2247
2248 dom->priv = NULL;
2249 }
2250
2251 static void amd_iommu_detach_device(struct iommu_domain *dom,
2252 struct device *dev)
2253 {
2254 struct protection_domain *domain = dom->priv;
2255 struct amd_iommu *iommu;
2256 struct pci_dev *pdev;
2257 u16 devid;
2258
2259 if (dev->bus != &pci_bus_type)
2260 return;
2261
2262 pdev = to_pci_dev(dev);
2263
2264 devid = calc_devid(pdev->bus->number, pdev->devfn);
2265
2266 if (devid > 0)
2267 detach_device(domain, devid);
2268
2269 iommu = amd_iommu_rlookup_table[devid];
2270 if (!iommu)
2271 return;
2272
2273 iommu_queue_inv_dev_entry(iommu, devid);
2274 iommu_completion_wait(iommu);
2275 }
2276
2277 static int amd_iommu_attach_device(struct iommu_domain *dom,
2278 struct device *dev)
2279 {
2280 struct protection_domain *domain = dom->priv;
2281 struct protection_domain *old_domain;
2282 struct amd_iommu *iommu;
2283 struct pci_dev *pdev;
2284 u16 devid;
2285
2286 if (dev->bus != &pci_bus_type)
2287 return -EINVAL;
2288
2289 pdev = to_pci_dev(dev);
2290
2291 devid = calc_devid(pdev->bus->number, pdev->devfn);
2292
2293 if (devid >= amd_iommu_last_bdf ||
2294 devid != amd_iommu_alias_table[devid])
2295 return -EINVAL;
2296
2297 iommu = amd_iommu_rlookup_table[devid];
2298 if (!iommu)
2299 return -EINVAL;
2300
2301 old_domain = domain_for_device(devid);
2302 if (old_domain)
2303 detach_device(old_domain, devid);
2304
2305 attach_device(iommu, domain, devid);
2306
2307 iommu_completion_wait(iommu);
2308
2309 return 0;
2310 }
2311
2312 static int amd_iommu_map_range(struct iommu_domain *dom,
2313 unsigned long iova, phys_addr_t paddr,
2314 size_t size, int iommu_prot)
2315 {
2316 struct protection_domain *domain = dom->priv;
2317 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2318 int prot = 0;
2319 int ret;
2320
2321 if (iommu_prot & IOMMU_READ)
2322 prot |= IOMMU_PROT_IR;
2323 if (iommu_prot & IOMMU_WRITE)
2324 prot |= IOMMU_PROT_IW;
2325
2326 iova &= PAGE_MASK;
2327 paddr &= PAGE_MASK;
2328
2329 for (i = 0; i < npages; ++i) {
2330 ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k);
2331 if (ret)
2332 return ret;
2333
2334 iova += PAGE_SIZE;
2335 paddr += PAGE_SIZE;
2336 }
2337
2338 return 0;
2339 }
2340
2341 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2342 unsigned long iova, size_t size)
2343 {
2344
2345 struct protection_domain *domain = dom->priv;
2346 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2347
2348 iova &= PAGE_MASK;
2349
2350 for (i = 0; i < npages; ++i) {
2351 iommu_unmap_page(domain, iova, PM_MAP_4k);
2352 iova += PAGE_SIZE;
2353 }
2354
2355 iommu_flush_domain(domain->id);
2356 }
2357
2358 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2359 unsigned long iova)
2360 {
2361 struct protection_domain *domain = dom->priv;
2362 unsigned long offset = iova & ~PAGE_MASK;
2363 phys_addr_t paddr;
2364 u64 *pte;
2365
2366 pte = fetch_pte(domain, iova, PM_MAP_4k);
2367
2368 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2369 return 0;
2370
2371 paddr = *pte & IOMMU_PAGE_MASK;
2372 paddr |= offset;
2373
2374 return paddr;
2375 }
2376
2377 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2378 unsigned long cap)
2379 {
2380 return 0;
2381 }
2382
2383 static struct iommu_ops amd_iommu_ops = {
2384 .domain_init = amd_iommu_domain_init,
2385 .domain_destroy = amd_iommu_domain_destroy,
2386 .attach_dev = amd_iommu_attach_device,
2387 .detach_dev = amd_iommu_detach_device,
2388 .map = amd_iommu_map_range,
2389 .unmap = amd_iommu_unmap_range,
2390 .iova_to_phys = amd_iommu_iova_to_phys,
2391 .domain_has_cap = amd_iommu_domain_has_cap,
2392 };
2393
2394 /*****************************************************************************
2395 *
2396 * The next functions do a basic initialization of IOMMU for pass through
2397 * mode
2398 *
2399 * In passthrough mode the IOMMU is initialized and enabled but not used for
2400 * DMA-API translation.
2401 *
2402 *****************************************************************************/
2403
2404 int __init amd_iommu_init_passthrough(void)
2405 {
2406 struct pci_dev *dev = NULL;
2407 u16 devid, devid2;
2408
2409 /* allocate passthroug domain */
2410 pt_domain = protection_domain_alloc();
2411 if (!pt_domain)
2412 return -ENOMEM;
2413
2414 pt_domain->mode |= PAGE_MODE_NONE;
2415
2416 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2417 struct amd_iommu *iommu;
2418
2419 devid = calc_devid(dev->bus->number, dev->devfn);
2420 if (devid > amd_iommu_last_bdf)
2421 continue;
2422
2423 devid2 = amd_iommu_alias_table[devid];
2424
2425 iommu = amd_iommu_rlookup_table[devid2];
2426 if (!iommu)
2427 continue;
2428
2429 __attach_device(iommu, pt_domain, devid);
2430 __attach_device(iommu, pt_domain, devid2);
2431 }
2432
2433 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
2434
2435 return 0;
2436 }
Linux with added FPC-III support