x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / ata / pata_at32.c
blob5c129f99a7e36256c18772b074ac87eb95bfdcb5
1 /*
2 * AVR32 SMC/CFC PATA Driver
4 * Copyright (C) 2007 Atmel Norway
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 */
11 #define DEBUG
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <scsi/scsi_host.h>
22 #include <linux/ata.h>
23 #include <linux/libata.h>
24 #include <linux/err.h>
25 #include <linux/io.h>
27 #include <mach/board.h>
28 #include <mach/smc.h>
30 #define DRV_NAME "pata_at32"
31 #define DRV_VERSION "0.0.3"
34 * CompactFlash controller memory layout relative to the base address:
36 * Attribute memory: 0000 0000 -> 003f ffff
37 * Common memory: 0040 0000 -> 007f ffff
38 * I/O memory: 0080 0000 -> 00bf ffff
39 * True IDE Mode: 00c0 0000 -> 00df ffff
40 * Alt IDE Mode: 00e0 0000 -> 00ff ffff
42 * Only True IDE and Alt True IDE mode are needed for this driver.
44 * True IDE mode => CS0 = 0, CS1 = 1 (cmd, error, stat, etc)
45 * Alt True IDE mode => CS0 = 1, CS1 = 0 (ctl, alt_stat)
47 #define CF_IDE_OFFSET 0x00c00000
48 #define CF_ALT_IDE_OFFSET 0x00e00000
49 #define CF_RES_SIZE 2048
52 * Define DEBUG_BUS if you are doing debugging of your own EBI -> PATA
53 * adaptor with a logic analyzer or similar.
55 #undef DEBUG_BUS
58 * ATA PIO modes
60 * Name | Mb/s | Min cycle time | Mask
61 * --------+-------+----------------+--------
62 * Mode 0 | 3.3 | 600 ns | 0x01
63 * Mode 1 | 5.2 | 383 ns | 0x03
64 * Mode 2 | 8.3 | 240 ns | 0x07
65 * Mode 3 | 11.1 | 180 ns | 0x0f
66 * Mode 4 | 16.7 | 120 ns | 0x1f
68 * Alter PIO_MASK below according to table to set maximal PIO mode.
70 enum {
71 PIO_MASK = ATA_PIO4,
75 * Struct containing private information about device.
77 struct at32_ide_info {
78 unsigned int irq;
79 struct resource res_ide;
80 struct resource res_alt;
81 void __iomem *ide_addr;
82 void __iomem *alt_addr;
83 unsigned int cs;
84 struct smc_config smc;
88 * Setup SMC for the given ATA timing.
90 static int pata_at32_setup_timing(struct device *dev,
91 struct at32_ide_info *info,
92 const struct ata_timing *ata)
94 struct smc_config *smc = &info->smc;
95 struct smc_timing timing;
97 int active;
98 int recover;
100 memset(&timing, 0, sizeof(struct smc_timing));
102 /* Total cycle time */
103 timing.read_cycle = ata->cyc8b;
105 /* DIOR <= CFIOR timings */
106 timing.nrd_setup = ata->setup;
107 timing.nrd_pulse = ata->act8b;
108 timing.nrd_recover = ata->rec8b;
110 /* Convert nanosecond timing to clock cycles */
111 smc_set_timing(smc, &timing);
113 /* Add one extra cycle setup due to signal ring */
114 smc->nrd_setup = smc->nrd_setup + 1;
116 active = smc->nrd_setup + smc->nrd_pulse;
117 recover = smc->read_cycle - active;
119 /* Need at least two cycles recovery */
120 if (recover < 2)
121 smc->read_cycle = active + 2;
123 /* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */
124 smc->ncs_read_setup = 1;
125 smc->ncs_read_pulse = smc->read_cycle - 2;
127 /* Write timings same as read timings */
128 smc->write_cycle = smc->read_cycle;
129 smc->nwe_setup = smc->nrd_setup;
130 smc->nwe_pulse = smc->nrd_pulse;
131 smc->ncs_write_setup = smc->ncs_read_setup;
132 smc->ncs_write_pulse = smc->ncs_read_pulse;
134 /* Do some debugging output of ATA and SMC timings */
135 dev_dbg(dev, "ATA: C=%d S=%d P=%d R=%d\n",
136 ata->cyc8b, ata->setup, ata->act8b, ata->rec8b);
138 dev_dbg(dev, "SMC: C=%d S=%d P=%d NS=%d NP=%d\n",
139 smc->read_cycle, smc->nrd_setup, smc->nrd_pulse,
140 smc->ncs_read_setup, smc->ncs_read_pulse);
142 /* Finally, configure the SMC */
143 return smc_set_configuration(info->cs, smc);
147 * Procedures for libATA.
149 static void pata_at32_set_piomode(struct ata_port *ap, struct ata_device *adev)
151 struct ata_timing timing;
152 struct at32_ide_info *info = ap->host->private_data;
154 int ret;
156 /* Compute ATA timing */
157 ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0);
158 if (ret) {
159 dev_warn(ap->dev, "Failed to compute ATA timing %d\n", ret);
160 return;
163 /* Setup SMC to ATA timing */
164 ret = pata_at32_setup_timing(ap->dev, info, &timing);
165 if (ret) {
166 dev_warn(ap->dev, "Failed to setup ATA timing %d\n", ret);
167 return;
171 static struct scsi_host_template at32_sht = {
172 ATA_PIO_SHT(DRV_NAME),
175 static struct ata_port_operations at32_port_ops = {
176 .inherits = &ata_sff_port_ops,
177 .cable_detect = ata_cable_40wire,
178 .set_piomode = pata_at32_set_piomode,
181 static int __init pata_at32_init_one(struct device *dev,
182 struct at32_ide_info *info)
184 struct ata_host *host;
185 struct ata_port *ap;
187 host = ata_host_alloc(dev, 1);
188 if (!host)
189 return -ENOMEM;
191 ap = host->ports[0];
193 /* Setup ATA bindings */
194 ap->ops = &at32_port_ops;
195 ap->pio_mask = PIO_MASK;
196 ap->flags |= ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS;
199 * Since all 8-bit taskfile transfers has to go on the lower
200 * byte of the data bus and there is a bug in the SMC that
201 * makes it impossible to alter the bus width during runtime,
202 * we need to hardwire the address signals as follows:
204 * A_IDE(2:0) <= A_EBI(3:1)
206 * This makes all addresses on the EBI even, thus all data
207 * will be on the lower byte of the data bus. All addresses
208 * used by libATA need to be altered according to this.
210 ap->ioaddr.altstatus_addr = info->alt_addr + (0x06 << 1);
211 ap->ioaddr.ctl_addr = info->alt_addr + (0x06 << 1);
213 ap->ioaddr.data_addr = info->ide_addr + (ATA_REG_DATA << 1);
214 ap->ioaddr.error_addr = info->ide_addr + (ATA_REG_ERR << 1);
215 ap->ioaddr.feature_addr = info->ide_addr + (ATA_REG_FEATURE << 1);
216 ap->ioaddr.nsect_addr = info->ide_addr + (ATA_REG_NSECT << 1);
217 ap->ioaddr.lbal_addr = info->ide_addr + (ATA_REG_LBAL << 1);
218 ap->ioaddr.lbam_addr = info->ide_addr + (ATA_REG_LBAM << 1);
219 ap->ioaddr.lbah_addr = info->ide_addr + (ATA_REG_LBAH << 1);
220 ap->ioaddr.device_addr = info->ide_addr + (ATA_REG_DEVICE << 1);
221 ap->ioaddr.status_addr = info->ide_addr + (ATA_REG_STATUS << 1);
222 ap->ioaddr.command_addr = info->ide_addr + (ATA_REG_CMD << 1);
224 /* Set info as private data of ATA host */
225 host->private_data = info;
227 /* Register ATA device and return */
228 return ata_host_activate(host, info->irq, ata_sff_interrupt,
229 IRQF_SHARED | IRQF_TRIGGER_RISING,
230 &at32_sht);
234 * This function may come in handy for people analyzing their own
235 * EBI -> PATA adaptors.
237 #ifdef DEBUG_BUS
239 static void __init pata_at32_debug_bus(struct device *dev,
240 struct at32_ide_info *info)
242 const int d1 = 0xff;
243 const int d2 = 0x00;
245 int i;
247 /* Write 8-bit values (registers) */
248 iowrite8(d1, info->alt_addr + (0x06 << 1));
249 iowrite8(d2, info->alt_addr + (0x06 << 1));
251 for (i = 0; i < 8; i++) {
252 iowrite8(d1, info->ide_addr + (i << 1));
253 iowrite8(d2, info->ide_addr + (i << 1));
256 /* Write 16 bit values (data) */
257 iowrite16(d1, info->ide_addr);
258 iowrite16(d1 << 8, info->ide_addr);
260 iowrite16(d1, info->ide_addr);
261 iowrite16(d1 << 8, info->ide_addr);
264 #endif
266 static int __init pata_at32_probe(struct platform_device *pdev)
268 const struct ata_timing initial_timing =
269 {XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0};
271 struct device *dev = &pdev->dev;
272 struct at32_ide_info *info;
273 struct ide_platform_data *board = pdev->dev.platform_data;
274 struct resource *res;
276 int irq;
277 int ret;
279 if (!board)
280 return -ENXIO;
282 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
283 if (!res)
284 return -ENXIO;
286 /* Retrive IRQ */
287 irq = platform_get_irq(pdev, 0);
288 if (irq < 0)
289 return irq;
291 /* Setup struct containing private information */
292 info = kzalloc(sizeof(struct at32_ide_info), GFP_KERNEL);
293 if (!info)
294 return -ENOMEM;
296 info->irq = irq;
297 info->cs = board->cs;
299 /* Request memory resources */
300 info->res_ide.start = res->start + CF_IDE_OFFSET;
301 info->res_ide.end = info->res_ide.start + CF_RES_SIZE - 1;
302 info->res_ide.name = "ide";
303 info->res_ide.flags = IORESOURCE_MEM;
305 ret = request_resource(res, &info->res_ide);
306 if (ret)
307 goto err_req_res_ide;
309 info->res_alt.start = res->start + CF_ALT_IDE_OFFSET;
310 info->res_alt.end = info->res_alt.start + CF_RES_SIZE - 1;
311 info->res_alt.name = "alt";
312 info->res_alt.flags = IORESOURCE_MEM;
314 ret = request_resource(res, &info->res_alt);
315 if (ret)
316 goto err_req_res_alt;
318 /* Setup non-timing elements of SMC */
319 info->smc.bus_width = 2; /* 16 bit data bus */
320 info->smc.nrd_controlled = 1; /* Sample data on rising edge of NRD */
321 info->smc.nwe_controlled = 0; /* Drive data on falling edge of NCS */
322 info->smc.nwait_mode = 3; /* NWAIT is in READY mode */
323 info->smc.byte_write = 0; /* Byte select access type */
324 info->smc.tdf_mode = 0; /* TDF optimization disabled */
325 info->smc.tdf_cycles = 0; /* No TDF wait cycles */
327 /* Setup SMC to ATA timing */
328 ret = pata_at32_setup_timing(dev, info, &initial_timing);
329 if (ret)
330 goto err_setup_timing;
332 /* Map ATA address space */
333 ret = -ENOMEM;
334 info->ide_addr = devm_ioremap(dev, info->res_ide.start, 16);
335 info->alt_addr = devm_ioremap(dev, info->res_alt.start, 16);
336 if (!info->ide_addr || !info->alt_addr)
337 goto err_ioremap;
339 #ifdef DEBUG_BUS
340 pata_at32_debug_bus(dev, info);
341 #endif
343 /* Setup and register ATA device */
344 ret = pata_at32_init_one(dev, info);
345 if (ret)
346 goto err_ata_device;
348 return 0;
350 err_ata_device:
351 err_ioremap:
352 err_setup_timing:
353 release_resource(&info->res_alt);
354 err_req_res_alt:
355 release_resource(&info->res_ide);
356 err_req_res_ide:
357 kfree(info);
359 return ret;
362 static int __exit pata_at32_remove(struct platform_device *pdev)
364 struct ata_host *host = platform_get_drvdata(pdev);
365 struct at32_ide_info *info;
367 if (!host)
368 return 0;
370 info = host->private_data;
371 ata_host_detach(host);
373 if (!info)
374 return 0;
376 release_resource(&info->res_ide);
377 release_resource(&info->res_alt);
379 kfree(info);
381 return 0;
384 /* work with hotplug and coldplug */
385 MODULE_ALIAS("platform:at32_ide");
387 static struct platform_driver pata_at32_driver = {
388 .remove = __exit_p(pata_at32_remove),
389 .driver = {
390 .name = "at32_ide",
391 .owner = THIS_MODULE,
395 static int __init pata_at32_init(void)
397 return platform_driver_probe(&pata_at32_driver, pata_at32_probe);
400 static void __exit pata_at32_exit(void)
402 platform_driver_unregister(&pata_at32_driver);
405 module_init(pata_at32_init);
406 module_exit(pata_at32_exit);
408 MODULE_LICENSE("GPL");
409 MODULE_DESCRIPTION("AVR32 SMC/CFC PATA Driver");
410 MODULE_AUTHOR("Kristoffer Nyborg Gregertsen <kngregertsen@norway.atmel.com>");
411 MODULE_VERSION(DRV_VERSION);