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x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / ata / sata_promise.c
blob07d8d00b4d344cb38740f9d6a60ed6478e2b2b67
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Mikael Pettersson <mikpe@it.uu.se>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2003-2004 Red Hat, Inc.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware information only available under NDA.
31 *
32 */
33
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/device.h>
42 #include <scsi/scsi.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "2.12"
50
51 enum {
52 PDC_MAX_PORTS = 4,
53 PDC_MMIO_BAR = 3,
54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
55
56 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
57 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
58 PDC_FLASH_CTL = 0x44, /* Flash control register */
59 PDC_PCI_CTL = 0x48, /* PCI control/status reg */
60 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
61 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
62 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
63 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
64
65 /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */
66 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
67 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
68 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
69 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
70 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
71 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
72 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
73 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
74 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
75 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
76 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
77
78 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */
79 PDC_SATA_ERROR = 0x04,
80 PDC_PHYMODE4 = 0x14,
81 PDC_LINK_LAYER_ERRORS = 0x6C,
82 PDC_FPDMA_CTLSTAT = 0xD8,
83 PDC_INTERNAL_DEBUG_1 = 0xF8, /* also used for PATA */
84 PDC_INTERNAL_DEBUG_2 = 0xFC, /* also used for PATA */
85
86 /* PDC_FPDMA_CTLSTAT bit definitions */
87 PDC_FPDMA_CTLSTAT_RESET = 1 << 3,
88 PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG = 1 << 10,
89 PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG = 1 << 11,
90
91 /* PDC_GLOBAL_CTL bit definitions */
92 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
93 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
94 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
95 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
96 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
97 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
98 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
99 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
100 PDC_DRIVE_ERR = (1 << 21), /* drive error */
101 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
102 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
103 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
104 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
105 PDC2_ATA_DMA_CNT_ERR,
106 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
107 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
108 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
109 PDC1_ERR_MASK | PDC2_ERR_MASK,
110
111 board_2037x = 0, /* FastTrak S150 TX2plus */
112 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
113 board_20319 = 2, /* FastTrak S150 TX4 */
114 board_20619 = 3, /* FastTrak TX4000 */
115 board_2057x = 4, /* SATAII150 Tx2plus */
116 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
117 board_40518 = 6, /* SATAII150 Tx4 */
118
119 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
120
121 /* Sequence counter control registers bit definitions */
122 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
123
124 /* Feature register values */
125 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
126 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
127
128 /* Device/Head register values */
129 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
130
131 /* PDC_CTLSTAT bit definitions */
132 PDC_DMA_ENABLE = (1 << 7),
133 PDC_IRQ_DISABLE = (1 << 10),
134 PDC_RESET = (1 << 11), /* HDMA reset */
135
136 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
137 ATA_FLAG_MMIO |
138 ATA_FLAG_PIO_POLLING,
139
140 /* ap->flags bits */
141 PDC_FLAG_GEN_II = (1 << 24),
142 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
143 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
144 };
145
146 struct pdc_port_priv {
147 u8 *pkt;
148 dma_addr_t pkt_dma;
149 };
150
151 static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
152 static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
153 static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
154 static int pdc_common_port_start(struct ata_port *ap);
155 static int pdc_sata_port_start(struct ata_port *ap);
156 static void pdc_qc_prep(struct ata_queued_cmd *qc);
157 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
158 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
159 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
160 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
161 static void pdc_irq_clear(struct ata_port *ap);
162 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc);
163 static void pdc_freeze(struct ata_port *ap);
164 static void pdc_sata_freeze(struct ata_port *ap);
165 static void pdc_thaw(struct ata_port *ap);
166 static void pdc_sata_thaw(struct ata_port *ap);
167 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
168 unsigned long deadline);
169 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
170 unsigned long deadline);
171 static void pdc_error_handler(struct ata_port *ap);
172 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
173 static int pdc_pata_cable_detect(struct ata_port *ap);
174 static int pdc_sata_cable_detect(struct ata_port *ap);
175
176 static struct scsi_host_template pdc_ata_sht = {
177 ATA_BASE_SHT(DRV_NAME),
178 .sg_tablesize = PDC_MAX_PRD,
179 .dma_boundary = ATA_DMA_BOUNDARY,
180 };
181
182 static const struct ata_port_operations pdc_common_ops = {
183 .inherits = &ata_sff_port_ops,
184
185 .sff_tf_load = pdc_tf_load_mmio,
186 .sff_exec_command = pdc_exec_command_mmio,
187 .check_atapi_dma = pdc_check_atapi_dma,
188 .qc_prep = pdc_qc_prep,
189 .qc_issue = pdc_qc_issue,
190
191 .sff_irq_clear = pdc_irq_clear,
192 .lost_interrupt = ATA_OP_NULL,
193
194 .post_internal_cmd = pdc_post_internal_cmd,
195 .error_handler = pdc_error_handler,
196 };
197
198 static struct ata_port_operations pdc_sata_ops = {
199 .inherits = &pdc_common_ops,
200 .cable_detect = pdc_sata_cable_detect,
201 .freeze = pdc_sata_freeze,
202 .thaw = pdc_sata_thaw,
203 .scr_read = pdc_sata_scr_read,
204 .scr_write = pdc_sata_scr_write,
205 .port_start = pdc_sata_port_start,
206 .hardreset = pdc_sata_hardreset,
207 };
208
209 /* First-generation chips need a more restrictive ->check_atapi_dma op,
210 and ->freeze/thaw that ignore the hotplug controls. */
211 static struct ata_port_operations pdc_old_sata_ops = {
212 .inherits = &pdc_sata_ops,
213 .freeze = pdc_freeze,
214 .thaw = pdc_thaw,
215 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
216 };
217
218 static struct ata_port_operations pdc_pata_ops = {
219 .inherits = &pdc_common_ops,
220 .cable_detect = pdc_pata_cable_detect,
221 .freeze = pdc_freeze,
222 .thaw = pdc_thaw,
223 .port_start = pdc_common_port_start,
224 .softreset = pdc_pata_softreset,
225 };
226
227 static const struct ata_port_info pdc_port_info[] = {
228 [board_2037x] =
229 {
230 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
231 PDC_FLAG_SATA_PATA,
232 .pio_mask = ATA_PIO4,
233 .mwdma_mask = ATA_MWDMA2,
234 .udma_mask = ATA_UDMA6,
235 .port_ops = &pdc_old_sata_ops,
236 },
237
238 [board_2037x_pata] =
239 {
240 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
241 .pio_mask = ATA_PIO4,
242 .mwdma_mask = ATA_MWDMA2,
243 .udma_mask = ATA_UDMA6,
244 .port_ops = &pdc_pata_ops,
245 },
246
247 [board_20319] =
248 {
249 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
250 PDC_FLAG_4_PORTS,
251 .pio_mask = ATA_PIO4,
252 .mwdma_mask = ATA_MWDMA2,
253 .udma_mask = ATA_UDMA6,
254 .port_ops = &pdc_old_sata_ops,
255 },
256
257 [board_20619] =
258 {
259 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
260 PDC_FLAG_4_PORTS,
261 .pio_mask = ATA_PIO4,
262 .mwdma_mask = ATA_MWDMA2,
263 .udma_mask = ATA_UDMA6,
264 .port_ops = &pdc_pata_ops,
265 },
266
267 [board_2057x] =
268 {
269 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
270 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
271 .pio_mask = ATA_PIO4,
272 .mwdma_mask = ATA_MWDMA2,
273 .udma_mask = ATA_UDMA6,
274 .port_ops = &pdc_sata_ops,
275 },
276
277 [board_2057x_pata] =
278 {
279 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
280 PDC_FLAG_GEN_II,
281 .pio_mask = ATA_PIO4,
282 .mwdma_mask = ATA_MWDMA2,
283 .udma_mask = ATA_UDMA6,
284 .port_ops = &pdc_pata_ops,
285 },
286
287 [board_40518] =
288 {
289 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
290 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
291 .pio_mask = ATA_PIO4,
292 .mwdma_mask = ATA_MWDMA2,
293 .udma_mask = ATA_UDMA6,
294 .port_ops = &pdc_sata_ops,
295 },
296 };
297
298 static const struct pci_device_id pdc_ata_pci_tbl[] = {
299 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
300 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
301 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
302 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
303 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
304 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
305 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
306 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
307 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
308 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
309
310 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
311 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
312 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
313 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
314 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
315 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
316
317 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
318
319 { } /* terminate list */
320 };
321
322 static struct pci_driver pdc_ata_pci_driver = {
323 .name = DRV_NAME,
324 .id_table = pdc_ata_pci_tbl,
325 .probe = pdc_ata_init_one,
326 .remove = ata_pci_remove_one,
327 };
328
329 static int pdc_common_port_start(struct ata_port *ap)
330 {
331 struct device *dev = ap->host->dev;
332 struct pdc_port_priv *pp;
333 int rc;
334
335 rc = ata_port_start(ap);
336 if (rc)
337 return rc;
338
339 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
340 if (!pp)
341 return -ENOMEM;
342
343 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
344 if (!pp->pkt)
345 return -ENOMEM;
346
347 ap->private_data = pp;
348
349 return 0;
350 }
351
352 static int pdc_sata_port_start(struct ata_port *ap)
353 {
354 int rc;
355
356 rc = pdc_common_port_start(ap);
357 if (rc)
358 return rc;
359
360 /* fix up PHYMODE4 align timing */
361 if (ap->flags & PDC_FLAG_GEN_II) {
362 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
363 unsigned int tmp;
364
365 tmp = readl(sata_mmio + PDC_PHYMODE4);
366 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
367 writel(tmp, sata_mmio + PDC_PHYMODE4);
368 }
369
370 return 0;
371 }
372
373 static void pdc_fpdma_clear_interrupt_flag(struct ata_port *ap)
374 {
375 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
376 u32 tmp;
377
378 tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT);
379 tmp |= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG;
380 tmp |= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG;
381
382 /* It's not allowed to write to the entire FPDMA_CTLSTAT register
383 when NCQ is running. So do a byte-sized write to bits 10 and 11. */
384 writeb(tmp >> 8, sata_mmio + PDC_FPDMA_CTLSTAT + 1);
385 readb(sata_mmio + PDC_FPDMA_CTLSTAT + 1); /* flush */
386 }
387
388 static void pdc_fpdma_reset(struct ata_port *ap)
389 {
390 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
391 u8 tmp;
392
393 tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT);
394 tmp &= 0x7F;
395 tmp |= PDC_FPDMA_CTLSTAT_RESET;
396 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
397 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
398 udelay(100);
399 tmp &= ~PDC_FPDMA_CTLSTAT_RESET;
400 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
401 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
402
403 pdc_fpdma_clear_interrupt_flag(ap);
404 }
405
406 static void pdc_not_at_command_packet_phase(struct ata_port *ap)
407 {
408 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
409 unsigned int i;
410 u32 tmp;
411
412 /* check not at ASIC packet command phase */
413 for (i = 0; i < 100; ++i) {
414 writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1);
415 tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2);
416 if ((tmp & 0xF) != 1)
417 break;
418 udelay(100);
419 }
420 }
421
422 static void pdc_clear_internal_debug_record_error_register(struct ata_port *ap)
423 {
424 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
425
426 writel(0xffffffff, sata_mmio + PDC_SATA_ERROR);
427 writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS);
428 }
429
430 static void pdc_reset_port(struct ata_port *ap)
431 {
432 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
433 unsigned int i;
434 u32 tmp;
435
436 if (ap->flags & PDC_FLAG_GEN_II)
437 pdc_not_at_command_packet_phase(ap);
438
439 tmp = readl(ata_ctlstat_mmio);
440 tmp |= PDC_RESET;
441 writel(tmp, ata_ctlstat_mmio);
442
443 for (i = 11; i > 0; i--) {
444 tmp = readl(ata_ctlstat_mmio);
445 if (tmp & PDC_RESET)
446 break;
447
448 udelay(100);
449
450 tmp |= PDC_RESET;
451 writel(tmp, ata_ctlstat_mmio);
452 }
453
454 tmp &= ~PDC_RESET;
455 writel(tmp, ata_ctlstat_mmio);
456 readl(ata_ctlstat_mmio); /* flush */
457
458 if (sata_scr_valid(&ap->link) && (ap->flags & PDC_FLAG_GEN_II)) {
459 pdc_fpdma_reset(ap);
460 pdc_clear_internal_debug_record_error_register(ap);
461 }
462 }
463
464 static int pdc_pata_cable_detect(struct ata_port *ap)
465 {
466 u8 tmp;
467 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
468
469 tmp = readb(ata_mmio + PDC_CTLSTAT + 3);
470 if (tmp & 0x01)
471 return ATA_CBL_PATA40;
472 return ATA_CBL_PATA80;
473 }
474
475 static int pdc_sata_cable_detect(struct ata_port *ap)
476 {
477 return ATA_CBL_SATA;
478 }
479
480 static int pdc_sata_scr_read(struct ata_link *link,
481 unsigned int sc_reg, u32 *val)
482 {
483 if (sc_reg > SCR_CONTROL)
484 return -EINVAL;
485 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
486 return 0;
487 }
488
489 static int pdc_sata_scr_write(struct ata_link *link,
490 unsigned int sc_reg, u32 val)
491 {
492 if (sc_reg > SCR_CONTROL)
493 return -EINVAL;
494 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
495 return 0;
496 }
497
498 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
499 {
500 struct ata_port *ap = qc->ap;
501 dma_addr_t sg_table = ap->prd_dma;
502 unsigned int cdb_len = qc->dev->cdb_len;
503 u8 *cdb = qc->cdb;
504 struct pdc_port_priv *pp = ap->private_data;
505 u8 *buf = pp->pkt;
506 __le32 *buf32 = (__le32 *) buf;
507 unsigned int dev_sel, feature;
508
509 /* set control bits (byte 0), zero delay seq id (byte 3),
510 * and seq id (byte 2)
511 */
512 switch (qc->tf.protocol) {
513 case ATAPI_PROT_DMA:
514 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
515 buf32[0] = cpu_to_le32(PDC_PKT_READ);
516 else
517 buf32[0] = 0;
518 break;
519 case ATAPI_PROT_NODATA:
520 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
521 break;
522 default:
523 BUG();
524 break;
525 }
526 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
527 buf32[2] = 0; /* no next-packet */
528
529 /* select drive */
530 if (sata_scr_valid(&ap->link))
531 dev_sel = PDC_DEVICE_SATA;
532 else
533 dev_sel = qc->tf.device;
534
535 buf[12] = (1 << 5) | ATA_REG_DEVICE;
536 buf[13] = dev_sel;
537 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
538 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
539
540 buf[16] = (1 << 5) | ATA_REG_NSECT;
541 buf[17] = qc->tf.nsect;
542 buf[18] = (1 << 5) | ATA_REG_LBAL;
543 buf[19] = qc->tf.lbal;
544
545 /* set feature and byte counter registers */
546 if (qc->tf.protocol != ATAPI_PROT_DMA)
547 feature = PDC_FEATURE_ATAPI_PIO;
548 else
549 feature = PDC_FEATURE_ATAPI_DMA;
550
551 buf[20] = (1 << 5) | ATA_REG_FEATURE;
552 buf[21] = feature;
553 buf[22] = (1 << 5) | ATA_REG_BYTEL;
554 buf[23] = qc->tf.lbam;
555 buf[24] = (1 << 5) | ATA_REG_BYTEH;
556 buf[25] = qc->tf.lbah;
557
558 /* send ATAPI packet command 0xA0 */
559 buf[26] = (1 << 5) | ATA_REG_CMD;
560 buf[27] = qc->tf.command;
561
562 /* select drive and check DRQ */
563 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
564 buf[29] = dev_sel;
565
566 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
567 BUG_ON(cdb_len & ~0x1E);
568
569 /* append the CDB as the final part */
570 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
571 memcpy(buf+31, cdb, cdb_len);
572 }
573
574 /**
575 * pdc_fill_sg - Fill PCI IDE PRD table
576 * @qc: Metadata associated with taskfile to be transferred
577 *
578 * Fill PCI IDE PRD (scatter-gather) table with segments
579 * associated with the current disk command.
580 * Make sure hardware does not choke on it.
581 *
582 * LOCKING:
583 * spin_lock_irqsave(host lock)
584 *
585 */
586 static void pdc_fill_sg(struct ata_queued_cmd *qc)
587 {
588 struct ata_port *ap = qc->ap;
589 struct scatterlist *sg;
590 const u32 SG_COUNT_ASIC_BUG = 41*4;
591 unsigned int si, idx;
592 u32 len;
593
594 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
595 return;
596
597 idx = 0;
598 for_each_sg(qc->sg, sg, qc->n_elem, si) {
599 u32 addr, offset;
600 u32 sg_len;
601
602 /* determine if physical DMA addr spans 64K boundary.
603 * Note h/w doesn't support 64-bit, so we unconditionally
604 * truncate dma_addr_t to u32.
605 */
606 addr = (u32) sg_dma_address(sg);
607 sg_len = sg_dma_len(sg);
608
609 while (sg_len) {
610 offset = addr & 0xffff;
611 len = sg_len;
612 if ((offset + sg_len) > 0x10000)
613 len = 0x10000 - offset;
614
615 ap->prd[idx].addr = cpu_to_le32(addr);
616 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
617 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
618
619 idx++;
620 sg_len -= len;
621 addr += len;
622 }
623 }
624
625 len = le32_to_cpu(ap->prd[idx - 1].flags_len);
626
627 if (len > SG_COUNT_ASIC_BUG) {
628 u32 addr;
629
630 VPRINTK("Splitting last PRD.\n");
631
632 addr = le32_to_cpu(ap->prd[idx - 1].addr);
633 ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
634 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
635
636 addr = addr + len - SG_COUNT_ASIC_BUG;
637 len = SG_COUNT_ASIC_BUG;
638 ap->prd[idx].addr = cpu_to_le32(addr);
639 ap->prd[idx].flags_len = cpu_to_le32(len);
640 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
641
642 idx++;
643 }
644
645 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
646 }
647
648 static void pdc_qc_prep(struct ata_queued_cmd *qc)
649 {
650 struct pdc_port_priv *pp = qc->ap->private_data;
651 unsigned int i;
652
653 VPRINTK("ENTER\n");
654
655 switch (qc->tf.protocol) {
656 case ATA_PROT_DMA:
657 pdc_fill_sg(qc);
658 /*FALLTHROUGH*/
659 case ATA_PROT_NODATA:
660 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
661 qc->dev->devno, pp->pkt);
662 if (qc->tf.flags & ATA_TFLAG_LBA48)
663 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
664 else
665 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
666 pdc_pkt_footer(&qc->tf, pp->pkt, i);
667 break;
668 case ATAPI_PROT_PIO:
669 pdc_fill_sg(qc);
670 break;
671 case ATAPI_PROT_DMA:
672 pdc_fill_sg(qc);
673 /*FALLTHROUGH*/
674 case ATAPI_PROT_NODATA:
675 pdc_atapi_pkt(qc);
676 break;
677 default:
678 break;
679 }
680 }
681
682 static int pdc_is_sataii_tx4(unsigned long flags)
683 {
684 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
685 return (flags & mask) == mask;
686 }
687
688 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
689 int is_sataii_tx4)
690 {
691 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
692 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
693 }
694
695 static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
696 {
697 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
698 }
699
700 static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
701 {
702 const struct ata_host *host = ap->host;
703 unsigned int nr_ports = pdc_sata_nr_ports(ap);
704 unsigned int i;
705
706 for (i = 0; i < nr_ports && host->ports[i] != ap; ++i)
707 ;
708 BUG_ON(i >= nr_ports);
709 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
710 }
711
712 static void pdc_freeze(struct ata_port *ap)
713 {
714 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
715 u32 tmp;
716
717 tmp = readl(ata_mmio + PDC_CTLSTAT);
718 tmp |= PDC_IRQ_DISABLE;
719 tmp &= ~PDC_DMA_ENABLE;
720 writel(tmp, ata_mmio + PDC_CTLSTAT);
721 readl(ata_mmio + PDC_CTLSTAT); /* flush */
722 }
723
724 static void pdc_sata_freeze(struct ata_port *ap)
725 {
726 struct ata_host *host = ap->host;
727 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
728 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
729 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
730 u32 hotplug_status;
731
732 /* Disable hotplug events on this port.
733 *
734 * Locking:
735 * 1) hotplug register accesses must be serialised via host->lock
736 * 2) ap->lock == &ap->host->lock
737 * 3) ->freeze() and ->thaw() are called with ap->lock held
738 */
739 hotplug_status = readl(host_mmio + hotplug_offset);
740 hotplug_status |= 0x11 << (ata_no + 16);
741 writel(hotplug_status, host_mmio + hotplug_offset);
742 readl(host_mmio + hotplug_offset); /* flush */
743
744 pdc_freeze(ap);
745 }
746
747 static void pdc_thaw(struct ata_port *ap)
748 {
749 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
750 u32 tmp;
751
752 /* clear IRQ */
753 readl(ata_mmio + PDC_COMMAND);
754
755 /* turn IRQ back on */
756 tmp = readl(ata_mmio + PDC_CTLSTAT);
757 tmp &= ~PDC_IRQ_DISABLE;
758 writel(tmp, ata_mmio + PDC_CTLSTAT);
759 readl(ata_mmio + PDC_CTLSTAT); /* flush */
760 }
761
762 static void pdc_sata_thaw(struct ata_port *ap)
763 {
764 struct ata_host *host = ap->host;
765 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
766 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
767 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
768 u32 hotplug_status;
769
770 pdc_thaw(ap);
771
772 /* Enable hotplug events on this port.
773 * Locking: see pdc_sata_freeze().
774 */
775 hotplug_status = readl(host_mmio + hotplug_offset);
776 hotplug_status |= 0x11 << ata_no;
777 hotplug_status &= ~(0x11 << (ata_no + 16));
778 writel(hotplug_status, host_mmio + hotplug_offset);
779 readl(host_mmio + hotplug_offset); /* flush */
780 }
781
782 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
783 unsigned long deadline)
784 {
785 pdc_reset_port(link->ap);
786 return ata_sff_softreset(link, class, deadline);
787 }
788
789 static unsigned int pdc_ata_port_to_ata_no(const struct ata_port *ap)
790 {
791 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
792 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
793
794 /* ata_mmio == host_mmio + 0x200 + ata_no * 0x80 */
795 return (ata_mmio - host_mmio - 0x200) / 0x80;
796 }
797
798 static void pdc_hard_reset_port(struct ata_port *ap)
799 {
800 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
801 void __iomem *pcictl_b1_mmio = host_mmio + PDC_PCI_CTL + 1;
802 unsigned int ata_no = pdc_ata_port_to_ata_no(ap);
803 u8 tmp;
804
805 spin_lock(&ap->host->lock);
806
807 tmp = readb(pcictl_b1_mmio);
808 tmp &= ~(0x10 << ata_no);
809 writeb(tmp, pcictl_b1_mmio);
810 readb(pcictl_b1_mmio); /* flush */
811 udelay(100);
812 tmp |= (0x10 << ata_no);
813 writeb(tmp, pcictl_b1_mmio);
814 readb(pcictl_b1_mmio); /* flush */
815
816 spin_unlock(&ap->host->lock);
817 }
818
819 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
820 unsigned long deadline)
821 {
822 if (link->ap->flags & PDC_FLAG_GEN_II)
823 pdc_not_at_command_packet_phase(link->ap);
824 /* hotplug IRQs should have been masked by pdc_sata_freeze() */
825 pdc_hard_reset_port(link->ap);
826 pdc_reset_port(link->ap);
827
828 /* sata_promise can't reliably acquire the first D2H Reg FIS
829 * after hardreset. Do non-waiting hardreset and request
830 * follow-up SRST.
831 */
832 return sata_std_hardreset(link, class, deadline);
833 }
834
835 static void pdc_error_handler(struct ata_port *ap)
836 {
837 if (!(ap->pflags & ATA_PFLAG_FROZEN))
838 pdc_reset_port(ap);
839
840 ata_std_error_handler(ap);
841 }
842
843 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
844 {
845 struct ata_port *ap = qc->ap;
846
847 /* make DMA engine forget about the failed command */
848 if (qc->flags & ATA_QCFLAG_FAILED)
849 pdc_reset_port(ap);
850 }
851
852 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
853 u32 port_status, u32 err_mask)
854 {
855 struct ata_eh_info *ehi = &ap->link.eh_info;
856 unsigned int ac_err_mask = 0;
857
858 ata_ehi_clear_desc(ehi);
859 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
860 port_status &= err_mask;
861
862 if (port_status & PDC_DRIVE_ERR)
863 ac_err_mask |= AC_ERR_DEV;
864 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
865 ac_err_mask |= AC_ERR_HSM;
866 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
867 ac_err_mask |= AC_ERR_ATA_BUS;
868 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
869 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
870 ac_err_mask |= AC_ERR_HOST_BUS;
871
872 if (sata_scr_valid(&ap->link)) {
873 u32 serror;
874
875 pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror);
876 ehi->serror |= serror;
877 }
878
879 qc->err_mask |= ac_err_mask;
880
881 pdc_reset_port(ap);
882
883 ata_port_abort(ap);
884 }
885
886 static unsigned int pdc_host_intr(struct ata_port *ap,
887 struct ata_queued_cmd *qc)
888 {
889 unsigned int handled = 0;
890 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
891 u32 port_status, err_mask;
892
893 err_mask = PDC_ERR_MASK;
894 if (ap->flags & PDC_FLAG_GEN_II)
895 err_mask &= ~PDC1_ERR_MASK;
896 else
897 err_mask &= ~PDC2_ERR_MASK;
898 port_status = readl(ata_mmio + PDC_GLOBAL_CTL);
899 if (unlikely(port_status & err_mask)) {
900 pdc_error_intr(ap, qc, port_status, err_mask);
901 return 1;
902 }
903
904 switch (qc->tf.protocol) {
905 case ATA_PROT_DMA:
906 case ATA_PROT_NODATA:
907 case ATAPI_PROT_DMA:
908 case ATAPI_PROT_NODATA:
909 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
910 ata_qc_complete(qc);
911 handled = 1;
912 break;
913 default:
914 ap->stats.idle_irq++;
915 break;
916 }
917
918 return handled;
919 }
920
921 static void pdc_irq_clear(struct ata_port *ap)
922 {
923 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
924
925 readl(ata_mmio + PDC_COMMAND);
926 }
927
928 static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
929 {
930 struct ata_host *host = dev_instance;
931 struct ata_port *ap;
932 u32 mask = 0;
933 unsigned int i, tmp;
934 unsigned int handled = 0;
935 void __iomem *host_mmio;
936 unsigned int hotplug_offset, ata_no;
937 u32 hotplug_status;
938 int is_sataii_tx4;
939
940 VPRINTK("ENTER\n");
941
942 if (!host || !host->iomap[PDC_MMIO_BAR]) {
943 VPRINTK("QUICK EXIT\n");
944 return IRQ_NONE;
945 }
946
947 host_mmio = host->iomap[PDC_MMIO_BAR];
948
949 spin_lock(&host->lock);
950
951 /* read and clear hotplug flags for all ports */
952 if (host->ports[0]->flags & PDC_FLAG_GEN_II) {
953 hotplug_offset = PDC2_SATA_PLUG_CSR;
954 hotplug_status = readl(host_mmio + hotplug_offset);
955 if (hotplug_status & 0xff)
956 writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
957 hotplug_status &= 0xff; /* clear uninteresting bits */
958 } else
959 hotplug_status = 0;
960
961 /* reading should also clear interrupts */
962 mask = readl(host_mmio + PDC_INT_SEQMASK);
963
964 if (mask == 0xffffffff && hotplug_status == 0) {
965 VPRINTK("QUICK EXIT 2\n");
966 goto done_irq;
967 }
968
969 mask &= 0xffff; /* only 16 SEQIDs possible */
970 if (mask == 0 && hotplug_status == 0) {
971 VPRINTK("QUICK EXIT 3\n");
972 goto done_irq;
973 }
974
975 writel(mask, host_mmio + PDC_INT_SEQMASK);
976
977 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
978
979 for (i = 0; i < host->n_ports; i++) {
980 VPRINTK("port %u\n", i);
981 ap = host->ports[i];
982
983 /* check for a plug or unplug event */
984 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
985 tmp = hotplug_status & (0x11 << ata_no);
986 if (tmp && ap &&
987 !(ap->flags & ATA_FLAG_DISABLED)) {
988 struct ata_eh_info *ehi = &ap->link.eh_info;
989 ata_ehi_clear_desc(ehi);
990 ata_ehi_hotplugged(ehi);
991 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
992 ata_port_freeze(ap);
993 ++handled;
994 continue;
995 }
996
997 /* check for a packet interrupt */
998 tmp = mask & (1 << (i + 1));
999 if (tmp && ap &&
1000 !(ap->flags & ATA_FLAG_DISABLED)) {
1001 struct ata_queued_cmd *qc;
1002
1003 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1004 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1005 handled += pdc_host_intr(ap, qc);
1006 }
1007 }
1008
1009 VPRINTK("EXIT\n");
1010
1011 done_irq:
1012 spin_unlock(&host->lock);
1013 return IRQ_RETVAL(handled);
1014 }
1015
1016 static void pdc_packet_start(struct ata_queued_cmd *qc)
1017 {
1018 struct ata_port *ap = qc->ap;
1019 struct pdc_port_priv *pp = ap->private_data;
1020 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
1021 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
1022 unsigned int port_no = ap->port_no;
1023 u8 seq = (u8) (port_no + 1);
1024
1025 VPRINTK("ENTER, ap %p\n", ap);
1026
1027 writel(0x00000001, host_mmio + (seq * 4));
1028 readl(host_mmio + (seq * 4)); /* flush */
1029
1030 pp->pkt[2] = seq;
1031 wmb(); /* flush PRD, pkt writes */
1032 writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
1033 readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */
1034 }
1035
1036 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
1037 {
1038 switch (qc->tf.protocol) {
1039 case ATAPI_PROT_NODATA:
1040 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1041 break;
1042 /*FALLTHROUGH*/
1043 case ATA_PROT_NODATA:
1044 if (qc->tf.flags & ATA_TFLAG_POLLING)
1045 break;
1046 /*FALLTHROUGH*/
1047 case ATAPI_PROT_DMA:
1048 case ATA_PROT_DMA:
1049 pdc_packet_start(qc);
1050 return 0;
1051 default:
1052 break;
1053 }
1054 return ata_sff_qc_issue(qc);
1055 }
1056
1057 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1058 {
1059 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1060 ata_sff_tf_load(ap, tf);
1061 }
1062
1063 static void pdc_exec_command_mmio(struct ata_port *ap,
1064 const struct ata_taskfile *tf)
1065 {
1066 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1067 ata_sff_exec_command(ap, tf);
1068 }
1069
1070 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
1071 {
1072 u8 *scsicmd = qc->scsicmd->cmnd;
1073 int pio = 1; /* atapi dma off by default */
1074
1075 /* Whitelist commands that may use DMA. */
1076 switch (scsicmd[0]) {
1077 case WRITE_12:
1078 case WRITE_10:
1079 case WRITE_6:
1080 case READ_12:
1081 case READ_10:
1082 case READ_6:
1083 case 0xad: /* READ_DVD_STRUCTURE */
1084 case 0xbe: /* READ_CD */
1085 pio = 0;
1086 }
1087 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
1088 if (scsicmd[0] == WRITE_10) {
1089 unsigned int lba =
1090 (scsicmd[2] << 24) |
1091 (scsicmd[3] << 16) |
1092 (scsicmd[4] << 8) |
1093 scsicmd[5];
1094 if (lba >= 0xFFFF4FA2)
1095 pio = 1;
1096 }
1097 return pio;
1098 }
1099
1100 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
1101 {
1102 /* First generation chips cannot use ATAPI DMA on SATA ports */
1103 return 1;
1104 }
1105
1106 static void pdc_ata_setup_port(struct ata_port *ap,
1107 void __iomem *base, void __iomem *scr_addr)
1108 {
1109 ap->ioaddr.cmd_addr = base;
1110 ap->ioaddr.data_addr = base;
1111 ap->ioaddr.feature_addr =
1112 ap->ioaddr.error_addr = base + 0x4;
1113 ap->ioaddr.nsect_addr = base + 0x8;
1114 ap->ioaddr.lbal_addr = base + 0xc;
1115 ap->ioaddr.lbam_addr = base + 0x10;
1116 ap->ioaddr.lbah_addr = base + 0x14;
1117 ap->ioaddr.device_addr = base + 0x18;
1118 ap->ioaddr.command_addr =
1119 ap->ioaddr.status_addr = base + 0x1c;
1120 ap->ioaddr.altstatus_addr =
1121 ap->ioaddr.ctl_addr = base + 0x38;
1122 ap->ioaddr.scr_addr = scr_addr;
1123 }
1124
1125 static void pdc_host_init(struct ata_host *host)
1126 {
1127 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
1128 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
1129 int hotplug_offset;
1130 u32 tmp;
1131
1132 if (is_gen2)
1133 hotplug_offset = PDC2_SATA_PLUG_CSR;
1134 else
1135 hotplug_offset = PDC_SATA_PLUG_CSR;
1136
1137 /*
1138 * Except for the hotplug stuff, this is voodoo from the
1139 * Promise driver. Label this entire section
1140 * "TODO: figure out why we do this"
1141 */
1142
1143 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1144 tmp = readl(host_mmio + PDC_FLASH_CTL);
1145 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
1146 if (!is_gen2)
1147 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1148 writel(tmp, host_mmio + PDC_FLASH_CTL);
1149
1150 /* clear plug/unplug flags for all ports */
1151 tmp = readl(host_mmio + hotplug_offset);
1152 writel(tmp | 0xff, host_mmio + hotplug_offset);
1153
1154 tmp = readl(host_mmio + hotplug_offset);
1155 if (is_gen2) /* unmask plug/unplug ints */
1156 writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
1157 else /* mask plug/unplug ints */
1158 writel(tmp | 0xff0000, host_mmio + hotplug_offset);
1159
1160 /* don't initialise TBG or SLEW on 2nd generation chips */
1161 if (is_gen2)
1162 return;
1163
1164 /* reduce TBG clock to 133 Mhz. */
1165 tmp = readl(host_mmio + PDC_TBG_MODE);
1166 tmp &= ~0x30000; /* clear bit 17, 16*/
1167 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
1168 writel(tmp, host_mmio + PDC_TBG_MODE);
1169
1170 readl(host_mmio + PDC_TBG_MODE); /* flush */
1171 msleep(10);
1172
1173 /* adjust slew rate control register. */
1174 tmp = readl(host_mmio + PDC_SLEW_CTL);
1175 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1176 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1177 writel(tmp, host_mmio + PDC_SLEW_CTL);
1178 }
1179
1180 static int pdc_ata_init_one(struct pci_dev *pdev,
1181 const struct pci_device_id *ent)
1182 {
1183 static int printed_version;
1184 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1185 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1186 struct ata_host *host;
1187 void __iomem *host_mmio;
1188 int n_ports, i, rc;
1189 int is_sataii_tx4;
1190
1191 if (!printed_version++)
1192 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1193
1194 /* enable and acquire resources */
1195 rc = pcim_enable_device(pdev);
1196 if (rc)
1197 return rc;
1198
1199 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1200 if (rc == -EBUSY)
1201 pcim_pin_device(pdev);
1202 if (rc)
1203 return rc;
1204 host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1205
1206 /* determine port configuration and setup host */
1207 n_ports = 2;
1208 if (pi->flags & PDC_FLAG_4_PORTS)
1209 n_ports = 4;
1210 for (i = 0; i < n_ports; i++)
1211 ppi[i] = pi;
1212
1213 if (pi->flags & PDC_FLAG_SATA_PATA) {
1214 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1);
1215 if (!(tmp & 0x80))
1216 ppi[n_ports++] = pi + 1;
1217 }
1218
1219 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1220 if (!host) {
1221 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
1222 return -ENOMEM;
1223 }
1224 host->iomap = pcim_iomap_table(pdev);
1225
1226 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1227 for (i = 0; i < host->n_ports; i++) {
1228 struct ata_port *ap = host->ports[i];
1229 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1230 unsigned int ata_offset = 0x200 + ata_no * 0x80;
1231 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1232
1233 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset);
1234
1235 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1236 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata");
1237 }
1238
1239 /* initialize adapter */
1240 pdc_host_init(host);
1241
1242 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1243 if (rc)
1244 return rc;
1245 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1246 if (rc)
1247 return rc;
1248
1249 /* start host, request IRQ and attach */
1250 pci_set_master(pdev);
1251 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1252 &pdc_ata_sht);
1253 }
1254
1255 static int __init pdc_ata_init(void)
1256 {
1257 return pci_register_driver(&pdc_ata_pci_driver);
1258 }
1259
1260 static void __exit pdc_ata_exit(void)
1261 {
1262 pci_unregister_driver(&pdc_ata_pci_driver);
1263 }
1264
1265 MODULE_AUTHOR("Jeff Garzik");
1266 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1267 MODULE_LICENSE("GPL");
1268 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1269 MODULE_VERSION(DRV_VERSION);
1270
1271 module_init(pdc_ata_init);
1272 module_exit(pdc_ata_exit);
Linux with added FPC-III support