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x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / char / synclink.c
blob4846b73ef28dc0e5db78ff11a4e3fd2b972b5a84
1 /*
2 * linux/drivers/char/synclink.c
3 *
4 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
5 *
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
15 *
16 * Original release 01/11/99
17 *
18 * This code is released under the GNU General Public License (GPL)
19 *
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
22 *
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
27 *
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
32 *
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
35 *
36 * 2000/02/16
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
42 *
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56 #if defined(__i386__)
57 # define BREAKPOINT() asm(" int $3");
58 #else
59 # define BREAKPOINT() { }
60 #endif
61
62 #define MAX_ISA_DEVICES 10
63 #define MAX_PCI_DEVICES 10
64 #define MAX_TOTAL_DEVICES 20
65
66 #include <linux/module.h>
67 #include <linux/errno.h>
68 #include <linux/signal.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/pci.h>
73 #include <linux/tty.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/major.h>
77 #include <linux/string.h>
78 #include <linux/fcntl.h>
79 #include <linux/ptrace.h>
80 #include <linux/ioport.h>
81 #include <linux/mm.h>
82 #include <linux/seq_file.h>
83 #include <linux/slab.h>
84 #include <linux/smp_lock.h>
85 #include <linux/delay.h>
86 #include <linux/netdevice.h>
87 #include <linux/vmalloc.h>
88 #include <linux/init.h>
89 #include <linux/ioctl.h>
90 #include <linux/synclink.h>
91
92 #include <asm/system.h>
93 #include <asm/io.h>
94 #include <asm/irq.h>
95 #include <asm/dma.h>
96 #include <linux/bitops.h>
97 #include <asm/types.h>
98 #include <linux/termios.h>
99 #include <linux/workqueue.h>
100 #include <linux/hdlc.h>
101 #include <linux/dma-mapping.h>
102
103 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
104 #define SYNCLINK_GENERIC_HDLC 1
105 #else
106 #define SYNCLINK_GENERIC_HDLC 0
107 #endif
108
109 #define GET_USER(error,value,addr) error = get_user(value,addr)
110 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
111 #define PUT_USER(error,value,addr) error = put_user(value,addr)
112 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
113
114 #include <asm/uaccess.h>
115
116 #define RCLRVALUE 0xffff
117
118 static MGSL_PARAMS default_params = {
119 MGSL_MODE_HDLC, /* unsigned long mode */
120 0, /* unsigned char loopback; */
121 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
122 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
123 0, /* unsigned long clock_speed; */
124 0xff, /* unsigned char addr_filter; */
125 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
126 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
127 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
128 9600, /* unsigned long data_rate; */
129 8, /* unsigned char data_bits; */
130 1, /* unsigned char stop_bits; */
131 ASYNC_PARITY_NONE /* unsigned char parity; */
132 };
133
134 #define SHARED_MEM_ADDRESS_SIZE 0x40000
135 #define BUFFERLISTSIZE 4096
136 #define DMABUFFERSIZE 4096
137 #define MAXRXFRAMES 7
138
139 typedef struct _DMABUFFERENTRY
140 {
141 u32 phys_addr; /* 32-bit flat physical address of data buffer */
142 volatile u16 count; /* buffer size/data count */
143 volatile u16 status; /* Control/status field */
144 volatile u16 rcc; /* character count field */
145 u16 reserved; /* padding required by 16C32 */
146 u32 link; /* 32-bit flat link to next buffer entry */
147 char *virt_addr; /* virtual address of data buffer */
148 u32 phys_entry; /* physical address of this buffer entry */
149 dma_addr_t dma_addr;
150 } DMABUFFERENTRY, *DMAPBUFFERENTRY;
151
152 /* The queue of BH actions to be performed */
153
154 #define BH_RECEIVE 1
155 #define BH_TRANSMIT 2
156 #define BH_STATUS 4
157
158 #define IO_PIN_SHUTDOWN_LIMIT 100
159
160 struct _input_signal_events {
161 int ri_up;
162 int ri_down;
163 int dsr_up;
164 int dsr_down;
165 int dcd_up;
166 int dcd_down;
167 int cts_up;
168 int cts_down;
169 };
170
171 /* transmit holding buffer definitions*/
172 #define MAX_TX_HOLDING_BUFFERS 5
173 struct tx_holding_buffer {
174 int buffer_size;
175 unsigned char * buffer;
176 };
177
178
179 /*
180 * Device instance data structure
181 */
182
183 struct mgsl_struct {
184 int magic;
185 struct tty_port port;
186 int line;
187 int hw_version;
188
189 struct mgsl_icount icount;
190
191 int timeout;
192 int x_char; /* xon/xoff character */
193 u16 read_status_mask;
194 u16 ignore_status_mask;
195 unsigned char *xmit_buf;
196 int xmit_head;
197 int xmit_tail;
198 int xmit_cnt;
199
200 wait_queue_head_t status_event_wait_q;
201 wait_queue_head_t event_wait_q;
202 struct timer_list tx_timer; /* HDLC transmit timeout timer */
203 struct mgsl_struct *next_device; /* device list link */
204
205 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
206 struct work_struct task; /* task structure for scheduling bh */
207
208 u32 EventMask; /* event trigger mask */
209 u32 RecordedEvents; /* pending events */
210
211 u32 max_frame_size; /* as set by device config */
212
213 u32 pending_bh;
214
215 bool bh_running; /* Protection from multiple */
216 int isr_overflow;
217 bool bh_requested;
218
219 int dcd_chkcount; /* check counts to prevent */
220 int cts_chkcount; /* too many IRQs if a signal */
221 int dsr_chkcount; /* is floating */
222 int ri_chkcount;
223
224 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
225 u32 buffer_list_phys;
226 dma_addr_t buffer_list_dma_addr;
227
228 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
229 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
230 unsigned int current_rx_buffer;
231
232 int num_tx_dma_buffers; /* number of tx dma frames required */
233 int tx_dma_buffers_used;
234 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
235 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
236 int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
237 int current_tx_buffer; /* next tx dma buffer to be loaded */
238
239 unsigned char *intermediate_rxbuffer;
240
241 int num_tx_holding_buffers; /* number of tx holding buffer allocated */
242 int get_tx_holding_index; /* next tx holding buffer for adapter to load */
243 int put_tx_holding_index; /* next tx holding buffer to store user request */
244 int tx_holding_count; /* number of tx holding buffers waiting */
245 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
246
247 bool rx_enabled;
248 bool rx_overflow;
249 bool rx_rcc_underrun;
250
251 bool tx_enabled;
252 bool tx_active;
253 u32 idle_mode;
254
255 u16 cmr_value;
256 u16 tcsr_value;
257
258 char device_name[25]; /* device instance name */
259
260 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
261 unsigned char bus; /* expansion bus number (zero based) */
262 unsigned char function; /* PCI device number */
263
264 unsigned int io_base; /* base I/O address of adapter */
265 unsigned int io_addr_size; /* size of the I/O address range */
266 bool io_addr_requested; /* true if I/O address requested */
267
268 unsigned int irq_level; /* interrupt level */
269 unsigned long irq_flags;
270 bool irq_requested; /* true if IRQ requested */
271
272 unsigned int dma_level; /* DMA channel */
273 bool dma_requested; /* true if dma channel requested */
274
275 u16 mbre_bit;
276 u16 loopback_bits;
277 u16 usc_idle_mode;
278
279 MGSL_PARAMS params; /* communications parameters */
280
281 unsigned char serial_signals; /* current serial signal states */
282
283 bool irq_occurred; /* for diagnostics use */
284 unsigned int init_error; /* Initialization startup error (DIAGS) */
285 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
286
287 u32 last_mem_alloc;
288 unsigned char* memory_base; /* shared memory address (PCI only) */
289 u32 phys_memory_base;
290 bool shared_mem_requested;
291
292 unsigned char* lcr_base; /* local config registers (PCI only) */
293 u32 phys_lcr_base;
294 u32 lcr_offset;
295 bool lcr_mem_requested;
296
297 u32 misc_ctrl_value;
298 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
299 char char_buf[MAX_ASYNC_BUFFER_SIZE];
300 bool drop_rts_on_tx_done;
301
302 bool loopmode_insert_requested;
303 bool loopmode_send_done_requested;
304
305 struct _input_signal_events input_signal_events;
306
307 /* generic HDLC device parts */
308 int netcount;
309 spinlock_t netlock;
310
311 #if SYNCLINK_GENERIC_HDLC
312 struct net_device *netdev;
313 #endif
314 };
315
316 #define MGSL_MAGIC 0x5401
317
318 /*
319 * The size of the serial xmit buffer is 1 page, or 4096 bytes
320 */
321 #ifndef SERIAL_XMIT_SIZE
322 #define SERIAL_XMIT_SIZE 4096
323 #endif
324
325 /*
326 * These macros define the offsets used in calculating the
327 * I/O address of the specified USC registers.
328 */
329
330
331 #define DCPIN 2 /* Bit 1 of I/O address */
332 #define SDPIN 4 /* Bit 2 of I/O address */
333
334 #define DCAR 0 /* DMA command/address register */
335 #define CCAR SDPIN /* channel command/address register */
336 #define DATAREG DCPIN + SDPIN /* serial data register */
337 #define MSBONLY 0x41
338 #define LSBONLY 0x40
339
340 /*
341 * These macros define the register address (ordinal number)
342 * used for writing address/value pairs to the USC.
343 */
344
345 #define CMR 0x02 /* Channel mode Register */
346 #define CCSR 0x04 /* Channel Command/status Register */
347 #define CCR 0x06 /* Channel Control Register */
348 #define PSR 0x08 /* Port status Register */
349 #define PCR 0x0a /* Port Control Register */
350 #define TMDR 0x0c /* Test mode Data Register */
351 #define TMCR 0x0e /* Test mode Control Register */
352 #define CMCR 0x10 /* Clock mode Control Register */
353 #define HCR 0x12 /* Hardware Configuration Register */
354 #define IVR 0x14 /* Interrupt Vector Register */
355 #define IOCR 0x16 /* Input/Output Control Register */
356 #define ICR 0x18 /* Interrupt Control Register */
357 #define DCCR 0x1a /* Daisy Chain Control Register */
358 #define MISR 0x1c /* Misc Interrupt status Register */
359 #define SICR 0x1e /* status Interrupt Control Register */
360 #define RDR 0x20 /* Receive Data Register */
361 #define RMR 0x22 /* Receive mode Register */
362 #define RCSR 0x24 /* Receive Command/status Register */
363 #define RICR 0x26 /* Receive Interrupt Control Register */
364 #define RSR 0x28 /* Receive Sync Register */
365 #define RCLR 0x2a /* Receive count Limit Register */
366 #define RCCR 0x2c /* Receive Character count Register */
367 #define TC0R 0x2e /* Time Constant 0 Register */
368 #define TDR 0x30 /* Transmit Data Register */
369 #define TMR 0x32 /* Transmit mode Register */
370 #define TCSR 0x34 /* Transmit Command/status Register */
371 #define TICR 0x36 /* Transmit Interrupt Control Register */
372 #define TSR 0x38 /* Transmit Sync Register */
373 #define TCLR 0x3a /* Transmit count Limit Register */
374 #define TCCR 0x3c /* Transmit Character count Register */
375 #define TC1R 0x3e /* Time Constant 1 Register */
376
377
378 /*
379 * MACRO DEFINITIONS FOR DMA REGISTERS
380 */
381
382 #define DCR 0x06 /* DMA Control Register (shared) */
383 #define DACR 0x08 /* DMA Array count Register (shared) */
384 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
385 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
386 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
387 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
388 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
389
390 #define TDMR 0x02 /* Transmit DMA mode Register */
391 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
392 #define TBCR 0x2a /* Transmit Byte count Register */
393 #define TARL 0x2c /* Transmit Address Register (low) */
394 #define TARU 0x2e /* Transmit Address Register (high) */
395 #define NTBCR 0x3a /* Next Transmit Byte count Register */
396 #define NTARL 0x3c /* Next Transmit Address Register (low) */
397 #define NTARU 0x3e /* Next Transmit Address Register (high) */
398
399 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
400 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
401 #define RBCR 0xaa /* Receive Byte count Register */
402 #define RARL 0xac /* Receive Address Register (low) */
403 #define RARU 0xae /* Receive Address Register (high) */
404 #define NRBCR 0xba /* Next Receive Byte count Register */
405 #define NRARL 0xbc /* Next Receive Address Register (low) */
406 #define NRARU 0xbe /* Next Receive Address Register (high) */
407
408
409 /*
410 * MACRO DEFINITIONS FOR MODEM STATUS BITS
411 */
412
413 #define MODEMSTATUS_DTR 0x80
414 #define MODEMSTATUS_DSR 0x40
415 #define MODEMSTATUS_RTS 0x20
416 #define MODEMSTATUS_CTS 0x10
417 #define MODEMSTATUS_RI 0x04
418 #define MODEMSTATUS_DCD 0x01
419
420
421 /*
422 * Channel Command/Address Register (CCAR) Command Codes
423 */
424
425 #define RTCmd_Null 0x0000
426 #define RTCmd_ResetHighestIus 0x1000
427 #define RTCmd_TriggerChannelLoadDma 0x2000
428 #define RTCmd_TriggerRxDma 0x2800
429 #define RTCmd_TriggerTxDma 0x3000
430 #define RTCmd_TriggerRxAndTxDma 0x3800
431 #define RTCmd_PurgeRxFifo 0x4800
432 #define RTCmd_PurgeTxFifo 0x5000
433 #define RTCmd_PurgeRxAndTxFifo 0x5800
434 #define RTCmd_LoadRcc 0x6800
435 #define RTCmd_LoadTcc 0x7000
436 #define RTCmd_LoadRccAndTcc 0x7800
437 #define RTCmd_LoadTC0 0x8800
438 #define RTCmd_LoadTC1 0x9000
439 #define RTCmd_LoadTC0AndTC1 0x9800
440 #define RTCmd_SerialDataLSBFirst 0xa000
441 #define RTCmd_SerialDataMSBFirst 0xa800
442 #define RTCmd_SelectBigEndian 0xb000
443 #define RTCmd_SelectLittleEndian 0xb800
444
445
446 /*
447 * DMA Command/Address Register (DCAR) Command Codes
448 */
449
450 #define DmaCmd_Null 0x0000
451 #define DmaCmd_ResetTxChannel 0x1000
452 #define DmaCmd_ResetRxChannel 0x1200
453 #define DmaCmd_StartTxChannel 0x2000
454 #define DmaCmd_StartRxChannel 0x2200
455 #define DmaCmd_ContinueTxChannel 0x3000
456 #define DmaCmd_ContinueRxChannel 0x3200
457 #define DmaCmd_PauseTxChannel 0x4000
458 #define DmaCmd_PauseRxChannel 0x4200
459 #define DmaCmd_AbortTxChannel 0x5000
460 #define DmaCmd_AbortRxChannel 0x5200
461 #define DmaCmd_InitTxChannel 0x7000
462 #define DmaCmd_InitRxChannel 0x7200
463 #define DmaCmd_ResetHighestDmaIus 0x8000
464 #define DmaCmd_ResetAllChannels 0x9000
465 #define DmaCmd_StartAllChannels 0xa000
466 #define DmaCmd_ContinueAllChannels 0xb000
467 #define DmaCmd_PauseAllChannels 0xc000
468 #define DmaCmd_AbortAllChannels 0xd000
469 #define DmaCmd_InitAllChannels 0xf000
470
471 #define TCmd_Null 0x0000
472 #define TCmd_ClearTxCRC 0x2000
473 #define TCmd_SelectTicrTtsaData 0x4000
474 #define TCmd_SelectTicrTxFifostatus 0x5000
475 #define TCmd_SelectTicrIntLevel 0x6000
476 #define TCmd_SelectTicrdma_level 0x7000
477 #define TCmd_SendFrame 0x8000
478 #define TCmd_SendAbort 0x9000
479 #define TCmd_EnableDleInsertion 0xc000
480 #define TCmd_DisableDleInsertion 0xd000
481 #define TCmd_ClearEofEom 0xe000
482 #define TCmd_SetEofEom 0xf000
483
484 #define RCmd_Null 0x0000
485 #define RCmd_ClearRxCRC 0x2000
486 #define RCmd_EnterHuntmode 0x3000
487 #define RCmd_SelectRicrRtsaData 0x4000
488 #define RCmd_SelectRicrRxFifostatus 0x5000
489 #define RCmd_SelectRicrIntLevel 0x6000
490 #define RCmd_SelectRicrdma_level 0x7000
491
492 /*
493 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
494 */
495
496 #define RECEIVE_STATUS BIT5
497 #define RECEIVE_DATA BIT4
498 #define TRANSMIT_STATUS BIT3
499 #define TRANSMIT_DATA BIT2
500 #define IO_PIN BIT1
501 #define MISC BIT0
502
503
504 /*
505 * Receive status Bits in Receive Command/status Register RCSR
506 */
507
508 #define RXSTATUS_SHORT_FRAME BIT8
509 #define RXSTATUS_CODE_VIOLATION BIT8
510 #define RXSTATUS_EXITED_HUNT BIT7
511 #define RXSTATUS_IDLE_RECEIVED BIT6
512 #define RXSTATUS_BREAK_RECEIVED BIT5
513 #define RXSTATUS_ABORT_RECEIVED BIT5
514 #define RXSTATUS_RXBOUND BIT4
515 #define RXSTATUS_CRC_ERROR BIT3
516 #define RXSTATUS_FRAMING_ERROR BIT3
517 #define RXSTATUS_ABORT BIT2
518 #define RXSTATUS_PARITY_ERROR BIT2
519 #define RXSTATUS_OVERRUN BIT1
520 #define RXSTATUS_DATA_AVAILABLE BIT0
521 #define RXSTATUS_ALL 0x01f6
522 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
523
524 /*
525 * Values for setting transmit idle mode in
526 * Transmit Control/status Register (TCSR)
527 */
528 #define IDLEMODE_FLAGS 0x0000
529 #define IDLEMODE_ALT_ONE_ZERO 0x0100
530 #define IDLEMODE_ZERO 0x0200
531 #define IDLEMODE_ONE 0x0300
532 #define IDLEMODE_ALT_MARK_SPACE 0x0500
533 #define IDLEMODE_SPACE 0x0600
534 #define IDLEMODE_MARK 0x0700
535 #define IDLEMODE_MASK 0x0700
536
537 /*
538 * IUSC revision identifiers
539 */
540 #define IUSC_SL1660 0x4d44
541 #define IUSC_PRE_SL1660 0x4553
542
543 /*
544 * Transmit status Bits in Transmit Command/status Register (TCSR)
545 */
546
547 #define TCSR_PRESERVE 0x0F00
548
549 #define TCSR_UNDERWAIT BIT11
550 #define TXSTATUS_PREAMBLE_SENT BIT7
551 #define TXSTATUS_IDLE_SENT BIT6
552 #define TXSTATUS_ABORT_SENT BIT5
553 #define TXSTATUS_EOF_SENT BIT4
554 #define TXSTATUS_EOM_SENT BIT4
555 #define TXSTATUS_CRC_SENT BIT3
556 #define TXSTATUS_ALL_SENT BIT2
557 #define TXSTATUS_UNDERRUN BIT1
558 #define TXSTATUS_FIFO_EMPTY BIT0
559 #define TXSTATUS_ALL 0x00fa
560 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
561
562
563 #define MISCSTATUS_RXC_LATCHED BIT15
564 #define MISCSTATUS_RXC BIT14
565 #define MISCSTATUS_TXC_LATCHED BIT13
566 #define MISCSTATUS_TXC BIT12
567 #define MISCSTATUS_RI_LATCHED BIT11
568 #define MISCSTATUS_RI BIT10
569 #define MISCSTATUS_DSR_LATCHED BIT9
570 #define MISCSTATUS_DSR BIT8
571 #define MISCSTATUS_DCD_LATCHED BIT7
572 #define MISCSTATUS_DCD BIT6
573 #define MISCSTATUS_CTS_LATCHED BIT5
574 #define MISCSTATUS_CTS BIT4
575 #define MISCSTATUS_RCC_UNDERRUN BIT3
576 #define MISCSTATUS_DPLL_NO_SYNC BIT2
577 #define MISCSTATUS_BRG1_ZERO BIT1
578 #define MISCSTATUS_BRG0_ZERO BIT0
579
580 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
581 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
582
583 #define SICR_RXC_ACTIVE BIT15
584 #define SICR_RXC_INACTIVE BIT14
585 #define SICR_RXC (BIT15+BIT14)
586 #define SICR_TXC_ACTIVE BIT13
587 #define SICR_TXC_INACTIVE BIT12
588 #define SICR_TXC (BIT13+BIT12)
589 #define SICR_RI_ACTIVE BIT11
590 #define SICR_RI_INACTIVE BIT10
591 #define SICR_RI (BIT11+BIT10)
592 #define SICR_DSR_ACTIVE BIT9
593 #define SICR_DSR_INACTIVE BIT8
594 #define SICR_DSR (BIT9+BIT8)
595 #define SICR_DCD_ACTIVE BIT7
596 #define SICR_DCD_INACTIVE BIT6
597 #define SICR_DCD (BIT7+BIT6)
598 #define SICR_CTS_ACTIVE BIT5
599 #define SICR_CTS_INACTIVE BIT4
600 #define SICR_CTS (BIT5+BIT4)
601 #define SICR_RCC_UNDERFLOW BIT3
602 #define SICR_DPLL_NO_SYNC BIT2
603 #define SICR_BRG1_ZERO BIT1
604 #define SICR_BRG0_ZERO BIT0
605
606 void usc_DisableMasterIrqBit( struct mgsl_struct *info );
607 void usc_EnableMasterIrqBit( struct mgsl_struct *info );
608 void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
609 void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
610 void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
611
612 #define usc_EnableInterrupts( a, b ) \
613 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
614
615 #define usc_DisableInterrupts( a, b ) \
616 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
617
618 #define usc_EnableMasterIrqBit(a) \
619 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
620
621 #define usc_DisableMasterIrqBit(a) \
622 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
623
624 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
625
626 /*
627 * Transmit status Bits in Transmit Control status Register (TCSR)
628 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
629 */
630
631 #define TXSTATUS_PREAMBLE_SENT BIT7
632 #define TXSTATUS_IDLE_SENT BIT6
633 #define TXSTATUS_ABORT_SENT BIT5
634 #define TXSTATUS_EOF BIT4
635 #define TXSTATUS_CRC_SENT BIT3
636 #define TXSTATUS_ALL_SENT BIT2
637 #define TXSTATUS_UNDERRUN BIT1
638 #define TXSTATUS_FIFO_EMPTY BIT0
639
640 #define DICR_MASTER BIT15
641 #define DICR_TRANSMIT BIT0
642 #define DICR_RECEIVE BIT1
643
644 #define usc_EnableDmaInterrupts(a,b) \
645 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
646
647 #define usc_DisableDmaInterrupts(a,b) \
648 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
649
650 #define usc_EnableStatusIrqs(a,b) \
651 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
652
653 #define usc_DisablestatusIrqs(a,b) \
654 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
655
656 /* Transmit status Bits in Transmit Control status Register (TCSR) */
657 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
658
659
660 #define DISABLE_UNCONDITIONAL 0
661 #define DISABLE_END_OF_FRAME 1
662 #define ENABLE_UNCONDITIONAL 2
663 #define ENABLE_AUTO_CTS 3
664 #define ENABLE_AUTO_DCD 3
665 #define usc_EnableTransmitter(a,b) \
666 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
667 #define usc_EnableReceiver(a,b) \
668 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
669
670 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
671 static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
672 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
673
674 static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
675 static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
676 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
677 void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
678 void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
679
680 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
681 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
682
683 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
684
685 static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
686 static void usc_start_receiver( struct mgsl_struct *info );
687 static void usc_stop_receiver( struct mgsl_struct *info );
688
689 static void usc_start_transmitter( struct mgsl_struct *info );
690 static void usc_stop_transmitter( struct mgsl_struct *info );
691 static void usc_set_txidle( struct mgsl_struct *info );
692 static void usc_load_txfifo( struct mgsl_struct *info );
693
694 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
695 static void usc_enable_loopback( struct mgsl_struct *info, int enable );
696
697 static void usc_get_serial_signals( struct mgsl_struct *info );
698 static void usc_set_serial_signals( struct mgsl_struct *info );
699
700 static void usc_reset( struct mgsl_struct *info );
701
702 static void usc_set_sync_mode( struct mgsl_struct *info );
703 static void usc_set_sdlc_mode( struct mgsl_struct *info );
704 static void usc_set_async_mode( struct mgsl_struct *info );
705 static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
706
707 static void usc_loopback_frame( struct mgsl_struct *info );
708
709 static void mgsl_tx_timeout(unsigned long context);
710
711
712 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
713 static void usc_loopmode_insert_request( struct mgsl_struct * info );
714 static int usc_loopmode_active( struct mgsl_struct * info);
715 static void usc_loopmode_send_done( struct mgsl_struct * info );
716
717 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
718
719 #if SYNCLINK_GENERIC_HDLC
720 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
721 static void hdlcdev_tx_done(struct mgsl_struct *info);
722 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
723 static int hdlcdev_init(struct mgsl_struct *info);
724 static void hdlcdev_exit(struct mgsl_struct *info);
725 #endif
726
727 /*
728 * Defines a BUS descriptor value for the PCI adapter
729 * local bus address ranges.
730 */
731
732 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
733 (0x00400020 + \
734 ((WrHold) << 30) + \
735 ((WrDly) << 28) + \
736 ((RdDly) << 26) + \
737 ((Nwdd) << 20) + \
738 ((Nwad) << 15) + \
739 ((Nxda) << 13) + \
740 ((Nrdd) << 11) + \
741 ((Nrad) << 6) )
742
743 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
744
745 /*
746 * Adapter diagnostic routines
747 */
748 static bool mgsl_register_test( struct mgsl_struct *info );
749 static bool mgsl_irq_test( struct mgsl_struct *info );
750 static bool mgsl_dma_test( struct mgsl_struct *info );
751 static bool mgsl_memory_test( struct mgsl_struct *info );
752 static int mgsl_adapter_test( struct mgsl_struct *info );
753
754 /*
755 * device and resource management routines
756 */
757 static int mgsl_claim_resources(struct mgsl_struct *info);
758 static void mgsl_release_resources(struct mgsl_struct *info);
759 static void mgsl_add_device(struct mgsl_struct *info);
760 static struct mgsl_struct* mgsl_allocate_device(void);
761
762 /*
763 * DMA buffer manupulation functions.
764 */
765 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
766 static bool mgsl_get_rx_frame( struct mgsl_struct *info );
767 static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
768 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
769 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
770 static int num_free_tx_dma_buffers(struct mgsl_struct *info);
771 static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
772 static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
773
774 /*
775 * DMA and Shared Memory buffer allocation and formatting
776 */
777 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
778 static void mgsl_free_dma_buffers(struct mgsl_struct *info);
779 static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
780 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
781 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
782 static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
783 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
784 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
785 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
786 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
787 static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
788 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
789
790 /*
791 * Bottom half interrupt handlers
792 */
793 static void mgsl_bh_handler(struct work_struct *work);
794 static void mgsl_bh_receive(struct mgsl_struct *info);
795 static void mgsl_bh_transmit(struct mgsl_struct *info);
796 static void mgsl_bh_status(struct mgsl_struct *info);
797
798 /*
799 * Interrupt handler routines and dispatch table.
800 */
801 static void mgsl_isr_null( struct mgsl_struct *info );
802 static void mgsl_isr_transmit_data( struct mgsl_struct *info );
803 static void mgsl_isr_receive_data( struct mgsl_struct *info );
804 static void mgsl_isr_receive_status( struct mgsl_struct *info );
805 static void mgsl_isr_transmit_status( struct mgsl_struct *info );
806 static void mgsl_isr_io_pin( struct mgsl_struct *info );
807 static void mgsl_isr_misc( struct mgsl_struct *info );
808 static void mgsl_isr_receive_dma( struct mgsl_struct *info );
809 static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
810
811 typedef void (*isr_dispatch_func)(struct mgsl_struct *);
812
813 static isr_dispatch_func UscIsrTable[7] =
814 {
815 mgsl_isr_null,
816 mgsl_isr_misc,
817 mgsl_isr_io_pin,
818 mgsl_isr_transmit_data,
819 mgsl_isr_transmit_status,
820 mgsl_isr_receive_data,
821 mgsl_isr_receive_status
822 };
823
824 /*
825 * ioctl call handlers
826 */
827 static int tiocmget(struct tty_struct *tty, struct file *file);
828 static int tiocmset(struct tty_struct *tty, struct file *file,
829 unsigned int set, unsigned int clear);
830 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
831 __user *user_icount);
832 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
833 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
834 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
835 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
836 static int mgsl_txenable(struct mgsl_struct * info, int enable);
837 static int mgsl_txabort(struct mgsl_struct * info);
838 static int mgsl_rxenable(struct mgsl_struct * info, int enable);
839 static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
840 static int mgsl_loopmode_send_done( struct mgsl_struct * info );
841
842 /* set non-zero on successful registration with PCI subsystem */
843 static bool pci_registered;
844
845 /*
846 * Global linked list of SyncLink devices
847 */
848 static struct mgsl_struct *mgsl_device_list;
849 static int mgsl_device_count;
850
851 /*
852 * Set this param to non-zero to load eax with the
853 * .text section address and breakpoint on module load.
854 * This is useful for use with gdb and add-symbol-file command.
855 */
856 static int break_on_load;
857
858 /*
859 * Driver major number, defaults to zero to get auto
860 * assigned major number. May be forced as module parameter.
861 */
862 static int ttymajor;
863
864 /*
865 * Array of user specified options for ISA adapters.
866 */
867 static int io[MAX_ISA_DEVICES];
868 static int irq[MAX_ISA_DEVICES];
869 static int dma[MAX_ISA_DEVICES];
870 static int debug_level;
871 static int maxframe[MAX_TOTAL_DEVICES];
872 static int txdmabufs[MAX_TOTAL_DEVICES];
873 static int txholdbufs[MAX_TOTAL_DEVICES];
874
875 module_param(break_on_load, bool, 0);
876 module_param(ttymajor, int, 0);
877 module_param_array(io, int, NULL, 0);
878 module_param_array(irq, int, NULL, 0);
879 module_param_array(dma, int, NULL, 0);
880 module_param(debug_level, int, 0);
881 module_param_array(maxframe, int, NULL, 0);
882 module_param_array(txdmabufs, int, NULL, 0);
883 module_param_array(txholdbufs, int, NULL, 0);
884
885 static char *driver_name = "SyncLink serial driver";
886 static char *driver_version = "$Revision: 4.38 $";
887
888 static int synclink_init_one (struct pci_dev *dev,
889 const struct pci_device_id *ent);
890 static void synclink_remove_one (struct pci_dev *dev);
891
892 static struct pci_device_id synclink_pci_tbl[] = {
893 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
894 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
895 { 0, }, /* terminate list */
896 };
897 MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
898
899 MODULE_LICENSE("GPL");
900
901 static struct pci_driver synclink_pci_driver = {
902 .name = "synclink",
903 .id_table = synclink_pci_tbl,
904 .probe = synclink_init_one,
905 .remove = __devexit_p(synclink_remove_one),
906 };
907
908 static struct tty_driver *serial_driver;
909
910 /* number of characters left in xmit buffer before we ask for more */
911 #define WAKEUP_CHARS 256
912
913
914 static void mgsl_change_params(struct mgsl_struct *info);
915 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
916
917 /*
918 * 1st function defined in .text section. Calling this function in
919 * init_module() followed by a breakpoint allows a remote debugger
920 * (gdb) to get the .text address for the add-symbol-file command.
921 * This allows remote debugging of dynamically loadable modules.
922 */
923 static void* mgsl_get_text_ptr(void)
924 {
925 return mgsl_get_text_ptr;
926 }
927
928 static inline int mgsl_paranoia_check(struct mgsl_struct *info,
929 char *name, const char *routine)
930 {
931 #ifdef MGSL_PARANOIA_CHECK
932 static const char *badmagic =
933 "Warning: bad magic number for mgsl struct (%s) in %s\n";
934 static const char *badinfo =
935 "Warning: null mgsl_struct for (%s) in %s\n";
936
937 if (!info) {
938 printk(badinfo, name, routine);
939 return 1;
940 }
941 if (info->magic != MGSL_MAGIC) {
942 printk(badmagic, name, routine);
943 return 1;
944 }
945 #else
946 if (!info)
947 return 1;
948 #endif
949 return 0;
950 }
951
952 /**
953 * line discipline callback wrappers
954 *
955 * The wrappers maintain line discipline references
956 * while calling into the line discipline.
957 *
958 * ldisc_receive_buf - pass receive data to line discipline
959 */
960
961 static void ldisc_receive_buf(struct tty_struct *tty,
962 const __u8 *data, char *flags, int count)
963 {
964 struct tty_ldisc *ld;
965 if (!tty)
966 return;
967 ld = tty_ldisc_ref(tty);
968 if (ld) {
969 if (ld->ops->receive_buf)
970 ld->ops->receive_buf(tty, data, flags, count);
971 tty_ldisc_deref(ld);
972 }
973 }
974
975 /* mgsl_stop() throttle (stop) transmitter
976 *
977 * Arguments: tty pointer to tty info structure
978 * Return Value: None
979 */
980 static void mgsl_stop(struct tty_struct *tty)
981 {
982 struct mgsl_struct *info = tty->driver_data;
983 unsigned long flags;
984
985 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
986 return;
987
988 if ( debug_level >= DEBUG_LEVEL_INFO )
989 printk("mgsl_stop(%s)\n",info->device_name);
990
991 spin_lock_irqsave(&info->irq_spinlock,flags);
992 if (info->tx_enabled)
993 usc_stop_transmitter(info);
994 spin_unlock_irqrestore(&info->irq_spinlock,flags);
995
996 } /* end of mgsl_stop() */
997
998 /* mgsl_start() release (start) transmitter
999 *
1000 * Arguments: tty pointer to tty info structure
1001 * Return Value: None
1002 */
1003 static void mgsl_start(struct tty_struct *tty)
1004 {
1005 struct mgsl_struct *info = tty->driver_data;
1006 unsigned long flags;
1007
1008 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1009 return;
1010
1011 if ( debug_level >= DEBUG_LEVEL_INFO )
1012 printk("mgsl_start(%s)\n",info->device_name);
1013
1014 spin_lock_irqsave(&info->irq_spinlock,flags);
1015 if (!info->tx_enabled)
1016 usc_start_transmitter(info);
1017 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1018
1019 } /* end of mgsl_start() */
1020
1021 /*
1022 * Bottom half work queue access functions
1023 */
1024
1025 /* mgsl_bh_action() Return next bottom half action to perform.
1026 * Return Value: BH action code or 0 if nothing to do.
1027 */
1028 static int mgsl_bh_action(struct mgsl_struct *info)
1029 {
1030 unsigned long flags;
1031 int rc = 0;
1032
1033 spin_lock_irqsave(&info->irq_spinlock,flags);
1034
1035 if (info->pending_bh & BH_RECEIVE) {
1036 info->pending_bh &= ~BH_RECEIVE;
1037 rc = BH_RECEIVE;
1038 } else if (info->pending_bh & BH_TRANSMIT) {
1039 info->pending_bh &= ~BH_TRANSMIT;
1040 rc = BH_TRANSMIT;
1041 } else if (info->pending_bh & BH_STATUS) {
1042 info->pending_bh &= ~BH_STATUS;
1043 rc = BH_STATUS;
1044 }
1045
1046 if (!rc) {
1047 /* Mark BH routine as complete */
1048 info->bh_running = false;
1049 info->bh_requested = false;
1050 }
1051
1052 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1053
1054 return rc;
1055 }
1056
1057 /*
1058 * Perform bottom half processing of work items queued by ISR.
1059 */
1060 static void mgsl_bh_handler(struct work_struct *work)
1061 {
1062 struct mgsl_struct *info =
1063 container_of(work, struct mgsl_struct, task);
1064 int action;
1065
1066 if (!info)
1067 return;
1068
1069 if ( debug_level >= DEBUG_LEVEL_BH )
1070 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1071 __FILE__,__LINE__,info->device_name);
1072
1073 info->bh_running = true;
1074
1075 while((action = mgsl_bh_action(info)) != 0) {
1076
1077 /* Process work item */
1078 if ( debug_level >= DEBUG_LEVEL_BH )
1079 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1080 __FILE__,__LINE__,action);
1081
1082 switch (action) {
1083
1084 case BH_RECEIVE:
1085 mgsl_bh_receive(info);
1086 break;
1087 case BH_TRANSMIT:
1088 mgsl_bh_transmit(info);
1089 break;
1090 case BH_STATUS:
1091 mgsl_bh_status(info);
1092 break;
1093 default:
1094 /* unknown work item ID */
1095 printk("Unknown work item ID=%08X!\n", action);
1096 break;
1097 }
1098 }
1099
1100 if ( debug_level >= DEBUG_LEVEL_BH )
1101 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1102 __FILE__,__LINE__,info->device_name);
1103 }
1104
1105 static void mgsl_bh_receive(struct mgsl_struct *info)
1106 {
1107 bool (*get_rx_frame)(struct mgsl_struct *info) =
1108 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1109
1110 if ( debug_level >= DEBUG_LEVEL_BH )
1111 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1112 __FILE__,__LINE__,info->device_name);
1113
1114 do
1115 {
1116 if (info->rx_rcc_underrun) {
1117 unsigned long flags;
1118 spin_lock_irqsave(&info->irq_spinlock,flags);
1119 usc_start_receiver(info);
1120 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1121 return;
1122 }
1123 } while(get_rx_frame(info));
1124 }
1125
1126 static void mgsl_bh_transmit(struct mgsl_struct *info)
1127 {
1128 struct tty_struct *tty = info->port.tty;
1129 unsigned long flags;
1130
1131 if ( debug_level >= DEBUG_LEVEL_BH )
1132 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1133 __FILE__,__LINE__,info->device_name);
1134
1135 if (tty)
1136 tty_wakeup(tty);
1137
1138 /* if transmitter idle and loopmode_send_done_requested
1139 * then start echoing RxD to TxD
1140 */
1141 spin_lock_irqsave(&info->irq_spinlock,flags);
1142 if ( !info->tx_active && info->loopmode_send_done_requested )
1143 usc_loopmode_send_done( info );
1144 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1145 }
1146
1147 static void mgsl_bh_status(struct mgsl_struct *info)
1148 {
1149 if ( debug_level >= DEBUG_LEVEL_BH )
1150 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1151 __FILE__,__LINE__,info->device_name);
1152
1153 info->ri_chkcount = 0;
1154 info->dsr_chkcount = 0;
1155 info->dcd_chkcount = 0;
1156 info->cts_chkcount = 0;
1157 }
1158
1159 /* mgsl_isr_receive_status()
1160 *
1161 * Service a receive status interrupt. The type of status
1162 * interrupt is indicated by the state of the RCSR.
1163 * This is only used for HDLC mode.
1164 *
1165 * Arguments: info pointer to device instance data
1166 * Return Value: None
1167 */
1168 static void mgsl_isr_receive_status( struct mgsl_struct *info )
1169 {
1170 u16 status = usc_InReg( info, RCSR );
1171
1172 if ( debug_level >= DEBUG_LEVEL_ISR )
1173 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1174 __FILE__,__LINE__,status);
1175
1176 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1177 info->loopmode_insert_requested &&
1178 usc_loopmode_active(info) )
1179 {
1180 ++info->icount.rxabort;
1181 info->loopmode_insert_requested = false;
1182
1183 /* clear CMR:13 to start echoing RxD to TxD */
1184 info->cmr_value &= ~BIT13;
1185 usc_OutReg(info, CMR, info->cmr_value);
1186
1187 /* disable received abort irq (no longer required) */
1188 usc_OutReg(info, RICR,
1189 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1190 }
1191
1192 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1193 if (status & RXSTATUS_EXITED_HUNT)
1194 info->icount.exithunt++;
1195 if (status & RXSTATUS_IDLE_RECEIVED)
1196 info->icount.rxidle++;
1197 wake_up_interruptible(&info->event_wait_q);
1198 }
1199
1200 if (status & RXSTATUS_OVERRUN){
1201 info->icount.rxover++;
1202 usc_process_rxoverrun_sync( info );
1203 }
1204
1205 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1206 usc_UnlatchRxstatusBits( info, status );
1207
1208 } /* end of mgsl_isr_receive_status() */
1209
1210 /* mgsl_isr_transmit_status()
1211 *
1212 * Service a transmit status interrupt
1213 * HDLC mode :end of transmit frame
1214 * Async mode:all data is sent
1215 * transmit status is indicated by bits in the TCSR.
1216 *
1217 * Arguments: info pointer to device instance data
1218 * Return Value: None
1219 */
1220 static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1221 {
1222 u16 status = usc_InReg( info, TCSR );
1223
1224 if ( debug_level >= DEBUG_LEVEL_ISR )
1225 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1226 __FILE__,__LINE__,status);
1227
1228 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1229 usc_UnlatchTxstatusBits( info, status );
1230
1231 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1232 {
1233 /* finished sending HDLC abort. This may leave */
1234 /* the TxFifo with data from the aborted frame */
1235 /* so purge the TxFifo. Also shutdown the DMA */
1236 /* channel in case there is data remaining in */
1237 /* the DMA buffer */
1238 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1239 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1240 }
1241
1242 if ( status & TXSTATUS_EOF_SENT )
1243 info->icount.txok++;
1244 else if ( status & TXSTATUS_UNDERRUN )
1245 info->icount.txunder++;
1246 else if ( status & TXSTATUS_ABORT_SENT )
1247 info->icount.txabort++;
1248 else
1249 info->icount.txunder++;
1250
1251 info->tx_active = false;
1252 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1253 del_timer(&info->tx_timer);
1254
1255 if ( info->drop_rts_on_tx_done ) {
1256 usc_get_serial_signals( info );
1257 if ( info->serial_signals & SerialSignal_RTS ) {
1258 info->serial_signals &= ~SerialSignal_RTS;
1259 usc_set_serial_signals( info );
1260 }
1261 info->drop_rts_on_tx_done = false;
1262 }
1263
1264 #if SYNCLINK_GENERIC_HDLC
1265 if (info->netcount)
1266 hdlcdev_tx_done(info);
1267 else
1268 #endif
1269 {
1270 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1271 usc_stop_transmitter(info);
1272 return;
1273 }
1274 info->pending_bh |= BH_TRANSMIT;
1275 }
1276
1277 } /* end of mgsl_isr_transmit_status() */
1278
1279 /* mgsl_isr_io_pin()
1280 *
1281 * Service an Input/Output pin interrupt. The type of
1282 * interrupt is indicated by bits in the MISR
1283 *
1284 * Arguments: info pointer to device instance data
1285 * Return Value: None
1286 */
1287 static void mgsl_isr_io_pin( struct mgsl_struct *info )
1288 {
1289 struct mgsl_icount *icount;
1290 u16 status = usc_InReg( info, MISR );
1291
1292 if ( debug_level >= DEBUG_LEVEL_ISR )
1293 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1294 __FILE__,__LINE__,status);
1295
1296 usc_ClearIrqPendingBits( info, IO_PIN );
1297 usc_UnlatchIostatusBits( info, status );
1298
1299 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1300 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1301 icount = &info->icount;
1302 /* update input line counters */
1303 if (status & MISCSTATUS_RI_LATCHED) {
1304 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1305 usc_DisablestatusIrqs(info,SICR_RI);
1306 icount->rng++;
1307 if ( status & MISCSTATUS_RI )
1308 info->input_signal_events.ri_up++;
1309 else
1310 info->input_signal_events.ri_down++;
1311 }
1312 if (status & MISCSTATUS_DSR_LATCHED) {
1313 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1314 usc_DisablestatusIrqs(info,SICR_DSR);
1315 icount->dsr++;
1316 if ( status & MISCSTATUS_DSR )
1317 info->input_signal_events.dsr_up++;
1318 else
1319 info->input_signal_events.dsr_down++;
1320 }
1321 if (status & MISCSTATUS_DCD_LATCHED) {
1322 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1323 usc_DisablestatusIrqs(info,SICR_DCD);
1324 icount->dcd++;
1325 if (status & MISCSTATUS_DCD) {
1326 info->input_signal_events.dcd_up++;
1327 } else
1328 info->input_signal_events.dcd_down++;
1329 #if SYNCLINK_GENERIC_HDLC
1330 if (info->netcount) {
1331 if (status & MISCSTATUS_DCD)
1332 netif_carrier_on(info->netdev);
1333 else
1334 netif_carrier_off(info->netdev);
1335 }
1336 #endif
1337 }
1338 if (status & MISCSTATUS_CTS_LATCHED)
1339 {
1340 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1341 usc_DisablestatusIrqs(info,SICR_CTS);
1342 icount->cts++;
1343 if ( status & MISCSTATUS_CTS )
1344 info->input_signal_events.cts_up++;
1345 else
1346 info->input_signal_events.cts_down++;
1347 }
1348 wake_up_interruptible(&info->status_event_wait_q);
1349 wake_up_interruptible(&info->event_wait_q);
1350
1351 if ( (info->port.flags & ASYNC_CHECK_CD) &&
1352 (status & MISCSTATUS_DCD_LATCHED) ) {
1353 if ( debug_level >= DEBUG_LEVEL_ISR )
1354 printk("%s CD now %s...", info->device_name,
1355 (status & MISCSTATUS_DCD) ? "on" : "off");
1356 if (status & MISCSTATUS_DCD)
1357 wake_up_interruptible(&info->port.open_wait);
1358 else {
1359 if ( debug_level >= DEBUG_LEVEL_ISR )
1360 printk("doing serial hangup...");
1361 if (info->port.tty)
1362 tty_hangup(info->port.tty);
1363 }
1364 }
1365
1366 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
1367 (status & MISCSTATUS_CTS_LATCHED) ) {
1368 if (info->port.tty->hw_stopped) {
1369 if (status & MISCSTATUS_CTS) {
1370 if ( debug_level >= DEBUG_LEVEL_ISR )
1371 printk("CTS tx start...");
1372 if (info->port.tty)
1373 info->port.tty->hw_stopped = 0;
1374 usc_start_transmitter(info);
1375 info->pending_bh |= BH_TRANSMIT;
1376 return;
1377 }
1378 } else {
1379 if (!(status & MISCSTATUS_CTS)) {
1380 if ( debug_level >= DEBUG_LEVEL_ISR )
1381 printk("CTS tx stop...");
1382 if (info->port.tty)
1383 info->port.tty->hw_stopped = 1;
1384 usc_stop_transmitter(info);
1385 }
1386 }
1387 }
1388 }
1389
1390 info->pending_bh |= BH_STATUS;
1391
1392 /* for diagnostics set IRQ flag */
1393 if ( status & MISCSTATUS_TXC_LATCHED ){
1394 usc_OutReg( info, SICR,
1395 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1396 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1397 info->irq_occurred = true;
1398 }
1399
1400 } /* end of mgsl_isr_io_pin() */
1401
1402 /* mgsl_isr_transmit_data()
1403 *
1404 * Service a transmit data interrupt (async mode only).
1405 *
1406 * Arguments: info pointer to device instance data
1407 * Return Value: None
1408 */
1409 static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1410 {
1411 if ( debug_level >= DEBUG_LEVEL_ISR )
1412 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1413 __FILE__,__LINE__,info->xmit_cnt);
1414
1415 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1416
1417 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1418 usc_stop_transmitter(info);
1419 return;
1420 }
1421
1422 if ( info->xmit_cnt )
1423 usc_load_txfifo( info );
1424 else
1425 info->tx_active = false;
1426
1427 if (info->xmit_cnt < WAKEUP_CHARS)
1428 info->pending_bh |= BH_TRANSMIT;
1429
1430 } /* end of mgsl_isr_transmit_data() */
1431
1432 /* mgsl_isr_receive_data()
1433 *
1434 * Service a receive data interrupt. This occurs
1435 * when operating in asynchronous interrupt transfer mode.
1436 * The receive data FIFO is flushed to the receive data buffers.
1437 *
1438 * Arguments: info pointer to device instance data
1439 * Return Value: None
1440 */
1441 static void mgsl_isr_receive_data( struct mgsl_struct *info )
1442 {
1443 int Fifocount;
1444 u16 status;
1445 int work = 0;
1446 unsigned char DataByte;
1447 struct tty_struct *tty = info->port.tty;
1448 struct mgsl_icount *icount = &info->icount;
1449
1450 if ( debug_level >= DEBUG_LEVEL_ISR )
1451 printk("%s(%d):mgsl_isr_receive_data\n",
1452 __FILE__,__LINE__);
1453
1454 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1455
1456 /* select FIFO status for RICR readback */
1457 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1458
1459 /* clear the Wordstatus bit so that status readback */
1460 /* only reflects the status of this byte */
1461 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1462
1463 /* flush the receive FIFO */
1464
1465 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1466 int flag;
1467
1468 /* read one byte from RxFIFO */
1469 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1470 info->io_base + CCAR );
1471 DataByte = inb( info->io_base + CCAR );
1472
1473 /* get the status of the received byte */
1474 status = usc_InReg(info, RCSR);
1475 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1476 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1477 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1478
1479 icount->rx++;
1480
1481 flag = 0;
1482 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1483 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1484 printk("rxerr=%04X\n",status);
1485 /* update error statistics */
1486 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1487 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1488 icount->brk++;
1489 } else if (status & RXSTATUS_PARITY_ERROR)
1490 icount->parity++;
1491 else if (status & RXSTATUS_FRAMING_ERROR)
1492 icount->frame++;
1493 else if (status & RXSTATUS_OVERRUN) {
1494 /* must issue purge fifo cmd before */
1495 /* 16C32 accepts more receive chars */
1496 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1497 icount->overrun++;
1498 }
1499
1500 /* discard char if tty control flags say so */
1501 if (status & info->ignore_status_mask)
1502 continue;
1503
1504 status &= info->read_status_mask;
1505
1506 if (status & RXSTATUS_BREAK_RECEIVED) {
1507 flag = TTY_BREAK;
1508 if (info->port.flags & ASYNC_SAK)
1509 do_SAK(tty);
1510 } else if (status & RXSTATUS_PARITY_ERROR)
1511 flag = TTY_PARITY;
1512 else if (status & RXSTATUS_FRAMING_ERROR)
1513 flag = TTY_FRAME;
1514 } /* end of if (error) */
1515 tty_insert_flip_char(tty, DataByte, flag);
1516 if (status & RXSTATUS_OVERRUN) {
1517 /* Overrun is special, since it's
1518 * reported immediately, and doesn't
1519 * affect the current character
1520 */
1521 work += tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1522 }
1523 }
1524
1525 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1526 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1527 __FILE__,__LINE__,icount->rx,icount->brk,
1528 icount->parity,icount->frame,icount->overrun);
1529 }
1530
1531 if(work)
1532 tty_flip_buffer_push(tty);
1533 }
1534
1535 /* mgsl_isr_misc()
1536 *
1537 * Service a miscellaneous interrupt source.
1538 *
1539 * Arguments: info pointer to device extension (instance data)
1540 * Return Value: None
1541 */
1542 static void mgsl_isr_misc( struct mgsl_struct *info )
1543 {
1544 u16 status = usc_InReg( info, MISR );
1545
1546 if ( debug_level >= DEBUG_LEVEL_ISR )
1547 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1548 __FILE__,__LINE__,status);
1549
1550 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1551 (info->params.mode == MGSL_MODE_HDLC)) {
1552
1553 /* turn off receiver and rx DMA */
1554 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1555 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1556 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1557 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1558 usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1559
1560 /* schedule BH handler to restart receiver */
1561 info->pending_bh |= BH_RECEIVE;
1562 info->rx_rcc_underrun = true;
1563 }
1564
1565 usc_ClearIrqPendingBits( info, MISC );
1566 usc_UnlatchMiscstatusBits( info, status );
1567
1568 } /* end of mgsl_isr_misc() */
1569
1570 /* mgsl_isr_null()
1571 *
1572 * Services undefined interrupt vectors from the
1573 * USC. (hence this function SHOULD never be called)
1574 *
1575 * Arguments: info pointer to device extension (instance data)
1576 * Return Value: None
1577 */
1578 static void mgsl_isr_null( struct mgsl_struct *info )
1579 {
1580
1581 } /* end of mgsl_isr_null() */
1582
1583 /* mgsl_isr_receive_dma()
1584 *
1585 * Service a receive DMA channel interrupt.
1586 * For this driver there are two sources of receive DMA interrupts
1587 * as identified in the Receive DMA mode Register (RDMR):
1588 *
1589 * BIT3 EOA/EOL End of List, all receive buffers in receive
1590 * buffer list have been filled (no more free buffers
1591 * available). The DMA controller has shut down.
1592 *
1593 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1594 * DMA buffer is terminated in response to completion
1595 * of a good frame or a frame with errors. The status
1596 * of the frame is stored in the buffer entry in the
1597 * list of receive buffer entries.
1598 *
1599 * Arguments: info pointer to device instance data
1600 * Return Value: None
1601 */
1602 static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1603 {
1604 u16 status;
1605
1606 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1607 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1608
1609 /* Read the receive DMA status to identify interrupt type. */
1610 /* This also clears the status bits. */
1611 status = usc_InDmaReg( info, RDMR );
1612
1613 if ( debug_level >= DEBUG_LEVEL_ISR )
1614 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1615 __FILE__,__LINE__,info->device_name,status);
1616
1617 info->pending_bh |= BH_RECEIVE;
1618
1619 if ( status & BIT3 ) {
1620 info->rx_overflow = true;
1621 info->icount.buf_overrun++;
1622 }
1623
1624 } /* end of mgsl_isr_receive_dma() */
1625
1626 /* mgsl_isr_transmit_dma()
1627 *
1628 * This function services a transmit DMA channel interrupt.
1629 *
1630 * For this driver there is one source of transmit DMA interrupts
1631 * as identified in the Transmit DMA Mode Register (TDMR):
1632 *
1633 * BIT2 EOB End of Buffer. This interrupt occurs when a
1634 * transmit DMA buffer has been emptied.
1635 *
1636 * The driver maintains enough transmit DMA buffers to hold at least
1637 * one max frame size transmit frame. When operating in a buffered
1638 * transmit mode, there may be enough transmit DMA buffers to hold at
1639 * least two or more max frame size frames. On an EOB condition,
1640 * determine if there are any queued transmit buffers and copy into
1641 * transmit DMA buffers if we have room.
1642 *
1643 * Arguments: info pointer to device instance data
1644 * Return Value: None
1645 */
1646 static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1647 {
1648 u16 status;
1649
1650 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1651 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1652
1653 /* Read the transmit DMA status to identify interrupt type. */
1654 /* This also clears the status bits. */
1655
1656 status = usc_InDmaReg( info, TDMR );
1657
1658 if ( debug_level >= DEBUG_LEVEL_ISR )
1659 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1660 __FILE__,__LINE__,info->device_name,status);
1661
1662 if ( status & BIT2 ) {
1663 --info->tx_dma_buffers_used;
1664
1665 /* if there are transmit frames queued,
1666 * try to load the next one
1667 */
1668 if ( load_next_tx_holding_buffer(info) ) {
1669 /* if call returns non-zero value, we have
1670 * at least one free tx holding buffer
1671 */
1672 info->pending_bh |= BH_TRANSMIT;
1673 }
1674 }
1675
1676 } /* end of mgsl_isr_transmit_dma() */
1677
1678 /* mgsl_interrupt()
1679 *
1680 * Interrupt service routine entry point.
1681 *
1682 * Arguments:
1683 *
1684 * irq interrupt number that caused interrupt
1685 * dev_id device ID supplied during interrupt registration
1686 *
1687 * Return Value: None
1688 */
1689 static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1690 {
1691 struct mgsl_struct *info = dev_id;
1692 u16 UscVector;
1693 u16 DmaVector;
1694
1695 if ( debug_level >= DEBUG_LEVEL_ISR )
1696 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1697 __FILE__, __LINE__, info->irq_level);
1698
1699 spin_lock(&info->irq_spinlock);
1700
1701 for(;;) {
1702 /* Read the interrupt vectors from hardware. */
1703 UscVector = usc_InReg(info, IVR) >> 9;
1704 DmaVector = usc_InDmaReg(info, DIVR);
1705
1706 if ( debug_level >= DEBUG_LEVEL_ISR )
1707 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1708 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1709
1710 if ( !UscVector && !DmaVector )
1711 break;
1712
1713 /* Dispatch interrupt vector */
1714 if ( UscVector )
1715 (*UscIsrTable[UscVector])(info);
1716 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1717 mgsl_isr_transmit_dma(info);
1718 else
1719 mgsl_isr_receive_dma(info);
1720
1721 if ( info->isr_overflow ) {
1722 printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1723 __FILE__, __LINE__, info->device_name, info->irq_level);
1724 usc_DisableMasterIrqBit(info);
1725 usc_DisableDmaInterrupts(info,DICR_MASTER);
1726 break;
1727 }
1728 }
1729
1730 /* Request bottom half processing if there's something
1731 * for it to do and the bh is not already running
1732 */
1733
1734 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1735 if ( debug_level >= DEBUG_LEVEL_ISR )
1736 printk("%s(%d):%s queueing bh task.\n",
1737 __FILE__,__LINE__,info->device_name);
1738 schedule_work(&info->task);
1739 info->bh_requested = true;
1740 }
1741
1742 spin_unlock(&info->irq_spinlock);
1743
1744 if ( debug_level >= DEBUG_LEVEL_ISR )
1745 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1746 __FILE__, __LINE__, info->irq_level);
1747
1748 return IRQ_HANDLED;
1749 } /* end of mgsl_interrupt() */
1750
1751 /* startup()
1752 *
1753 * Initialize and start device.
1754 *
1755 * Arguments: info pointer to device instance data
1756 * Return Value: 0 if success, otherwise error code
1757 */
1758 static int startup(struct mgsl_struct * info)
1759 {
1760 int retval = 0;
1761
1762 if ( debug_level >= DEBUG_LEVEL_INFO )
1763 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1764
1765 if (info->port.flags & ASYNC_INITIALIZED)
1766 return 0;
1767
1768 if (!info->xmit_buf) {
1769 /* allocate a page of memory for a transmit buffer */
1770 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1771 if (!info->xmit_buf) {
1772 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1773 __FILE__,__LINE__,info->device_name);
1774 return -ENOMEM;
1775 }
1776 }
1777
1778 info->pending_bh = 0;
1779
1780 memset(&info->icount, 0, sizeof(info->icount));
1781
1782 setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1783
1784 /* Allocate and claim adapter resources */
1785 retval = mgsl_claim_resources(info);
1786
1787 /* perform existence check and diagnostics */
1788 if ( !retval )
1789 retval = mgsl_adapter_test(info);
1790
1791 if ( retval ) {
1792 if (capable(CAP_SYS_ADMIN) && info->port.tty)
1793 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1794 mgsl_release_resources(info);
1795 return retval;
1796 }
1797
1798 /* program hardware for current parameters */
1799 mgsl_change_params(info);
1800
1801 if (info->port.tty)
1802 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1803
1804 info->port.flags |= ASYNC_INITIALIZED;
1805
1806 return 0;
1807
1808 } /* end of startup() */
1809
1810 /* shutdown()
1811 *
1812 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1813 *
1814 * Arguments: info pointer to device instance data
1815 * Return Value: None
1816 */
1817 static void shutdown(struct mgsl_struct * info)
1818 {
1819 unsigned long flags;
1820
1821 if (!(info->port.flags & ASYNC_INITIALIZED))
1822 return;
1823
1824 if (debug_level >= DEBUG_LEVEL_INFO)
1825 printk("%s(%d):mgsl_shutdown(%s)\n",
1826 __FILE__,__LINE__, info->device_name );
1827
1828 /* clear status wait queue because status changes */
1829 /* can't happen after shutting down the hardware */
1830 wake_up_interruptible(&info->status_event_wait_q);
1831 wake_up_interruptible(&info->event_wait_q);
1832
1833 del_timer_sync(&info->tx_timer);
1834
1835 if (info->xmit_buf) {
1836 free_page((unsigned long) info->xmit_buf);
1837 info->xmit_buf = NULL;
1838 }
1839
1840 spin_lock_irqsave(&info->irq_spinlock,flags);
1841 usc_DisableMasterIrqBit(info);
1842 usc_stop_receiver(info);
1843 usc_stop_transmitter(info);
1844 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1845 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1846 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1847
1848 /* Disable DMAEN (Port 7, Bit 14) */
1849 /* This disconnects the DMA request signal from the ISA bus */
1850 /* on the ISA adapter. This has no effect for the PCI adapter */
1851 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1852
1853 /* Disable INTEN (Port 6, Bit12) */
1854 /* This disconnects the IRQ request signal to the ISA bus */
1855 /* on the ISA adapter. This has no effect for the PCI adapter */
1856 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1857
1858 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
1859 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1860 usc_set_serial_signals(info);
1861 }
1862
1863 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1864
1865 mgsl_release_resources(info);
1866
1867 if (info->port.tty)
1868 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1869
1870 info->port.flags &= ~ASYNC_INITIALIZED;
1871
1872 } /* end of shutdown() */
1873
1874 static void mgsl_program_hw(struct mgsl_struct *info)
1875 {
1876 unsigned long flags;
1877
1878 spin_lock_irqsave(&info->irq_spinlock,flags);
1879
1880 usc_stop_receiver(info);
1881 usc_stop_transmitter(info);
1882 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1883
1884 if (info->params.mode == MGSL_MODE_HDLC ||
1885 info->params.mode == MGSL_MODE_RAW ||
1886 info->netcount)
1887 usc_set_sync_mode(info);
1888 else
1889 usc_set_async_mode(info);
1890
1891 usc_set_serial_signals(info);
1892
1893 info->dcd_chkcount = 0;
1894 info->cts_chkcount = 0;
1895 info->ri_chkcount = 0;
1896 info->dsr_chkcount = 0;
1897
1898 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1899 usc_EnableInterrupts(info, IO_PIN);
1900 usc_get_serial_signals(info);
1901
1902 if (info->netcount || info->port.tty->termios->c_cflag & CREAD)
1903 usc_start_receiver(info);
1904
1905 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1906 }
1907
1908 /* Reconfigure adapter based on new parameters
1909 */
1910 static void mgsl_change_params(struct mgsl_struct *info)
1911 {
1912 unsigned cflag;
1913 int bits_per_char;
1914
1915 if (!info->port.tty || !info->port.tty->termios)
1916 return;
1917
1918 if (debug_level >= DEBUG_LEVEL_INFO)
1919 printk("%s(%d):mgsl_change_params(%s)\n",
1920 __FILE__,__LINE__, info->device_name );
1921
1922 cflag = info->port.tty->termios->c_cflag;
1923
1924 /* if B0 rate (hangup) specified then negate DTR and RTS */
1925 /* otherwise assert DTR and RTS */
1926 if (cflag & CBAUD)
1927 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1928 else
1929 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1930
1931 /* byte size and parity */
1932
1933 switch (cflag & CSIZE) {
1934 case CS5: info->params.data_bits = 5; break;
1935 case CS6: info->params.data_bits = 6; break;
1936 case CS7: info->params.data_bits = 7; break;
1937 case CS8: info->params.data_bits = 8; break;
1938 /* Never happens, but GCC is too dumb to figure it out */
1939 default: info->params.data_bits = 7; break;
1940 }
1941
1942 if (cflag & CSTOPB)
1943 info->params.stop_bits = 2;
1944 else
1945 info->params.stop_bits = 1;
1946
1947 info->params.parity = ASYNC_PARITY_NONE;
1948 if (cflag & PARENB) {
1949 if (cflag & PARODD)
1950 info->params.parity = ASYNC_PARITY_ODD;
1951 else
1952 info->params.parity = ASYNC_PARITY_EVEN;
1953 #ifdef CMSPAR
1954 if (cflag & CMSPAR)
1955 info->params.parity = ASYNC_PARITY_SPACE;
1956 #endif
1957 }
1958
1959 /* calculate number of jiffies to transmit a full
1960 * FIFO (32 bytes) at specified data rate
1961 */
1962 bits_per_char = info->params.data_bits +
1963 info->params.stop_bits + 1;
1964
1965 /* if port data rate is set to 460800 or less then
1966 * allow tty settings to override, otherwise keep the
1967 * current data rate.
1968 */
1969 if (info->params.data_rate <= 460800)
1970 info->params.data_rate = tty_get_baud_rate(info->port.tty);
1971
1972 if ( info->params.data_rate ) {
1973 info->timeout = (32*HZ*bits_per_char) /
1974 info->params.data_rate;
1975 }
1976 info->timeout += HZ/50; /* Add .02 seconds of slop */
1977
1978 if (cflag & CRTSCTS)
1979 info->port.flags |= ASYNC_CTS_FLOW;
1980 else
1981 info->port.flags &= ~ASYNC_CTS_FLOW;
1982
1983 if (cflag & CLOCAL)
1984 info->port.flags &= ~ASYNC_CHECK_CD;
1985 else
1986 info->port.flags |= ASYNC_CHECK_CD;
1987
1988 /* process tty input control flags */
1989
1990 info->read_status_mask = RXSTATUS_OVERRUN;
1991 if (I_INPCK(info->port.tty))
1992 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1993 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1994 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1995
1996 if (I_IGNPAR(info->port.tty))
1997 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1998 if (I_IGNBRK(info->port.tty)) {
1999 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
2000 /* If ignoring parity and break indicators, ignore
2001 * overruns too. (For real raw support).
2002 */
2003 if (I_IGNPAR(info->port.tty))
2004 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2005 }
2006
2007 mgsl_program_hw(info);
2008
2009 } /* end of mgsl_change_params() */
2010
2011 /* mgsl_put_char()
2012 *
2013 * Add a character to the transmit buffer.
2014 *
2015 * Arguments: tty pointer to tty information structure
2016 * ch character to add to transmit buffer
2017 *
2018 * Return Value: None
2019 */
2020 static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2021 {
2022 struct mgsl_struct *info = tty->driver_data;
2023 unsigned long flags;
2024 int ret = 0;
2025
2026 if (debug_level >= DEBUG_LEVEL_INFO) {
2027 printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
2028 __FILE__, __LINE__, ch, info->device_name);
2029 }
2030
2031 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2032 return 0;
2033
2034 if (!tty || !info->xmit_buf)
2035 return 0;
2036
2037 spin_lock_irqsave(&info->irq_spinlock, flags);
2038
2039 if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
2040 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2041 info->xmit_buf[info->xmit_head++] = ch;
2042 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2043 info->xmit_cnt++;
2044 ret = 1;
2045 }
2046 }
2047 spin_unlock_irqrestore(&info->irq_spinlock, flags);
2048 return ret;
2049
2050 } /* end of mgsl_put_char() */
2051
2052 /* mgsl_flush_chars()
2053 *
2054 * Enable transmitter so remaining characters in the
2055 * transmit buffer are sent.
2056 *
2057 * Arguments: tty pointer to tty information structure
2058 * Return Value: None
2059 */
2060 static void mgsl_flush_chars(struct tty_struct *tty)
2061 {
2062 struct mgsl_struct *info = tty->driver_data;
2063 unsigned long flags;
2064
2065 if ( debug_level >= DEBUG_LEVEL_INFO )
2066 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2067 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2068
2069 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2070 return;
2071
2072 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2073 !info->xmit_buf)
2074 return;
2075
2076 if ( debug_level >= DEBUG_LEVEL_INFO )
2077 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2078 __FILE__,__LINE__,info->device_name );
2079
2080 spin_lock_irqsave(&info->irq_spinlock,flags);
2081
2082 if (!info->tx_active) {
2083 if ( (info->params.mode == MGSL_MODE_HDLC ||
2084 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2085 /* operating in synchronous (frame oriented) mode */
2086 /* copy data from circular xmit_buf to */
2087 /* transmit DMA buffer. */
2088 mgsl_load_tx_dma_buffer(info,
2089 info->xmit_buf,info->xmit_cnt);
2090 }
2091 usc_start_transmitter(info);
2092 }
2093
2094 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2095
2096 } /* end of mgsl_flush_chars() */
2097
2098 /* mgsl_write()
2099 *
2100 * Send a block of data
2101 *
2102 * Arguments:
2103 *
2104 * tty pointer to tty information structure
2105 * buf pointer to buffer containing send data
2106 * count size of send data in bytes
2107 *
2108 * Return Value: number of characters written
2109 */
2110 static int mgsl_write(struct tty_struct * tty,
2111 const unsigned char *buf, int count)
2112 {
2113 int c, ret = 0;
2114 struct mgsl_struct *info = tty->driver_data;
2115 unsigned long flags;
2116
2117 if ( debug_level >= DEBUG_LEVEL_INFO )
2118 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2119 __FILE__,__LINE__,info->device_name,count);
2120
2121 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2122 goto cleanup;
2123
2124 if (!tty || !info->xmit_buf)
2125 goto cleanup;
2126
2127 if ( info->params.mode == MGSL_MODE_HDLC ||
2128 info->params.mode == MGSL_MODE_RAW ) {
2129 /* operating in synchronous (frame oriented) mode */
2130 /* operating in synchronous (frame oriented) mode */
2131 if (info->tx_active) {
2132
2133 if ( info->params.mode == MGSL_MODE_HDLC ) {
2134 ret = 0;
2135 goto cleanup;
2136 }
2137 /* transmitter is actively sending data -
2138 * if we have multiple transmit dma and
2139 * holding buffers, attempt to queue this
2140 * frame for transmission at a later time.
2141 */
2142 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2143 /* no tx holding buffers available */
2144 ret = 0;
2145 goto cleanup;
2146 }
2147
2148 /* queue transmit frame request */
2149 ret = count;
2150 save_tx_buffer_request(info,buf,count);
2151
2152 /* if we have sufficient tx dma buffers,
2153 * load the next buffered tx request
2154 */
2155 spin_lock_irqsave(&info->irq_spinlock,flags);
2156 load_next_tx_holding_buffer(info);
2157 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2158 goto cleanup;
2159 }
2160
2161 /* if operating in HDLC LoopMode and the adapter */
2162 /* has yet to be inserted into the loop, we can't */
2163 /* transmit */
2164
2165 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2166 !usc_loopmode_active(info) )
2167 {
2168 ret = 0;
2169 goto cleanup;
2170 }
2171
2172 if ( info->xmit_cnt ) {
2173 /* Send accumulated from send_char() calls */
2174 /* as frame and wait before accepting more data. */
2175 ret = 0;
2176
2177 /* copy data from circular xmit_buf to */
2178 /* transmit DMA buffer. */
2179 mgsl_load_tx_dma_buffer(info,
2180 info->xmit_buf,info->xmit_cnt);
2181 if ( debug_level >= DEBUG_LEVEL_INFO )
2182 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2183 __FILE__,__LINE__,info->device_name);
2184 } else {
2185 if ( debug_level >= DEBUG_LEVEL_INFO )
2186 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2187 __FILE__,__LINE__,info->device_name);
2188 ret = count;
2189 info->xmit_cnt = count;
2190 mgsl_load_tx_dma_buffer(info,buf,count);
2191 }
2192 } else {
2193 while (1) {
2194 spin_lock_irqsave(&info->irq_spinlock,flags);
2195 c = min_t(int, count,
2196 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2197 SERIAL_XMIT_SIZE - info->xmit_head));
2198 if (c <= 0) {
2199 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2200 break;
2201 }
2202 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2203 info->xmit_head = ((info->xmit_head + c) &
2204 (SERIAL_XMIT_SIZE-1));
2205 info->xmit_cnt += c;
2206 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2207 buf += c;
2208 count -= c;
2209 ret += c;
2210 }
2211 }
2212
2213 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2214 spin_lock_irqsave(&info->irq_spinlock,flags);
2215 if (!info->tx_active)
2216 usc_start_transmitter(info);
2217 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2218 }
2219 cleanup:
2220 if ( debug_level >= DEBUG_LEVEL_INFO )
2221 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2222 __FILE__,__LINE__,info->device_name,ret);
2223
2224 return ret;
2225
2226 } /* end of mgsl_write() */
2227
2228 /* mgsl_write_room()
2229 *
2230 * Return the count of free bytes in transmit buffer
2231 *
2232 * Arguments: tty pointer to tty info structure
2233 * Return Value: None
2234 */
2235 static int mgsl_write_room(struct tty_struct *tty)
2236 {
2237 struct mgsl_struct *info = tty->driver_data;
2238 int ret;
2239
2240 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2241 return 0;
2242 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2243 if (ret < 0)
2244 ret = 0;
2245
2246 if (debug_level >= DEBUG_LEVEL_INFO)
2247 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2248 __FILE__,__LINE__, info->device_name,ret );
2249
2250 if ( info->params.mode == MGSL_MODE_HDLC ||
2251 info->params.mode == MGSL_MODE_RAW ) {
2252 /* operating in synchronous (frame oriented) mode */
2253 if ( info->tx_active )
2254 return 0;
2255 else
2256 return HDLC_MAX_FRAME_SIZE;
2257 }
2258
2259 return ret;
2260
2261 } /* end of mgsl_write_room() */
2262
2263 /* mgsl_chars_in_buffer()
2264 *
2265 * Return the count of bytes in transmit buffer
2266 *
2267 * Arguments: tty pointer to tty info structure
2268 * Return Value: None
2269 */
2270 static int mgsl_chars_in_buffer(struct tty_struct *tty)
2271 {
2272 struct mgsl_struct *info = tty->driver_data;
2273
2274 if (debug_level >= DEBUG_LEVEL_INFO)
2275 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2276 __FILE__,__LINE__, info->device_name );
2277
2278 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2279 return 0;
2280
2281 if (debug_level >= DEBUG_LEVEL_INFO)
2282 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2283 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2284
2285 if ( info->params.mode == MGSL_MODE_HDLC ||
2286 info->params.mode == MGSL_MODE_RAW ) {
2287 /* operating in synchronous (frame oriented) mode */
2288 if ( info->tx_active )
2289 return info->max_frame_size;
2290 else
2291 return 0;
2292 }
2293
2294 return info->xmit_cnt;
2295 } /* end of mgsl_chars_in_buffer() */
2296
2297 /* mgsl_flush_buffer()
2298 *
2299 * Discard all data in the send buffer
2300 *
2301 * Arguments: tty pointer to tty info structure
2302 * Return Value: None
2303 */
2304 static void mgsl_flush_buffer(struct tty_struct *tty)
2305 {
2306 struct mgsl_struct *info = tty->driver_data;
2307 unsigned long flags;
2308
2309 if (debug_level >= DEBUG_LEVEL_INFO)
2310 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2311 __FILE__,__LINE__, info->device_name );
2312
2313 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2314 return;
2315
2316 spin_lock_irqsave(&info->irq_spinlock,flags);
2317 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2318 del_timer(&info->tx_timer);
2319 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2320
2321 tty_wakeup(tty);
2322 }
2323
2324 /* mgsl_send_xchar()
2325 *
2326 * Send a high-priority XON/XOFF character
2327 *
2328 * Arguments: tty pointer to tty info structure
2329 * ch character to send
2330 * Return Value: None
2331 */
2332 static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2333 {
2334 struct mgsl_struct *info = tty->driver_data;
2335 unsigned long flags;
2336
2337 if (debug_level >= DEBUG_LEVEL_INFO)
2338 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2339 __FILE__,__LINE__, info->device_name, ch );
2340
2341 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2342 return;
2343
2344 info->x_char = ch;
2345 if (ch) {
2346 /* Make sure transmit interrupts are on */
2347 spin_lock_irqsave(&info->irq_spinlock,flags);
2348 if (!info->tx_enabled)
2349 usc_start_transmitter(info);
2350 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2351 }
2352 } /* end of mgsl_send_xchar() */
2353
2354 /* mgsl_throttle()
2355 *
2356 * Signal remote device to throttle send data (our receive data)
2357 *
2358 * Arguments: tty pointer to tty info structure
2359 * Return Value: None
2360 */
2361 static void mgsl_throttle(struct tty_struct * tty)
2362 {
2363 struct mgsl_struct *info = tty->driver_data;
2364 unsigned long flags;
2365
2366 if (debug_level >= DEBUG_LEVEL_INFO)
2367 printk("%s(%d):mgsl_throttle(%s) entry\n",
2368 __FILE__,__LINE__, info->device_name );
2369
2370 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2371 return;
2372
2373 if (I_IXOFF(tty))
2374 mgsl_send_xchar(tty, STOP_CHAR(tty));
2375
2376 if (tty->termios->c_cflag & CRTSCTS) {
2377 spin_lock_irqsave(&info->irq_spinlock,flags);
2378 info->serial_signals &= ~SerialSignal_RTS;
2379 usc_set_serial_signals(info);
2380 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2381 }
2382 } /* end of mgsl_throttle() */
2383
2384 /* mgsl_unthrottle()
2385 *
2386 * Signal remote device to stop throttling send data (our receive data)
2387 *
2388 * Arguments: tty pointer to tty info structure
2389 * Return Value: None
2390 */
2391 static void mgsl_unthrottle(struct tty_struct * tty)
2392 {
2393 struct mgsl_struct *info = tty->driver_data;
2394 unsigned long flags;
2395
2396 if (debug_level >= DEBUG_LEVEL_INFO)
2397 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2398 __FILE__,__LINE__, info->device_name );
2399
2400 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2401 return;
2402
2403 if (I_IXOFF(tty)) {
2404 if (info->x_char)
2405 info->x_char = 0;
2406 else
2407 mgsl_send_xchar(tty, START_CHAR(tty));
2408 }
2409
2410 if (tty->termios->c_cflag & CRTSCTS) {
2411 spin_lock_irqsave(&info->irq_spinlock,flags);
2412 info->serial_signals |= SerialSignal_RTS;
2413 usc_set_serial_signals(info);
2414 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2415 }
2416
2417 } /* end of mgsl_unthrottle() */
2418
2419 /* mgsl_get_stats()
2420 *
2421 * get the current serial parameters information
2422 *
2423 * Arguments: info pointer to device instance data
2424 * user_icount pointer to buffer to hold returned stats
2425 *
2426 * Return Value: 0 if success, otherwise error code
2427 */
2428 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2429 {
2430 int err;
2431
2432 if (debug_level >= DEBUG_LEVEL_INFO)
2433 printk("%s(%d):mgsl_get_params(%s)\n",
2434 __FILE__,__LINE__, info->device_name);
2435
2436 if (!user_icount) {
2437 memset(&info->icount, 0, sizeof(info->icount));
2438 } else {
2439 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2440 if (err)
2441 return -EFAULT;
2442 }
2443
2444 return 0;
2445
2446 } /* end of mgsl_get_stats() */
2447
2448 /* mgsl_get_params()
2449 *
2450 * get the current serial parameters information
2451 *
2452 * Arguments: info pointer to device instance data
2453 * user_params pointer to buffer to hold returned params
2454 *
2455 * Return Value: 0 if success, otherwise error code
2456 */
2457 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2458 {
2459 int err;
2460 if (debug_level >= DEBUG_LEVEL_INFO)
2461 printk("%s(%d):mgsl_get_params(%s)\n",
2462 __FILE__,__LINE__, info->device_name);
2463
2464 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2465 if (err) {
2466 if ( debug_level >= DEBUG_LEVEL_INFO )
2467 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2468 __FILE__,__LINE__,info->device_name);
2469 return -EFAULT;
2470 }
2471
2472 return 0;
2473
2474 } /* end of mgsl_get_params() */
2475
2476 /* mgsl_set_params()
2477 *
2478 * set the serial parameters
2479 *
2480 * Arguments:
2481 *
2482 * info pointer to device instance data
2483 * new_params user buffer containing new serial params
2484 *
2485 * Return Value: 0 if success, otherwise error code
2486 */
2487 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2488 {
2489 unsigned long flags;
2490 MGSL_PARAMS tmp_params;
2491 int err;
2492
2493 if (debug_level >= DEBUG_LEVEL_INFO)
2494 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2495 info->device_name );
2496 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2497 if (err) {
2498 if ( debug_level >= DEBUG_LEVEL_INFO )
2499 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2500 __FILE__,__LINE__,info->device_name);
2501 return -EFAULT;
2502 }
2503
2504 spin_lock_irqsave(&info->irq_spinlock,flags);
2505 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2506 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2507
2508 mgsl_change_params(info);
2509
2510 return 0;
2511
2512 } /* end of mgsl_set_params() */
2513
2514 /* mgsl_get_txidle()
2515 *
2516 * get the current transmit idle mode
2517 *
2518 * Arguments: info pointer to device instance data
2519 * idle_mode pointer to buffer to hold returned idle mode
2520 *
2521 * Return Value: 0 if success, otherwise error code
2522 */
2523 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2524 {
2525 int err;
2526
2527 if (debug_level >= DEBUG_LEVEL_INFO)
2528 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2529 __FILE__,__LINE__, info->device_name, info->idle_mode);
2530
2531 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2532 if (err) {
2533 if ( debug_level >= DEBUG_LEVEL_INFO )
2534 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2535 __FILE__,__LINE__,info->device_name);
2536 return -EFAULT;
2537 }
2538
2539 return 0;
2540
2541 } /* end of mgsl_get_txidle() */
2542
2543 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2544 *
2545 * Arguments: info pointer to device instance data
2546 * idle_mode new idle mode
2547 *
2548 * Return Value: 0 if success, otherwise error code
2549 */
2550 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2551 {
2552 unsigned long flags;
2553
2554 if (debug_level >= DEBUG_LEVEL_INFO)
2555 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2556 info->device_name, idle_mode );
2557
2558 spin_lock_irqsave(&info->irq_spinlock,flags);
2559 info->idle_mode = idle_mode;
2560 usc_set_txidle( info );
2561 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2562 return 0;
2563
2564 } /* end of mgsl_set_txidle() */
2565
2566 /* mgsl_txenable()
2567 *
2568 * enable or disable the transmitter
2569 *
2570 * Arguments:
2571 *
2572 * info pointer to device instance data
2573 * enable 1 = enable, 0 = disable
2574 *
2575 * Return Value: 0 if success, otherwise error code
2576 */
2577 static int mgsl_txenable(struct mgsl_struct * info, int enable)
2578 {
2579 unsigned long flags;
2580
2581 if (debug_level >= DEBUG_LEVEL_INFO)
2582 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2583 info->device_name, enable);
2584
2585 spin_lock_irqsave(&info->irq_spinlock,flags);
2586 if ( enable ) {
2587 if ( !info->tx_enabled ) {
2588
2589 usc_start_transmitter(info);
2590 /*--------------------------------------------------
2591 * if HDLC/SDLC Loop mode, attempt to insert the
2592 * station in the 'loop' by setting CMR:13. Upon
2593 * receipt of the next GoAhead (RxAbort) sequence,
2594 * the OnLoop indicator (CCSR:7) should go active
2595 * to indicate that we are on the loop
2596 *--------------------------------------------------*/
2597 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2598 usc_loopmode_insert_request( info );
2599 }
2600 } else {
2601 if ( info->tx_enabled )
2602 usc_stop_transmitter(info);
2603 }
2604 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2605 return 0;
2606
2607 } /* end of mgsl_txenable() */
2608
2609 /* mgsl_txabort() abort send HDLC frame
2610 *
2611 * Arguments: info pointer to device instance data
2612 * Return Value: 0 if success, otherwise error code
2613 */
2614 static int mgsl_txabort(struct mgsl_struct * info)
2615 {
2616 unsigned long flags;
2617
2618 if (debug_level >= DEBUG_LEVEL_INFO)
2619 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2620 info->device_name);
2621
2622 spin_lock_irqsave(&info->irq_spinlock,flags);
2623 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2624 {
2625 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2626 usc_loopmode_cancel_transmit( info );
2627 else
2628 usc_TCmd(info,TCmd_SendAbort);
2629 }
2630 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2631 return 0;
2632
2633 } /* end of mgsl_txabort() */
2634
2635 /* mgsl_rxenable() enable or disable the receiver
2636 *
2637 * Arguments: info pointer to device instance data
2638 * enable 1 = enable, 0 = disable
2639 * Return Value: 0 if success, otherwise error code
2640 */
2641 static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2642 {
2643 unsigned long flags;
2644
2645 if (debug_level >= DEBUG_LEVEL_INFO)
2646 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2647 info->device_name, enable);
2648
2649 spin_lock_irqsave(&info->irq_spinlock,flags);
2650 if ( enable ) {
2651 if ( !info->rx_enabled )
2652 usc_start_receiver(info);
2653 } else {
2654 if ( info->rx_enabled )
2655 usc_stop_receiver(info);
2656 }
2657 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2658 return 0;
2659
2660 } /* end of mgsl_rxenable() */
2661
2662 /* mgsl_wait_event() wait for specified event to occur
2663 *
2664 * Arguments: info pointer to device instance data
2665 * mask pointer to bitmask of events to wait for
2666 * Return Value: 0 if successful and bit mask updated with
2667 * of events triggerred,
2668 * otherwise error code
2669 */
2670 static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2671 {
2672 unsigned long flags;
2673 int s;
2674 int rc=0;
2675 struct mgsl_icount cprev, cnow;
2676 int events;
2677 int mask;
2678 struct _input_signal_events oldsigs, newsigs;
2679 DECLARE_WAITQUEUE(wait, current);
2680
2681 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2682 if (rc) {
2683 return -EFAULT;
2684 }
2685
2686 if (debug_level >= DEBUG_LEVEL_INFO)
2687 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2688 info->device_name, mask);
2689
2690 spin_lock_irqsave(&info->irq_spinlock,flags);
2691
2692 /* return immediately if state matches requested events */
2693 usc_get_serial_signals(info);
2694 s = info->serial_signals;
2695 events = mask &
2696 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2697 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2698 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2699 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2700 if (events) {
2701 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2702 goto exit;
2703 }
2704
2705 /* save current irq counts */
2706 cprev = info->icount;
2707 oldsigs = info->input_signal_events;
2708
2709 /* enable hunt and idle irqs if needed */
2710 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2711 u16 oldreg = usc_InReg(info,RICR);
2712 u16 newreg = oldreg +
2713 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2714 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2715 if (oldreg != newreg)
2716 usc_OutReg(info, RICR, newreg);
2717 }
2718
2719 set_current_state(TASK_INTERRUPTIBLE);
2720 add_wait_queue(&info->event_wait_q, &wait);
2721
2722 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2723
2724
2725 for(;;) {
2726 schedule();
2727 if (signal_pending(current)) {
2728 rc = -ERESTARTSYS;
2729 break;
2730 }
2731
2732 /* get current irq counts */
2733 spin_lock_irqsave(&info->irq_spinlock,flags);
2734 cnow = info->icount;
2735 newsigs = info->input_signal_events;
2736 set_current_state(TASK_INTERRUPTIBLE);
2737 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2738
2739 /* if no change, wait aborted for some reason */
2740 if (newsigs.dsr_up == oldsigs.dsr_up &&
2741 newsigs.dsr_down == oldsigs.dsr_down &&
2742 newsigs.dcd_up == oldsigs.dcd_up &&
2743 newsigs.dcd_down == oldsigs.dcd_down &&
2744 newsigs.cts_up == oldsigs.cts_up &&
2745 newsigs.cts_down == oldsigs.cts_down &&
2746 newsigs.ri_up == oldsigs.ri_up &&
2747 newsigs.ri_down == oldsigs.ri_down &&
2748 cnow.exithunt == cprev.exithunt &&
2749 cnow.rxidle == cprev.rxidle) {
2750 rc = -EIO;
2751 break;
2752 }
2753
2754 events = mask &
2755 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2756 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2757 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2758 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2759 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2760 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2761 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2762 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2763 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2764 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2765 if (events)
2766 break;
2767
2768 cprev = cnow;
2769 oldsigs = newsigs;
2770 }
2771
2772 remove_wait_queue(&info->event_wait_q, &wait);
2773 set_current_state(TASK_RUNNING);
2774
2775 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2776 spin_lock_irqsave(&info->irq_spinlock,flags);
2777 if (!waitqueue_active(&info->event_wait_q)) {
2778 /* disable enable exit hunt mode/idle rcvd IRQs */
2779 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2780 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2781 }
2782 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2783 }
2784 exit:
2785 if ( rc == 0 )
2786 PUT_USER(rc, events, mask_ptr);
2787
2788 return rc;
2789
2790 } /* end of mgsl_wait_event() */
2791
2792 static int modem_input_wait(struct mgsl_struct *info,int arg)
2793 {
2794 unsigned long flags;
2795 int rc;
2796 struct mgsl_icount cprev, cnow;
2797 DECLARE_WAITQUEUE(wait, current);
2798
2799 /* save current irq counts */
2800 spin_lock_irqsave(&info->irq_spinlock,flags);
2801 cprev = info->icount;
2802 add_wait_queue(&info->status_event_wait_q, &wait);
2803 set_current_state(TASK_INTERRUPTIBLE);
2804 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2805
2806 for(;;) {
2807 schedule();
2808 if (signal_pending(current)) {
2809 rc = -ERESTARTSYS;
2810 break;
2811 }
2812
2813 /* get new irq counts */
2814 spin_lock_irqsave(&info->irq_spinlock,flags);
2815 cnow = info->icount;
2816 set_current_state(TASK_INTERRUPTIBLE);
2817 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2818
2819 /* if no change, wait aborted for some reason */
2820 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2821 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2822 rc = -EIO;
2823 break;
2824 }
2825
2826 /* check for change in caller specified modem input */
2827 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2828 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2829 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2830 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2831 rc = 0;
2832 break;
2833 }
2834
2835 cprev = cnow;
2836 }
2837 remove_wait_queue(&info->status_event_wait_q, &wait);
2838 set_current_state(TASK_RUNNING);
2839 return rc;
2840 }
2841
2842 /* return the state of the serial control and status signals
2843 */
2844 static int tiocmget(struct tty_struct *tty, struct file *file)
2845 {
2846 struct mgsl_struct *info = tty->driver_data;
2847 unsigned int result;
2848 unsigned long flags;
2849
2850 spin_lock_irqsave(&info->irq_spinlock,flags);
2851 usc_get_serial_signals(info);
2852 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2853
2854 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2855 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2856 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2857 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2858 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2859 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2860
2861 if (debug_level >= DEBUG_LEVEL_INFO)
2862 printk("%s(%d):%s tiocmget() value=%08X\n",
2863 __FILE__,__LINE__, info->device_name, result );
2864 return result;
2865 }
2866
2867 /* set modem control signals (DTR/RTS)
2868 */
2869 static int tiocmset(struct tty_struct *tty, struct file *file,
2870 unsigned int set, unsigned int clear)
2871 {
2872 struct mgsl_struct *info = tty->driver_data;
2873 unsigned long flags;
2874
2875 if (debug_level >= DEBUG_LEVEL_INFO)
2876 printk("%s(%d):%s tiocmset(%x,%x)\n",
2877 __FILE__,__LINE__,info->device_name, set, clear);
2878
2879 if (set & TIOCM_RTS)
2880 info->serial_signals |= SerialSignal_RTS;
2881 if (set & TIOCM_DTR)
2882 info->serial_signals |= SerialSignal_DTR;
2883 if (clear & TIOCM_RTS)
2884 info->serial_signals &= ~SerialSignal_RTS;
2885 if (clear & TIOCM_DTR)
2886 info->serial_signals &= ~SerialSignal_DTR;
2887
2888 spin_lock_irqsave(&info->irq_spinlock,flags);
2889 usc_set_serial_signals(info);
2890 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2891
2892 return 0;
2893 }
2894
2895 /* mgsl_break() Set or clear transmit break condition
2896 *
2897 * Arguments: tty pointer to tty instance data
2898 * break_state -1=set break condition, 0=clear
2899 * Return Value: error code
2900 */
2901 static int mgsl_break(struct tty_struct *tty, int break_state)
2902 {
2903 struct mgsl_struct * info = tty->driver_data;
2904 unsigned long flags;
2905
2906 if (debug_level >= DEBUG_LEVEL_INFO)
2907 printk("%s(%d):mgsl_break(%s,%d)\n",
2908 __FILE__,__LINE__, info->device_name, break_state);
2909
2910 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2911 return -EINVAL;
2912
2913 spin_lock_irqsave(&info->irq_spinlock,flags);
2914 if (break_state == -1)
2915 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2916 else
2917 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2918 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2919 return 0;
2920
2921 } /* end of mgsl_break() */
2922
2923 /* mgsl_ioctl() Service an IOCTL request
2924 *
2925 * Arguments:
2926 *
2927 * tty pointer to tty instance data
2928 * file pointer to associated file object for device
2929 * cmd IOCTL command code
2930 * arg command argument/context
2931 *
2932 * Return Value: 0 if success, otherwise error code
2933 */
2934 static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
2935 unsigned int cmd, unsigned long arg)
2936 {
2937 struct mgsl_struct * info = tty->driver_data;
2938 int ret;
2939
2940 if (debug_level >= DEBUG_LEVEL_INFO)
2941 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2942 info->device_name, cmd );
2943
2944 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2945 return -ENODEV;
2946
2947 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2948 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
2949 if (tty->flags & (1 << TTY_IO_ERROR))
2950 return -EIO;
2951 }
2952
2953 lock_kernel();
2954 ret = mgsl_ioctl_common(info, cmd, arg);
2955 unlock_kernel();
2956 return ret;
2957 }
2958
2959 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2960 {
2961 int error;
2962 struct mgsl_icount cnow; /* kernel counter temps */
2963 void __user *argp = (void __user *)arg;
2964 struct serial_icounter_struct __user *p_cuser; /* user space */
2965 unsigned long flags;
2966
2967 switch (cmd) {
2968 case MGSL_IOCGPARAMS:
2969 return mgsl_get_params(info, argp);
2970 case MGSL_IOCSPARAMS:
2971 return mgsl_set_params(info, argp);
2972 case MGSL_IOCGTXIDLE:
2973 return mgsl_get_txidle(info, argp);
2974 case MGSL_IOCSTXIDLE:
2975 return mgsl_set_txidle(info,(int)arg);
2976 case MGSL_IOCTXENABLE:
2977 return mgsl_txenable(info,(int)arg);
2978 case MGSL_IOCRXENABLE:
2979 return mgsl_rxenable(info,(int)arg);
2980 case MGSL_IOCTXABORT:
2981 return mgsl_txabort(info);
2982 case MGSL_IOCGSTATS:
2983 return mgsl_get_stats(info, argp);
2984 case MGSL_IOCWAITEVENT:
2985 return mgsl_wait_event(info, argp);
2986 case MGSL_IOCLOOPTXDONE:
2987 return mgsl_loopmode_send_done(info);
2988 /* Wait for modem input (DCD,RI,DSR,CTS) change
2989 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
2990 */
2991 case TIOCMIWAIT:
2992 return modem_input_wait(info,(int)arg);
2993
2994 /*
2995 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2996 * Return: write counters to the user passed counter struct
2997 * NB: both 1->0 and 0->1 transitions are counted except for
2998 * RI where only 0->1 is counted.
2999 */
3000 case TIOCGICOUNT:
3001 spin_lock_irqsave(&info->irq_spinlock,flags);
3002 cnow = info->icount;
3003 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3004 p_cuser = argp;
3005 PUT_USER(error,cnow.cts, &p_cuser->cts);
3006 if (error) return error;
3007 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
3008 if (error) return error;
3009 PUT_USER(error,cnow.rng, &p_cuser->rng);
3010 if (error) return error;
3011 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
3012 if (error) return error;
3013 PUT_USER(error,cnow.rx, &p_cuser->rx);
3014 if (error) return error;
3015 PUT_USER(error,cnow.tx, &p_cuser->tx);
3016 if (error) return error;
3017 PUT_USER(error,cnow.frame, &p_cuser->frame);
3018 if (error) return error;
3019 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
3020 if (error) return error;
3021 PUT_USER(error,cnow.parity, &p_cuser->parity);
3022 if (error) return error;
3023 PUT_USER(error,cnow.brk, &p_cuser->brk);
3024 if (error) return error;
3025 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
3026 if (error) return error;
3027 return 0;
3028 default:
3029 return -ENOIOCTLCMD;
3030 }
3031 return 0;
3032 }
3033
3034 /* mgsl_set_termios()
3035 *
3036 * Set new termios settings
3037 *
3038 * Arguments:
3039 *
3040 * tty pointer to tty structure
3041 * termios pointer to buffer to hold returned old termios
3042 *
3043 * Return Value: None
3044 */
3045 static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3046 {
3047 struct mgsl_struct *info = tty->driver_data;
3048 unsigned long flags;
3049
3050 if (debug_level >= DEBUG_LEVEL_INFO)
3051 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3052 tty->driver->name );
3053
3054 mgsl_change_params(info);
3055
3056 /* Handle transition to B0 status */
3057 if (old_termios->c_cflag & CBAUD &&
3058 !(tty->termios->c_cflag & CBAUD)) {
3059 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3060 spin_lock_irqsave(&info->irq_spinlock,flags);
3061 usc_set_serial_signals(info);
3062 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3063 }
3064
3065 /* Handle transition away from B0 status */
3066 if (!(old_termios->c_cflag & CBAUD) &&
3067 tty->termios->c_cflag & CBAUD) {
3068 info->serial_signals |= SerialSignal_DTR;
3069 if (!(tty->termios->c_cflag & CRTSCTS) ||
3070 !test_bit(TTY_THROTTLED, &tty->flags)) {
3071 info->serial_signals |= SerialSignal_RTS;
3072 }
3073 spin_lock_irqsave(&info->irq_spinlock,flags);
3074 usc_set_serial_signals(info);
3075 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3076 }
3077
3078 /* Handle turning off CRTSCTS */
3079 if (old_termios->c_cflag & CRTSCTS &&
3080 !(tty->termios->c_cflag & CRTSCTS)) {
3081 tty->hw_stopped = 0;
3082 mgsl_start(tty);
3083 }
3084
3085 } /* end of mgsl_set_termios() */
3086
3087 /* mgsl_close()
3088 *
3089 * Called when port is closed. Wait for remaining data to be
3090 * sent. Disable port and free resources.
3091 *
3092 * Arguments:
3093 *
3094 * tty pointer to open tty structure
3095 * filp pointer to open file object
3096 *
3097 * Return Value: None
3098 */
3099 static void mgsl_close(struct tty_struct *tty, struct file * filp)
3100 {
3101 struct mgsl_struct * info = tty->driver_data;
3102
3103 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3104 return;
3105
3106 if (debug_level >= DEBUG_LEVEL_INFO)
3107 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3108 __FILE__,__LINE__, info->device_name, info->port.count);
3109
3110 if (tty_port_close_start(&info->port, tty, filp) == 0)
3111 goto cleanup;
3112
3113 if (info->port.flags & ASYNC_INITIALIZED)
3114 mgsl_wait_until_sent(tty, info->timeout);
3115 mgsl_flush_buffer(tty);
3116 tty_ldisc_flush(tty);
3117 shutdown(info);
3118
3119 tty_port_close_end(&info->port, tty);
3120 info->port.tty = NULL;
3121 cleanup:
3122 if (debug_level >= DEBUG_LEVEL_INFO)
3123 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3124 tty->driver->name, info->port.count);
3125
3126 } /* end of mgsl_close() */
3127
3128 /* mgsl_wait_until_sent()
3129 *
3130 * Wait until the transmitter is empty.
3131 *
3132 * Arguments:
3133 *
3134 * tty pointer to tty info structure
3135 * timeout time to wait for send completion
3136 *
3137 * Return Value: None
3138 */
3139 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3140 {
3141 struct mgsl_struct * info = tty->driver_data;
3142 unsigned long orig_jiffies, char_time;
3143
3144 if (!info )
3145 return;
3146
3147 if (debug_level >= DEBUG_LEVEL_INFO)
3148 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3149 __FILE__,__LINE__, info->device_name );
3150
3151 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3152 return;
3153
3154 if (!(info->port.flags & ASYNC_INITIALIZED))
3155 goto exit;
3156
3157 orig_jiffies = jiffies;
3158
3159 /* Set check interval to 1/5 of estimated time to
3160 * send a character, and make it at least 1. The check
3161 * interval should also be less than the timeout.
3162 * Note: use tight timings here to satisfy the NIST-PCTS.
3163 */
3164
3165 lock_kernel();
3166 if ( info->params.data_rate ) {
3167 char_time = info->timeout/(32 * 5);
3168 if (!char_time)
3169 char_time++;
3170 } else
3171 char_time = 1;
3172
3173 if (timeout)
3174 char_time = min_t(unsigned long, char_time, timeout);
3175
3176 if ( info->params.mode == MGSL_MODE_HDLC ||
3177 info->params.mode == MGSL_MODE_RAW ) {
3178 while (info->tx_active) {
3179 msleep_interruptible(jiffies_to_msecs(char_time));
3180 if (signal_pending(current))
3181 break;
3182 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3183 break;
3184 }
3185 } else {
3186 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3187 info->tx_enabled) {
3188 msleep_interruptible(jiffies_to_msecs(char_time));
3189 if (signal_pending(current))
3190 break;
3191 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3192 break;
3193 }
3194 }
3195 unlock_kernel();
3196
3197 exit:
3198 if (debug_level >= DEBUG_LEVEL_INFO)
3199 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3200 __FILE__,__LINE__, info->device_name );
3201
3202 } /* end of mgsl_wait_until_sent() */
3203
3204 /* mgsl_hangup()
3205 *
3206 * Called by tty_hangup() when a hangup is signaled.
3207 * This is the same as to closing all open files for the port.
3208 *
3209 * Arguments: tty pointer to associated tty object
3210 * Return Value: None
3211 */
3212 static void mgsl_hangup(struct tty_struct *tty)
3213 {
3214 struct mgsl_struct * info = tty->driver_data;
3215
3216 if (debug_level >= DEBUG_LEVEL_INFO)
3217 printk("%s(%d):mgsl_hangup(%s)\n",
3218 __FILE__,__LINE__, info->device_name );
3219
3220 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3221 return;
3222
3223 mgsl_flush_buffer(tty);
3224 shutdown(info);
3225
3226 info->port.count = 0;
3227 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3228 info->port.tty = NULL;
3229
3230 wake_up_interruptible(&info->port.open_wait);
3231
3232 } /* end of mgsl_hangup() */
3233
3234 /*
3235 * carrier_raised()
3236 *
3237 * Return true if carrier is raised
3238 */
3239
3240 static int carrier_raised(struct tty_port *port)
3241 {
3242 unsigned long flags;
3243 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3244
3245 spin_lock_irqsave(&info->irq_spinlock, flags);
3246 usc_get_serial_signals(info);
3247 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3248 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3249 }
3250
3251 static void dtr_rts(struct tty_port *port, int on)
3252 {
3253 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3254 unsigned long flags;
3255
3256 spin_lock_irqsave(&info->irq_spinlock,flags);
3257 if (on)
3258 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3259 else
3260 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3261 usc_set_serial_signals(info);
3262 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3263 }
3264
3265
3266 /* block_til_ready()
3267 *
3268 * Block the current process until the specified port
3269 * is ready to be opened.
3270 *
3271 * Arguments:
3272 *
3273 * tty pointer to tty info structure
3274 * filp pointer to open file object
3275 * info pointer to device instance data
3276 *
3277 * Return Value: 0 if success, otherwise error code
3278 */
3279 static int block_til_ready(struct tty_struct *tty, struct file * filp,
3280 struct mgsl_struct *info)
3281 {
3282 DECLARE_WAITQUEUE(wait, current);
3283 int retval;
3284 bool do_clocal = false;
3285 bool extra_count = false;
3286 unsigned long flags;
3287 int dcd;
3288 struct tty_port *port = &info->port;
3289
3290 if (debug_level >= DEBUG_LEVEL_INFO)
3291 printk("%s(%d):block_til_ready on %s\n",
3292 __FILE__,__LINE__, tty->driver->name );
3293
3294 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3295 /* nonblock mode is set or port is not enabled */
3296 port->flags |= ASYNC_NORMAL_ACTIVE;
3297 return 0;
3298 }
3299
3300 if (tty->termios->c_cflag & CLOCAL)
3301 do_clocal = true;
3302
3303 /* Wait for carrier detect and the line to become
3304 * free (i.e., not in use by the callout). While we are in
3305 * this loop, port->count is dropped by one, so that
3306 * mgsl_close() knows when to free things. We restore it upon
3307 * exit, either normal or abnormal.
3308 */
3309
3310 retval = 0;
3311 add_wait_queue(&port->open_wait, &wait);
3312
3313 if (debug_level >= DEBUG_LEVEL_INFO)
3314 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3315 __FILE__,__LINE__, tty->driver->name, port->count );
3316
3317 spin_lock_irqsave(&info->irq_spinlock, flags);
3318 if (!tty_hung_up_p(filp)) {
3319 extra_count = true;
3320 port->count--;
3321 }
3322 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3323 port->blocked_open++;
3324
3325 while (1) {
3326 if (tty->termios->c_cflag & CBAUD)
3327 tty_port_raise_dtr_rts(port);
3328
3329 set_current_state(TASK_INTERRUPTIBLE);
3330
3331 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3332 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3333 -EAGAIN : -ERESTARTSYS;
3334 break;
3335 }
3336
3337 dcd = tty_port_carrier_raised(&info->port);
3338
3339 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || dcd))
3340 break;
3341
3342 if (signal_pending(current)) {
3343 retval = -ERESTARTSYS;
3344 break;
3345 }
3346
3347 if (debug_level >= DEBUG_LEVEL_INFO)
3348 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3349 __FILE__,__LINE__, tty->driver->name, port->count );
3350
3351 schedule();
3352 }
3353
3354 set_current_state(TASK_RUNNING);
3355 remove_wait_queue(&port->open_wait, &wait);
3356
3357 /* FIXME: Racy on hangup during close wait */
3358 if (extra_count)
3359 port->count++;
3360 port->blocked_open--;
3361
3362 if (debug_level >= DEBUG_LEVEL_INFO)
3363 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3364 __FILE__,__LINE__, tty->driver->name, port->count );
3365
3366 if (!retval)
3367 port->flags |= ASYNC_NORMAL_ACTIVE;
3368
3369 return retval;
3370
3371 } /* end of block_til_ready() */
3372
3373 /* mgsl_open()
3374 *
3375 * Called when a port is opened. Init and enable port.
3376 * Perform serial-specific initialization for the tty structure.
3377 *
3378 * Arguments: tty pointer to tty info structure
3379 * filp associated file pointer
3380 *
3381 * Return Value: 0 if success, otherwise error code
3382 */
3383 static int mgsl_open(struct tty_struct *tty, struct file * filp)
3384 {
3385 struct mgsl_struct *info;
3386 int retval, line;
3387 unsigned long flags;
3388
3389 /* verify range of specified line number */
3390 line = tty->index;
3391 if ((line < 0) || (line >= mgsl_device_count)) {
3392 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3393 __FILE__,__LINE__,line);
3394 return -ENODEV;
3395 }
3396
3397 /* find the info structure for the specified line */
3398 info = mgsl_device_list;
3399 while(info && info->line != line)
3400 info = info->next_device;
3401 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3402 return -ENODEV;
3403
3404 tty->driver_data = info;
3405 info->port.tty = tty;
3406
3407 if (debug_level >= DEBUG_LEVEL_INFO)
3408 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3409 __FILE__,__LINE__,tty->driver->name, info->port.count);
3410
3411 /* If port is closing, signal caller to try again */
3412 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
3413 if (info->port.flags & ASYNC_CLOSING)
3414 interruptible_sleep_on(&info->port.close_wait);
3415 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
3416 -EAGAIN : -ERESTARTSYS);
3417 goto cleanup;
3418 }
3419
3420 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3421
3422 spin_lock_irqsave(&info->netlock, flags);
3423 if (info->netcount) {
3424 retval = -EBUSY;
3425 spin_unlock_irqrestore(&info->netlock, flags);
3426 goto cleanup;
3427 }
3428 info->port.count++;
3429 spin_unlock_irqrestore(&info->netlock, flags);
3430
3431 if (info->port.count == 1) {
3432 /* 1st open on this device, init hardware */
3433 retval = startup(info);
3434 if (retval < 0)
3435 goto cleanup;
3436 }
3437
3438 retval = block_til_ready(tty, filp, info);
3439 if (retval) {
3440 if (debug_level >= DEBUG_LEVEL_INFO)
3441 printk("%s(%d):block_til_ready(%s) returned %d\n",
3442 __FILE__,__LINE__, info->device_name, retval);
3443 goto cleanup;
3444 }
3445
3446 if (debug_level >= DEBUG_LEVEL_INFO)
3447 printk("%s(%d):mgsl_open(%s) success\n",
3448 __FILE__,__LINE__, info->device_name);
3449 retval = 0;
3450
3451 cleanup:
3452 if (retval) {
3453 if (tty->count == 1)
3454 info->port.tty = NULL; /* tty layer will release tty struct */
3455 if(info->port.count)
3456 info->port.count--;
3457 }
3458
3459 return retval;
3460
3461 } /* end of mgsl_open() */
3462
3463 /*
3464 * /proc fs routines....
3465 */
3466
3467 static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
3468 {
3469 char stat_buf[30];
3470 unsigned long flags;
3471
3472 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3473 seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3474 info->device_name, info->io_base, info->irq_level,
3475 info->phys_memory_base, info->phys_lcr_base);
3476 } else {
3477 seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
3478 info->device_name, info->io_base,
3479 info->irq_level, info->dma_level);
3480 }
3481
3482 /* output current serial signal states */
3483 spin_lock_irqsave(&info->irq_spinlock,flags);
3484 usc_get_serial_signals(info);
3485 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3486
3487 stat_buf[0] = 0;
3488 stat_buf[1] = 0;
3489 if (info->serial_signals & SerialSignal_RTS)
3490 strcat(stat_buf, "|RTS");
3491 if (info->serial_signals & SerialSignal_CTS)
3492 strcat(stat_buf, "|CTS");
3493 if (info->serial_signals & SerialSignal_DTR)
3494 strcat(stat_buf, "|DTR");
3495 if (info->serial_signals & SerialSignal_DSR)
3496 strcat(stat_buf, "|DSR");
3497 if (info->serial_signals & SerialSignal_DCD)
3498 strcat(stat_buf, "|CD");
3499 if (info->serial_signals & SerialSignal_RI)
3500 strcat(stat_buf, "|RI");
3501
3502 if (info->params.mode == MGSL_MODE_HDLC ||
3503 info->params.mode == MGSL_MODE_RAW ) {
3504 seq_printf(m, " HDLC txok:%d rxok:%d",
3505 info->icount.txok, info->icount.rxok);
3506 if (info->icount.txunder)
3507 seq_printf(m, " txunder:%d", info->icount.txunder);
3508 if (info->icount.txabort)
3509 seq_printf(m, " txabort:%d", info->icount.txabort);
3510 if (info->icount.rxshort)
3511 seq_printf(m, " rxshort:%d", info->icount.rxshort);
3512 if (info->icount.rxlong)
3513 seq_printf(m, " rxlong:%d", info->icount.rxlong);
3514 if (info->icount.rxover)
3515 seq_printf(m, " rxover:%d", info->icount.rxover);
3516 if (info->icount.rxcrc)
3517 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
3518 } else {
3519 seq_printf(m, " ASYNC tx:%d rx:%d",
3520 info->icount.tx, info->icount.rx);
3521 if (info->icount.frame)
3522 seq_printf(m, " fe:%d", info->icount.frame);
3523 if (info->icount.parity)
3524 seq_printf(m, " pe:%d", info->icount.parity);
3525 if (info->icount.brk)
3526 seq_printf(m, " brk:%d", info->icount.brk);
3527 if (info->icount.overrun)
3528 seq_printf(m, " oe:%d", info->icount.overrun);
3529 }
3530
3531 /* Append serial signal status to end */
3532 seq_printf(m, " %s\n", stat_buf+1);
3533
3534 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3535 info->tx_active,info->bh_requested,info->bh_running,
3536 info->pending_bh);
3537
3538 spin_lock_irqsave(&info->irq_spinlock,flags);
3539 {
3540 u16 Tcsr = usc_InReg( info, TCSR );
3541 u16 Tdmr = usc_InDmaReg( info, TDMR );
3542 u16 Ticr = usc_InReg( info, TICR );
3543 u16 Rscr = usc_InReg( info, RCSR );
3544 u16 Rdmr = usc_InDmaReg( info, RDMR );
3545 u16 Ricr = usc_InReg( info, RICR );
3546 u16 Icr = usc_InReg( info, ICR );
3547 u16 Dccr = usc_InReg( info, DCCR );
3548 u16 Tmr = usc_InReg( info, TMR );
3549 u16 Tccr = usc_InReg( info, TCCR );
3550 u16 Ccar = inw( info->io_base + CCAR );
3551 seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3552 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3553 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3554 }
3555 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3556 }
3557
3558 /* Called to print information about devices */
3559 static int mgsl_proc_show(struct seq_file *m, void *v)
3560 {
3561 struct mgsl_struct *info;
3562
3563 seq_printf(m, "synclink driver:%s\n", driver_version);
3564
3565 info = mgsl_device_list;
3566 while( info ) {
3567 line_info(m, info);
3568 info = info->next_device;
3569 }
3570 return 0;
3571 }
3572
3573 static int mgsl_proc_open(struct inode *inode, struct file *file)
3574 {
3575 return single_open(file, mgsl_proc_show, NULL);
3576 }
3577
3578 static const struct file_operations mgsl_proc_fops = {
3579 .owner = THIS_MODULE,
3580 .open = mgsl_proc_open,
3581 .read = seq_read,
3582 .llseek = seq_lseek,
3583 .release = single_release,
3584 };
3585
3586 /* mgsl_allocate_dma_buffers()
3587 *
3588 * Allocate and format DMA buffers (ISA adapter)
3589 * or format shared memory buffers (PCI adapter).
3590 *
3591 * Arguments: info pointer to device instance data
3592 * Return Value: 0 if success, otherwise error
3593 */
3594 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3595 {
3596 unsigned short BuffersPerFrame;
3597
3598 info->last_mem_alloc = 0;
3599
3600 /* Calculate the number of DMA buffers necessary to hold the */
3601 /* largest allowable frame size. Note: If the max frame size is */
3602 /* not an even multiple of the DMA buffer size then we need to */
3603 /* round the buffer count per frame up one. */
3604
3605 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3606 if ( info->max_frame_size % DMABUFFERSIZE )
3607 BuffersPerFrame++;
3608
3609 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3610 /*
3611 * The PCI adapter has 256KBytes of shared memory to use.
3612 * This is 64 PAGE_SIZE buffers.
3613 *
3614 * The first page is used for padding at this time so the
3615 * buffer list does not begin at offset 0 of the PCI
3616 * adapter's shared memory.
3617 *
3618 * The 2nd page is used for the buffer list. A 4K buffer
3619 * list can hold 128 DMA_BUFFER structures at 32 bytes
3620 * each.
3621 *
3622 * This leaves 62 4K pages.
3623 *
3624 * The next N pages are used for transmit frame(s). We
3625 * reserve enough 4K page blocks to hold the required
3626 * number of transmit dma buffers (num_tx_dma_buffers),
3627 * each of MaxFrameSize size.
3628 *
3629 * Of the remaining pages (62-N), determine how many can
3630 * be used to receive full MaxFrameSize inbound frames
3631 */
3632 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3633 info->rx_buffer_count = 62 - info->tx_buffer_count;
3634 } else {
3635 /* Calculate the number of PAGE_SIZE buffers needed for */
3636 /* receive and transmit DMA buffers. */
3637
3638
3639 /* Calculate the number of DMA buffers necessary to */
3640 /* hold 7 max size receive frames and one max size transmit frame. */
3641 /* The receive buffer count is bumped by one so we avoid an */
3642 /* End of List condition if all receive buffers are used when */
3643 /* using linked list DMA buffers. */
3644
3645 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3646 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3647
3648 /*
3649 * limit total TxBuffers & RxBuffers to 62 4K total
3650 * (ala PCI Allocation)
3651 */
3652
3653 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3654 info->rx_buffer_count = 62 - info->tx_buffer_count;
3655
3656 }
3657
3658 if ( debug_level >= DEBUG_LEVEL_INFO )
3659 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3660 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3661
3662 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3663 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3664 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3665 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3666 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3667 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3668 return -ENOMEM;
3669 }
3670
3671 mgsl_reset_rx_dma_buffers( info );
3672 mgsl_reset_tx_dma_buffers( info );
3673
3674 return 0;
3675
3676 } /* end of mgsl_allocate_dma_buffers() */
3677
3678 /*
3679 * mgsl_alloc_buffer_list_memory()
3680 *
3681 * Allocate a common DMA buffer for use as the
3682 * receive and transmit buffer lists.
3683 *
3684 * A buffer list is a set of buffer entries where each entry contains
3685 * a pointer to an actual buffer and a pointer to the next buffer entry
3686 * (plus some other info about the buffer).
3687 *
3688 * The buffer entries for a list are built to form a circular list so
3689 * that when the entire list has been traversed you start back at the
3690 * beginning.
3691 *
3692 * This function allocates memory for just the buffer entries.
3693 * The links (pointer to next entry) are filled in with the physical
3694 * address of the next entry so the adapter can navigate the list
3695 * using bus master DMA. The pointers to the actual buffers are filled
3696 * out later when the actual buffers are allocated.
3697 *
3698 * Arguments: info pointer to device instance data
3699 * Return Value: 0 if success, otherwise error
3700 */
3701 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3702 {
3703 unsigned int i;
3704
3705 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3706 /* PCI adapter uses shared memory. */
3707 info->buffer_list = info->memory_base + info->last_mem_alloc;
3708 info->buffer_list_phys = info->last_mem_alloc;
3709 info->last_mem_alloc += BUFFERLISTSIZE;
3710 } else {
3711 /* ISA adapter uses system memory. */
3712 /* The buffer lists are allocated as a common buffer that both */
3713 /* the processor and adapter can access. This allows the driver to */
3714 /* inspect portions of the buffer while other portions are being */
3715 /* updated by the adapter using Bus Master DMA. */
3716
3717 info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3718 if (info->buffer_list == NULL)
3719 return -ENOMEM;
3720 info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3721 }
3722
3723 /* We got the memory for the buffer entry lists. */
3724 /* Initialize the memory block to all zeros. */
3725 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3726
3727 /* Save virtual address pointers to the receive and */
3728 /* transmit buffer lists. (Receive 1st). These pointers will */
3729 /* be used by the processor to access the lists. */
3730 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3731 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3732 info->tx_buffer_list += info->rx_buffer_count;
3733
3734 /*
3735 * Build the links for the buffer entry lists such that
3736 * two circular lists are built. (Transmit and Receive).
3737 *
3738 * Note: the links are physical addresses
3739 * which are read by the adapter to determine the next
3740 * buffer entry to use.
3741 */
3742
3743 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3744 /* calculate and store physical address of this buffer entry */
3745 info->rx_buffer_list[i].phys_entry =
3746 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3747
3748 /* calculate and store physical address of */
3749 /* next entry in cirular list of entries */
3750
3751 info->rx_buffer_list[i].link = info->buffer_list_phys;
3752
3753 if ( i < info->rx_buffer_count - 1 )
3754 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3755 }
3756
3757 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3758 /* calculate and store physical address of this buffer entry */
3759 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3760 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3761
3762 /* calculate and store physical address of */
3763 /* next entry in cirular list of entries */
3764
3765 info->tx_buffer_list[i].link = info->buffer_list_phys +
3766 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3767
3768 if ( i < info->tx_buffer_count - 1 )
3769 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3770 }
3771
3772 return 0;
3773
3774 } /* end of mgsl_alloc_buffer_list_memory() */
3775
3776 /* Free DMA buffers allocated for use as the
3777 * receive and transmit buffer lists.
3778 * Warning:
3779 *
3780 * The data transfer buffers associated with the buffer list
3781 * MUST be freed before freeing the buffer list itself because
3782 * the buffer list contains the information necessary to free
3783 * the individual buffers!
3784 */
3785 static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3786 {
3787 if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3788 dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3789
3790 info->buffer_list = NULL;
3791 info->rx_buffer_list = NULL;
3792 info->tx_buffer_list = NULL;
3793
3794 } /* end of mgsl_free_buffer_list_memory() */
3795
3796 /*
3797 * mgsl_alloc_frame_memory()
3798 *
3799 * Allocate the frame DMA buffers used by the specified buffer list.
3800 * Each DMA buffer will be one memory page in size. This is necessary
3801 * because memory can fragment enough that it may be impossible
3802 * contiguous pages.
3803 *
3804 * Arguments:
3805 *
3806 * info pointer to device instance data
3807 * BufferList pointer to list of buffer entries
3808 * Buffercount count of buffer entries in buffer list
3809 *
3810 * Return Value: 0 if success, otherwise -ENOMEM
3811 */
3812 static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3813 {
3814 int i;
3815 u32 phys_addr;
3816
3817 /* Allocate page sized buffers for the receive buffer list */
3818
3819 for ( i = 0; i < Buffercount; i++ ) {
3820 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3821 /* PCI adapter uses shared memory buffers. */
3822 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3823 phys_addr = info->last_mem_alloc;
3824 info->last_mem_alloc += DMABUFFERSIZE;
3825 } else {
3826 /* ISA adapter uses system memory. */
3827 BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3828 if (BufferList[i].virt_addr == NULL)
3829 return -ENOMEM;
3830 phys_addr = (u32)(BufferList[i].dma_addr);
3831 }
3832 BufferList[i].phys_addr = phys_addr;
3833 }
3834
3835 return 0;
3836
3837 } /* end of mgsl_alloc_frame_memory() */
3838
3839 /*
3840 * mgsl_free_frame_memory()
3841 *
3842 * Free the buffers associated with
3843 * each buffer entry of a buffer list.
3844 *
3845 * Arguments:
3846 *
3847 * info pointer to device instance data
3848 * BufferList pointer to list of buffer entries
3849 * Buffercount count of buffer entries in buffer list
3850 *
3851 * Return Value: None
3852 */
3853 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3854 {
3855 int i;
3856
3857 if ( BufferList ) {
3858 for ( i = 0 ; i < Buffercount ; i++ ) {
3859 if ( BufferList[i].virt_addr ) {
3860 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3861 dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3862 BufferList[i].virt_addr = NULL;
3863 }
3864 }
3865 }
3866
3867 } /* end of mgsl_free_frame_memory() */
3868
3869 /* mgsl_free_dma_buffers()
3870 *
3871 * Free DMA buffers
3872 *
3873 * Arguments: info pointer to device instance data
3874 * Return Value: None
3875 */
3876 static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3877 {
3878 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3879 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3880 mgsl_free_buffer_list_memory( info );
3881
3882 } /* end of mgsl_free_dma_buffers() */
3883
3884
3885 /*
3886 * mgsl_alloc_intermediate_rxbuffer_memory()
3887 *
3888 * Allocate a buffer large enough to hold max_frame_size. This buffer
3889 * is used to pass an assembled frame to the line discipline.
3890 *
3891 * Arguments:
3892 *
3893 * info pointer to device instance data
3894 *
3895 * Return Value: 0 if success, otherwise -ENOMEM
3896 */
3897 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3898 {
3899 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3900 if ( info->intermediate_rxbuffer == NULL )
3901 return -ENOMEM;
3902
3903 return 0;
3904
3905 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3906
3907 /*
3908 * mgsl_free_intermediate_rxbuffer_memory()
3909 *
3910 *
3911 * Arguments:
3912 *
3913 * info pointer to device instance data
3914 *
3915 * Return Value: None
3916 */
3917 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3918 {
3919 kfree(info->intermediate_rxbuffer);
3920 info->intermediate_rxbuffer = NULL;
3921
3922 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
3923
3924 /*
3925 * mgsl_alloc_intermediate_txbuffer_memory()
3926 *
3927 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3928 * This buffer is used to load transmit frames into the adapter's dma transfer
3929 * buffers when there is sufficient space.
3930 *
3931 * Arguments:
3932 *
3933 * info pointer to device instance data
3934 *
3935 * Return Value: 0 if success, otherwise -ENOMEM
3936 */
3937 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3938 {
3939 int i;
3940
3941 if ( debug_level >= DEBUG_LEVEL_INFO )
3942 printk("%s %s(%d) allocating %d tx holding buffers\n",
3943 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3944
3945 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3946
3947 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3948 info->tx_holding_buffers[i].buffer =
3949 kmalloc(info->max_frame_size, GFP_KERNEL);
3950 if (info->tx_holding_buffers[i].buffer == NULL) {
3951 for (--i; i >= 0; i--) {
3952 kfree(info->tx_holding_buffers[i].buffer);
3953 info->tx_holding_buffers[i].buffer = NULL;
3954 }
3955 return -ENOMEM;
3956 }
3957 }
3958
3959 return 0;
3960
3961 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
3962
3963 /*
3964 * mgsl_free_intermediate_txbuffer_memory()
3965 *
3966 *
3967 * Arguments:
3968 *
3969 * info pointer to device instance data
3970 *
3971 * Return Value: None
3972 */
3973 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
3974 {
3975 int i;
3976
3977 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
3978 kfree(info->tx_holding_buffers[i].buffer);
3979 info->tx_holding_buffers[i].buffer = NULL;
3980 }
3981
3982 info->get_tx_holding_index = 0;
3983 info->put_tx_holding_index = 0;
3984 info->tx_holding_count = 0;
3985
3986 } /* end of mgsl_free_intermediate_txbuffer_memory() */
3987
3988
3989 /*
3990 * load_next_tx_holding_buffer()
3991 *
3992 * attempts to load the next buffered tx request into the
3993 * tx dma buffers
3994 *
3995 * Arguments:
3996 *
3997 * info pointer to device instance data
3998 *
3999 * Return Value: true if next buffered tx request loaded
4000 * into adapter's tx dma buffer,
4001 * false otherwise
4002 */
4003 static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
4004 {
4005 bool ret = false;
4006
4007 if ( info->tx_holding_count ) {
4008 /* determine if we have enough tx dma buffers
4009 * to accommodate the next tx frame
4010 */
4011 struct tx_holding_buffer *ptx =
4012 &info->tx_holding_buffers[info->get_tx_holding_index];
4013 int num_free = num_free_tx_dma_buffers(info);
4014 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4015 if ( ptx->buffer_size % DMABUFFERSIZE )
4016 ++num_needed;
4017
4018 if (num_needed <= num_free) {
4019 info->xmit_cnt = ptx->buffer_size;
4020 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4021
4022 --info->tx_holding_count;
4023 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4024 info->get_tx_holding_index=0;
4025
4026 /* restart transmit timer */
4027 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4028
4029 ret = true;
4030 }
4031 }
4032
4033 return ret;
4034 }
4035
4036 /*
4037 * save_tx_buffer_request()
4038 *
4039 * attempt to store transmit frame request for later transmission
4040 *
4041 * Arguments:
4042 *
4043 * info pointer to device instance data
4044 * Buffer pointer to buffer containing frame to load
4045 * BufferSize size in bytes of frame in Buffer
4046 *
4047 * Return Value: 1 if able to store, 0 otherwise
4048 */
4049 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4050 {
4051 struct tx_holding_buffer *ptx;
4052
4053 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4054 return 0; /* all buffers in use */
4055 }
4056
4057 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4058 ptx->buffer_size = BufferSize;
4059 memcpy( ptx->buffer, Buffer, BufferSize);
4060
4061 ++info->tx_holding_count;
4062 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4063 info->put_tx_holding_index=0;
4064
4065 return 1;
4066 }
4067
4068 static int mgsl_claim_resources(struct mgsl_struct *info)
4069 {
4070 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4071 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4072 __FILE__,__LINE__,info->device_name, info->io_base);
4073 return -ENODEV;
4074 }
4075 info->io_addr_requested = true;
4076
4077 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4078 info->device_name, info ) < 0 ) {
4079 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4080 __FILE__,__LINE__,info->device_name, info->irq_level );
4081 goto errout;
4082 }
4083 info->irq_requested = true;
4084
4085 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4086 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4087 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4088 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4089 goto errout;
4090 }
4091 info->shared_mem_requested = true;
4092 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4093 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4094 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4095 goto errout;
4096 }
4097 info->lcr_mem_requested = true;
4098
4099 info->memory_base = ioremap_nocache(info->phys_memory_base,
4100 0x40000);
4101 if (!info->memory_base) {
4102 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4103 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4104 goto errout;
4105 }
4106
4107 if ( !mgsl_memory_test(info) ) {
4108 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4109 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4110 goto errout;
4111 }
4112
4113 info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4114 PAGE_SIZE);
4115 if (!info->lcr_base) {
4116 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4117 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4118 goto errout;
4119 }
4120 info->lcr_base += info->lcr_offset;
4121
4122 } else {
4123 /* claim DMA channel */
4124
4125 if (request_dma(info->dma_level,info->device_name) < 0){
4126 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4127 __FILE__,__LINE__,info->device_name, info->dma_level );
4128 mgsl_release_resources( info );
4129 return -ENODEV;
4130 }
4131 info->dma_requested = true;
4132
4133 /* ISA adapter uses bus master DMA */
4134 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4135 enable_dma(info->dma_level);
4136 }
4137
4138 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4139 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4140 __FILE__,__LINE__,info->device_name, info->dma_level );
4141 goto errout;
4142 }
4143
4144 return 0;
4145 errout:
4146 mgsl_release_resources(info);
4147 return -ENODEV;
4148
4149 } /* end of mgsl_claim_resources() */
4150
4151 static void mgsl_release_resources(struct mgsl_struct *info)
4152 {
4153 if ( debug_level >= DEBUG_LEVEL_INFO )
4154 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4155 __FILE__,__LINE__,info->device_name );
4156
4157 if ( info->irq_requested ) {
4158 free_irq(info->irq_level, info);
4159 info->irq_requested = false;
4160 }
4161 if ( info->dma_requested ) {
4162 disable_dma(info->dma_level);
4163 free_dma(info->dma_level);
4164 info->dma_requested = false;
4165 }
4166 mgsl_free_dma_buffers(info);
4167 mgsl_free_intermediate_rxbuffer_memory(info);
4168 mgsl_free_intermediate_txbuffer_memory(info);
4169
4170 if ( info->io_addr_requested ) {
4171 release_region(info->io_base,info->io_addr_size);
4172 info->io_addr_requested = false;
4173 }
4174 if ( info->shared_mem_requested ) {
4175 release_mem_region(info->phys_memory_base,0x40000);
4176 info->shared_mem_requested = false;
4177 }
4178 if ( info->lcr_mem_requested ) {
4179 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4180 info->lcr_mem_requested = false;
4181 }
4182 if (info->memory_base){
4183 iounmap(info->memory_base);
4184 info->memory_base = NULL;
4185 }
4186 if (info->lcr_base){
4187 iounmap(info->lcr_base - info->lcr_offset);
4188 info->lcr_base = NULL;
4189 }
4190
4191 if ( debug_level >= DEBUG_LEVEL_INFO )
4192 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4193 __FILE__,__LINE__,info->device_name );
4194
4195 } /* end of mgsl_release_resources() */
4196
4197 /* mgsl_add_device()
4198 *
4199 * Add the specified device instance data structure to the
4200 * global linked list of devices and increment the device count.
4201 *
4202 * Arguments: info pointer to device instance data
4203 * Return Value: None
4204 */
4205 static void mgsl_add_device( struct mgsl_struct *info )
4206 {
4207 info->next_device = NULL;
4208 info->line = mgsl_device_count;
4209 sprintf(info->device_name,"ttySL%d",info->line);
4210
4211 if (info->line < MAX_TOTAL_DEVICES) {
4212 if (maxframe[info->line])
4213 info->max_frame_size = maxframe[info->line];
4214
4215 if (txdmabufs[info->line]) {
4216 info->num_tx_dma_buffers = txdmabufs[info->line];
4217 if (info->num_tx_dma_buffers < 1)
4218 info->num_tx_dma_buffers = 1;
4219 }
4220
4221 if (txholdbufs[info->line]) {
4222 info->num_tx_holding_buffers = txholdbufs[info->line];
4223 if (info->num_tx_holding_buffers < 1)
4224 info->num_tx_holding_buffers = 1;
4225 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4226 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4227 }
4228 }
4229
4230 mgsl_device_count++;
4231
4232 if ( !mgsl_device_list )
4233 mgsl_device_list = info;
4234 else {
4235 struct mgsl_struct *current_dev = mgsl_device_list;
4236 while( current_dev->next_device )
4237 current_dev = current_dev->next_device;
4238 current_dev->next_device = info;
4239 }
4240
4241 if ( info->max_frame_size < 4096 )
4242 info->max_frame_size = 4096;
4243 else if ( info->max_frame_size > 65535 )
4244 info->max_frame_size = 65535;
4245
4246 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4247 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4248 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4249 info->phys_memory_base, info->phys_lcr_base,
4250 info->max_frame_size );
4251 } else {
4252 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4253 info->device_name, info->io_base, info->irq_level, info->dma_level,
4254 info->max_frame_size );
4255 }
4256
4257 #if SYNCLINK_GENERIC_HDLC
4258 hdlcdev_init(info);
4259 #endif
4260
4261 } /* end of mgsl_add_device() */
4262
4263 static const struct tty_port_operations mgsl_port_ops = {
4264 .carrier_raised = carrier_raised,
4265 .dtr_rts = dtr_rts,
4266 };
4267
4268
4269 /* mgsl_allocate_device()
4270 *
4271 * Allocate and initialize a device instance structure
4272 *
4273 * Arguments: none
4274 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4275 */
4276 static struct mgsl_struct* mgsl_allocate_device(void)
4277 {
4278 struct mgsl_struct *info;
4279
4280 info = kzalloc(sizeof(struct mgsl_struct),
4281 GFP_KERNEL);
4282
4283 if (!info) {
4284 printk("Error can't allocate device instance data\n");
4285 } else {
4286 tty_port_init(&info->port);
4287 info->port.ops = &mgsl_port_ops;
4288 info->magic = MGSL_MAGIC;
4289 INIT_WORK(&info->task, mgsl_bh_handler);
4290 info->max_frame_size = 4096;
4291 info->port.close_delay = 5*HZ/10;
4292 info->port.closing_wait = 30*HZ;
4293 init_waitqueue_head(&info->status_event_wait_q);
4294 init_waitqueue_head(&info->event_wait_q);
4295 spin_lock_init(&info->irq_spinlock);
4296 spin_lock_init(&info->netlock);
4297 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4298 info->idle_mode = HDLC_TXIDLE_FLAGS;
4299 info->num_tx_dma_buffers = 1;
4300 info->num_tx_holding_buffers = 0;
4301 }
4302
4303 return info;
4304
4305 } /* end of mgsl_allocate_device()*/
4306
4307 static const struct tty_operations mgsl_ops = {
4308 .open = mgsl_open,
4309 .close = mgsl_close,
4310 .write = mgsl_write,
4311 .put_char = mgsl_put_char,
4312 .flush_chars = mgsl_flush_chars,
4313 .write_room = mgsl_write_room,
4314 .chars_in_buffer = mgsl_chars_in_buffer,
4315 .flush_buffer = mgsl_flush_buffer,
4316 .ioctl = mgsl_ioctl,
4317 .throttle = mgsl_throttle,
4318 .unthrottle = mgsl_unthrottle,
4319 .send_xchar = mgsl_send_xchar,
4320 .break_ctl = mgsl_break,
4321 .wait_until_sent = mgsl_wait_until_sent,
4322 .set_termios = mgsl_set_termios,
4323 .stop = mgsl_stop,
4324 .start = mgsl_start,
4325 .hangup = mgsl_hangup,
4326 .tiocmget = tiocmget,
4327 .tiocmset = tiocmset,
4328 .proc_fops = &mgsl_proc_fops,
4329 };
4330
4331 /*
4332 * perform tty device initialization
4333 */
4334 static int mgsl_init_tty(void)
4335 {
4336 int rc;
4337
4338 serial_driver = alloc_tty_driver(128);
4339 if (!serial_driver)
4340 return -ENOMEM;
4341
4342 serial_driver->owner = THIS_MODULE;
4343 serial_driver->driver_name = "synclink";
4344 serial_driver->name = "ttySL";
4345 serial_driver->major = ttymajor;
4346 serial_driver->minor_start = 64;
4347 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4348 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4349 serial_driver->init_termios = tty_std_termios;
4350 serial_driver->init_termios.c_cflag =
4351 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4352 serial_driver->init_termios.c_ispeed = 9600;
4353 serial_driver->init_termios.c_ospeed = 9600;
4354 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4355 tty_set_operations(serial_driver, &mgsl_ops);
4356 if ((rc = tty_register_driver(serial_driver)) < 0) {
4357 printk("%s(%d):Couldn't register serial driver\n",
4358 __FILE__,__LINE__);
4359 put_tty_driver(serial_driver);
4360 serial_driver = NULL;
4361 return rc;
4362 }
4363
4364 printk("%s %s, tty major#%d\n",
4365 driver_name, driver_version,
4366 serial_driver->major);
4367 return 0;
4368 }
4369
4370 /* enumerate user specified ISA adapters
4371 */
4372 static void mgsl_enum_isa_devices(void)
4373 {
4374 struct mgsl_struct *info;
4375 int i;
4376
4377 /* Check for user specified ISA devices */
4378
4379 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4380 if ( debug_level >= DEBUG_LEVEL_INFO )
4381 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4382 io[i], irq[i], dma[i] );
4383
4384 info = mgsl_allocate_device();
4385 if ( !info ) {
4386 /* error allocating device instance data */
4387 if ( debug_level >= DEBUG_LEVEL_ERROR )
4388 printk( "can't allocate device instance data.\n");
4389 continue;
4390 }
4391
4392 /* Copy user configuration info to device instance data */
4393 info->io_base = (unsigned int)io[i];
4394 info->irq_level = (unsigned int)irq[i];
4395 info->irq_level = irq_canonicalize(info->irq_level);
4396 info->dma_level = (unsigned int)dma[i];
4397 info->bus_type = MGSL_BUS_TYPE_ISA;
4398 info->io_addr_size = 16;
4399 info->irq_flags = 0;
4400
4401 mgsl_add_device( info );
4402 }
4403 }
4404
4405 static void synclink_cleanup(void)
4406 {
4407 int rc;
4408 struct mgsl_struct *info;
4409 struct mgsl_struct *tmp;
4410
4411 printk("Unloading %s: %s\n", driver_name, driver_version);
4412
4413 if (serial_driver) {
4414 if ((rc = tty_unregister_driver(serial_driver)))
4415 printk("%s(%d) failed to unregister tty driver err=%d\n",
4416 __FILE__,__LINE__,rc);
4417 put_tty_driver(serial_driver);
4418 }
4419
4420 info = mgsl_device_list;
4421 while(info) {
4422 #if SYNCLINK_GENERIC_HDLC
4423 hdlcdev_exit(info);
4424 #endif
4425 mgsl_release_resources(info);
4426 tmp = info;
4427 info = info->next_device;
4428 kfree(tmp);
4429 }
4430
4431 if (pci_registered)
4432 pci_unregister_driver(&synclink_pci_driver);
4433 }
4434
4435 static int __init synclink_init(void)
4436 {
4437 int rc;
4438
4439 if (break_on_load) {
4440 mgsl_get_text_ptr();
4441 BREAKPOINT();
4442 }
4443
4444 printk("%s %s\n", driver_name, driver_version);
4445
4446 mgsl_enum_isa_devices();
4447 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4448 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4449 else
4450 pci_registered = true;
4451
4452 if ((rc = mgsl_init_tty()) < 0)
4453 goto error;
4454
4455 return 0;
4456
4457 error:
4458 synclink_cleanup();
4459 return rc;
4460 }
4461
4462 static void __exit synclink_exit(void)
4463 {
4464 synclink_cleanup();
4465 }
4466
4467 module_init(synclink_init);
4468 module_exit(synclink_exit);
4469
4470 /*
4471 * usc_RTCmd()
4472 *
4473 * Issue a USC Receive/Transmit command to the
4474 * Channel Command/Address Register (CCAR).
4475 *
4476 * Notes:
4477 *
4478 * The command is encoded in the most significant 5 bits <15..11>
4479 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4480 * and Bits <6..0> must be written as zeros.
4481 *
4482 * Arguments:
4483 *
4484 * info pointer to device information structure
4485 * Cmd command mask (use symbolic macros)
4486 *
4487 * Return Value:
4488 *
4489 * None
4490 */
4491 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4492 {
4493 /* output command to CCAR in bits <15..11> */
4494 /* preserve bits <10..7>, bits <6..0> must be zero */
4495
4496 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4497
4498 /* Read to flush write to CCAR */
4499 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4500 inw( info->io_base + CCAR );
4501
4502 } /* end of usc_RTCmd() */
4503
4504 /*
4505 * usc_DmaCmd()
4506 *
4507 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4508 *
4509 * Arguments:
4510 *
4511 * info pointer to device information structure
4512 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4513 *
4514 * Return Value:
4515 *
4516 * None
4517 */
4518 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4519 {
4520 /* write command mask to DCAR */
4521 outw( Cmd + info->mbre_bit, info->io_base );
4522
4523 /* Read to flush write to DCAR */
4524 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4525 inw( info->io_base );
4526
4527 } /* end of usc_DmaCmd() */
4528
4529 /*
4530 * usc_OutDmaReg()
4531 *
4532 * Write a 16-bit value to a USC DMA register
4533 *
4534 * Arguments:
4535 *
4536 * info pointer to device info structure
4537 * RegAddr register address (number) for write
4538 * RegValue 16-bit value to write to register
4539 *
4540 * Return Value:
4541 *
4542 * None
4543 *
4544 */
4545 static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4546 {
4547 /* Note: The DCAR is located at the adapter base address */
4548 /* Note: must preserve state of BIT8 in DCAR */
4549
4550 outw( RegAddr + info->mbre_bit, info->io_base );
4551 outw( RegValue, info->io_base );
4552
4553 /* Read to flush write to DCAR */
4554 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4555 inw( info->io_base );
4556
4557 } /* end of usc_OutDmaReg() */
4558
4559 /*
4560 * usc_InDmaReg()
4561 *
4562 * Read a 16-bit value from a DMA register
4563 *
4564 * Arguments:
4565 *
4566 * info pointer to device info structure
4567 * RegAddr register address (number) to read from
4568 *
4569 * Return Value:
4570 *
4571 * The 16-bit value read from register
4572 *
4573 */
4574 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4575 {
4576 /* Note: The DCAR is located at the adapter base address */
4577 /* Note: must preserve state of BIT8 in DCAR */
4578
4579 outw( RegAddr + info->mbre_bit, info->io_base );
4580 return inw( info->io_base );
4581
4582 } /* end of usc_InDmaReg() */
4583
4584 /*
4585 *
4586 * usc_OutReg()
4587 *
4588 * Write a 16-bit value to a USC serial channel register
4589 *
4590 * Arguments:
4591 *
4592 * info pointer to device info structure
4593 * RegAddr register address (number) to write to
4594 * RegValue 16-bit value to write to register
4595 *
4596 * Return Value:
4597 *
4598 * None
4599 *
4600 */
4601 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4602 {
4603 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4604 outw( RegValue, info->io_base + CCAR );
4605
4606 /* Read to flush write to CCAR */
4607 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4608 inw( info->io_base + CCAR );
4609
4610 } /* end of usc_OutReg() */
4611
4612 /*
4613 * usc_InReg()
4614 *
4615 * Reads a 16-bit value from a USC serial channel register
4616 *
4617 * Arguments:
4618 *
4619 * info pointer to device extension
4620 * RegAddr register address (number) to read from
4621 *
4622 * Return Value:
4623 *
4624 * 16-bit value read from register
4625 */
4626 static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4627 {
4628 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4629 return inw( info->io_base + CCAR );
4630
4631 } /* end of usc_InReg() */
4632
4633 /* usc_set_sdlc_mode()
4634 *
4635 * Set up the adapter for SDLC DMA communications.
4636 *
4637 * Arguments: info pointer to device instance data
4638 * Return Value: NONE
4639 */
4640 static void usc_set_sdlc_mode( struct mgsl_struct *info )
4641 {
4642 u16 RegValue;
4643 bool PreSL1660;
4644
4645 /*
4646 * determine if the IUSC on the adapter is pre-SL1660. If
4647 * not, take advantage of the UnderWait feature of more
4648 * modern chips. If an underrun occurs and this bit is set,
4649 * the transmitter will idle the programmed idle pattern
4650 * until the driver has time to service the underrun. Otherwise,
4651 * the dma controller may get the cycles previously requested
4652 * and begin transmitting queued tx data.
4653 */
4654 usc_OutReg(info,TMCR,0x1f);
4655 RegValue=usc_InReg(info,TMDR);
4656 PreSL1660 = (RegValue == IUSC_PRE_SL1660);
4657
4658 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4659 {
4660 /*
4661 ** Channel Mode Register (CMR)
4662 **
4663 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4664 ** <13> 0 0 = Transmit Disabled (initially)
4665 ** <12> 0 1 = Consecutive Idles share common 0
4666 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4667 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4668 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4669 **
4670 ** 1000 1110 0000 0110 = 0x8e06
4671 */
4672 RegValue = 0x8e06;
4673
4674 /*--------------------------------------------------
4675 * ignore user options for UnderRun Actions and
4676 * preambles
4677 *--------------------------------------------------*/
4678 }
4679 else
4680 {
4681 /* Channel mode Register (CMR)
4682 *
4683 * <15..14> 00 Tx Sub modes, Underrun Action
4684 * <13> 0 1 = Send Preamble before opening flag
4685 * <12> 0 1 = Consecutive Idles share common 0
4686 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4687 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4688 * <3..0> 0110 Receiver mode = HDLC/SDLC
4689 *
4690 * 0000 0110 0000 0110 = 0x0606
4691 */
4692 if (info->params.mode == MGSL_MODE_RAW) {
4693 RegValue = 0x0001; /* Set Receive mode = external sync */
4694
4695 usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
4696 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4697
4698 /*
4699 * TxSubMode:
4700 * CMR <15> 0 Don't send CRC on Tx Underrun
4701 * CMR <14> x undefined
4702 * CMR <13> 0 Send preamble before openning sync
4703 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4704 *
4705 * TxMode:
4706 * CMR <11-8) 0100 MonoSync
4707 *
4708 * 0x00 0100 xxxx xxxx 04xx
4709 */
4710 RegValue |= 0x0400;
4711 }
4712 else {
4713
4714 RegValue = 0x0606;
4715
4716 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4717 RegValue |= BIT14;
4718 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4719 RegValue |= BIT15;
4720 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4721 RegValue |= BIT15 + BIT14;
4722 }
4723
4724 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4725 RegValue |= BIT13;
4726 }
4727
4728 if ( info->params.mode == MGSL_MODE_HDLC &&
4729 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4730 RegValue |= BIT12;
4731
4732 if ( info->params.addr_filter != 0xff )
4733 {
4734 /* set up receive address filtering */
4735 usc_OutReg( info, RSR, info->params.addr_filter );
4736 RegValue |= BIT4;
4737 }
4738
4739 usc_OutReg( info, CMR, RegValue );
4740 info->cmr_value = RegValue;
4741
4742 /* Receiver mode Register (RMR)
4743 *
4744 * <15..13> 000 encoding
4745 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4746 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4747 * <9> 0 1 = Include Receive chars in CRC
4748 * <8> 1 1 = Use Abort/PE bit as abort indicator
4749 * <7..6> 00 Even parity
4750 * <5> 0 parity disabled
4751 * <4..2> 000 Receive Char Length = 8 bits
4752 * <1..0> 00 Disable Receiver
4753 *
4754 * 0000 0101 0000 0000 = 0x0500
4755 */
4756
4757 RegValue = 0x0500;
4758
4759 switch ( info->params.encoding ) {
4760 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4761 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4762 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4763 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4764 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4765 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4766 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4767 }
4768
4769 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4770 RegValue |= BIT9;
4771 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4772 RegValue |= ( BIT12 | BIT10 | BIT9 );
4773
4774 usc_OutReg( info, RMR, RegValue );
4775
4776 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4777 /* When an opening flag of an SDLC frame is recognized the */
4778 /* Receive Character count (RCC) is loaded with the value in */
4779 /* RCLR. The RCC is decremented for each received byte. The */
4780 /* value of RCC is stored after the closing flag of the frame */
4781 /* allowing the frame size to be computed. */
4782
4783 usc_OutReg( info, RCLR, RCLRVALUE );
4784
4785 usc_RCmd( info, RCmd_SelectRicrdma_level );
4786
4787 /* Receive Interrupt Control Register (RICR)
4788 *
4789 * <15..8> ? RxFIFO DMA Request Level
4790 * <7> 0 Exited Hunt IA (Interrupt Arm)
4791 * <6> 0 Idle Received IA
4792 * <5> 0 Break/Abort IA
4793 * <4> 0 Rx Bound IA
4794 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4795 * <2> 0 Abort/PE IA
4796 * <1> 1 Rx Overrun IA
4797 * <0> 0 Select TC0 value for readback
4798 *
4799 * 0000 0000 0000 1000 = 0x000a
4800 */
4801
4802 /* Carry over the Exit Hunt and Idle Received bits */
4803 /* in case they have been armed by usc_ArmEvents. */
4804
4805 RegValue = usc_InReg( info, RICR ) & 0xc0;
4806
4807 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4808 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4809 else
4810 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4811
4812 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4813
4814 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4815 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4816
4817 /* Transmit mode Register (TMR)
4818 *
4819 * <15..13> 000 encoding
4820 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4821 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4822 * <9> 0 1 = Tx CRC Enabled
4823 * <8> 0 1 = Append CRC to end of transmit frame
4824 * <7..6> 00 Transmit parity Even
4825 * <5> 0 Transmit parity Disabled
4826 * <4..2> 000 Tx Char Length = 8 bits
4827 * <1..0> 00 Disable Transmitter
4828 *
4829 * 0000 0100 0000 0000 = 0x0400
4830 */
4831
4832 RegValue = 0x0400;
4833
4834 switch ( info->params.encoding ) {
4835 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4836 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4837 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4838 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4839 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4840 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4841 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4842 }
4843
4844 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4845 RegValue |= BIT9 + BIT8;
4846 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4847 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4848
4849 usc_OutReg( info, TMR, RegValue );
4850
4851 usc_set_txidle( info );
4852
4853
4854 usc_TCmd( info, TCmd_SelectTicrdma_level );
4855
4856 /* Transmit Interrupt Control Register (TICR)
4857 *
4858 * <15..8> ? Transmit FIFO DMA Level
4859 * <7> 0 Present IA (Interrupt Arm)
4860 * <6> 0 Idle Sent IA
4861 * <5> 1 Abort Sent IA
4862 * <4> 1 EOF/EOM Sent IA
4863 * <3> 0 CRC Sent IA
4864 * <2> 1 1 = Wait for SW Trigger to Start Frame
4865 * <1> 1 Tx Underrun IA
4866 * <0> 0 TC0 constant on read back
4867 *
4868 * 0000 0000 0011 0110 = 0x0036
4869 */
4870
4871 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4872 usc_OutReg( info, TICR, 0x0736 );
4873 else
4874 usc_OutReg( info, TICR, 0x1436 );
4875
4876 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4877 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4878
4879 /*
4880 ** Transmit Command/Status Register (TCSR)
4881 **
4882 ** <15..12> 0000 TCmd
4883 ** <11> 0/1 UnderWait
4884 ** <10..08> 000 TxIdle
4885 ** <7> x PreSent
4886 ** <6> x IdleSent
4887 ** <5> x AbortSent
4888 ** <4> x EOF/EOM Sent
4889 ** <3> x CRC Sent
4890 ** <2> x All Sent
4891 ** <1> x TxUnder
4892 ** <0> x TxEmpty
4893 **
4894 ** 0000 0000 0000 0000 = 0x0000
4895 */
4896 info->tcsr_value = 0;
4897
4898 if ( !PreSL1660 )
4899 info->tcsr_value |= TCSR_UNDERWAIT;
4900
4901 usc_OutReg( info, TCSR, info->tcsr_value );
4902
4903 /* Clock mode Control Register (CMCR)
4904 *
4905 * <15..14> 00 counter 1 Source = Disabled
4906 * <13..12> 00 counter 0 Source = Disabled
4907 * <11..10> 11 BRG1 Input is TxC Pin
4908 * <9..8> 11 BRG0 Input is TxC Pin
4909 * <7..6> 01 DPLL Input is BRG1 Output
4910 * <5..3> XXX TxCLK comes from Port 0
4911 * <2..0> XXX RxCLK comes from Port 1
4912 *
4913 * 0000 1111 0111 0111 = 0x0f77
4914 */
4915
4916 RegValue = 0x0f40;
4917
4918 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4919 RegValue |= 0x0003; /* RxCLK from DPLL */
4920 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4921 RegValue |= 0x0004; /* RxCLK from BRG0 */
4922 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4923 RegValue |= 0x0006; /* RxCLK from TXC Input */
4924 else
4925 RegValue |= 0x0007; /* RxCLK from Port1 */
4926
4927 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4928 RegValue |= 0x0018; /* TxCLK from DPLL */
4929 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4930 RegValue |= 0x0020; /* TxCLK from BRG0 */
4931 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4932 RegValue |= 0x0038; /* RxCLK from TXC Input */
4933 else
4934 RegValue |= 0x0030; /* TxCLK from Port0 */
4935
4936 usc_OutReg( info, CMCR, RegValue );
4937
4938
4939 /* Hardware Configuration Register (HCR)
4940 *
4941 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4942 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4943 * <12> 0 CVOK:0=report code violation in biphase
4944 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4945 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4946 * <7..6> 00 reserved
4947 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4948 * <4> X BRG1 Enable
4949 * <3..2> 00 reserved
4950 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4951 * <0> 0 BRG0 Enable
4952 */
4953
4954 RegValue = 0x0000;
4955
4956 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
4957 u32 XtalSpeed;
4958 u32 DpllDivisor;
4959 u16 Tc;
4960
4961 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
4962 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4963
4964 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4965 XtalSpeed = 11059200;
4966 else
4967 XtalSpeed = 14745600;
4968
4969 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4970 DpllDivisor = 16;
4971 RegValue |= BIT10;
4972 }
4973 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4974 DpllDivisor = 8;
4975 RegValue |= BIT11;
4976 }
4977 else
4978 DpllDivisor = 32;
4979
4980 /* Tc = (Xtal/Speed) - 1 */
4981 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
4982 /* then rounding up gives a more precise time constant. Instead */
4983 /* of rounding up and then subtracting 1 we just don't subtract */
4984 /* the one in this case. */
4985
4986 /*--------------------------------------------------
4987 * ejz: for DPLL mode, application should use the
4988 * same clock speed as the partner system, even
4989 * though clocking is derived from the input RxData.
4990 * In case the user uses a 0 for the clock speed,
4991 * default to 0xffffffff and don't try to divide by
4992 * zero
4993 *--------------------------------------------------*/
4994 if ( info->params.clock_speed )
4995 {
4996 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
4997 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
4998 / info->params.clock_speed) )
4999 Tc--;
5000 }
5001 else
5002 Tc = -1;
5003
5004
5005 /* Write 16-bit Time Constant for BRG1 */
5006 usc_OutReg( info, TC1R, Tc );
5007
5008 RegValue |= BIT4; /* enable BRG1 */
5009
5010 switch ( info->params.encoding ) {
5011 case HDLC_ENCODING_NRZ:
5012 case HDLC_ENCODING_NRZB:
5013 case HDLC_ENCODING_NRZI_MARK:
5014 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5015 case HDLC_ENCODING_BIPHASE_MARK:
5016 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5017 case HDLC_ENCODING_BIPHASE_LEVEL:
5018 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5019 }
5020 }
5021
5022 usc_OutReg( info, HCR, RegValue );
5023
5024
5025 /* Channel Control/status Register (CCSR)
5026 *
5027 * <15> X RCC FIFO Overflow status (RO)
5028 * <14> X RCC FIFO Not Empty status (RO)
5029 * <13> 0 1 = Clear RCC FIFO (WO)
5030 * <12> X DPLL Sync (RW)
5031 * <11> X DPLL 2 Missed Clocks status (RO)
5032 * <10> X DPLL 1 Missed Clock status (RO)
5033 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5034 * <7> X SDLC Loop On status (RO)
5035 * <6> X SDLC Loop Send status (RO)
5036 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5037 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5038 * <1..0> 00 reserved
5039 *
5040 * 0000 0000 0010 0000 = 0x0020
5041 */
5042
5043 usc_OutReg( info, CCSR, 0x1020 );
5044
5045
5046 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5047 usc_OutReg( info, SICR,
5048 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5049 }
5050
5051
5052 /* enable Master Interrupt Enable bit (MIE) */
5053 usc_EnableMasterIrqBit( info );
5054
5055 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5056 TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5057
5058 /* arm RCC underflow interrupt */
5059 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5060 usc_EnableInterrupts(info, MISC);
5061
5062 info->mbre_bit = 0;
5063 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5064 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5065 info->mbre_bit = BIT8;
5066 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5067
5068 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5069 /* Enable DMAEN (Port 7, Bit 14) */
5070 /* This connects the DMA request signal to the ISA bus */
5071 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5072 }
5073
5074 /* DMA Control Register (DCR)
5075 *
5076 * <15..14> 10 Priority mode = Alternating Tx/Rx
5077 * 01 Rx has priority
5078 * 00 Tx has priority
5079 *
5080 * <13> 1 Enable Priority Preempt per DCR<15..14>
5081 * (WARNING DCR<11..10> must be 00 when this is 1)
5082 * 0 Choose activate channel per DCR<11..10>
5083 *
5084 * <12> 0 Little Endian for Array/List
5085 * <11..10> 00 Both Channels can use each bus grant
5086 * <9..6> 0000 reserved
5087 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5088 * <4> 0 1 = drive D/C and S/D pins
5089 * <3> 1 1 = Add one wait state to all DMA cycles.
5090 * <2> 0 1 = Strobe /UAS on every transfer.
5091 * <1..0> 11 Addr incrementing only affects LS24 bits
5092 *
5093 * 0110 0000 0000 1011 = 0x600b
5094 */
5095
5096 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5097 /* PCI adapter does not need DMA wait state */
5098 usc_OutDmaReg( info, DCR, 0xa00b );
5099 }
5100 else
5101 usc_OutDmaReg( info, DCR, 0x800b );
5102
5103
5104 /* Receive DMA mode Register (RDMR)
5105 *
5106 * <15..14> 11 DMA mode = Linked List Buffer mode
5107 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5108 * <12> 1 Clear count of List Entry after fetching
5109 * <11..10> 00 Address mode = Increment
5110 * <9> 1 Terminate Buffer on RxBound
5111 * <8> 0 Bus Width = 16bits
5112 * <7..0> ? status Bits (write as 0s)
5113 *
5114 * 1111 0010 0000 0000 = 0xf200
5115 */
5116
5117 usc_OutDmaReg( info, RDMR, 0xf200 );
5118
5119
5120 /* Transmit DMA mode Register (TDMR)
5121 *
5122 * <15..14> 11 DMA mode = Linked List Buffer mode
5123 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5124 * <12> 1 Clear count of List Entry after fetching
5125 * <11..10> 00 Address mode = Increment
5126 * <9> 1 Terminate Buffer on end of frame
5127 * <8> 0 Bus Width = 16bits
5128 * <7..0> ? status Bits (Read Only so write as 0)
5129 *
5130 * 1111 0010 0000 0000 = 0xf200
5131 */
5132
5133 usc_OutDmaReg( info, TDMR, 0xf200 );
5134
5135
5136 /* DMA Interrupt Control Register (DICR)
5137 *
5138 * <15> 1 DMA Interrupt Enable
5139 * <14> 0 1 = Disable IEO from USC
5140 * <13> 0 1 = Don't provide vector during IntAck
5141 * <12> 1 1 = Include status in Vector
5142 * <10..2> 0 reserved, Must be 0s
5143 * <1> 0 1 = Rx DMA Interrupt Enabled
5144 * <0> 0 1 = Tx DMA Interrupt Enabled
5145 *
5146 * 1001 0000 0000 0000 = 0x9000
5147 */
5148
5149 usc_OutDmaReg( info, DICR, 0x9000 );
5150
5151 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5152 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5153 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5154
5155 /* Channel Control Register (CCR)
5156 *
5157 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5158 * <13> 0 Trigger Tx on SW Command Disabled
5159 * <12> 0 Flag Preamble Disabled
5160 * <11..10> 00 Preamble Length
5161 * <9..8> 00 Preamble Pattern
5162 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5163 * <5> 0 Trigger Rx on SW Command Disabled
5164 * <4..0> 0 reserved
5165 *
5166 * 1000 0000 1000 0000 = 0x8080
5167 */
5168
5169 RegValue = 0x8080;
5170
5171 switch ( info->params.preamble_length ) {
5172 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5173 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5174 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5175 }
5176
5177 switch ( info->params.preamble ) {
5178 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5179 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5180 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5181 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5182 }
5183
5184 usc_OutReg( info, CCR, RegValue );
5185
5186
5187 /*
5188 * Burst/Dwell Control Register
5189 *
5190 * <15..8> 0x20 Maximum number of transfers per bus grant
5191 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5192 */
5193
5194 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5195 /* don't limit bus occupancy on PCI adapter */
5196 usc_OutDmaReg( info, BDCR, 0x0000 );
5197 }
5198 else
5199 usc_OutDmaReg( info, BDCR, 0x2000 );
5200
5201 usc_stop_transmitter(info);
5202 usc_stop_receiver(info);
5203
5204 } /* end of usc_set_sdlc_mode() */
5205
5206 /* usc_enable_loopback()
5207 *
5208 * Set the 16C32 for internal loopback mode.
5209 * The TxCLK and RxCLK signals are generated from the BRG0 and
5210 * the TxD is looped back to the RxD internally.
5211 *
5212 * Arguments: info pointer to device instance data
5213 * enable 1 = enable loopback, 0 = disable
5214 * Return Value: None
5215 */
5216 static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5217 {
5218 if (enable) {
5219 /* blank external TXD output */
5220 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5221
5222 /* Clock mode Control Register (CMCR)
5223 *
5224 * <15..14> 00 counter 1 Disabled
5225 * <13..12> 00 counter 0 Disabled
5226 * <11..10> 11 BRG1 Input is TxC Pin
5227 * <9..8> 11 BRG0 Input is TxC Pin
5228 * <7..6> 01 DPLL Input is BRG1 Output
5229 * <5..3> 100 TxCLK comes from BRG0
5230 * <2..0> 100 RxCLK comes from BRG0
5231 *
5232 * 0000 1111 0110 0100 = 0x0f64
5233 */
5234
5235 usc_OutReg( info, CMCR, 0x0f64 );
5236
5237 /* Write 16-bit Time Constant for BRG0 */
5238 /* use clock speed if available, otherwise use 8 for diagnostics */
5239 if (info->params.clock_speed) {
5240 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5241 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5242 else
5243 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5244 } else
5245 usc_OutReg(info, TC0R, (u16)8);
5246
5247 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5248 mode = Continuous Set Bit 0 to enable BRG0. */
5249 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5250
5251 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5252 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5253
5254 /* set Internal Data loopback mode */
5255 info->loopback_bits = 0x300;
5256 outw( 0x0300, info->io_base + CCAR );
5257 } else {
5258 /* enable external TXD output */
5259 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5260
5261 /* clear Internal Data loopback mode */
5262 info->loopback_bits = 0;
5263 outw( 0,info->io_base + CCAR );
5264 }
5265
5266 } /* end of usc_enable_loopback() */
5267
5268 /* usc_enable_aux_clock()
5269 *
5270 * Enabled the AUX clock output at the specified frequency.
5271 *
5272 * Arguments:
5273 *
5274 * info pointer to device extension
5275 * data_rate data rate of clock in bits per second
5276 * A data rate of 0 disables the AUX clock.
5277 *
5278 * Return Value: None
5279 */
5280 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5281 {
5282 u32 XtalSpeed;
5283 u16 Tc;
5284
5285 if ( data_rate ) {
5286 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5287 XtalSpeed = 11059200;
5288 else
5289 XtalSpeed = 14745600;
5290
5291
5292 /* Tc = (Xtal/Speed) - 1 */
5293 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5294 /* then rounding up gives a more precise time constant. Instead */
5295 /* of rounding up and then subtracting 1 we just don't subtract */
5296 /* the one in this case. */
5297
5298
5299 Tc = (u16)(XtalSpeed/data_rate);
5300 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5301 Tc--;
5302
5303 /* Write 16-bit Time Constant for BRG0 */
5304 usc_OutReg( info, TC0R, Tc );
5305
5306 /*
5307 * Hardware Configuration Register (HCR)
5308 * Clear Bit 1, BRG0 mode = Continuous
5309 * Set Bit 0 to enable BRG0.
5310 */
5311
5312 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5313
5314 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5315 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5316 } else {
5317 /* data rate == 0 so turn off BRG0 */
5318 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5319 }
5320
5321 } /* end of usc_enable_aux_clock() */
5322
5323 /*
5324 *
5325 * usc_process_rxoverrun_sync()
5326 *
5327 * This function processes a receive overrun by resetting the
5328 * receive DMA buffers and issuing a Purge Rx FIFO command
5329 * to allow the receiver to continue receiving.
5330 *
5331 * Arguments:
5332 *
5333 * info pointer to device extension
5334 *
5335 * Return Value: None
5336 */
5337 static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5338 {
5339 int start_index;
5340 int end_index;
5341 int frame_start_index;
5342 bool start_of_frame_found = false;
5343 bool end_of_frame_found = false;
5344 bool reprogram_dma = false;
5345
5346 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5347 u32 phys_addr;
5348
5349 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5350 usc_RCmd( info, RCmd_EnterHuntmode );
5351 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5352
5353 /* CurrentRxBuffer points to the 1st buffer of the next */
5354 /* possibly available receive frame. */
5355
5356 frame_start_index = start_index = end_index = info->current_rx_buffer;
5357
5358 /* Search for an unfinished string of buffers. This means */
5359 /* that a receive frame started (at least one buffer with */
5360 /* count set to zero) but there is no terminiting buffer */
5361 /* (status set to non-zero). */
5362
5363 while( !buffer_list[end_index].count )
5364 {
5365 /* Count field has been reset to zero by 16C32. */
5366 /* This buffer is currently in use. */
5367
5368 if ( !start_of_frame_found )
5369 {
5370 start_of_frame_found = true;
5371 frame_start_index = end_index;
5372 end_of_frame_found = false;
5373 }
5374
5375 if ( buffer_list[end_index].status )
5376 {
5377 /* Status field has been set by 16C32. */
5378 /* This is the last buffer of a received frame. */
5379
5380 /* We want to leave the buffers for this frame intact. */
5381 /* Move on to next possible frame. */
5382
5383 start_of_frame_found = false;
5384 end_of_frame_found = true;
5385 }
5386
5387 /* advance to next buffer entry in linked list */
5388 end_index++;
5389 if ( end_index == info->rx_buffer_count )
5390 end_index = 0;
5391
5392 if ( start_index == end_index )
5393 {
5394 /* The entire list has been searched with all Counts == 0 and */
5395 /* all Status == 0. The receive buffers are */
5396 /* completely screwed, reset all receive buffers! */
5397 mgsl_reset_rx_dma_buffers( info );
5398 frame_start_index = 0;
5399 start_of_frame_found = false;
5400 reprogram_dma = true;
5401 break;
5402 }
5403 }
5404
5405 if ( start_of_frame_found && !end_of_frame_found )
5406 {
5407 /* There is an unfinished string of receive DMA buffers */
5408 /* as a result of the receiver overrun. */
5409
5410 /* Reset the buffers for the unfinished frame */
5411 /* and reprogram the receive DMA controller to start */
5412 /* at the 1st buffer of unfinished frame. */
5413
5414 start_index = frame_start_index;
5415
5416 do
5417 {
5418 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5419
5420 /* Adjust index for wrap around. */
5421 if ( start_index == info->rx_buffer_count )
5422 start_index = 0;
5423
5424 } while( start_index != end_index );
5425
5426 reprogram_dma = true;
5427 }
5428
5429 if ( reprogram_dma )
5430 {
5431 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5432 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5433 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5434
5435 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5436
5437 /* This empties the receive FIFO and loads the RCC with RCLR */
5438 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5439
5440 /* program 16C32 with physical address of 1st DMA buffer entry */
5441 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5442 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5443 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5444
5445 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5446 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5447 usc_EnableInterrupts( info, RECEIVE_STATUS );
5448
5449 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5450 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5451
5452 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5453 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5454 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5455 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5456 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5457 else
5458 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5459 }
5460 else
5461 {
5462 /* This empties the receive FIFO and loads the RCC with RCLR */
5463 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5464 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5465 }
5466
5467 } /* end of usc_process_rxoverrun_sync() */
5468
5469 /* usc_stop_receiver()
5470 *
5471 * Disable USC receiver
5472 *
5473 * Arguments: info pointer to device instance data
5474 * Return Value: None
5475 */
5476 static void usc_stop_receiver( struct mgsl_struct *info )
5477 {
5478 if (debug_level >= DEBUG_LEVEL_ISR)
5479 printk("%s(%d):usc_stop_receiver(%s)\n",
5480 __FILE__,__LINE__, info->device_name );
5481
5482 /* Disable receive DMA channel. */
5483 /* This also disables receive DMA channel interrupts */
5484 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5485
5486 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5487 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5488 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5489
5490 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5491
5492 /* This empties the receive FIFO and loads the RCC with RCLR */
5493 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5494 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5495
5496 info->rx_enabled = false;
5497 info->rx_overflow = false;
5498 info->rx_rcc_underrun = false;
5499
5500 } /* end of stop_receiver() */
5501
5502 /* usc_start_receiver()
5503 *
5504 * Enable the USC receiver
5505 *
5506 * Arguments: info pointer to device instance data
5507 * Return Value: None
5508 */
5509 static void usc_start_receiver( struct mgsl_struct *info )
5510 {
5511 u32 phys_addr;
5512
5513 if (debug_level >= DEBUG_LEVEL_ISR)
5514 printk("%s(%d):usc_start_receiver(%s)\n",
5515 __FILE__,__LINE__, info->device_name );
5516
5517 mgsl_reset_rx_dma_buffers( info );
5518 usc_stop_receiver( info );
5519
5520 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5521 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5522
5523 if ( info->params.mode == MGSL_MODE_HDLC ||
5524 info->params.mode == MGSL_MODE_RAW ) {
5525 /* DMA mode Transfers */
5526 /* Program the DMA controller. */
5527 /* Enable the DMA controller end of buffer interrupt. */
5528
5529 /* program 16C32 with physical address of 1st DMA buffer entry */
5530 phys_addr = info->rx_buffer_list[0].phys_entry;
5531 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5532 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5533
5534 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5535 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5536 usc_EnableInterrupts( info, RECEIVE_STATUS );
5537
5538 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5539 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5540
5541 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5542 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5543 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5544 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5545 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5546 else
5547 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5548 } else {
5549 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5550 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5551 usc_EnableInterrupts(info, RECEIVE_DATA);
5552
5553 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5554 usc_RCmd( info, RCmd_EnterHuntmode );
5555
5556 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5557 }
5558
5559 usc_OutReg( info, CCSR, 0x1020 );
5560
5561 info->rx_enabled = true;
5562
5563 } /* end of usc_start_receiver() */
5564
5565 /* usc_start_transmitter()
5566 *
5567 * Enable the USC transmitter and send a transmit frame if
5568 * one is loaded in the DMA buffers.
5569 *
5570 * Arguments: info pointer to device instance data
5571 * Return Value: None
5572 */
5573 static void usc_start_transmitter( struct mgsl_struct *info )
5574 {
5575 u32 phys_addr;
5576 unsigned int FrameSize;
5577
5578 if (debug_level >= DEBUG_LEVEL_ISR)
5579 printk("%s(%d):usc_start_transmitter(%s)\n",
5580 __FILE__,__LINE__, info->device_name );
5581
5582 if ( info->xmit_cnt ) {
5583
5584 /* If auto RTS enabled and RTS is inactive, then assert */
5585 /* RTS and set a flag indicating that the driver should */
5586 /* negate RTS when the transmission completes. */
5587
5588 info->drop_rts_on_tx_done = false;
5589
5590 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5591 usc_get_serial_signals( info );
5592 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5593 info->serial_signals |= SerialSignal_RTS;
5594 usc_set_serial_signals( info );
5595 info->drop_rts_on_tx_done = true;
5596 }
5597 }
5598
5599
5600 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5601 if ( !info->tx_active ) {
5602 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5603 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5604 usc_EnableInterrupts(info, TRANSMIT_DATA);
5605 usc_load_txfifo(info);
5606 }
5607 } else {
5608 /* Disable transmit DMA controller while programming. */
5609 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5610
5611 /* Transmit DMA buffer is loaded, so program USC */
5612 /* to send the frame contained in the buffers. */
5613
5614 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5615
5616 /* if operating in Raw sync mode, reset the rcc component
5617 * of the tx dma buffer entry, otherwise, the serial controller
5618 * will send a closing sync char after this count.
5619 */
5620 if ( info->params.mode == MGSL_MODE_RAW )
5621 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5622
5623 /* Program the Transmit Character Length Register (TCLR) */
5624 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5625 usc_OutReg( info, TCLR, (u16)FrameSize );
5626
5627 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5628
5629 /* Program the address of the 1st DMA Buffer Entry in linked list */
5630 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5631 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5632 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5633
5634 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5635 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5636 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5637
5638 if ( info->params.mode == MGSL_MODE_RAW &&
5639 info->num_tx_dma_buffers > 1 ) {
5640 /* When running external sync mode, attempt to 'stream' transmit */
5641 /* by filling tx dma buffers as they become available. To do this */
5642 /* we need to enable Tx DMA EOB Status interrupts : */
5643 /* */
5644 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5645 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5646
5647 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5648 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5649 }
5650
5651 /* Initialize Transmit DMA Channel */
5652 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5653
5654 usc_TCmd( info, TCmd_SendFrame );
5655
5656 mod_timer(&info->tx_timer, jiffies +
5657 msecs_to_jiffies(5000));
5658 }
5659 info->tx_active = true;
5660 }
5661
5662 if ( !info->tx_enabled ) {
5663 info->tx_enabled = true;
5664 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5665 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5666 else
5667 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5668 }
5669
5670 } /* end of usc_start_transmitter() */
5671
5672 /* usc_stop_transmitter()
5673 *
5674 * Stops the transmitter and DMA
5675 *
5676 * Arguments: info pointer to device isntance data
5677 * Return Value: None
5678 */
5679 static void usc_stop_transmitter( struct mgsl_struct *info )
5680 {
5681 if (debug_level >= DEBUG_LEVEL_ISR)
5682 printk("%s(%d):usc_stop_transmitter(%s)\n",
5683 __FILE__,__LINE__, info->device_name );
5684
5685 del_timer(&info->tx_timer);
5686
5687 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5688 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5689 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5690
5691 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5692 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5693 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5694
5695 info->tx_enabled = false;
5696 info->tx_active = false;
5697
5698 } /* end of usc_stop_transmitter() */
5699
5700 /* usc_load_txfifo()
5701 *
5702 * Fill the transmit FIFO until the FIFO is full or
5703 * there is no more data to load.
5704 *
5705 * Arguments: info pointer to device extension (instance data)
5706 * Return Value: None
5707 */
5708 static void usc_load_txfifo( struct mgsl_struct *info )
5709 {
5710 int Fifocount;
5711 u8 TwoBytes[2];
5712
5713 if ( !info->xmit_cnt && !info->x_char )
5714 return;
5715
5716 /* Select transmit FIFO status readback in TICR */
5717 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5718
5719 /* load the Transmit FIFO until FIFOs full or all data sent */
5720
5721 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5722 /* there is more space in the transmit FIFO and */
5723 /* there is more data in transmit buffer */
5724
5725 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5726 /* write a 16-bit word from transmit buffer to 16C32 */
5727
5728 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5729 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5730 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5731 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5732
5733 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5734
5735 info->xmit_cnt -= 2;
5736 info->icount.tx += 2;
5737 } else {
5738 /* only 1 byte left to transmit or 1 FIFO slot left */
5739
5740 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5741 info->io_base + CCAR );
5742
5743 if (info->x_char) {
5744 /* transmit pending high priority char */
5745 outw( info->x_char,info->io_base + CCAR );
5746 info->x_char = 0;
5747 } else {
5748 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5749 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5750 info->xmit_cnt--;
5751 }
5752 info->icount.tx++;
5753 }
5754 }
5755
5756 } /* end of usc_load_txfifo() */
5757
5758 /* usc_reset()
5759 *
5760 * Reset the adapter to a known state and prepare it for further use.
5761 *
5762 * Arguments: info pointer to device instance data
5763 * Return Value: None
5764 */
5765 static void usc_reset( struct mgsl_struct *info )
5766 {
5767 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5768 int i;
5769 u32 readval;
5770
5771 /* Set BIT30 of Misc Control Register */
5772 /* (Local Control Register 0x50) to force reset of USC. */
5773
5774 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5775 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5776
5777 info->misc_ctrl_value |= BIT30;
5778 *MiscCtrl = info->misc_ctrl_value;
5779
5780 /*
5781 * Force at least 170ns delay before clearing
5782 * reset bit. Each read from LCR takes at least
5783 * 30ns so 10 times for 300ns to be safe.
5784 */
5785 for(i=0;i<10;i++)
5786 readval = *MiscCtrl;
5787
5788 info->misc_ctrl_value &= ~BIT30;
5789 *MiscCtrl = info->misc_ctrl_value;
5790
5791 *LCR0BRDR = BUS_DESCRIPTOR(
5792 1, // Write Strobe Hold (0-3)
5793 2, // Write Strobe Delay (0-3)
5794 2, // Read Strobe Delay (0-3)
5795 0, // NWDD (Write data-data) (0-3)
5796 4, // NWAD (Write Addr-data) (0-31)
5797 0, // NXDA (Read/Write Data-Addr) (0-3)
5798 0, // NRDD (Read Data-Data) (0-3)
5799 5 // NRAD (Read Addr-Data) (0-31)
5800 );
5801 } else {
5802 /* do HW reset */
5803 outb( 0,info->io_base + 8 );
5804 }
5805
5806 info->mbre_bit = 0;
5807 info->loopback_bits = 0;
5808 info->usc_idle_mode = 0;
5809
5810 /*
5811 * Program the Bus Configuration Register (BCR)
5812 *
5813 * <15> 0 Don't use separate address
5814 * <14..6> 0 reserved
5815 * <5..4> 00 IAckmode = Default, don't care
5816 * <3> 1 Bus Request Totem Pole output
5817 * <2> 1 Use 16 Bit data bus
5818 * <1> 0 IRQ Totem Pole output
5819 * <0> 0 Don't Shift Right Addr
5820 *
5821 * 0000 0000 0000 1100 = 0x000c
5822 *
5823 * By writing to io_base + SDPIN the Wait/Ack pin is
5824 * programmed to work as a Wait pin.
5825 */
5826
5827 outw( 0x000c,info->io_base + SDPIN );
5828
5829
5830 outw( 0,info->io_base );
5831 outw( 0,info->io_base + CCAR );
5832
5833 /* select little endian byte ordering */
5834 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5835
5836
5837 /* Port Control Register (PCR)
5838 *
5839 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5840 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5841 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5842 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5843 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5844 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5845 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5846 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5847 *
5848 * 1111 0000 1111 0101 = 0xf0f5
5849 */
5850
5851 usc_OutReg( info, PCR, 0xf0f5 );
5852
5853
5854 /*
5855 * Input/Output Control Register
5856 *
5857 * <15..14> 00 CTS is active low input
5858 * <13..12> 00 DCD is active low input
5859 * <11..10> 00 TxREQ pin is input (DSR)
5860 * <9..8> 00 RxREQ pin is input (RI)
5861 * <7..6> 00 TxD is output (Transmit Data)
5862 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5863 * <2..0> 100 RxC is Output (drive with BRG0)
5864 *
5865 * 0000 0000 0000 0100 = 0x0004
5866 */
5867
5868 usc_OutReg( info, IOCR, 0x0004 );
5869
5870 } /* end of usc_reset() */
5871
5872 /* usc_set_async_mode()
5873 *
5874 * Program adapter for asynchronous communications.
5875 *
5876 * Arguments: info pointer to device instance data
5877 * Return Value: None
5878 */
5879 static void usc_set_async_mode( struct mgsl_struct *info )
5880 {
5881 u16 RegValue;
5882
5883 /* disable interrupts while programming USC */
5884 usc_DisableMasterIrqBit( info );
5885
5886 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5887 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5888
5889 usc_loopback_frame( info );
5890
5891 /* Channel mode Register (CMR)
5892 *
5893 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5894 * <13..12> 00 00 = 16X Clock
5895 * <11..8> 0000 Transmitter mode = Asynchronous
5896 * <7..6> 00 reserved?
5897 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5898 * <3..0> 0000 Receiver mode = Asynchronous
5899 *
5900 * 0000 0000 0000 0000 = 0x0
5901 */
5902
5903 RegValue = 0;
5904 if ( info->params.stop_bits != 1 )
5905 RegValue |= BIT14;
5906 usc_OutReg( info, CMR, RegValue );
5907
5908
5909 /* Receiver mode Register (RMR)
5910 *
5911 * <15..13> 000 encoding = None
5912 * <12..08> 00000 reserved (Sync Only)
5913 * <7..6> 00 Even parity
5914 * <5> 0 parity disabled
5915 * <4..2> 000 Receive Char Length = 8 bits
5916 * <1..0> 00 Disable Receiver
5917 *
5918 * 0000 0000 0000 0000 = 0x0
5919 */
5920
5921 RegValue = 0;
5922
5923 if ( info->params.data_bits != 8 )
5924 RegValue |= BIT4+BIT3+BIT2;
5925
5926 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5927 RegValue |= BIT5;
5928 if ( info->params.parity != ASYNC_PARITY_ODD )
5929 RegValue |= BIT6;
5930 }
5931
5932 usc_OutReg( info, RMR, RegValue );
5933
5934
5935 /* Set IRQ trigger level */
5936
5937 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5938
5939
5940 /* Receive Interrupt Control Register (RICR)
5941 *
5942 * <15..8> ? RxFIFO IRQ Request Level
5943 *
5944 * Note: For async mode the receive FIFO level must be set
5945 * to 0 to avoid the situation where the FIFO contains fewer bytes
5946 * than the trigger level and no more data is expected.
5947 *
5948 * <7> 0 Exited Hunt IA (Interrupt Arm)
5949 * <6> 0 Idle Received IA
5950 * <5> 0 Break/Abort IA
5951 * <4> 0 Rx Bound IA
5952 * <3> 0 Queued status reflects oldest byte in FIFO
5953 * <2> 0 Abort/PE IA
5954 * <1> 0 Rx Overrun IA
5955 * <0> 0 Select TC0 value for readback
5956 *
5957 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5958 */
5959
5960 usc_OutReg( info, RICR, 0x0000 );
5961
5962 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5963 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
5964
5965
5966 /* Transmit mode Register (TMR)
5967 *
5968 * <15..13> 000 encoding = None
5969 * <12..08> 00000 reserved (Sync Only)
5970 * <7..6> 00 Transmit parity Even
5971 * <5> 0 Transmit parity Disabled
5972 * <4..2> 000 Tx Char Length = 8 bits
5973 * <1..0> 00 Disable Transmitter
5974 *
5975 * 0000 0000 0000 0000 = 0x0
5976 */
5977
5978 RegValue = 0;
5979
5980 if ( info->params.data_bits != 8 )
5981 RegValue |= BIT4+BIT3+BIT2;
5982
5983 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5984 RegValue |= BIT5;
5985 if ( info->params.parity != ASYNC_PARITY_ODD )
5986 RegValue |= BIT6;
5987 }
5988
5989 usc_OutReg( info, TMR, RegValue );
5990
5991 usc_set_txidle( info );
5992
5993
5994 /* Set IRQ trigger level */
5995
5996 usc_TCmd( info, TCmd_SelectTicrIntLevel );
5997
5998
5999 /* Transmit Interrupt Control Register (TICR)
6000 *
6001 * <15..8> ? Transmit FIFO IRQ Level
6002 * <7> 0 Present IA (Interrupt Arm)
6003 * <6> 1 Idle Sent IA
6004 * <5> 0 Abort Sent IA
6005 * <4> 0 EOF/EOM Sent IA
6006 * <3> 0 CRC Sent IA
6007 * <2> 0 1 = Wait for SW Trigger to Start Frame
6008 * <1> 0 Tx Underrun IA
6009 * <0> 0 TC0 constant on read back
6010 *
6011 * 0000 0000 0100 0000 = 0x0040
6012 */
6013
6014 usc_OutReg( info, TICR, 0x1f40 );
6015
6016 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6017 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6018
6019 usc_enable_async_clock( info, info->params.data_rate );
6020
6021
6022 /* Channel Control/status Register (CCSR)
6023 *
6024 * <15> X RCC FIFO Overflow status (RO)
6025 * <14> X RCC FIFO Not Empty status (RO)
6026 * <13> 0 1 = Clear RCC FIFO (WO)
6027 * <12> X DPLL in Sync status (RO)
6028 * <11> X DPLL 2 Missed Clocks status (RO)
6029 * <10> X DPLL 1 Missed Clock status (RO)
6030 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6031 * <7> X SDLC Loop On status (RO)
6032 * <6> X SDLC Loop Send status (RO)
6033 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6034 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6035 * <1..0> 00 reserved
6036 *
6037 * 0000 0000 0010 0000 = 0x0020
6038 */
6039
6040 usc_OutReg( info, CCSR, 0x0020 );
6041
6042 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6043 RECEIVE_DATA + RECEIVE_STATUS );
6044
6045 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6046 RECEIVE_DATA + RECEIVE_STATUS );
6047
6048 usc_EnableMasterIrqBit( info );
6049
6050 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6051 /* Enable INTEN (Port 6, Bit12) */
6052 /* This connects the IRQ request signal to the ISA bus */
6053 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6054 }
6055
6056 if (info->params.loopback) {
6057 info->loopback_bits = 0x300;
6058 outw(0x0300, info->io_base + CCAR);
6059 }
6060
6061 } /* end of usc_set_async_mode() */
6062
6063 /* usc_loopback_frame()
6064 *
6065 * Loop back a small (2 byte) dummy SDLC frame.
6066 * Interrupts and DMA are NOT used. The purpose of this is to
6067 * clear any 'stale' status info left over from running in async mode.
6068 *
6069 * The 16C32 shows the strange behaviour of marking the 1st
6070 * received SDLC frame with a CRC error even when there is no
6071 * CRC error. To get around this a small dummy from of 2 bytes
6072 * is looped back when switching from async to sync mode.
6073 *
6074 * Arguments: info pointer to device instance data
6075 * Return Value: None
6076 */
6077 static void usc_loopback_frame( struct mgsl_struct *info )
6078 {
6079 int i;
6080 unsigned long oldmode = info->params.mode;
6081
6082 info->params.mode = MGSL_MODE_HDLC;
6083
6084 usc_DisableMasterIrqBit( info );
6085
6086 usc_set_sdlc_mode( info );
6087 usc_enable_loopback( info, 1 );
6088
6089 /* Write 16-bit Time Constant for BRG0 */
6090 usc_OutReg( info, TC0R, 0 );
6091
6092 /* Channel Control Register (CCR)
6093 *
6094 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6095 * <13> 0 Trigger Tx on SW Command Disabled
6096 * <12> 0 Flag Preamble Disabled
6097 * <11..10> 00 Preamble Length = 8-Bits
6098 * <9..8> 01 Preamble Pattern = flags
6099 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6100 * <5> 0 Trigger Rx on SW Command Disabled
6101 * <4..0> 0 reserved
6102 *
6103 * 0000 0001 0000 0000 = 0x0100
6104 */
6105
6106 usc_OutReg( info, CCR, 0x0100 );
6107
6108 /* SETUP RECEIVER */
6109 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6110 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6111
6112 /* SETUP TRANSMITTER */
6113 /* Program the Transmit Character Length Register (TCLR) */
6114 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6115 usc_OutReg( info, TCLR, 2 );
6116 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6117
6118 /* unlatch Tx status bits, and start transmit channel. */
6119 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6120 outw(0,info->io_base + DATAREG);
6121
6122 /* ENABLE TRANSMITTER */
6123 usc_TCmd( info, TCmd_SendFrame );
6124 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6125
6126 /* WAIT FOR RECEIVE COMPLETE */
6127 for (i=0 ; i<1000 ; i++)
6128 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6129 break;
6130
6131 /* clear Internal Data loopback mode */
6132 usc_enable_loopback(info, 0);
6133
6134 usc_EnableMasterIrqBit(info);
6135
6136 info->params.mode = oldmode;
6137
6138 } /* end of usc_loopback_frame() */
6139
6140 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6141 *
6142 * Arguments: info pointer to adapter info structure
6143 * Return Value: None
6144 */
6145 static void usc_set_sync_mode( struct mgsl_struct *info )
6146 {
6147 usc_loopback_frame( info );
6148 usc_set_sdlc_mode( info );
6149
6150 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6151 /* Enable INTEN (Port 6, Bit12) */
6152 /* This connects the IRQ request signal to the ISA bus */
6153 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6154 }
6155
6156 usc_enable_aux_clock(info, info->params.clock_speed);
6157
6158 if (info->params.loopback)
6159 usc_enable_loopback(info,1);
6160
6161 } /* end of mgsl_set_sync_mode() */
6162
6163 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6164 *
6165 * Arguments: info pointer to device instance data
6166 * Return Value: None
6167 */
6168 static void usc_set_txidle( struct mgsl_struct *info )
6169 {
6170 u16 usc_idle_mode = IDLEMODE_FLAGS;
6171
6172 /* Map API idle mode to USC register bits */
6173
6174 switch( info->idle_mode ){
6175 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6176 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6177 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6178 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6179 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6180 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6181 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6182 }
6183
6184 info->usc_idle_mode = usc_idle_mode;
6185 //usc_OutReg(info, TCSR, usc_idle_mode);
6186 info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
6187 info->tcsr_value += usc_idle_mode;
6188 usc_OutReg(info, TCSR, info->tcsr_value);
6189
6190 /*
6191 * if SyncLink WAN adapter is running in external sync mode, the
6192 * transmitter has been set to Monosync in order to try to mimic
6193 * a true raw outbound bit stream. Monosync still sends an open/close
6194 * sync char at the start/end of a frame. Try to match those sync
6195 * patterns to the idle mode set here
6196 */
6197 if ( info->params.mode == MGSL_MODE_RAW ) {
6198 unsigned char syncpat = 0;
6199 switch( info->idle_mode ) {
6200 case HDLC_TXIDLE_FLAGS:
6201 syncpat = 0x7e;
6202 break;
6203 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6204 syncpat = 0x55;
6205 break;
6206 case HDLC_TXIDLE_ZEROS:
6207 case HDLC_TXIDLE_SPACE:
6208 syncpat = 0x00;
6209 break;
6210 case HDLC_TXIDLE_ONES:
6211 case HDLC_TXIDLE_MARK:
6212 syncpat = 0xff;
6213 break;
6214 case HDLC_TXIDLE_ALT_MARK_SPACE:
6215 syncpat = 0xaa;
6216 break;
6217 }
6218
6219 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6220 }
6221
6222 } /* end of usc_set_txidle() */
6223
6224 /* usc_get_serial_signals()
6225 *
6226 * Query the adapter for the state of the V24 status (input) signals.
6227 *
6228 * Arguments: info pointer to device instance data
6229 * Return Value: None
6230 */
6231 static void usc_get_serial_signals( struct mgsl_struct *info )
6232 {
6233 u16 status;
6234
6235 /* clear all serial signals except DTR and RTS */
6236 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6237
6238 /* Read the Misc Interrupt status Register (MISR) to get */
6239 /* the V24 status signals. */
6240
6241 status = usc_InReg( info, MISR );
6242
6243 /* set serial signal bits to reflect MISR */
6244
6245 if ( status & MISCSTATUS_CTS )
6246 info->serial_signals |= SerialSignal_CTS;
6247
6248 if ( status & MISCSTATUS_DCD )
6249 info->serial_signals |= SerialSignal_DCD;
6250
6251 if ( status & MISCSTATUS_RI )
6252 info->serial_signals |= SerialSignal_RI;
6253
6254 if ( status & MISCSTATUS_DSR )
6255 info->serial_signals |= SerialSignal_DSR;
6256
6257 } /* end of usc_get_serial_signals() */
6258
6259 /* usc_set_serial_signals()
6260 *
6261 * Set the state of DTR and RTS based on contents of
6262 * serial_signals member of device extension.
6263 *
6264 * Arguments: info pointer to device instance data
6265 * Return Value: None
6266 */
6267 static void usc_set_serial_signals( struct mgsl_struct *info )
6268 {
6269 u16 Control;
6270 unsigned char V24Out = info->serial_signals;
6271
6272 /* get the current value of the Port Control Register (PCR) */
6273
6274 Control = usc_InReg( info, PCR );
6275
6276 if ( V24Out & SerialSignal_RTS )
6277 Control &= ~(BIT6);
6278 else
6279 Control |= BIT6;
6280
6281 if ( V24Out & SerialSignal_DTR )
6282 Control &= ~(BIT4);
6283 else
6284 Control |= BIT4;
6285
6286 usc_OutReg( info, PCR, Control );
6287
6288 } /* end of usc_set_serial_signals() */
6289
6290 /* usc_enable_async_clock()
6291 *
6292 * Enable the async clock at the specified frequency.
6293 *
6294 * Arguments: info pointer to device instance data
6295 * data_rate data rate of clock in bps
6296 * 0 disables the AUX clock.
6297 * Return Value: None
6298 */
6299 static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6300 {
6301 if ( data_rate ) {
6302 /*
6303 * Clock mode Control Register (CMCR)
6304 *
6305 * <15..14> 00 counter 1 Disabled
6306 * <13..12> 00 counter 0 Disabled
6307 * <11..10> 11 BRG1 Input is TxC Pin
6308 * <9..8> 11 BRG0 Input is TxC Pin
6309 * <7..6> 01 DPLL Input is BRG1 Output
6310 * <5..3> 100 TxCLK comes from BRG0
6311 * <2..0> 100 RxCLK comes from BRG0
6312 *
6313 * 0000 1111 0110 0100 = 0x0f64
6314 */
6315
6316 usc_OutReg( info, CMCR, 0x0f64 );
6317
6318
6319 /*
6320 * Write 16-bit Time Constant for BRG0
6321 * Time Constant = (ClkSpeed / data_rate) - 1
6322 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6323 */
6324
6325 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6326 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6327 else
6328 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6329
6330
6331 /*
6332 * Hardware Configuration Register (HCR)
6333 * Clear Bit 1, BRG0 mode = Continuous
6334 * Set Bit 0 to enable BRG0.
6335 */
6336
6337 usc_OutReg( info, HCR,
6338 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6339
6340
6341 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6342
6343 usc_OutReg( info, IOCR,
6344 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6345 } else {
6346 /* data rate == 0 so turn off BRG0 */
6347 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6348 }
6349
6350 } /* end of usc_enable_async_clock() */
6351
6352 /*
6353 * Buffer Structures:
6354 *
6355 * Normal memory access uses virtual addresses that can make discontiguous
6356 * physical memory pages appear to be contiguous in the virtual address
6357 * space (the processors memory mapping handles the conversions).
6358 *
6359 * DMA transfers require physically contiguous memory. This is because
6360 * the DMA system controller and DMA bus masters deal with memory using
6361 * only physical addresses.
6362 *
6363 * This causes a problem under Windows NT when large DMA buffers are
6364 * needed. Fragmentation of the nonpaged pool prevents allocations of
6365 * physically contiguous buffers larger than the PAGE_SIZE.
6366 *
6367 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6368 * allows DMA transfers to physically discontiguous buffers. Information
6369 * about each data transfer buffer is contained in a memory structure
6370 * called a 'buffer entry'. A list of buffer entries is maintained
6371 * to track and control the use of the data transfer buffers.
6372 *
6373 * To support this strategy we will allocate sufficient PAGE_SIZE
6374 * contiguous memory buffers to allow for the total required buffer
6375 * space.
6376 *
6377 * The 16C32 accesses the list of buffer entries using Bus Master
6378 * DMA. Control information is read from the buffer entries by the
6379 * 16C32 to control data transfers. status information is written to
6380 * the buffer entries by the 16C32 to indicate the status of completed
6381 * transfers.
6382 *
6383 * The CPU writes control information to the buffer entries to control
6384 * the 16C32 and reads status information from the buffer entries to
6385 * determine information about received and transmitted frames.
6386 *
6387 * Because the CPU and 16C32 (adapter) both need simultaneous access
6388 * to the buffer entries, the buffer entry memory is allocated with
6389 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6390 * entry list to PAGE_SIZE.
6391 *
6392 * The actual data buffers on the other hand will only be accessed
6393 * by the CPU or the adapter but not by both simultaneously. This allows
6394 * Scatter/Gather packet based DMA procedures for using physically
6395 * discontiguous pages.
6396 */
6397
6398 /*
6399 * mgsl_reset_tx_dma_buffers()
6400 *
6401 * Set the count for all transmit buffers to 0 to indicate the
6402 * buffer is available for use and set the current buffer to the
6403 * first buffer. This effectively makes all buffers free and
6404 * discards any data in buffers.
6405 *
6406 * Arguments: info pointer to device instance data
6407 * Return Value: None
6408 */
6409 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6410 {
6411 unsigned int i;
6412
6413 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6414 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6415 }
6416
6417 info->current_tx_buffer = 0;
6418 info->start_tx_dma_buffer = 0;
6419 info->tx_dma_buffers_used = 0;
6420
6421 info->get_tx_holding_index = 0;
6422 info->put_tx_holding_index = 0;
6423 info->tx_holding_count = 0;
6424
6425 } /* end of mgsl_reset_tx_dma_buffers() */
6426
6427 /*
6428 * num_free_tx_dma_buffers()
6429 *
6430 * returns the number of free tx dma buffers available
6431 *
6432 * Arguments: info pointer to device instance data
6433 * Return Value: number of free tx dma buffers
6434 */
6435 static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6436 {
6437 return info->tx_buffer_count - info->tx_dma_buffers_used;
6438 }
6439
6440 /*
6441 * mgsl_reset_rx_dma_buffers()
6442 *
6443 * Set the count for all receive buffers to DMABUFFERSIZE
6444 * and set the current buffer to the first buffer. This effectively
6445 * makes all buffers free and discards any data in buffers.
6446 *
6447 * Arguments: info pointer to device instance data
6448 * Return Value: None
6449 */
6450 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6451 {
6452 unsigned int i;
6453
6454 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6455 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6456 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6457 // info->rx_buffer_list[i].status = 0;
6458 }
6459
6460 info->current_rx_buffer = 0;
6461
6462 } /* end of mgsl_reset_rx_dma_buffers() */
6463
6464 /*
6465 * mgsl_free_rx_frame_buffers()
6466 *
6467 * Free the receive buffers used by a received SDLC
6468 * frame such that the buffers can be reused.
6469 *
6470 * Arguments:
6471 *
6472 * info pointer to device instance data
6473 * StartIndex index of 1st receive buffer of frame
6474 * EndIndex index of last receive buffer of frame
6475 *
6476 * Return Value: None
6477 */
6478 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6479 {
6480 bool Done = false;
6481 DMABUFFERENTRY *pBufEntry;
6482 unsigned int Index;
6483
6484 /* Starting with 1st buffer entry of the frame clear the status */
6485 /* field and set the count field to DMA Buffer Size. */
6486
6487 Index = StartIndex;
6488
6489 while( !Done ) {
6490 pBufEntry = &(info->rx_buffer_list[Index]);
6491
6492 if ( Index == EndIndex ) {
6493 /* This is the last buffer of the frame! */
6494 Done = true;
6495 }
6496
6497 /* reset current buffer for reuse */
6498 // pBufEntry->status = 0;
6499 // pBufEntry->count = DMABUFFERSIZE;
6500 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6501
6502 /* advance to next buffer entry in linked list */
6503 Index++;
6504 if ( Index == info->rx_buffer_count )
6505 Index = 0;
6506 }
6507
6508 /* set current buffer to next buffer after last buffer of frame */
6509 info->current_rx_buffer = Index;
6510
6511 } /* end of free_rx_frame_buffers() */
6512
6513 /* mgsl_get_rx_frame()
6514 *
6515 * This function attempts to return a received SDLC frame from the
6516 * receive DMA buffers. Only frames received without errors are returned.
6517 *
6518 * Arguments: info pointer to device extension
6519 * Return Value: true if frame returned, otherwise false
6520 */
6521 static bool mgsl_get_rx_frame(struct mgsl_struct *info)
6522 {
6523 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6524 unsigned short status;
6525 DMABUFFERENTRY *pBufEntry;
6526 unsigned int framesize = 0;
6527 bool ReturnCode = false;
6528 unsigned long flags;
6529 struct tty_struct *tty = info->port.tty;
6530 bool return_frame = false;
6531
6532 /*
6533 * current_rx_buffer points to the 1st buffer of the next available
6534 * receive frame. To find the last buffer of the frame look for
6535 * a non-zero status field in the buffer entries. (The status
6536 * field is set by the 16C32 after completing a receive frame.
6537 */
6538
6539 StartIndex = EndIndex = info->current_rx_buffer;
6540
6541 while( !info->rx_buffer_list[EndIndex].status ) {
6542 /*
6543 * If the count field of the buffer entry is non-zero then
6544 * this buffer has not been used. (The 16C32 clears the count
6545 * field when it starts using the buffer.) If an unused buffer
6546 * is encountered then there are no frames available.
6547 */
6548
6549 if ( info->rx_buffer_list[EndIndex].count )
6550 goto Cleanup;
6551
6552 /* advance to next buffer entry in linked list */
6553 EndIndex++;
6554 if ( EndIndex == info->rx_buffer_count )
6555 EndIndex = 0;
6556
6557 /* if entire list searched then no frame available */
6558 if ( EndIndex == StartIndex ) {
6559 /* If this occurs then something bad happened,
6560 * all buffers have been 'used' but none mark
6561 * the end of a frame. Reset buffers and receiver.
6562 */
6563
6564 if ( info->rx_enabled ){
6565 spin_lock_irqsave(&info->irq_spinlock,flags);
6566 usc_start_receiver(info);
6567 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6568 }
6569 goto Cleanup;
6570 }
6571 }
6572
6573
6574 /* check status of receive frame */
6575
6576 status = info->rx_buffer_list[EndIndex].status;
6577
6578 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6579 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6580 if ( status & RXSTATUS_SHORT_FRAME )
6581 info->icount.rxshort++;
6582 else if ( status & RXSTATUS_ABORT )
6583 info->icount.rxabort++;
6584 else if ( status & RXSTATUS_OVERRUN )
6585 info->icount.rxover++;
6586 else {
6587 info->icount.rxcrc++;
6588 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6589 return_frame = true;
6590 }
6591 framesize = 0;
6592 #if SYNCLINK_GENERIC_HDLC
6593 {
6594 info->netdev->stats.rx_errors++;
6595 info->netdev->stats.rx_frame_errors++;
6596 }
6597 #endif
6598 } else
6599 return_frame = true;
6600
6601 if ( return_frame ) {
6602 /* receive frame has no errors, get frame size.
6603 * The frame size is the starting value of the RCC (which was
6604 * set to 0xffff) minus the ending value of the RCC (decremented
6605 * once for each receive character) minus 2 for the 16-bit CRC.
6606 */
6607
6608 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6609
6610 /* adjust frame size for CRC if any */
6611 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6612 framesize -= 2;
6613 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6614 framesize -= 4;
6615 }
6616
6617 if ( debug_level >= DEBUG_LEVEL_BH )
6618 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6619 __FILE__,__LINE__,info->device_name,status,framesize);
6620
6621 if ( debug_level >= DEBUG_LEVEL_DATA )
6622 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6623 min_t(int, framesize, DMABUFFERSIZE),0);
6624
6625 if (framesize) {
6626 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6627 ((framesize+1) > info->max_frame_size) ) ||
6628 (framesize > info->max_frame_size) )
6629 info->icount.rxlong++;
6630 else {
6631 /* copy dma buffer(s) to contiguous intermediate buffer */
6632 int copy_count = framesize;
6633 int index = StartIndex;
6634 unsigned char *ptmp = info->intermediate_rxbuffer;
6635
6636 if ( !(status & RXSTATUS_CRC_ERROR))
6637 info->icount.rxok++;
6638
6639 while(copy_count) {
6640 int partial_count;
6641 if ( copy_count > DMABUFFERSIZE )
6642 partial_count = DMABUFFERSIZE;
6643 else
6644 partial_count = copy_count;
6645
6646 pBufEntry = &(info->rx_buffer_list[index]);
6647 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6648 ptmp += partial_count;
6649 copy_count -= partial_count;
6650
6651 if ( ++index == info->rx_buffer_count )
6652 index = 0;
6653 }
6654
6655 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6656 ++framesize;
6657 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6658 RX_CRC_ERROR :
6659 RX_OK);
6660
6661 if ( debug_level >= DEBUG_LEVEL_DATA )
6662 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6663 __FILE__,__LINE__,info->device_name,
6664 *ptmp);
6665 }
6666
6667 #if SYNCLINK_GENERIC_HDLC
6668 if (info->netcount)
6669 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6670 else
6671 #endif
6672 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6673 }
6674 }
6675 /* Free the buffers used by this frame. */
6676 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6677
6678 ReturnCode = true;
6679
6680 Cleanup:
6681
6682 if ( info->rx_enabled && info->rx_overflow ) {
6683 /* The receiver needs to restarted because of
6684 * a receive overflow (buffer or FIFO). If the
6685 * receive buffers are now empty, then restart receiver.
6686 */
6687
6688 if ( !info->rx_buffer_list[EndIndex].status &&
6689 info->rx_buffer_list[EndIndex].count ) {
6690 spin_lock_irqsave(&info->irq_spinlock,flags);
6691 usc_start_receiver(info);
6692 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6693 }
6694 }
6695
6696 return ReturnCode;
6697
6698 } /* end of mgsl_get_rx_frame() */
6699
6700 /* mgsl_get_raw_rx_frame()
6701 *
6702 * This function attempts to return a received frame from the
6703 * receive DMA buffers when running in external loop mode. In this mode,
6704 * we will return at most one DMABUFFERSIZE frame to the application.
6705 * The USC receiver is triggering off of DCD going active to start a new
6706 * frame, and DCD going inactive to terminate the frame (similar to
6707 * processing a closing flag character).
6708 *
6709 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6710 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6711 * status field and the RCC field will indicate the length of the
6712 * entire received frame. We take this RCC field and get the modulus
6713 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6714 * last Rx DMA buffer and return that last portion of the frame.
6715 *
6716 * Arguments: info pointer to device extension
6717 * Return Value: true if frame returned, otherwise false
6718 */
6719 static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6720 {
6721 unsigned int CurrentIndex, NextIndex;
6722 unsigned short status;
6723 DMABUFFERENTRY *pBufEntry;
6724 unsigned int framesize = 0;
6725 bool ReturnCode = false;
6726 unsigned long flags;
6727 struct tty_struct *tty = info->port.tty;
6728
6729 /*
6730 * current_rx_buffer points to the 1st buffer of the next available
6731 * receive frame. The status field is set by the 16C32 after
6732 * completing a receive frame. If the status field of this buffer
6733 * is zero, either the USC is still filling this buffer or this
6734 * is one of a series of buffers making up a received frame.
6735 *
6736 * If the count field of this buffer is zero, the USC is either
6737 * using this buffer or has used this buffer. Look at the count
6738 * field of the next buffer. If that next buffer's count is
6739 * non-zero, the USC is still actively using the current buffer.
6740 * Otherwise, if the next buffer's count field is zero, the
6741 * current buffer is complete and the USC is using the next
6742 * buffer.
6743 */
6744 CurrentIndex = NextIndex = info->current_rx_buffer;
6745 ++NextIndex;
6746 if ( NextIndex == info->rx_buffer_count )
6747 NextIndex = 0;
6748
6749 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6750 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6751 info->rx_buffer_list[NextIndex].count == 0)) {
6752 /*
6753 * Either the status field of this dma buffer is non-zero
6754 * (indicating the last buffer of a receive frame) or the next
6755 * buffer is marked as in use -- implying this buffer is complete
6756 * and an intermediate buffer for this received frame.
6757 */
6758
6759 status = info->rx_buffer_list[CurrentIndex].status;
6760
6761 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6762 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6763 if ( status & RXSTATUS_SHORT_FRAME )
6764 info->icount.rxshort++;
6765 else if ( status & RXSTATUS_ABORT )
6766 info->icount.rxabort++;
6767 else if ( status & RXSTATUS_OVERRUN )
6768 info->icount.rxover++;
6769 else
6770 info->icount.rxcrc++;
6771 framesize = 0;
6772 } else {
6773 /*
6774 * A receive frame is available, get frame size and status.
6775 *
6776 * The frame size is the starting value of the RCC (which was
6777 * set to 0xffff) minus the ending value of the RCC (decremented
6778 * once for each receive character) minus 2 or 4 for the 16-bit
6779 * or 32-bit CRC.
6780 *
6781 * If the status field is zero, this is an intermediate buffer.
6782 * It's size is 4K.
6783 *
6784 * If the DMA Buffer Entry's Status field is non-zero, the
6785 * receive operation completed normally (ie: DCD dropped). The
6786 * RCC field is valid and holds the received frame size.
6787 * It is possible that the RCC field will be zero on a DMA buffer
6788 * entry with a non-zero status. This can occur if the total
6789 * frame size (number of bytes between the time DCD goes active
6790 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6791 * case the 16C32 has underrun on the RCC count and appears to
6792 * stop updating this counter to let us know the actual received
6793 * frame size. If this happens (non-zero status and zero RCC),
6794 * simply return the entire RxDMA Buffer
6795 */
6796 if ( status ) {
6797 /*
6798 * In the event that the final RxDMA Buffer is
6799 * terminated with a non-zero status and the RCC
6800 * field is zero, we interpret this as the RCC
6801 * having underflowed (received frame > 65535 bytes).
6802 *
6803 * Signal the event to the user by passing back
6804 * a status of RxStatus_CrcError returning the full
6805 * buffer and let the app figure out what data is
6806 * actually valid
6807 */
6808 if ( info->rx_buffer_list[CurrentIndex].rcc )
6809 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6810 else
6811 framesize = DMABUFFERSIZE;
6812 }
6813 else
6814 framesize = DMABUFFERSIZE;
6815 }
6816
6817 if ( framesize > DMABUFFERSIZE ) {
6818 /*
6819 * if running in raw sync mode, ISR handler for
6820 * End Of Buffer events terminates all buffers at 4K.
6821 * If this frame size is said to be >4K, get the
6822 * actual number of bytes of the frame in this buffer.
6823 */
6824 framesize = framesize % DMABUFFERSIZE;
6825 }
6826
6827
6828 if ( debug_level >= DEBUG_LEVEL_BH )
6829 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6830 __FILE__,__LINE__,info->device_name,status,framesize);
6831
6832 if ( debug_level >= DEBUG_LEVEL_DATA )
6833 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6834 min_t(int, framesize, DMABUFFERSIZE),0);
6835
6836 if (framesize) {
6837 /* copy dma buffer(s) to contiguous intermediate buffer */
6838 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6839
6840 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6841 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6842 info->icount.rxok++;
6843
6844 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6845 }
6846
6847 /* Free the buffers used by this frame. */
6848 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6849
6850 ReturnCode = true;
6851 }
6852
6853
6854 if ( info->rx_enabled && info->rx_overflow ) {
6855 /* The receiver needs to restarted because of
6856 * a receive overflow (buffer or FIFO). If the
6857 * receive buffers are now empty, then restart receiver.
6858 */
6859
6860 if ( !info->rx_buffer_list[CurrentIndex].status &&
6861 info->rx_buffer_list[CurrentIndex].count ) {
6862 spin_lock_irqsave(&info->irq_spinlock,flags);
6863 usc_start_receiver(info);
6864 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6865 }
6866 }
6867
6868 return ReturnCode;
6869
6870 } /* end of mgsl_get_raw_rx_frame() */
6871
6872 /* mgsl_load_tx_dma_buffer()
6873 *
6874 * Load the transmit DMA buffer with the specified data.
6875 *
6876 * Arguments:
6877 *
6878 * info pointer to device extension
6879 * Buffer pointer to buffer containing frame to load
6880 * BufferSize size in bytes of frame in Buffer
6881 *
6882 * Return Value: None
6883 */
6884 static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6885 const char *Buffer, unsigned int BufferSize)
6886 {
6887 unsigned short Copycount;
6888 unsigned int i = 0;
6889 DMABUFFERENTRY *pBufEntry;
6890
6891 if ( debug_level >= DEBUG_LEVEL_DATA )
6892 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6893
6894 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6895 /* set CMR:13 to start transmit when
6896 * next GoAhead (abort) is received
6897 */
6898 info->cmr_value |= BIT13;
6899 }
6900
6901 /* begin loading the frame in the next available tx dma
6902 * buffer, remember it's starting location for setting
6903 * up tx dma operation
6904 */
6905 i = info->current_tx_buffer;
6906 info->start_tx_dma_buffer = i;
6907
6908 /* Setup the status and RCC (Frame Size) fields of the 1st */
6909 /* buffer entry in the transmit DMA buffer list. */
6910
6911 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6912 info->tx_buffer_list[i].rcc = BufferSize;
6913 info->tx_buffer_list[i].count = BufferSize;
6914
6915 /* Copy frame data from 1st source buffer to the DMA buffers. */
6916 /* The frame data may span multiple DMA buffers. */
6917
6918 while( BufferSize ){
6919 /* Get a pointer to next DMA buffer entry. */
6920 pBufEntry = &info->tx_buffer_list[i++];
6921
6922 if ( i == info->tx_buffer_count )
6923 i=0;
6924
6925 /* Calculate the number of bytes that can be copied from */
6926 /* the source buffer to this DMA buffer. */
6927 if ( BufferSize > DMABUFFERSIZE )
6928 Copycount = DMABUFFERSIZE;
6929 else
6930 Copycount = BufferSize;
6931
6932 /* Actually copy data from source buffer to DMA buffer. */
6933 /* Also set the data count for this individual DMA buffer. */
6934 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6935 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6936 else
6937 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6938
6939 pBufEntry->count = Copycount;
6940
6941 /* Advance source pointer and reduce remaining data count. */
6942 Buffer += Copycount;
6943 BufferSize -= Copycount;
6944
6945 ++info->tx_dma_buffers_used;
6946 }
6947
6948 /* remember next available tx dma buffer */
6949 info->current_tx_buffer = i;
6950
6951 } /* end of mgsl_load_tx_dma_buffer() */
6952
6953 /*
6954 * mgsl_register_test()
6955 *
6956 * Performs a register test of the 16C32.
6957 *
6958 * Arguments: info pointer to device instance data
6959 * Return Value: true if test passed, otherwise false
6960 */
6961 static bool mgsl_register_test( struct mgsl_struct *info )
6962 {
6963 static unsigned short BitPatterns[] =
6964 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6965 static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
6966 unsigned int i;
6967 bool rc = true;
6968 unsigned long flags;
6969
6970 spin_lock_irqsave(&info->irq_spinlock,flags);
6971 usc_reset(info);
6972
6973 /* Verify the reset state of some registers. */
6974
6975 if ( (usc_InReg( info, SICR ) != 0) ||
6976 (usc_InReg( info, IVR ) != 0) ||
6977 (usc_InDmaReg( info, DIVR ) != 0) ){
6978 rc = false;
6979 }
6980
6981 if ( rc ){
6982 /* Write bit patterns to various registers but do it out of */
6983 /* sync, then read back and verify values. */
6984
6985 for ( i = 0 ; i < Patterncount ; i++ ) {
6986 usc_OutReg( info, TC0R, BitPatterns[i] );
6987 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
6988 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
6989 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
6990 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
6991 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
6992
6993 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
6994 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
6995 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
6996 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
6997 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
6998 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
6999 rc = false;
7000 break;
7001 }
7002 }
7003 }
7004
7005 usc_reset(info);
7006 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7007
7008 return rc;
7009
7010 } /* end of mgsl_register_test() */
7011
7012 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7013 *
7014 * Arguments: info pointer to device instance data
7015 * Return Value: true if test passed, otherwise false
7016 */
7017 static bool mgsl_irq_test( struct mgsl_struct *info )
7018 {
7019 unsigned long EndTime;
7020 unsigned long flags;
7021
7022 spin_lock_irqsave(&info->irq_spinlock,flags);
7023 usc_reset(info);
7024
7025 /*
7026 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7027 * The ISR sets irq_occurred to true.
7028 */
7029
7030 info->irq_occurred = false;
7031
7032 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7033 /* Enable INTEN (Port 6, Bit12) */
7034 /* This connects the IRQ request signal to the ISA bus */
7035 /* on the ISA adapter. This has no effect for the PCI adapter */
7036 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7037
7038 usc_EnableMasterIrqBit(info);
7039 usc_EnableInterrupts(info, IO_PIN);
7040 usc_ClearIrqPendingBits(info, IO_PIN);
7041
7042 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7043 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7044
7045 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7046
7047 EndTime=100;
7048 while( EndTime-- && !info->irq_occurred ) {
7049 msleep_interruptible(10);
7050 }
7051
7052 spin_lock_irqsave(&info->irq_spinlock,flags);
7053 usc_reset(info);
7054 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7055
7056 return info->irq_occurred;
7057
7058 } /* end of mgsl_irq_test() */
7059
7060 /* mgsl_dma_test()
7061 *
7062 * Perform a DMA test of the 16C32. A small frame is
7063 * transmitted via DMA from a transmit buffer to a receive buffer
7064 * using single buffer DMA mode.
7065 *
7066 * Arguments: info pointer to device instance data
7067 * Return Value: true if test passed, otherwise false
7068 */
7069 static bool mgsl_dma_test( struct mgsl_struct *info )
7070 {
7071 unsigned short FifoLevel;
7072 unsigned long phys_addr;
7073 unsigned int FrameSize;
7074 unsigned int i;
7075 char *TmpPtr;
7076 bool rc = true;
7077 unsigned short status=0;
7078 unsigned long EndTime;
7079 unsigned long flags;
7080 MGSL_PARAMS tmp_params;
7081
7082 /* save current port options */
7083 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7084 /* load default port options */
7085 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7086
7087 #define TESTFRAMESIZE 40
7088
7089 spin_lock_irqsave(&info->irq_spinlock,flags);
7090
7091 /* setup 16C32 for SDLC DMA transfer mode */
7092
7093 usc_reset(info);
7094 usc_set_sdlc_mode(info);
7095 usc_enable_loopback(info,1);
7096
7097 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7098 * field of the buffer entry after fetching buffer address. This
7099 * way we can detect a DMA failure for a DMA read (which should be
7100 * non-destructive to system memory) before we try and write to
7101 * memory (where a failure could corrupt system memory).
7102 */
7103
7104 /* Receive DMA mode Register (RDMR)
7105 *
7106 * <15..14> 11 DMA mode = Linked List Buffer mode
7107 * <13> 1 RSBinA/L = store Rx status Block in List entry
7108 * <12> 0 1 = Clear count of List Entry after fetching
7109 * <11..10> 00 Address mode = Increment
7110 * <9> 1 Terminate Buffer on RxBound
7111 * <8> 0 Bus Width = 16bits
7112 * <7..0> ? status Bits (write as 0s)
7113 *
7114 * 1110 0010 0000 0000 = 0xe200
7115 */
7116
7117 usc_OutDmaReg( info, RDMR, 0xe200 );
7118
7119 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7120
7121
7122 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7123
7124 FrameSize = TESTFRAMESIZE;
7125
7126 /* setup 1st transmit buffer entry: */
7127 /* with frame size and transmit control word */
7128
7129 info->tx_buffer_list[0].count = FrameSize;
7130 info->tx_buffer_list[0].rcc = FrameSize;
7131 info->tx_buffer_list[0].status = 0x4000;
7132
7133 /* build a transmit frame in 1st transmit DMA buffer */
7134
7135 TmpPtr = info->tx_buffer_list[0].virt_addr;
7136 for (i = 0; i < FrameSize; i++ )
7137 *TmpPtr++ = i;
7138
7139 /* setup 1st receive buffer entry: */
7140 /* clear status, set max receive buffer size */
7141
7142 info->rx_buffer_list[0].status = 0;
7143 info->rx_buffer_list[0].count = FrameSize + 4;
7144
7145 /* zero out the 1st receive buffer */
7146
7147 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7148
7149 /* Set count field of next buffer entries to prevent */
7150 /* 16C32 from using buffers after the 1st one. */
7151
7152 info->tx_buffer_list[1].count = 0;
7153 info->rx_buffer_list[1].count = 0;
7154
7155
7156 /***************************/
7157 /* Program 16C32 receiver. */
7158 /***************************/
7159
7160 spin_lock_irqsave(&info->irq_spinlock,flags);
7161
7162 /* setup DMA transfers */
7163 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7164
7165 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7166 phys_addr = info->rx_buffer_list[0].phys_entry;
7167 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7168 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7169
7170 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7171 usc_InDmaReg( info, RDMR );
7172 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7173
7174 /* Enable Receiver (RMR <1..0> = 10) */
7175 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7176
7177 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7178
7179
7180 /*************************************************************/
7181 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7182 /*************************************************************/
7183
7184 /* Wait 100ms for interrupt. */
7185 EndTime = jiffies + msecs_to_jiffies(100);
7186
7187 for(;;) {
7188 if (time_after(jiffies, EndTime)) {
7189 rc = false;
7190 break;
7191 }
7192
7193 spin_lock_irqsave(&info->irq_spinlock,flags);
7194 status = usc_InDmaReg( info, RDMR );
7195 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7196
7197 if ( !(status & BIT4) && (status & BIT5) ) {
7198 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7199 /* BUSY (BIT 5) is active (channel still active). */
7200 /* This means the buffer entry read has completed. */
7201 break;
7202 }
7203 }
7204
7205
7206 /******************************/
7207 /* Program 16C32 transmitter. */
7208 /******************************/
7209
7210 spin_lock_irqsave(&info->irq_spinlock,flags);
7211
7212 /* Program the Transmit Character Length Register (TCLR) */
7213 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7214
7215 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7216 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7217
7218 /* Program the address of the 1st DMA Buffer Entry in linked list */
7219
7220 phys_addr = info->tx_buffer_list[0].phys_entry;
7221 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7222 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7223
7224 /* unlatch Tx status bits, and start transmit channel. */
7225
7226 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7227 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7228
7229 /* wait for DMA controller to fill transmit FIFO */
7230
7231 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7232
7233 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7234
7235
7236 /**********************************/
7237 /* WAIT FOR TRANSMIT FIFO TO FILL */
7238 /**********************************/
7239
7240 /* Wait 100ms */
7241 EndTime = jiffies + msecs_to_jiffies(100);
7242
7243 for(;;) {
7244 if (time_after(jiffies, EndTime)) {
7245 rc = false;
7246 break;
7247 }
7248
7249 spin_lock_irqsave(&info->irq_spinlock,flags);
7250 FifoLevel = usc_InReg(info, TICR) >> 8;
7251 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7252
7253 if ( FifoLevel < 16 )
7254 break;
7255 else
7256 if ( FrameSize < 32 ) {
7257 /* This frame is smaller than the entire transmit FIFO */
7258 /* so wait for the entire frame to be loaded. */
7259 if ( FifoLevel <= (32 - FrameSize) )
7260 break;
7261 }
7262 }
7263
7264
7265 if ( rc )
7266 {
7267 /* Enable 16C32 transmitter. */
7268
7269 spin_lock_irqsave(&info->irq_spinlock,flags);
7270
7271 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7272 usc_TCmd( info, TCmd_SendFrame );
7273 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7274
7275 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7276
7277
7278 /******************************/
7279 /* WAIT FOR TRANSMIT COMPLETE */
7280 /******************************/
7281
7282 /* Wait 100ms */
7283 EndTime = jiffies + msecs_to_jiffies(100);
7284
7285 /* While timer not expired wait for transmit complete */
7286
7287 spin_lock_irqsave(&info->irq_spinlock,flags);
7288 status = usc_InReg( info, TCSR );
7289 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7290
7291 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7292 if (time_after(jiffies, EndTime)) {
7293 rc = false;
7294 break;
7295 }
7296
7297 spin_lock_irqsave(&info->irq_spinlock,flags);
7298 status = usc_InReg( info, TCSR );
7299 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7300 }
7301 }
7302
7303
7304 if ( rc ){
7305 /* CHECK FOR TRANSMIT ERRORS */
7306 if ( status & (BIT5 + BIT1) )
7307 rc = false;
7308 }
7309
7310 if ( rc ) {
7311 /* WAIT FOR RECEIVE COMPLETE */
7312
7313 /* Wait 100ms */
7314 EndTime = jiffies + msecs_to_jiffies(100);
7315
7316 /* Wait for 16C32 to write receive status to buffer entry. */
7317 status=info->rx_buffer_list[0].status;
7318 while ( status == 0 ) {
7319 if (time_after(jiffies, EndTime)) {
7320 rc = false;
7321 break;
7322 }
7323 status=info->rx_buffer_list[0].status;
7324 }
7325 }
7326
7327
7328 if ( rc ) {
7329 /* CHECK FOR RECEIVE ERRORS */
7330 status = info->rx_buffer_list[0].status;
7331
7332 if ( status & (BIT8 + BIT3 + BIT1) ) {
7333 /* receive error has occurred */
7334 rc = false;
7335 } else {
7336 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7337 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7338 rc = false;
7339 }
7340 }
7341 }
7342
7343 spin_lock_irqsave(&info->irq_spinlock,flags);
7344 usc_reset( info );
7345 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7346
7347 /* restore current port options */
7348 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7349
7350 return rc;
7351
7352 } /* end of mgsl_dma_test() */
7353
7354 /* mgsl_adapter_test()
7355 *
7356 * Perform the register, IRQ, and DMA tests for the 16C32.
7357 *
7358 * Arguments: info pointer to device instance data
7359 * Return Value: 0 if success, otherwise -ENODEV
7360 */
7361 static int mgsl_adapter_test( struct mgsl_struct *info )
7362 {
7363 if ( debug_level >= DEBUG_LEVEL_INFO )
7364 printk( "%s(%d):Testing device %s\n",
7365 __FILE__,__LINE__,info->device_name );
7366
7367 if ( !mgsl_register_test( info ) ) {
7368 info->init_error = DiagStatus_AddressFailure;
7369 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7370 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7371 return -ENODEV;
7372 }
7373
7374 if ( !mgsl_irq_test( info ) ) {
7375 info->init_error = DiagStatus_IrqFailure;
7376 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7377 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7378 return -ENODEV;
7379 }
7380
7381 if ( !mgsl_dma_test( info ) ) {
7382 info->init_error = DiagStatus_DmaFailure;
7383 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7384 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7385 return -ENODEV;
7386 }
7387
7388 if ( debug_level >= DEBUG_LEVEL_INFO )
7389 printk( "%s(%d):device %s passed diagnostics\n",
7390 __FILE__,__LINE__,info->device_name );
7391
7392 return 0;
7393
7394 } /* end of mgsl_adapter_test() */
7395
7396 /* mgsl_memory_test()
7397 *
7398 * Test the shared memory on a PCI adapter.
7399 *
7400 * Arguments: info pointer to device instance data
7401 * Return Value: true if test passed, otherwise false
7402 */
7403 static bool mgsl_memory_test( struct mgsl_struct *info )
7404 {
7405 static unsigned long BitPatterns[] =
7406 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7407 unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
7408 unsigned long i;
7409 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7410 unsigned long * TestAddr;
7411
7412 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7413 return true;
7414
7415 TestAddr = (unsigned long *)info->memory_base;
7416
7417 /* Test data lines with test pattern at one location. */
7418
7419 for ( i = 0 ; i < Patterncount ; i++ ) {
7420 *TestAddr = BitPatterns[i];
7421 if ( *TestAddr != BitPatterns[i] )
7422 return false;
7423 }
7424
7425 /* Test address lines with incrementing pattern over */
7426 /* entire address range. */
7427
7428 for ( i = 0 ; i < TestLimit ; i++ ) {
7429 *TestAddr = i * 4;
7430 TestAddr++;
7431 }
7432
7433 TestAddr = (unsigned long *)info->memory_base;
7434
7435 for ( i = 0 ; i < TestLimit ; i++ ) {
7436 if ( *TestAddr != i * 4 )
7437 return false;
7438 TestAddr++;
7439 }
7440
7441 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7442
7443 return true;
7444
7445 } /* End Of mgsl_memory_test() */
7446
7447
7448 /* mgsl_load_pci_memory()
7449 *
7450 * Load a large block of data into the PCI shared memory.
7451 * Use this instead of memcpy() or memmove() to move data
7452 * into the PCI shared memory.
7453 *
7454 * Notes:
7455 *
7456 * This function prevents the PCI9050 interface chip from hogging
7457 * the adapter local bus, which can starve the 16C32 by preventing
7458 * 16C32 bus master cycles.
7459 *
7460 * The PCI9050 documentation says that the 9050 will always release
7461 * control of the local bus after completing the current read
7462 * or write operation.
7463 *
7464 * It appears that as long as the PCI9050 write FIFO is full, the
7465 * PCI9050 treats all of the writes as a single burst transaction
7466 * and will not release the bus. This causes DMA latency problems
7467 * at high speeds when copying large data blocks to the shared
7468 * memory.
7469 *
7470 * This function in effect, breaks the a large shared memory write
7471 * into multiple transations by interleaving a shared memory read
7472 * which will flush the write FIFO and 'complete' the write
7473 * transation. This allows any pending DMA request to gain control
7474 * of the local bus in a timely fasion.
7475 *
7476 * Arguments:
7477 *
7478 * TargetPtr pointer to target address in PCI shared memory
7479 * SourcePtr pointer to source buffer for data
7480 * count count in bytes of data to copy
7481 *
7482 * Return Value: None
7483 */
7484 static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7485 unsigned short count )
7486 {
7487 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7488 #define PCI_LOAD_INTERVAL 64
7489
7490 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7491 unsigned short Index;
7492 unsigned long Dummy;
7493
7494 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7495 {
7496 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7497 Dummy = *((volatile unsigned long *)TargetPtr);
7498 TargetPtr += PCI_LOAD_INTERVAL;
7499 SourcePtr += PCI_LOAD_INTERVAL;
7500 }
7501
7502 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7503
7504 } /* End Of mgsl_load_pci_memory() */
7505
7506 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7507 {
7508 int i;
7509 int linecount;
7510 if (xmit)
7511 printk("%s tx data:\n",info->device_name);
7512 else
7513 printk("%s rx data:\n",info->device_name);
7514
7515 while(count) {
7516 if (count > 16)
7517 linecount = 16;
7518 else
7519 linecount = count;
7520
7521 for(i=0;i<linecount;i++)
7522 printk("%02X ",(unsigned char)data[i]);
7523 for(;i<17;i++)
7524 printk(" ");
7525 for(i=0;i<linecount;i++) {
7526 if (data[i]>=040 && data[i]<=0176)
7527 printk("%c",data[i]);
7528 else
7529 printk(".");
7530 }
7531 printk("\n");
7532
7533 data += linecount;
7534 count -= linecount;
7535 }
7536 } /* end of mgsl_trace_block() */
7537
7538 /* mgsl_tx_timeout()
7539 *
7540 * called when HDLC frame times out
7541 * update stats and do tx completion processing
7542 *
7543 * Arguments: context pointer to device instance data
7544 * Return Value: None
7545 */
7546 static void mgsl_tx_timeout(unsigned long context)
7547 {
7548 struct mgsl_struct *info = (struct mgsl_struct*)context;
7549 unsigned long flags;
7550
7551 if ( debug_level >= DEBUG_LEVEL_INFO )
7552 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7553 __FILE__,__LINE__,info->device_name);
7554 if(info->tx_active &&
7555 (info->params.mode == MGSL_MODE_HDLC ||
7556 info->params.mode == MGSL_MODE_RAW) ) {
7557 info->icount.txtimeout++;
7558 }
7559 spin_lock_irqsave(&info->irq_spinlock,flags);
7560 info->tx_active = false;
7561 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7562
7563 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7564 usc_loopmode_cancel_transmit( info );
7565
7566 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7567
7568 #if SYNCLINK_GENERIC_HDLC
7569 if (info->netcount)
7570 hdlcdev_tx_done(info);
7571 else
7572 #endif
7573 mgsl_bh_transmit(info);
7574
7575 } /* end of mgsl_tx_timeout() */
7576
7577 /* signal that there are no more frames to send, so that
7578 * line is 'released' by echoing RxD to TxD when current
7579 * transmission is complete (or immediately if no tx in progress).
7580 */
7581 static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7582 {
7583 unsigned long flags;
7584
7585 spin_lock_irqsave(&info->irq_spinlock,flags);
7586 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7587 if (info->tx_active)
7588 info->loopmode_send_done_requested = true;
7589 else
7590 usc_loopmode_send_done(info);
7591 }
7592 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7593
7594 return 0;
7595 }
7596
7597 /* release the line by echoing RxD to TxD
7598 * upon completion of a transmit frame
7599 */
7600 static void usc_loopmode_send_done( struct mgsl_struct * info )
7601 {
7602 info->loopmode_send_done_requested = false;
7603 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7604 info->cmr_value &= ~BIT13;
7605 usc_OutReg(info, CMR, info->cmr_value);
7606 }
7607
7608 /* abort a transmit in progress while in HDLC LoopMode
7609 */
7610 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7611 {
7612 /* reset tx dma channel and purge TxFifo */
7613 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7614 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7615 usc_loopmode_send_done( info );
7616 }
7617
7618 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7619 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7620 * we must clear CMR:13 to begin repeating TxData to RxData
7621 */
7622 static void usc_loopmode_insert_request( struct mgsl_struct * info )
7623 {
7624 info->loopmode_insert_requested = true;
7625
7626 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7627 * begin repeating TxData on RxData (complete insertion)
7628 */
7629 usc_OutReg( info, RICR,
7630 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7631
7632 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7633 info->cmr_value |= BIT13;
7634 usc_OutReg(info, CMR, info->cmr_value);
7635 }
7636
7637 /* return 1 if station is inserted into the loop, otherwise 0
7638 */
7639 static int usc_loopmode_active( struct mgsl_struct * info)
7640 {
7641 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7642 }
7643
7644 #if SYNCLINK_GENERIC_HDLC
7645
7646 /**
7647 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7648 * set encoding and frame check sequence (FCS) options
7649 *
7650 * dev pointer to network device structure
7651 * encoding serial encoding setting
7652 * parity FCS setting
7653 *
7654 * returns 0 if success, otherwise error code
7655 */
7656 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7657 unsigned short parity)
7658 {
7659 struct mgsl_struct *info = dev_to_port(dev);
7660 unsigned char new_encoding;
7661 unsigned short new_crctype;
7662
7663 /* return error if TTY interface open */
7664 if (info->port.count)
7665 return -EBUSY;
7666
7667 switch (encoding)
7668 {
7669 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7670 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7671 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7672 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7673 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7674 default: return -EINVAL;
7675 }
7676
7677 switch (parity)
7678 {
7679 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7680 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7681 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7682 default: return -EINVAL;
7683 }
7684
7685 info->params.encoding = new_encoding;
7686 info->params.crc_type = new_crctype;
7687
7688 /* if network interface up, reprogram hardware */
7689 if (info->netcount)
7690 mgsl_program_hw(info);
7691
7692 return 0;
7693 }
7694
7695 /**
7696 * called by generic HDLC layer to send frame
7697 *
7698 * skb socket buffer containing HDLC frame
7699 * dev pointer to network device structure
7700 */
7701 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
7702 struct net_device *dev)
7703 {
7704 struct mgsl_struct *info = dev_to_port(dev);
7705 unsigned long flags;
7706
7707 if (debug_level >= DEBUG_LEVEL_INFO)
7708 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7709
7710 /* stop sending until this frame completes */
7711 netif_stop_queue(dev);
7712
7713 /* copy data to device buffers */
7714 info->xmit_cnt = skb->len;
7715 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7716
7717 /* update network statistics */
7718 dev->stats.tx_packets++;
7719 dev->stats.tx_bytes += skb->len;
7720
7721 /* done with socket buffer, so free it */
7722 dev_kfree_skb(skb);
7723
7724 /* save start time for transmit timeout detection */
7725 dev->trans_start = jiffies;
7726
7727 /* start hardware transmitter if necessary */
7728 spin_lock_irqsave(&info->irq_spinlock,flags);
7729 if (!info->tx_active)
7730 usc_start_transmitter(info);
7731 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7732
7733 return NETDEV_TX_OK;
7734 }
7735
7736 /**
7737 * called by network layer when interface enabled
7738 * claim resources and initialize hardware
7739 *
7740 * dev pointer to network device structure
7741 *
7742 * returns 0 if success, otherwise error code
7743 */
7744 static int hdlcdev_open(struct net_device *dev)
7745 {
7746 struct mgsl_struct *info = dev_to_port(dev);
7747 int rc;
7748 unsigned long flags;
7749
7750 if (debug_level >= DEBUG_LEVEL_INFO)
7751 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7752
7753 /* generic HDLC layer open processing */
7754 if ((rc = hdlc_open(dev)))
7755 return rc;
7756
7757 /* arbitrate between network and tty opens */
7758 spin_lock_irqsave(&info->netlock, flags);
7759 if (info->port.count != 0 || info->netcount != 0) {
7760 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7761 spin_unlock_irqrestore(&info->netlock, flags);
7762 return -EBUSY;
7763 }
7764 info->netcount=1;
7765 spin_unlock_irqrestore(&info->netlock, flags);
7766
7767 /* claim resources and init adapter */
7768 if ((rc = startup(info)) != 0) {
7769 spin_lock_irqsave(&info->netlock, flags);
7770 info->netcount=0;
7771 spin_unlock_irqrestore(&info->netlock, flags);
7772 return rc;
7773 }
7774
7775 /* assert DTR and RTS, apply hardware settings */
7776 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
7777 mgsl_program_hw(info);
7778
7779 /* enable network layer transmit */
7780 dev->trans_start = jiffies;
7781 netif_start_queue(dev);
7782
7783 /* inform generic HDLC layer of current DCD status */
7784 spin_lock_irqsave(&info->irq_spinlock, flags);
7785 usc_get_serial_signals(info);
7786 spin_unlock_irqrestore(&info->irq_spinlock, flags);
7787 if (info->serial_signals & SerialSignal_DCD)
7788 netif_carrier_on(dev);
7789 else
7790 netif_carrier_off(dev);
7791 return 0;
7792 }
7793
7794 /**
7795 * called by network layer when interface is disabled
7796 * shutdown hardware and release resources
7797 *
7798 * dev pointer to network device structure
7799 *
7800 * returns 0 if success, otherwise error code
7801 */
7802 static int hdlcdev_close(struct net_device *dev)
7803 {
7804 struct mgsl_struct *info = dev_to_port(dev);
7805 unsigned long flags;
7806
7807 if (debug_level >= DEBUG_LEVEL_INFO)
7808 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7809
7810 netif_stop_queue(dev);
7811
7812 /* shutdown adapter and release resources */
7813 shutdown(info);
7814
7815 hdlc_close(dev);
7816
7817 spin_lock_irqsave(&info->netlock, flags);
7818 info->netcount=0;
7819 spin_unlock_irqrestore(&info->netlock, flags);
7820
7821 return 0;
7822 }
7823
7824 /**
7825 * called by network layer to process IOCTL call to network device
7826 *
7827 * dev pointer to network device structure
7828 * ifr pointer to network interface request structure
7829 * cmd IOCTL command code
7830 *
7831 * returns 0 if success, otherwise error code
7832 */
7833 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7834 {
7835 const size_t size = sizeof(sync_serial_settings);
7836 sync_serial_settings new_line;
7837 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7838 struct mgsl_struct *info = dev_to_port(dev);
7839 unsigned int flags;
7840
7841 if (debug_level >= DEBUG_LEVEL_INFO)
7842 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7843
7844 /* return error if TTY interface open */
7845 if (info->port.count)
7846 return -EBUSY;
7847
7848 if (cmd != SIOCWANDEV)
7849 return hdlc_ioctl(dev, ifr, cmd);
7850
7851 switch(ifr->ifr_settings.type) {
7852 case IF_GET_IFACE: /* return current sync_serial_settings */
7853
7854 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7855 if (ifr->ifr_settings.size < size) {
7856 ifr->ifr_settings.size = size; /* data size wanted */
7857 return -ENOBUFS;
7858 }
7859
7860 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7861 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7862 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7863 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7864
7865 switch (flags){
7866 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7867 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7868 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7869 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7870 default: new_line.clock_type = CLOCK_DEFAULT;
7871 }
7872
7873 new_line.clock_rate = info->params.clock_speed;
7874 new_line.loopback = info->params.loopback ? 1:0;
7875
7876 if (copy_to_user(line, &new_line, size))
7877 return -EFAULT;
7878 return 0;
7879
7880 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
7881
7882 if(!capable(CAP_NET_ADMIN))
7883 return -EPERM;
7884 if (copy_from_user(&new_line, line, size))
7885 return -EFAULT;
7886
7887 switch (new_line.clock_type)
7888 {
7889 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7890 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7891 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7892 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7893 case CLOCK_DEFAULT: flags = info->params.flags &
7894 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7895 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7896 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7897 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
7898 default: return -EINVAL;
7899 }
7900
7901 if (new_line.loopback != 0 && new_line.loopback != 1)
7902 return -EINVAL;
7903
7904 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7905 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7906 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7907 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7908 info->params.flags |= flags;
7909
7910 info->params.loopback = new_line.loopback;
7911
7912 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
7913 info->params.clock_speed = new_line.clock_rate;
7914 else
7915 info->params.clock_speed = 0;
7916
7917 /* if network interface up, reprogram hardware */
7918 if (info->netcount)
7919 mgsl_program_hw(info);
7920 return 0;
7921
7922 default:
7923 return hdlc_ioctl(dev, ifr, cmd);
7924 }
7925 }
7926
7927 /**
7928 * called by network layer when transmit timeout is detected
7929 *
7930 * dev pointer to network device structure
7931 */
7932 static void hdlcdev_tx_timeout(struct net_device *dev)
7933 {
7934 struct mgsl_struct *info = dev_to_port(dev);
7935 unsigned long flags;
7936
7937 if (debug_level >= DEBUG_LEVEL_INFO)
7938 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
7939
7940 dev->stats.tx_errors++;
7941 dev->stats.tx_aborted_errors++;
7942
7943 spin_lock_irqsave(&info->irq_spinlock,flags);
7944 usc_stop_transmitter(info);
7945 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7946
7947 netif_wake_queue(dev);
7948 }
7949
7950 /**
7951 * called by device driver when transmit completes
7952 * reenable network layer transmit if stopped
7953 *
7954 * info pointer to device instance information
7955 */
7956 static void hdlcdev_tx_done(struct mgsl_struct *info)
7957 {
7958 if (netif_queue_stopped(info->netdev))
7959 netif_wake_queue(info->netdev);
7960 }
7961
7962 /**
7963 * called by device driver when frame received
7964 * pass frame to network layer
7965 *
7966 * info pointer to device instance information
7967 * buf pointer to buffer contianing frame data
7968 * size count of data bytes in buf
7969 */
7970 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
7971 {
7972 struct sk_buff *skb = dev_alloc_skb(size);
7973 struct net_device *dev = info->netdev;
7974
7975 if (debug_level >= DEBUG_LEVEL_INFO)
7976 printk("hdlcdev_rx(%s)\n", dev->name);
7977
7978 if (skb == NULL) {
7979 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
7980 dev->name);
7981 dev->stats.rx_dropped++;
7982 return;
7983 }
7984
7985 memcpy(skb_put(skb, size), buf, size);
7986
7987 skb->protocol = hdlc_type_trans(skb, dev);
7988
7989 dev->stats.rx_packets++;
7990 dev->stats.rx_bytes += size;
7991
7992 netif_rx(skb);
7993 }
7994
7995 static const struct net_device_ops hdlcdev_ops = {
7996 .ndo_open = hdlcdev_open,
7997 .ndo_stop = hdlcdev_close,
7998 .ndo_change_mtu = hdlc_change_mtu,
7999 .ndo_start_xmit = hdlc_start_xmit,
8000 .ndo_do_ioctl = hdlcdev_ioctl,
8001 .ndo_tx_timeout = hdlcdev_tx_timeout,
8002 };
8003
8004 /**
8005 * called by device driver when adding device instance
8006 * do generic HDLC initialization
8007 *
8008 * info pointer to device instance information
8009 *
8010 * returns 0 if success, otherwise error code
8011 */
8012 static int hdlcdev_init(struct mgsl_struct *info)
8013 {
8014 int rc;
8015 struct net_device *dev;
8016 hdlc_device *hdlc;
8017
8018 /* allocate and initialize network and HDLC layer objects */
8019
8020 if (!(dev = alloc_hdlcdev(info))) {
8021 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8022 return -ENOMEM;
8023 }
8024
8025 /* for network layer reporting purposes only */
8026 dev->base_addr = info->io_base;
8027 dev->irq = info->irq_level;
8028 dev->dma = info->dma_level;
8029
8030 /* network layer callbacks and settings */
8031 dev->netdev_ops = &hdlcdev_ops;
8032 dev->watchdog_timeo = 10 * HZ;
8033 dev->tx_queue_len = 50;
8034
8035 /* generic HDLC layer callbacks and settings */
8036 hdlc = dev_to_hdlc(dev);
8037 hdlc->attach = hdlcdev_attach;
8038 hdlc->xmit = hdlcdev_xmit;
8039
8040 /* register objects with HDLC layer */
8041 if ((rc = register_hdlc_device(dev))) {
8042 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8043 free_netdev(dev);
8044 return rc;
8045 }
8046
8047 info->netdev = dev;
8048 return 0;
8049 }
8050
8051 /**
8052 * called by device driver when removing device instance
8053 * do generic HDLC cleanup
8054 *
8055 * info pointer to device instance information
8056 */
8057 static void hdlcdev_exit(struct mgsl_struct *info)
8058 {
8059 unregister_hdlc_device(info->netdev);
8060 free_netdev(info->netdev);
8061 info->netdev = NULL;
8062 }
8063
8064 #endif /* CONFIG_HDLC */
8065
8066
8067 static int __devinit synclink_init_one (struct pci_dev *dev,
8068 const struct pci_device_id *ent)
8069 {
8070 struct mgsl_struct *info;
8071
8072 if (pci_enable_device(dev)) {
8073 printk("error enabling pci device %p\n", dev);
8074 return -EIO;
8075 }
8076
8077 if (!(info = mgsl_allocate_device())) {
8078 printk("can't allocate device instance data.\n");
8079 return -EIO;
8080 }
8081
8082 /* Copy user configuration info to device instance data */
8083
8084 info->io_base = pci_resource_start(dev, 2);
8085 info->irq_level = dev->irq;
8086 info->phys_memory_base = pci_resource_start(dev, 3);
8087
8088 /* Because veremap only works on page boundaries we must map
8089 * a larger area than is actually implemented for the LCR
8090 * memory range. We map a full page starting at the page boundary.
8091 */
8092 info->phys_lcr_base = pci_resource_start(dev, 0);
8093 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8094 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8095
8096 info->bus_type = MGSL_BUS_TYPE_PCI;
8097 info->io_addr_size = 8;
8098 info->irq_flags = IRQF_SHARED;
8099
8100 if (dev->device == 0x0210) {
8101 /* Version 1 PCI9030 based universal PCI adapter */
8102 info->misc_ctrl_value = 0x007c4080;
8103 info->hw_version = 1;
8104 } else {
8105 /* Version 0 PCI9050 based 5V PCI adapter
8106 * A PCI9050 bug prevents reading LCR registers if
8107 * LCR base address bit 7 is set. Maintain shadow
8108 * value so we can write to LCR misc control reg.
8109 */
8110 info->misc_ctrl_value = 0x087e4546;
8111 info->hw_version = 0;
8112 }
8113
8114 mgsl_add_device(info);
8115
8116 return 0;
8117 }
8118
8119 static void __devexit synclink_remove_one (struct pci_dev *dev)
8120 {
8121 }
8122
Linux with added FPC-III support