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x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / i915_suspend.c
blob992d5617e79829d4a7586d81f4e4579a0de8c251
1 /*
2 *
3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27 #include "drmP.h"
28 #include "drm.h"
29 #include "i915_drm.h"
30 #include "i915_drv.h"
31
32 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
33 {
34 struct drm_i915_private *dev_priv = dev->dev_private;
35 u32 dpll_reg;
36
37 if (IS_IGDNG(dev)) {
38 dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B;
39 } else {
40 dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B;
41 }
42
43 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
44 }
45
46 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
47 {
48 struct drm_i915_private *dev_priv = dev->dev_private;
49 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
50 u32 *array;
51 int i;
52
53 if (!i915_pipe_enabled(dev, pipe))
54 return;
55
56 if (IS_IGDNG(dev))
57 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
58
59 if (pipe == PIPE_A)
60 array = dev_priv->save_palette_a;
61 else
62 array = dev_priv->save_palette_b;
63
64 for(i = 0; i < 256; i++)
65 array[i] = I915_READ(reg + (i << 2));
66 }
67
68 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
69 {
70 struct drm_i915_private *dev_priv = dev->dev_private;
71 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
72 u32 *array;
73 int i;
74
75 if (!i915_pipe_enabled(dev, pipe))
76 return;
77
78 if (IS_IGDNG(dev))
79 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
80
81 if (pipe == PIPE_A)
82 array = dev_priv->save_palette_a;
83 else
84 array = dev_priv->save_palette_b;
85
86 for(i = 0; i < 256; i++)
87 I915_WRITE(reg + (i << 2), array[i]);
88 }
89
90 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
91 {
92 struct drm_i915_private *dev_priv = dev->dev_private;
93
94 I915_WRITE8(index_port, reg);
95 return I915_READ8(data_port);
96 }
97
98 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
99 {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 I915_READ8(st01);
103 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
104 return I915_READ8(VGA_AR_DATA_READ);
105 }
106
107 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
108 {
109 struct drm_i915_private *dev_priv = dev->dev_private;
110
111 I915_READ8(st01);
112 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
113 I915_WRITE8(VGA_AR_DATA_WRITE, val);
114 }
115
116 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
117 {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119
120 I915_WRITE8(index_port, reg);
121 I915_WRITE8(data_port, val);
122 }
123
124 static void i915_save_vga(struct drm_device *dev)
125 {
126 struct drm_i915_private *dev_priv = dev->dev_private;
127 int i;
128 u16 cr_index, cr_data, st01;
129
130 /* VGA color palette registers */
131 dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
132
133 /* MSR bits */
134 dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
135 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
136 cr_index = VGA_CR_INDEX_CGA;
137 cr_data = VGA_CR_DATA_CGA;
138 st01 = VGA_ST01_CGA;
139 } else {
140 cr_index = VGA_CR_INDEX_MDA;
141 cr_data = VGA_CR_DATA_MDA;
142 st01 = VGA_ST01_MDA;
143 }
144
145 /* CRT controller regs */
146 i915_write_indexed(dev, cr_index, cr_data, 0x11,
147 i915_read_indexed(dev, cr_index, cr_data, 0x11) &
148 (~0x80));
149 for (i = 0; i <= 0x24; i++)
150 dev_priv->saveCR[i] =
151 i915_read_indexed(dev, cr_index, cr_data, i);
152 /* Make sure we don't turn off CR group 0 writes */
153 dev_priv->saveCR[0x11] &= ~0x80;
154
155 /* Attribute controller registers */
156 I915_READ8(st01);
157 dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
158 for (i = 0; i <= 0x14; i++)
159 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
160 I915_READ8(st01);
161 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
162 I915_READ8(st01);
163
164 /* Graphics controller registers */
165 for (i = 0; i < 9; i++)
166 dev_priv->saveGR[i] =
167 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
168
169 dev_priv->saveGR[0x10] =
170 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
171 dev_priv->saveGR[0x11] =
172 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
173 dev_priv->saveGR[0x18] =
174 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
175
176 /* Sequencer registers */
177 for (i = 0; i < 8; i++)
178 dev_priv->saveSR[i] =
179 i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
180 }
181
182 static void i915_restore_vga(struct drm_device *dev)
183 {
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 int i;
186 u16 cr_index, cr_data, st01;
187
188 /* MSR bits */
189 I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
190 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
191 cr_index = VGA_CR_INDEX_CGA;
192 cr_data = VGA_CR_DATA_CGA;
193 st01 = VGA_ST01_CGA;
194 } else {
195 cr_index = VGA_CR_INDEX_MDA;
196 cr_data = VGA_CR_DATA_MDA;
197 st01 = VGA_ST01_MDA;
198 }
199
200 /* Sequencer registers, don't write SR07 */
201 for (i = 0; i < 7; i++)
202 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
203 dev_priv->saveSR[i]);
204
205 /* CRT controller regs */
206 /* Enable CR group 0 writes */
207 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
208 for (i = 0; i <= 0x24; i++)
209 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
210
211 /* Graphics controller regs */
212 for (i = 0; i < 9; i++)
213 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
214 dev_priv->saveGR[i]);
215
216 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
217 dev_priv->saveGR[0x10]);
218 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
219 dev_priv->saveGR[0x11]);
220 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
221 dev_priv->saveGR[0x18]);
222
223 /* Attribute controller registers */
224 I915_READ8(st01); /* switch back to index mode */
225 for (i = 0; i <= 0x14; i++)
226 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
227 I915_READ8(st01); /* switch back to index mode */
228 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
229 I915_READ8(st01);
230
231 /* VGA color palette registers */
232 I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
233 }
234
235 static void i915_save_modeset_reg(struct drm_device *dev)
236 {
237 struct drm_i915_private *dev_priv = dev->dev_private;
238
239 if (drm_core_check_feature(dev, DRIVER_MODESET))
240 return;
241
242 /* Pipe & plane A info */
243 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
244 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
245 if (IS_IGDNG(dev)) {
246 dev_priv->saveFPA0 = I915_READ(PCH_FPA0);
247 dev_priv->saveFPA1 = I915_READ(PCH_FPA1);
248 dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A);
249 } else {
250 dev_priv->saveFPA0 = I915_READ(FPA0);
251 dev_priv->saveFPA1 = I915_READ(FPA1);
252 dev_priv->saveDPLL_A = I915_READ(DPLL_A);
253 }
254 if (IS_I965G(dev) && !IS_IGDNG(dev))
255 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
256 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
257 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
258 dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
259 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
260 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
261 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
262 if (!IS_IGDNG(dev))
263 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
264
265 if (IS_IGDNG(dev)) {
266 dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL);
267 dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL);
268
269 dev_priv->savePFA_CTL_1 = I915_READ(PFA_CTL_1);
270 dev_priv->savePFA_WIN_SZ = I915_READ(PFA_WIN_SZ);
271 dev_priv->savePFA_WIN_POS = I915_READ(PFA_WIN_POS);
272
273 dev_priv->saveTRANS_HTOTAL_A = I915_READ(TRANS_HTOTAL_A);
274 dev_priv->saveTRANS_HBLANK_A = I915_READ(TRANS_HBLANK_A);
275 dev_priv->saveTRANS_HSYNC_A = I915_READ(TRANS_HSYNC_A);
276 dev_priv->saveTRANS_VTOTAL_A = I915_READ(TRANS_VTOTAL_A);
277 dev_priv->saveTRANS_VBLANK_A = I915_READ(TRANS_VBLANK_A);
278 dev_priv->saveTRANS_VSYNC_A = I915_READ(TRANS_VSYNC_A);
279 }
280
281 dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
282 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
283 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
284 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
285 dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
286 if (IS_I965G(dev)) {
287 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
288 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
289 }
290 i915_save_palette(dev, PIPE_A);
291 dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
292
293 /* Pipe & plane B info */
294 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
295 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
296 if (IS_IGDNG(dev)) {
297 dev_priv->saveFPB0 = I915_READ(PCH_FPB0);
298 dev_priv->saveFPB1 = I915_READ(PCH_FPB1);
299 dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B);
300 } else {
301 dev_priv->saveFPB0 = I915_READ(FPB0);
302 dev_priv->saveFPB1 = I915_READ(FPB1);
303 dev_priv->saveDPLL_B = I915_READ(DPLL_B);
304 }
305 if (IS_I965G(dev) && !IS_IGDNG(dev))
306 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
307 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
308 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
309 dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
310 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
311 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
312 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
313 if (!IS_IGDNG(dev))
314 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B);
315
316 if (IS_IGDNG(dev)) {
317 dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL);
318 dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL);
319
320 dev_priv->savePFB_CTL_1 = I915_READ(PFB_CTL_1);
321 dev_priv->savePFB_WIN_SZ = I915_READ(PFB_WIN_SZ);
322 dev_priv->savePFB_WIN_POS = I915_READ(PFB_WIN_POS);
323
324 dev_priv->saveTRANS_HTOTAL_B = I915_READ(TRANS_HTOTAL_B);
325 dev_priv->saveTRANS_HBLANK_B = I915_READ(TRANS_HBLANK_B);
326 dev_priv->saveTRANS_HSYNC_B = I915_READ(TRANS_HSYNC_B);
327 dev_priv->saveTRANS_VTOTAL_B = I915_READ(TRANS_VTOTAL_B);
328 dev_priv->saveTRANS_VBLANK_B = I915_READ(TRANS_VBLANK_B);
329 dev_priv->saveTRANS_VSYNC_B = I915_READ(TRANS_VSYNC_B);
330 }
331
332 dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
333 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
334 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
335 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
336 dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
337 if (IS_I965GM(dev) || IS_GM45(dev)) {
338 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
339 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
340 }
341 i915_save_palette(dev, PIPE_B);
342 dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
343 return;
344 }
345
346 static void i915_restore_modeset_reg(struct drm_device *dev)
347 {
348 struct drm_i915_private *dev_priv = dev->dev_private;
349 int dpll_a_reg, fpa0_reg, fpa1_reg;
350 int dpll_b_reg, fpb0_reg, fpb1_reg;
351
352 if (drm_core_check_feature(dev, DRIVER_MODESET))
353 return;
354
355 if (IS_IGDNG(dev)) {
356 dpll_a_reg = PCH_DPLL_A;
357 dpll_b_reg = PCH_DPLL_B;
358 fpa0_reg = PCH_FPA0;
359 fpb0_reg = PCH_FPB0;
360 fpa1_reg = PCH_FPA1;
361 fpb1_reg = PCH_FPB1;
362 } else {
363 dpll_a_reg = DPLL_A;
364 dpll_b_reg = DPLL_B;
365 fpa0_reg = FPA0;
366 fpb0_reg = FPB0;
367 fpa1_reg = FPA1;
368 fpb1_reg = FPB1;
369 }
370
371 /* Pipe & plane A info */
372 /* Prime the clock */
373 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
374 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
375 ~DPLL_VCO_ENABLE);
376 DRM_UDELAY(150);
377 }
378 I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
379 I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
380 /* Actually enable it */
381 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
382 DRM_UDELAY(150);
383 if (IS_I965G(dev) && !IS_IGDNG(dev))
384 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
385 DRM_UDELAY(150);
386
387 /* Restore mode */
388 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
389 I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
390 I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
391 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
392 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
393 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
394 if (!IS_IGDNG(dev))
395 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
396
397 if (IS_IGDNG(dev)) {
398 I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
399 I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
400
401 I915_WRITE(PFA_CTL_1, dev_priv->savePFA_CTL_1);
402 I915_WRITE(PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
403 I915_WRITE(PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
404
405 I915_WRITE(TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
406 I915_WRITE(TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
407 I915_WRITE(TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
408 I915_WRITE(TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
409 I915_WRITE(TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
410 I915_WRITE(TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
411 }
412
413 /* Restore plane info */
414 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
415 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
416 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
417 I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
418 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
419 if (IS_I965G(dev)) {
420 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
421 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
422 }
423
424 I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
425
426 i915_restore_palette(dev, PIPE_A);
427 /* Enable the plane */
428 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
429 I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
430
431 /* Pipe & plane B info */
432 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
433 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
434 ~DPLL_VCO_ENABLE);
435 DRM_UDELAY(150);
436 }
437 I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
438 I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
439 /* Actually enable it */
440 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
441 DRM_UDELAY(150);
442 if (IS_I965G(dev))
443 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
444 DRM_UDELAY(150);
445
446 /* Restore mode */
447 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
448 I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
449 I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
450 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
451 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
452 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
453 if (!IS_IGDNG(dev))
454 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
455
456 if (IS_IGDNG(dev)) {
457 I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
458 I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
459
460 I915_WRITE(PFB_CTL_1, dev_priv->savePFB_CTL_1);
461 I915_WRITE(PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
462 I915_WRITE(PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
463
464 I915_WRITE(TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
465 I915_WRITE(TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
466 I915_WRITE(TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
467 I915_WRITE(TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
468 I915_WRITE(TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
469 I915_WRITE(TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
470 }
471
472 /* Restore plane info */
473 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
474 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
475 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
476 I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
477 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
478 if (IS_I965G(dev)) {
479 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
480 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
481 }
482
483 I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
484
485 i915_restore_palette(dev, PIPE_B);
486 /* Enable the plane */
487 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
488 I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
489
490 return;
491 }
492
493 void i915_save_display(struct drm_device *dev)
494 {
495 struct drm_i915_private *dev_priv = dev->dev_private;
496
497 /* Display arbitration control */
498 dev_priv->saveDSPARB = I915_READ(DSPARB);
499
500 /* This is only meaningful in non-KMS mode */
501 /* Don't save them in KMS mode */
502 i915_save_modeset_reg(dev);
503
504 /* Cursor state */
505 dev_priv->saveCURACNTR = I915_READ(CURACNTR);
506 dev_priv->saveCURAPOS = I915_READ(CURAPOS);
507 dev_priv->saveCURABASE = I915_READ(CURABASE);
508 dev_priv->saveCURBCNTR = I915_READ(CURBCNTR);
509 dev_priv->saveCURBPOS = I915_READ(CURBPOS);
510 dev_priv->saveCURBBASE = I915_READ(CURBBASE);
511 if (!IS_I9XX(dev))
512 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
513
514 /* CRT state */
515 if (IS_IGDNG(dev)) {
516 dev_priv->saveADPA = I915_READ(PCH_ADPA);
517 } else {
518 dev_priv->saveADPA = I915_READ(ADPA);
519 }
520
521 /* LVDS state */
522 if (IS_IGDNG(dev)) {
523 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
524 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
525 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
526 dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
527 dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
528 dev_priv->saveLVDS = I915_READ(PCH_LVDS);
529 } else {
530 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
531 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
532 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
533 dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
534 if (IS_I965G(dev))
535 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
536 if (IS_MOBILE(dev) && !IS_I830(dev))
537 dev_priv->saveLVDS = I915_READ(LVDS);
538 }
539
540 if (!IS_I830(dev) && !IS_845G(dev) && !IS_IGDNG(dev))
541 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
542
543 if (IS_IGDNG(dev)) {
544 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
545 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
546 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
547 } else {
548 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
549 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
550 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
551 }
552
553 /* Display Port state */
554 if (SUPPORTS_INTEGRATED_DP(dev)) {
555 dev_priv->saveDP_B = I915_READ(DP_B);
556 dev_priv->saveDP_C = I915_READ(DP_C);
557 dev_priv->saveDP_D = I915_READ(DP_D);
558 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(PIPEA_GMCH_DATA_M);
559 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(PIPEB_GMCH_DATA_M);
560 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(PIPEA_GMCH_DATA_N);
561 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(PIPEB_GMCH_DATA_N);
562 dev_priv->savePIPEA_DP_LINK_M = I915_READ(PIPEA_DP_LINK_M);
563 dev_priv->savePIPEB_DP_LINK_M = I915_READ(PIPEB_DP_LINK_M);
564 dev_priv->savePIPEA_DP_LINK_N = I915_READ(PIPEA_DP_LINK_N);
565 dev_priv->savePIPEB_DP_LINK_N = I915_READ(PIPEB_DP_LINK_N);
566 }
567 /* FIXME: save TV & SDVO state */
568
569 /* FBC state */
570 if (IS_GM45(dev)) {
571 dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
572 } else {
573 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
574 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
575 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
576 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
577 }
578
579 /* VGA state */
580 dev_priv->saveVGA0 = I915_READ(VGA0);
581 dev_priv->saveVGA1 = I915_READ(VGA1);
582 dev_priv->saveVGA_PD = I915_READ(VGA_PD);
583 if (IS_IGDNG(dev))
584 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);
585 else
586 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
587
588 i915_save_vga(dev);
589 }
590
591 void i915_restore_display(struct drm_device *dev)
592 {
593 struct drm_i915_private *dev_priv = dev->dev_private;
594
595 /* Display arbitration */
596 I915_WRITE(DSPARB, dev_priv->saveDSPARB);
597
598 /* Display port ratios (must be done before clock is set) */
599 if (SUPPORTS_INTEGRATED_DP(dev)) {
600 I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
601 I915_WRITE(PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
602 I915_WRITE(PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
603 I915_WRITE(PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
604 I915_WRITE(PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
605 I915_WRITE(PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
606 I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
607 I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
608 }
609
610 /* This is only meaningful in non-KMS mode */
611 /* Don't restore them in KMS mode */
612 i915_restore_modeset_reg(dev);
613
614 /* Cursor state */
615 I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
616 I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
617 I915_WRITE(CURABASE, dev_priv->saveCURABASE);
618 I915_WRITE(CURBPOS, dev_priv->saveCURBPOS);
619 I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR);
620 I915_WRITE(CURBBASE, dev_priv->saveCURBBASE);
621 if (!IS_I9XX(dev))
622 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
623
624 /* CRT state */
625 if (IS_IGDNG(dev))
626 I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
627 else
628 I915_WRITE(ADPA, dev_priv->saveADPA);
629
630 /* LVDS state */
631 if (IS_I965G(dev) && !IS_IGDNG(dev))
632 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
633
634 if (IS_IGDNG(dev)) {
635 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS);
636 } else if (IS_MOBILE(dev) && !IS_I830(dev))
637 I915_WRITE(LVDS, dev_priv->saveLVDS);
638
639 if (!IS_I830(dev) && !IS_845G(dev) && !IS_IGDNG(dev))
640 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
641
642 if (IS_IGDNG(dev)) {
643 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
644 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
645 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
646 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
647 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
648 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
649 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
650 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
651 } else {
652 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
653 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
654 I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL);
655 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
656 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
657 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
658 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
659 }
660
661 /* Display Port state */
662 if (SUPPORTS_INTEGRATED_DP(dev)) {
663 I915_WRITE(DP_B, dev_priv->saveDP_B);
664 I915_WRITE(DP_C, dev_priv->saveDP_C);
665 I915_WRITE(DP_D, dev_priv->saveDP_D);
666 }
667 /* FIXME: restore TV & SDVO state */
668
669 /* FBC info */
670 if (IS_GM45(dev)) {
671 g4x_disable_fbc(dev);
672 I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
673 } else {
674 i8xx_disable_fbc(dev);
675 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
676 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
677 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
678 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
679 }
680
681 /* VGA state */
682 if (IS_IGDNG(dev))
683 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
684 else
685 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
686 I915_WRITE(VGA0, dev_priv->saveVGA0);
687 I915_WRITE(VGA1, dev_priv->saveVGA1);
688 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
689 DRM_UDELAY(150);
690
691 i915_restore_vga(dev);
692 }
693
694 int i915_save_state(struct drm_device *dev)
695 {
696 struct drm_i915_private *dev_priv = dev->dev_private;
697 int i;
698
699 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
700
701 /* Render Standby */
702 if (IS_I965G(dev) && IS_MOBILE(dev))
703 dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
704
705 /* Hardware status page */
706 dev_priv->saveHWS = I915_READ(HWS_PGA);
707
708 i915_save_display(dev);
709
710 /* Interrupt state */
711 if (IS_IGDNG(dev)) {
712 dev_priv->saveDEIER = I915_READ(DEIER);
713 dev_priv->saveDEIMR = I915_READ(DEIMR);
714 dev_priv->saveGTIER = I915_READ(GTIER);
715 dev_priv->saveGTIMR = I915_READ(GTIMR);
716 dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR);
717 dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR);
718 } else {
719 dev_priv->saveIER = I915_READ(IER);
720 dev_priv->saveIMR = I915_READ(IMR);
721 }
722
723 /* Clock gating state */
724 dev_priv->saveD_STATE = I915_READ(D_STATE);
725 dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); /* Not sure about this */
726
727 /* Cache mode state */
728 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
729
730 /* Memory Arbitration state */
731 dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
732
733 /* Scratch space */
734 for (i = 0; i < 16; i++) {
735 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
736 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
737 }
738 for (i = 0; i < 3; i++)
739 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
740
741 /* Fences */
742 if (IS_I965G(dev)) {
743 for (i = 0; i < 16; i++)
744 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
745 } else {
746 for (i = 0; i < 8; i++)
747 dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
748
749 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
750 for (i = 0; i < 8; i++)
751 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
752 }
753
754 return 0;
755 }
756
757 int i915_restore_state(struct drm_device *dev)
758 {
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 int i;
761
762 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
763
764 /* Render Standby */
765 if (IS_I965G(dev) && IS_MOBILE(dev))
766 I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
767
768 /* Hardware status page */
769 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
770
771 /* Fences */
772 if (IS_I965G(dev)) {
773 for (i = 0; i < 16; i++)
774 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
775 } else {
776 for (i = 0; i < 8; i++)
777 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
778 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
779 for (i = 0; i < 8; i++)
780 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
781 }
782
783 i915_restore_display(dev);
784
785 /* Interrupt state */
786 if (IS_IGDNG(dev)) {
787 I915_WRITE(DEIER, dev_priv->saveDEIER);
788 I915_WRITE(DEIMR, dev_priv->saveDEIMR);
789 I915_WRITE(GTIER, dev_priv->saveGTIER);
790 I915_WRITE(GTIMR, dev_priv->saveGTIMR);
791 I915_WRITE(FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
792 I915_WRITE(FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
793 } else {
794 I915_WRITE (IER, dev_priv->saveIER);
795 I915_WRITE (IMR, dev_priv->saveIMR);
796 }
797
798 /* Clock gating state */
799 I915_WRITE (D_STATE, dev_priv->saveD_STATE);
800 I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
801
802 /* Cache mode state */
803 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
804
805 /* Memory arbitration state */
806 I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
807
808 for (i = 0; i < 16; i++) {
809 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
810 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
811 }
812 for (i = 0; i < 3; i++)
813 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
814
815 return 0;
816 }
817
Linux with added FPC-III support