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x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_display.c
blob3ba6546b7c7f6875938ac8bc9b7345a4ca3ac200
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include "drmP.h"
32 #include "intel_drv.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "intel_dp.h"
36
37 #include "drm_crtc_helper.h"
38
39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
40
41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
42 static void intel_update_watermarks(struct drm_device *dev);
43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
44
45 typedef struct {
46 /* given values */
47 int n;
48 int m1, m2;
49 int p1, p2;
50 /* derived values */
51 int dot;
52 int vco;
53 int m;
54 int p;
55 } intel_clock_t;
56
57 typedef struct {
58 int min, max;
59 } intel_range_t;
60
61 typedef struct {
62 int dot_limit;
63 int p2_slow, p2_fast;
64 } intel_p2_t;
65
66 #define INTEL_P2_NUM 2
67 typedef struct intel_limit intel_limit_t;
68 struct intel_limit {
69 intel_range_t dot, vco, n, m, m1, m2, p, p1;
70 intel_p2_t p2;
71 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
72 int, int, intel_clock_t *);
73 bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
74 int, int, intel_clock_t *);
75 };
76
77 #define I8XX_DOT_MIN 25000
78 #define I8XX_DOT_MAX 350000
79 #define I8XX_VCO_MIN 930000
80 #define I8XX_VCO_MAX 1400000
81 #define I8XX_N_MIN 3
82 #define I8XX_N_MAX 16
83 #define I8XX_M_MIN 96
84 #define I8XX_M_MAX 140
85 #define I8XX_M1_MIN 18
86 #define I8XX_M1_MAX 26
87 #define I8XX_M2_MIN 6
88 #define I8XX_M2_MAX 16
89 #define I8XX_P_MIN 4
90 #define I8XX_P_MAX 128
91 #define I8XX_P1_MIN 2
92 #define I8XX_P1_MAX 33
93 #define I8XX_P1_LVDS_MIN 1
94 #define I8XX_P1_LVDS_MAX 6
95 #define I8XX_P2_SLOW 4
96 #define I8XX_P2_FAST 2
97 #define I8XX_P2_LVDS_SLOW 14
98 #define I8XX_P2_LVDS_FAST 7
99 #define I8XX_P2_SLOW_LIMIT 165000
100
101 #define I9XX_DOT_MIN 20000
102 #define I9XX_DOT_MAX 400000
103 #define I9XX_VCO_MIN 1400000
104 #define I9XX_VCO_MAX 2800000
105 #define IGD_VCO_MIN 1700000
106 #define IGD_VCO_MAX 3500000
107 #define I9XX_N_MIN 1
108 #define I9XX_N_MAX 6
109 /* IGD's Ncounter is a ring counter */
110 #define IGD_N_MIN 3
111 #define IGD_N_MAX 6
112 #define I9XX_M_MIN 70
113 #define I9XX_M_MAX 120
114 #define IGD_M_MIN 2
115 #define IGD_M_MAX 256
116 #define I9XX_M1_MIN 10
117 #define I9XX_M1_MAX 22
118 #define I9XX_M2_MIN 5
119 #define I9XX_M2_MAX 9
120 /* IGD M1 is reserved, and must be 0 */
121 #define IGD_M1_MIN 0
122 #define IGD_M1_MAX 0
123 #define IGD_M2_MIN 0
124 #define IGD_M2_MAX 254
125 #define I9XX_P_SDVO_DAC_MIN 5
126 #define I9XX_P_SDVO_DAC_MAX 80
127 #define I9XX_P_LVDS_MIN 7
128 #define I9XX_P_LVDS_MAX 98
129 #define IGD_P_LVDS_MIN 7
130 #define IGD_P_LVDS_MAX 112
131 #define I9XX_P1_MIN 1
132 #define I9XX_P1_MAX 8
133 #define I9XX_P2_SDVO_DAC_SLOW 10
134 #define I9XX_P2_SDVO_DAC_FAST 5
135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
136 #define I9XX_P2_LVDS_SLOW 14
137 #define I9XX_P2_LVDS_FAST 7
138 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
139
140 /*The parameter is for SDVO on G4x platform*/
141 #define G4X_DOT_SDVO_MIN 25000
142 #define G4X_DOT_SDVO_MAX 270000
143 #define G4X_VCO_MIN 1750000
144 #define G4X_VCO_MAX 3500000
145 #define G4X_N_SDVO_MIN 1
146 #define G4X_N_SDVO_MAX 4
147 #define G4X_M_SDVO_MIN 104
148 #define G4X_M_SDVO_MAX 138
149 #define G4X_M1_SDVO_MIN 17
150 #define G4X_M1_SDVO_MAX 23
151 #define G4X_M2_SDVO_MIN 5
152 #define G4X_M2_SDVO_MAX 11
153 #define G4X_P_SDVO_MIN 10
154 #define G4X_P_SDVO_MAX 30
155 #define G4X_P1_SDVO_MIN 1
156 #define G4X_P1_SDVO_MAX 3
157 #define G4X_P2_SDVO_SLOW 10
158 #define G4X_P2_SDVO_FAST 10
159 #define G4X_P2_SDVO_LIMIT 270000
160
161 /*The parameter is for HDMI_DAC on G4x platform*/
162 #define G4X_DOT_HDMI_DAC_MIN 22000
163 #define G4X_DOT_HDMI_DAC_MAX 400000
164 #define G4X_N_HDMI_DAC_MIN 1
165 #define G4X_N_HDMI_DAC_MAX 4
166 #define G4X_M_HDMI_DAC_MIN 104
167 #define G4X_M_HDMI_DAC_MAX 138
168 #define G4X_M1_HDMI_DAC_MIN 16
169 #define G4X_M1_HDMI_DAC_MAX 23
170 #define G4X_M2_HDMI_DAC_MIN 5
171 #define G4X_M2_HDMI_DAC_MAX 11
172 #define G4X_P_HDMI_DAC_MIN 5
173 #define G4X_P_HDMI_DAC_MAX 80
174 #define G4X_P1_HDMI_DAC_MIN 1
175 #define G4X_P1_HDMI_DAC_MAX 8
176 #define G4X_P2_HDMI_DAC_SLOW 10
177 #define G4X_P2_HDMI_DAC_FAST 5
178 #define G4X_P2_HDMI_DAC_LIMIT 165000
179
180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
198
199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
217
218 /*The parameter is for DISPLAY PORT on G4x platform*/
219 #define G4X_DOT_DISPLAY_PORT_MIN 161670
220 #define G4X_DOT_DISPLAY_PORT_MAX 227000
221 #define G4X_N_DISPLAY_PORT_MIN 1
222 #define G4X_N_DISPLAY_PORT_MAX 2
223 #define G4X_M_DISPLAY_PORT_MIN 97
224 #define G4X_M_DISPLAY_PORT_MAX 108
225 #define G4X_M1_DISPLAY_PORT_MIN 0x10
226 #define G4X_M1_DISPLAY_PORT_MAX 0x12
227 #define G4X_M2_DISPLAY_PORT_MIN 0x05
228 #define G4X_M2_DISPLAY_PORT_MAX 0x06
229 #define G4X_P_DISPLAY_PORT_MIN 10
230 #define G4X_P_DISPLAY_PORT_MAX 20
231 #define G4X_P1_DISPLAY_PORT_MIN 1
232 #define G4X_P1_DISPLAY_PORT_MAX 2
233 #define G4X_P2_DISPLAY_PORT_SLOW 10
234 #define G4X_P2_DISPLAY_PORT_FAST 10
235 #define G4X_P2_DISPLAY_PORT_LIMIT 0
236
237 /* IGDNG */
238 /* as we calculate clock using (register_value + 2) for
239 N/M1/M2, so here the range value for them is (actual_value-2).
240 */
241 #define IGDNG_DOT_MIN 25000
242 #define IGDNG_DOT_MAX 350000
243 #define IGDNG_VCO_MIN 1760000
244 #define IGDNG_VCO_MAX 3510000
245 #define IGDNG_N_MIN 1
246 #define IGDNG_N_MAX 5
247 #define IGDNG_M_MIN 79
248 #define IGDNG_M_MAX 118
249 #define IGDNG_M1_MIN 12
250 #define IGDNG_M1_MAX 23
251 #define IGDNG_M2_MIN 5
252 #define IGDNG_M2_MAX 9
253 #define IGDNG_P_SDVO_DAC_MIN 5
254 #define IGDNG_P_SDVO_DAC_MAX 80
255 #define IGDNG_P_LVDS_MIN 28
256 #define IGDNG_P_LVDS_MAX 112
257 #define IGDNG_P1_MIN 1
258 #define IGDNG_P1_MAX 8
259 #define IGDNG_P2_SDVO_DAC_SLOW 10
260 #define IGDNG_P2_SDVO_DAC_FAST 5
261 #define IGDNG_P2_LVDS_SLOW 14 /* single channel */
262 #define IGDNG_P2_LVDS_FAST 7 /* double channel */
263 #define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */
264
265 static bool
266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
267 int target, int refclk, intel_clock_t *best_clock);
268 static bool
269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
270 int target, int refclk, intel_clock_t *best_clock);
271 static bool
272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
273 int target, int refclk, intel_clock_t *best_clock);
274 static bool
275 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
276 int target, int refclk, intel_clock_t *best_clock);
277
278 static bool
279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
280 int target, int refclk, intel_clock_t *best_clock);
281 static bool
282 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
283 int target, int refclk, intel_clock_t *best_clock);
284
285 static const intel_limit_t intel_limits_i8xx_dvo = {
286 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
287 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
288 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
289 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
290 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
291 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
292 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
293 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
294 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
295 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
296 .find_pll = intel_find_best_PLL,
297 .find_reduced_pll = intel_find_best_reduced_PLL,
298 };
299
300 static const intel_limit_t intel_limits_i8xx_lvds = {
301 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
302 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
303 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
304 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
305 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
306 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
307 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
308 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
309 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
310 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
311 .find_pll = intel_find_best_PLL,
312 .find_reduced_pll = intel_find_best_reduced_PLL,
313 };
314
315 static const intel_limit_t intel_limits_i9xx_sdvo = {
316 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
317 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
318 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
319 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
320 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
321 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
322 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
323 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
324 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
325 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
326 .find_pll = intel_find_best_PLL,
327 .find_reduced_pll = intel_find_best_reduced_PLL,
328 };
329
330 static const intel_limit_t intel_limits_i9xx_lvds = {
331 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
332 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
333 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
334 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
335 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
336 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
337 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
338 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
339 /* The single-channel range is 25-112Mhz, and dual-channel
340 * is 80-224Mhz. Prefer single channel as much as possible.
341 */
342 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
343 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
344 .find_pll = intel_find_best_PLL,
345 .find_reduced_pll = intel_find_best_reduced_PLL,
346 };
347
348 /* below parameter and function is for G4X Chipset Family*/
349 static const intel_limit_t intel_limits_g4x_sdvo = {
350 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
351 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
352 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
353 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
354 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
355 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
356 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
357 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
358 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
359 .p2_slow = G4X_P2_SDVO_SLOW,
360 .p2_fast = G4X_P2_SDVO_FAST
361 },
362 .find_pll = intel_g4x_find_best_PLL,
363 .find_reduced_pll = intel_g4x_find_best_PLL,
364 };
365
366 static const intel_limit_t intel_limits_g4x_hdmi = {
367 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
368 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
369 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
370 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
371 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
372 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
373 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
374 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
375 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
376 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
377 .p2_fast = G4X_P2_HDMI_DAC_FAST
378 },
379 .find_pll = intel_g4x_find_best_PLL,
380 .find_reduced_pll = intel_g4x_find_best_PLL,
381 };
382
383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
384 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
385 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
386 .vco = { .min = G4X_VCO_MIN,
387 .max = G4X_VCO_MAX },
388 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
389 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
390 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
391 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
392 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
393 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
394 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
395 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
396 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
397 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
398 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
399 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
400 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
401 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
402 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
403 },
404 .find_pll = intel_g4x_find_best_PLL,
405 .find_reduced_pll = intel_g4x_find_best_PLL,
406 };
407
408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
409 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
410 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
411 .vco = { .min = G4X_VCO_MIN,
412 .max = G4X_VCO_MAX },
413 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
414 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
415 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
416 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
417 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
418 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
419 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
420 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
421 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
422 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
423 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
424 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
425 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
426 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
427 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
428 },
429 .find_pll = intel_g4x_find_best_PLL,
430 .find_reduced_pll = intel_g4x_find_best_PLL,
431 };
432
433 static const intel_limit_t intel_limits_g4x_display_port = {
434 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
435 .max = G4X_DOT_DISPLAY_PORT_MAX },
436 .vco = { .min = G4X_VCO_MIN,
437 .max = G4X_VCO_MAX},
438 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
439 .max = G4X_N_DISPLAY_PORT_MAX },
440 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
441 .max = G4X_M_DISPLAY_PORT_MAX },
442 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
443 .max = G4X_M1_DISPLAY_PORT_MAX },
444 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
445 .max = G4X_M2_DISPLAY_PORT_MAX },
446 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
447 .max = G4X_P_DISPLAY_PORT_MAX },
448 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
449 .max = G4X_P1_DISPLAY_PORT_MAX},
450 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
451 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
452 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
453 .find_pll = intel_find_pll_g4x_dp,
454 };
455
456 static const intel_limit_t intel_limits_igd_sdvo = {
457 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
458 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
459 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
460 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
461 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
462 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
463 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
464 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
465 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
466 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
467 .find_pll = intel_find_best_PLL,
468 .find_reduced_pll = intel_find_best_reduced_PLL,
469 };
470
471 static const intel_limit_t intel_limits_igd_lvds = {
472 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
473 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
474 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
475 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
476 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
477 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
478 .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
479 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
480 /* IGD only supports single-channel mode. */
481 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
482 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
483 .find_pll = intel_find_best_PLL,
484 .find_reduced_pll = intel_find_best_reduced_PLL,
485 };
486
487 static const intel_limit_t intel_limits_igdng_sdvo = {
488 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
489 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
490 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
491 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
492 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
493 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
494 .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX },
495 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
496 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
497 .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
498 .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
499 .find_pll = intel_igdng_find_best_PLL,
500 };
501
502 static const intel_limit_t intel_limits_igdng_lvds = {
503 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
504 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
505 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
506 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
507 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
508 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
509 .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX },
510 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
511 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
512 .p2_slow = IGDNG_P2_LVDS_SLOW,
513 .p2_fast = IGDNG_P2_LVDS_FAST },
514 .find_pll = intel_igdng_find_best_PLL,
515 };
516
517 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
518 {
519 const intel_limit_t *limit;
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
521 limit = &intel_limits_igdng_lvds;
522 else
523 limit = &intel_limits_igdng_sdvo;
524
525 return limit;
526 }
527
528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
529 {
530 struct drm_device *dev = crtc->dev;
531 struct drm_i915_private *dev_priv = dev->dev_private;
532 const intel_limit_t *limit;
533
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
535 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
536 LVDS_CLKB_POWER_UP)
537 /* LVDS with dual channel */
538 limit = &intel_limits_g4x_dual_channel_lvds;
539 else
540 /* LVDS with dual channel */
541 limit = &intel_limits_g4x_single_channel_lvds;
542 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
543 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
544 limit = &intel_limits_g4x_hdmi;
545 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
546 limit = &intel_limits_g4x_sdvo;
547 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
548 limit = &intel_limits_g4x_display_port;
549 } else /* The option is for other outputs */
550 limit = &intel_limits_i9xx_sdvo;
551
552 return limit;
553 }
554
555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
556 {
557 struct drm_device *dev = crtc->dev;
558 const intel_limit_t *limit;
559
560 if (IS_IGDNG(dev))
561 limit = intel_igdng_limit(crtc);
562 else if (IS_G4X(dev)) {
563 limit = intel_g4x_limit(crtc);
564 } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
565 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
566 limit = &intel_limits_i9xx_lvds;
567 else
568 limit = &intel_limits_i9xx_sdvo;
569 } else if (IS_IGD(dev)) {
570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
571 limit = &intel_limits_igd_lvds;
572 else
573 limit = &intel_limits_igd_sdvo;
574 } else {
575 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
576 limit = &intel_limits_i8xx_lvds;
577 else
578 limit = &intel_limits_i8xx_dvo;
579 }
580 return limit;
581 }
582
583 /* m1 is reserved as 0 in IGD, n is a ring counter */
584 static void igd_clock(int refclk, intel_clock_t *clock)
585 {
586 clock->m = clock->m2 + 2;
587 clock->p = clock->p1 * clock->p2;
588 clock->vco = refclk * clock->m / clock->n;
589 clock->dot = clock->vco / clock->p;
590 }
591
592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
593 {
594 if (IS_IGD(dev)) {
595 igd_clock(refclk, clock);
596 return;
597 }
598 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
599 clock->p = clock->p1 * clock->p2;
600 clock->vco = refclk * clock->m / (clock->n + 2);
601 clock->dot = clock->vco / clock->p;
602 }
603
604 /**
605 * Returns whether any output on the specified pipe is of the specified type
606 */
607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
608 {
609 struct drm_device *dev = crtc->dev;
610 struct drm_mode_config *mode_config = &dev->mode_config;
611 struct drm_connector *l_entry;
612
613 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
614 if (l_entry->encoder &&
615 l_entry->encoder->crtc == crtc) {
616 struct intel_output *intel_output = to_intel_output(l_entry);
617 if (intel_output->type == type)
618 return true;
619 }
620 }
621 return false;
622 }
623
624 struct drm_connector *
625 intel_pipe_get_output (struct drm_crtc *crtc)
626 {
627 struct drm_device *dev = crtc->dev;
628 struct drm_mode_config *mode_config = &dev->mode_config;
629 struct drm_connector *l_entry, *ret = NULL;
630
631 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
632 if (l_entry->encoder &&
633 l_entry->encoder->crtc == crtc) {
634 ret = l_entry;
635 break;
636 }
637 }
638 return ret;
639 }
640
641 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
642 /**
643 * Returns whether the given set of divisors are valid for a given refclk with
644 * the given connectors.
645 */
646
647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
648 {
649 const intel_limit_t *limit = intel_limit (crtc);
650 struct drm_device *dev = crtc->dev;
651
652 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
653 INTELPllInvalid ("p1 out of range\n");
654 if (clock->p < limit->p.min || limit->p.max < clock->p)
655 INTELPllInvalid ("p out of range\n");
656 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
657 INTELPllInvalid ("m2 out of range\n");
658 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
659 INTELPllInvalid ("m1 out of range\n");
660 if (clock->m1 <= clock->m2 && !IS_IGD(dev))
661 INTELPllInvalid ("m1 <= m2\n");
662 if (clock->m < limit->m.min || limit->m.max < clock->m)
663 INTELPllInvalid ("m out of range\n");
664 if (clock->n < limit->n.min || limit->n.max < clock->n)
665 INTELPllInvalid ("n out of range\n");
666 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
667 INTELPllInvalid ("vco out of range\n");
668 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
669 * connector, etc., rather than just a single range.
670 */
671 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
672 INTELPllInvalid ("dot out of range\n");
673
674 return true;
675 }
676
677 static bool
678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
679 int target, int refclk, intel_clock_t *best_clock)
680
681 {
682 struct drm_device *dev = crtc->dev;
683 struct drm_i915_private *dev_priv = dev->dev_private;
684 intel_clock_t clock;
685 int err = target;
686
687 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
688 (I915_READ(LVDS)) != 0) {
689 /*
690 * For LVDS, if the panel is on, just rely on its current
691 * settings for dual-channel. We haven't figured out how to
692 * reliably set up different single/dual channel state, if we
693 * even can.
694 */
695 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
696 LVDS_CLKB_POWER_UP)
697 clock.p2 = limit->p2.p2_fast;
698 else
699 clock.p2 = limit->p2.p2_slow;
700 } else {
701 if (target < limit->p2.dot_limit)
702 clock.p2 = limit->p2.p2_slow;
703 else
704 clock.p2 = limit->p2.p2_fast;
705 }
706
707 memset (best_clock, 0, sizeof (*best_clock));
708
709 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
710 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
711 clock.m1++) {
712 for (clock.m2 = limit->m2.min;
713 clock.m2 <= limit->m2.max; clock.m2++) {
714 /* m1 is always 0 in IGD */
715 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
716 break;
717 for (clock.n = limit->n.min;
718 clock.n <= limit->n.max; clock.n++) {
719 int this_err;
720
721 intel_clock(dev, refclk, &clock);
722
723 if (!intel_PLL_is_valid(crtc, &clock))
724 continue;
725
726 this_err = abs(clock.dot - target);
727 if (this_err < err) {
728 *best_clock = clock;
729 err = this_err;
730 }
731 }
732 }
733 }
734 }
735
736 return (err != target);
737 }
738
739
740 static bool
741 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *best_clock)
743
744 {
745 struct drm_device *dev = crtc->dev;
746 intel_clock_t clock;
747 int err = target;
748 bool found = false;
749
750 memcpy(&clock, best_clock, sizeof(intel_clock_t));
751
752 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
753 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
754 /* m1 is always 0 in IGD */
755 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
756 break;
757 for (clock.n = limit->n.min; clock.n <= limit->n.max;
758 clock.n++) {
759 int this_err;
760
761 intel_clock(dev, refclk, &clock);
762
763 if (!intel_PLL_is_valid(crtc, &clock))
764 continue;
765
766 this_err = abs(clock.dot - target);
767 if (this_err < err) {
768 *best_clock = clock;
769 err = this_err;
770 found = true;
771 }
772 }
773 }
774 }
775
776 return found;
777 }
778
779 static bool
780 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
781 int target, int refclk, intel_clock_t *best_clock)
782 {
783 struct drm_device *dev = crtc->dev;
784 struct drm_i915_private *dev_priv = dev->dev_private;
785 intel_clock_t clock;
786 int max_n;
787 bool found;
788 /* approximately equals target * 0.00488 */
789 int err_most = (target >> 8) + (target >> 10);
790 found = false;
791
792 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
793 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
794 LVDS_CLKB_POWER_UP)
795 clock.p2 = limit->p2.p2_fast;
796 else
797 clock.p2 = limit->p2.p2_slow;
798 } else {
799 if (target < limit->p2.dot_limit)
800 clock.p2 = limit->p2.p2_slow;
801 else
802 clock.p2 = limit->p2.p2_fast;
803 }
804
805 memset(best_clock, 0, sizeof(*best_clock));
806 max_n = limit->n.max;
807 /* based on hardware requriment prefer smaller n to precision */
808 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
809 /* based on hardware requirment prefere larger m1,m2 */
810 for (clock.m1 = limit->m1.max;
811 clock.m1 >= limit->m1.min; clock.m1--) {
812 for (clock.m2 = limit->m2.max;
813 clock.m2 >= limit->m2.min; clock.m2--) {
814 for (clock.p1 = limit->p1.max;
815 clock.p1 >= limit->p1.min; clock.p1--) {
816 int this_err;
817
818 intel_clock(dev, refclk, &clock);
819 if (!intel_PLL_is_valid(crtc, &clock))
820 continue;
821 this_err = abs(clock.dot - target) ;
822 if (this_err < err_most) {
823 *best_clock = clock;
824 err_most = this_err;
825 max_n = clock.n;
826 found = true;
827 }
828 }
829 }
830 }
831 }
832 return found;
833 }
834
835 static bool
836 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *best_clock)
838 {
839 struct drm_device *dev = crtc->dev;
840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.n = 1;
843 clock.p1 = 2;
844 clock.p2 = 10;
845 clock.m1 = 12;
846 clock.m2 = 9;
847 } else {
848 clock.n = 2;
849 clock.p1 = 1;
850 clock.p2 = 10;
851 clock.m1 = 14;
852 clock.m2 = 8;
853 }
854 intel_clock(dev, refclk, &clock);
855 memcpy(best_clock, &clock, sizeof(intel_clock_t));
856 return true;
857 }
858
859 static bool
860 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
861 int target, int refclk, intel_clock_t *best_clock)
862 {
863 struct drm_device *dev = crtc->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private;
865 intel_clock_t clock;
866 int max_n;
867 bool found;
868 int err_most = 47;
869 found = false;
870
871 /* eDP has only 2 clock choice, no n/m/p setting */
872 if (HAS_eDP)
873 return true;
874
875 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
876 return intel_find_pll_igdng_dp(limit, crtc, target,
877 refclk, best_clock);
878
879 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
880 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
881 LVDS_CLKB_POWER_UP)
882 clock.p2 = limit->p2.p2_fast;
883 else
884 clock.p2 = limit->p2.p2_slow;
885 } else {
886 if (target < limit->p2.dot_limit)
887 clock.p2 = limit->p2.p2_slow;
888 else
889 clock.p2 = limit->p2.p2_fast;
890 }
891
892 memset(best_clock, 0, sizeof(*best_clock));
893 max_n = limit->n.max;
894 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
895 /* based on hardware requriment prefer smaller n to precision */
896 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
897 /* based on hardware requirment prefere larger m1,m2 */
898 for (clock.m1 = limit->m1.max;
899 clock.m1 >= limit->m1.min; clock.m1--) {
900 for (clock.m2 = limit->m2.max;
901 clock.m2 >= limit->m2.min; clock.m2--) {
902 int this_err;
903
904 intel_clock(dev, refclk, &clock);
905 if (!intel_PLL_is_valid(crtc, &clock))
906 continue;
907 this_err = abs((10000 - (target*10000/clock.dot)));
908 if (this_err < err_most) {
909 *best_clock = clock;
910 err_most = this_err;
911 max_n = clock.n;
912 found = true;
913 /* found on first matching */
914 goto out;
915 }
916 }
917 }
918 }
919 }
920 out:
921 return found;
922 }
923
924 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
925 static bool
926 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
927 int target, int refclk, intel_clock_t *best_clock)
928 {
929 intel_clock_t clock;
930 if (target < 200000) {
931 clock.p1 = 2;
932 clock.p2 = 10;
933 clock.n = 2;
934 clock.m1 = 23;
935 clock.m2 = 8;
936 } else {
937 clock.p1 = 1;
938 clock.p2 = 10;
939 clock.n = 1;
940 clock.m1 = 14;
941 clock.m2 = 2;
942 }
943 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
944 clock.p = (clock.p1 * clock.p2);
945 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
946 clock.vco = 0;
947 memcpy(best_clock, &clock, sizeof(intel_clock_t));
948 return true;
949 }
950
951 void
952 intel_wait_for_vblank(struct drm_device *dev)
953 {
954 /* Wait for 20ms, i.e. one cycle at 50hz. */
955 mdelay(20);
956 }
957
958 /* Parameters have changed, update FBC info */
959 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
960 {
961 struct drm_device *dev = crtc->dev;
962 struct drm_i915_private *dev_priv = dev->dev_private;
963 struct drm_framebuffer *fb = crtc->fb;
964 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
965 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
967 int plane, i;
968 u32 fbc_ctl, fbc_ctl2;
969
970 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
971
972 if (fb->pitch < dev_priv->cfb_pitch)
973 dev_priv->cfb_pitch = fb->pitch;
974
975 /* FBC_CTL wants 64B units */
976 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
977 dev_priv->cfb_fence = obj_priv->fence_reg;
978 dev_priv->cfb_plane = intel_crtc->plane;
979 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
980
981 /* Clear old tags */
982 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
983 I915_WRITE(FBC_TAG + (i * 4), 0);
984
985 /* Set it up... */
986 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
987 if (obj_priv->tiling_mode != I915_TILING_NONE)
988 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
989 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
990 I915_WRITE(FBC_FENCE_OFF, crtc->y);
991
992 /* enable it... */
993 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
994 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
995 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
996 if (obj_priv->tiling_mode != I915_TILING_NONE)
997 fbc_ctl |= dev_priv->cfb_fence;
998 I915_WRITE(FBC_CONTROL, fbc_ctl);
999
1000 DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1001 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1002 }
1003
1004 void i8xx_disable_fbc(struct drm_device *dev)
1005 {
1006 struct drm_i915_private *dev_priv = dev->dev_private;
1007 u32 fbc_ctl;
1008
1009 if (!I915_HAS_FBC(dev))
1010 return;
1011
1012 /* Disable compression */
1013 fbc_ctl = I915_READ(FBC_CONTROL);
1014 fbc_ctl &= ~FBC_CTL_EN;
1015 I915_WRITE(FBC_CONTROL, fbc_ctl);
1016
1017 /* Wait for compressing bit to clear */
1018 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1019 ; /* nothing */
1020
1021 intel_wait_for_vblank(dev);
1022
1023 DRM_DEBUG("disabled FBC\n");
1024 }
1025
1026 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1027 {
1028 struct drm_device *dev = crtc->dev;
1029 struct drm_i915_private *dev_priv = dev->dev_private;
1030
1031 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1032 }
1033
1034 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1035 {
1036 struct drm_device *dev = crtc->dev;
1037 struct drm_i915_private *dev_priv = dev->dev_private;
1038 struct drm_framebuffer *fb = crtc->fb;
1039 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1040 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1042 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1043 DPFC_CTL_PLANEB);
1044 unsigned long stall_watermark = 200;
1045 u32 dpfc_ctl;
1046
1047 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1048 dev_priv->cfb_fence = obj_priv->fence_reg;
1049 dev_priv->cfb_plane = intel_crtc->plane;
1050
1051 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1052 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1053 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1054 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1055 } else {
1056 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1057 }
1058
1059 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1060 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1061 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1062 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1063 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1064
1065 /* enable it... */
1066 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1067
1068 DRM_DEBUG("enabled fbc on plane %d\n", intel_crtc->plane);
1069 }
1070
1071 void g4x_disable_fbc(struct drm_device *dev)
1072 {
1073 struct drm_i915_private *dev_priv = dev->dev_private;
1074 u32 dpfc_ctl;
1075
1076 /* Disable compression */
1077 dpfc_ctl = I915_READ(DPFC_CONTROL);
1078 dpfc_ctl &= ~DPFC_CTL_EN;
1079 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1080 intel_wait_for_vblank(dev);
1081
1082 DRM_DEBUG("disabled FBC\n");
1083 }
1084
1085 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1086 {
1087 struct drm_device *dev = crtc->dev;
1088 struct drm_i915_private *dev_priv = dev->dev_private;
1089
1090 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1091 }
1092
1093 /**
1094 * intel_update_fbc - enable/disable FBC as needed
1095 * @crtc: CRTC to point the compressor at
1096 * @mode: mode in use
1097 *
1098 * Set up the framebuffer compression hardware at mode set time. We
1099 * enable it if possible:
1100 * - plane A only (on pre-965)
1101 * - no pixel mulitply/line duplication
1102 * - no alpha buffer discard
1103 * - no dual wide
1104 * - framebuffer <= 2048 in width, 1536 in height
1105 *
1106 * We can't assume that any compression will take place (worst case),
1107 * so the compressed buffer has to be the same size as the uncompressed
1108 * one. It also must reside (along with the line length buffer) in
1109 * stolen memory.
1110 *
1111 * We need to enable/disable FBC on a global basis.
1112 */
1113 static void intel_update_fbc(struct drm_crtc *crtc,
1114 struct drm_display_mode *mode)
1115 {
1116 struct drm_device *dev = crtc->dev;
1117 struct drm_i915_private *dev_priv = dev->dev_private;
1118 struct drm_framebuffer *fb = crtc->fb;
1119 struct intel_framebuffer *intel_fb;
1120 struct drm_i915_gem_object *obj_priv;
1121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1122 int plane = intel_crtc->plane;
1123
1124 if (!i915_powersave)
1125 return;
1126
1127 if (!dev_priv->display.fbc_enabled ||
1128 !dev_priv->display.enable_fbc ||
1129 !dev_priv->display.disable_fbc)
1130 return;
1131
1132 if (!crtc->fb)
1133 return;
1134
1135 intel_fb = to_intel_framebuffer(fb);
1136 obj_priv = intel_fb->obj->driver_private;
1137
1138 /*
1139 * If FBC is already on, we just have to verify that we can
1140 * keep it that way...
1141 * Need to disable if:
1142 * - changing FBC params (stride, fence, mode)
1143 * - new fb is too large to fit in compressed buffer
1144 * - going to an unsupported config (interlace, pixel multiply, etc.)
1145 */
1146 if (intel_fb->obj->size > dev_priv->cfb_size) {
1147 DRM_DEBUG("framebuffer too large, disabling compression\n");
1148 goto out_disable;
1149 }
1150 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1151 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1152 DRM_DEBUG("mode incompatible with compression, disabling\n");
1153 goto out_disable;
1154 }
1155 if ((mode->hdisplay > 2048) ||
1156 (mode->vdisplay > 1536)) {
1157 DRM_DEBUG("mode too large for compression, disabling\n");
1158 goto out_disable;
1159 }
1160 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1161 DRM_DEBUG("plane not 0, disabling compression\n");
1162 goto out_disable;
1163 }
1164 if (obj_priv->tiling_mode != I915_TILING_X) {
1165 DRM_DEBUG("framebuffer not tiled, disabling compression\n");
1166 goto out_disable;
1167 }
1168
1169 if (dev_priv->display.fbc_enabled(crtc)) {
1170 /* We can re-enable it in this case, but need to update pitch */
1171 if (fb->pitch > dev_priv->cfb_pitch)
1172 dev_priv->display.disable_fbc(dev);
1173 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1174 dev_priv->display.disable_fbc(dev);
1175 if (plane != dev_priv->cfb_plane)
1176 dev_priv->display.disable_fbc(dev);
1177 }
1178
1179 if (!dev_priv->display.fbc_enabled(crtc)) {
1180 /* Now try to turn it back on if possible */
1181 dev_priv->display.enable_fbc(crtc, 500);
1182 }
1183
1184 return;
1185
1186 out_disable:
1187 DRM_DEBUG("unsupported config, disabling FBC\n");
1188 /* Multiple disables should be harmless */
1189 if (dev_priv->display.fbc_enabled(crtc))
1190 dev_priv->display.disable_fbc(dev);
1191 }
1192
1193 static int
1194 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1195 struct drm_framebuffer *old_fb)
1196 {
1197 struct drm_device *dev = crtc->dev;
1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199 struct drm_i915_master_private *master_priv;
1200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1201 struct intel_framebuffer *intel_fb;
1202 struct drm_i915_gem_object *obj_priv;
1203 struct drm_gem_object *obj;
1204 int pipe = intel_crtc->pipe;
1205 int plane = intel_crtc->plane;
1206 unsigned long Start, Offset;
1207 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1208 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1209 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1210 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1211 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1212 u32 dspcntr, alignment;
1213 int ret;
1214
1215 /* no fb bound */
1216 if (!crtc->fb) {
1217 DRM_DEBUG("No FB bound\n");
1218 return 0;
1219 }
1220
1221 switch (plane) {
1222 case 0:
1223 case 1:
1224 break;
1225 default:
1226 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1227 return -EINVAL;
1228 }
1229
1230 intel_fb = to_intel_framebuffer(crtc->fb);
1231 obj = intel_fb->obj;
1232 obj_priv = obj->driver_private;
1233
1234 switch (obj_priv->tiling_mode) {
1235 case I915_TILING_NONE:
1236 alignment = 64 * 1024;
1237 break;
1238 case I915_TILING_X:
1239 /* pin() will align the object as required by fence */
1240 alignment = 0;
1241 break;
1242 case I915_TILING_Y:
1243 /* FIXME: Is this true? */
1244 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1245 return -EINVAL;
1246 default:
1247 BUG();
1248 }
1249
1250 mutex_lock(&dev->struct_mutex);
1251 ret = i915_gem_object_pin(obj, alignment);
1252 if (ret != 0) {
1253 mutex_unlock(&dev->struct_mutex);
1254 return ret;
1255 }
1256
1257 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1258 if (ret != 0) {
1259 i915_gem_object_unpin(obj);
1260 mutex_unlock(&dev->struct_mutex);
1261 return ret;
1262 }
1263
1264 /* Install a fence for tiled scan-out. Pre-i965 always needs a fence,
1265 * whereas 965+ only requires a fence if using framebuffer compression.
1266 * For simplicity, we always install a fence as the cost is not that onerous.
1267 */
1268 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1269 obj_priv->tiling_mode != I915_TILING_NONE) {
1270 ret = i915_gem_object_get_fence_reg(obj);
1271 if (ret != 0) {
1272 i915_gem_object_unpin(obj);
1273 mutex_unlock(&dev->struct_mutex);
1274 return ret;
1275 }
1276 }
1277
1278 dspcntr = I915_READ(dspcntr_reg);
1279 /* Mask out pixel format bits in case we change it */
1280 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1281 switch (crtc->fb->bits_per_pixel) {
1282 case 8:
1283 dspcntr |= DISPPLANE_8BPP;
1284 break;
1285 case 16:
1286 if (crtc->fb->depth == 15)
1287 dspcntr |= DISPPLANE_15_16BPP;
1288 else
1289 dspcntr |= DISPPLANE_16BPP;
1290 break;
1291 case 24:
1292 case 32:
1293 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1294 break;
1295 default:
1296 DRM_ERROR("Unknown color depth\n");
1297 i915_gem_object_unpin(obj);
1298 mutex_unlock(&dev->struct_mutex);
1299 return -EINVAL;
1300 }
1301 if (IS_I965G(dev)) {
1302 if (obj_priv->tiling_mode != I915_TILING_NONE)
1303 dspcntr |= DISPPLANE_TILED;
1304 else
1305 dspcntr &= ~DISPPLANE_TILED;
1306 }
1307
1308 if (IS_IGDNG(dev))
1309 /* must disable */
1310 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1311
1312 I915_WRITE(dspcntr_reg, dspcntr);
1313
1314 Start = obj_priv->gtt_offset;
1315 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1316
1317 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1318 I915_WRITE(dspstride, crtc->fb->pitch);
1319 if (IS_I965G(dev)) {
1320 I915_WRITE(dspbase, Offset);
1321 I915_READ(dspbase);
1322 I915_WRITE(dspsurf, Start);
1323 I915_READ(dspsurf);
1324 I915_WRITE(dsptileoff, (y << 16) | x);
1325 } else {
1326 I915_WRITE(dspbase, Start + Offset);
1327 I915_READ(dspbase);
1328 }
1329
1330 if ((IS_I965G(dev) || plane == 0))
1331 intel_update_fbc(crtc, &crtc->mode);
1332
1333 intel_wait_for_vblank(dev);
1334
1335 if (old_fb) {
1336 intel_fb = to_intel_framebuffer(old_fb);
1337 obj_priv = intel_fb->obj->driver_private;
1338 i915_gem_object_unpin(intel_fb->obj);
1339 }
1340 intel_increase_pllclock(crtc, true);
1341
1342 mutex_unlock(&dev->struct_mutex);
1343
1344 if (!dev->primary->master)
1345 return 0;
1346
1347 master_priv = dev->primary->master->driver_priv;
1348 if (!master_priv->sarea_priv)
1349 return 0;
1350
1351 if (pipe) {
1352 master_priv->sarea_priv->pipeB_x = x;
1353 master_priv->sarea_priv->pipeB_y = y;
1354 } else {
1355 master_priv->sarea_priv->pipeA_x = x;
1356 master_priv->sarea_priv->pipeA_y = y;
1357 }
1358
1359 return 0;
1360 }
1361
1362 /* Disable the VGA plane that we never use */
1363 static void i915_disable_vga (struct drm_device *dev)
1364 {
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366 u8 sr1;
1367 u32 vga_reg;
1368
1369 if (IS_IGDNG(dev))
1370 vga_reg = CPU_VGACNTRL;
1371 else
1372 vga_reg = VGACNTRL;
1373
1374 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1375 return;
1376
1377 I915_WRITE8(VGA_SR_INDEX, 1);
1378 sr1 = I915_READ8(VGA_SR_DATA);
1379 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1380 udelay(100);
1381
1382 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1383 }
1384
1385 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1386 {
1387 struct drm_device *dev = crtc->dev;
1388 struct drm_i915_private *dev_priv = dev->dev_private;
1389 u32 dpa_ctl;
1390
1391 DRM_DEBUG("\n");
1392 dpa_ctl = I915_READ(DP_A);
1393 dpa_ctl &= ~DP_PLL_ENABLE;
1394 I915_WRITE(DP_A, dpa_ctl);
1395 }
1396
1397 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1398 {
1399 struct drm_device *dev = crtc->dev;
1400 struct drm_i915_private *dev_priv = dev->dev_private;
1401 u32 dpa_ctl;
1402
1403 dpa_ctl = I915_READ(DP_A);
1404 dpa_ctl |= DP_PLL_ENABLE;
1405 I915_WRITE(DP_A, dpa_ctl);
1406 udelay(200);
1407 }
1408
1409
1410 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1411 {
1412 struct drm_device *dev = crtc->dev;
1413 struct drm_i915_private *dev_priv = dev->dev_private;
1414 u32 dpa_ctl;
1415
1416 DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
1417 dpa_ctl = I915_READ(DP_A);
1418 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1419
1420 if (clock < 200000) {
1421 u32 temp;
1422 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1423 /* workaround for 160Mhz:
1424 1) program 0x4600c bits 15:0 = 0x8124
1425 2) program 0x46010 bit 0 = 1
1426 3) program 0x46034 bit 24 = 1
1427 4) program 0x64000 bit 14 = 1
1428 */
1429 temp = I915_READ(0x4600c);
1430 temp &= 0xffff0000;
1431 I915_WRITE(0x4600c, temp | 0x8124);
1432
1433 temp = I915_READ(0x46010);
1434 I915_WRITE(0x46010, temp | 1);
1435
1436 temp = I915_READ(0x46034);
1437 I915_WRITE(0x46034, temp | (1 << 24));
1438 } else {
1439 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1440 }
1441 I915_WRITE(DP_A, dpa_ctl);
1442
1443 udelay(500);
1444 }
1445
1446 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1447 {
1448 struct drm_device *dev = crtc->dev;
1449 struct drm_i915_private *dev_priv = dev->dev_private;
1450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1451 int pipe = intel_crtc->pipe;
1452 int plane = intel_crtc->plane;
1453 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1454 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1455 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1456 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1457 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1458 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1459 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1460 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1461 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1462 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1463 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1464 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1465 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1466 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1467 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1468 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1469 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1470 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1471 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1472 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1473 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1474 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1475 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1476 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1477 u32 temp;
1478 int tries = 5, j, n;
1479
1480 /* XXX: When our outputs are all unaware of DPMS modes other than off
1481 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1482 */
1483 switch (mode) {
1484 case DRM_MODE_DPMS_ON:
1485 case DRM_MODE_DPMS_STANDBY:
1486 case DRM_MODE_DPMS_SUSPEND:
1487 DRM_DEBUG("crtc %d dpms on\n", pipe);
1488 if (HAS_eDP) {
1489 /* enable eDP PLL */
1490 igdng_enable_pll_edp(crtc);
1491 } else {
1492 /* enable PCH DPLL */
1493 temp = I915_READ(pch_dpll_reg);
1494 if ((temp & DPLL_VCO_ENABLE) == 0) {
1495 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1496 I915_READ(pch_dpll_reg);
1497 }
1498
1499 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1500 temp = I915_READ(fdi_rx_reg);
1501 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1502 FDI_SEL_PCDCLK |
1503 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1504 I915_READ(fdi_rx_reg);
1505 udelay(200);
1506
1507 /* Enable CPU FDI TX PLL, always on for IGDNG */
1508 temp = I915_READ(fdi_tx_reg);
1509 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1510 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1511 I915_READ(fdi_tx_reg);
1512 udelay(100);
1513 }
1514 }
1515
1516 /* Enable panel fitting for LVDS */
1517 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1518 temp = I915_READ(pf_ctl_reg);
1519 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1520
1521 /* currently full aspect */
1522 I915_WRITE(pf_win_pos, 0);
1523
1524 I915_WRITE(pf_win_size,
1525 (dev_priv->panel_fixed_mode->hdisplay << 16) |
1526 (dev_priv->panel_fixed_mode->vdisplay));
1527 }
1528
1529 /* Enable CPU pipe */
1530 temp = I915_READ(pipeconf_reg);
1531 if ((temp & PIPEACONF_ENABLE) == 0) {
1532 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1533 I915_READ(pipeconf_reg);
1534 udelay(100);
1535 }
1536
1537 /* configure and enable CPU plane */
1538 temp = I915_READ(dspcntr_reg);
1539 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1540 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1541 /* Flush the plane changes */
1542 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1543 }
1544
1545 if (!HAS_eDP) {
1546 /* enable CPU FDI TX and PCH FDI RX */
1547 temp = I915_READ(fdi_tx_reg);
1548 temp |= FDI_TX_ENABLE;
1549 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1550 temp &= ~FDI_LINK_TRAIN_NONE;
1551 temp |= FDI_LINK_TRAIN_PATTERN_1;
1552 I915_WRITE(fdi_tx_reg, temp);
1553 I915_READ(fdi_tx_reg);
1554
1555 temp = I915_READ(fdi_rx_reg);
1556 temp &= ~FDI_LINK_TRAIN_NONE;
1557 temp |= FDI_LINK_TRAIN_PATTERN_1;
1558 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1559 I915_READ(fdi_rx_reg);
1560
1561 udelay(150);
1562
1563 /* Train FDI. */
1564 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1565 for train result */
1566 temp = I915_READ(fdi_rx_imr_reg);
1567 temp &= ~FDI_RX_SYMBOL_LOCK;
1568 temp &= ~FDI_RX_BIT_LOCK;
1569 I915_WRITE(fdi_rx_imr_reg, temp);
1570 I915_READ(fdi_rx_imr_reg);
1571 udelay(150);
1572
1573 temp = I915_READ(fdi_rx_iir_reg);
1574 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1575
1576 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1577 for (j = 0; j < tries; j++) {
1578 temp = I915_READ(fdi_rx_iir_reg);
1579 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1580 if (temp & FDI_RX_BIT_LOCK)
1581 break;
1582 udelay(200);
1583 }
1584 if (j != tries)
1585 I915_WRITE(fdi_rx_iir_reg,
1586 temp | FDI_RX_BIT_LOCK);
1587 else
1588 DRM_DEBUG("train 1 fail\n");
1589 } else {
1590 I915_WRITE(fdi_rx_iir_reg,
1591 temp | FDI_RX_BIT_LOCK);
1592 DRM_DEBUG("train 1 ok 2!\n");
1593 }
1594 temp = I915_READ(fdi_tx_reg);
1595 temp &= ~FDI_LINK_TRAIN_NONE;
1596 temp |= FDI_LINK_TRAIN_PATTERN_2;
1597 I915_WRITE(fdi_tx_reg, temp);
1598
1599 temp = I915_READ(fdi_rx_reg);
1600 temp &= ~FDI_LINK_TRAIN_NONE;
1601 temp |= FDI_LINK_TRAIN_PATTERN_2;
1602 I915_WRITE(fdi_rx_reg, temp);
1603
1604 udelay(150);
1605
1606 temp = I915_READ(fdi_rx_iir_reg);
1607 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1608
1609 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1610 for (j = 0; j < tries; j++) {
1611 temp = I915_READ(fdi_rx_iir_reg);
1612 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1613 if (temp & FDI_RX_SYMBOL_LOCK)
1614 break;
1615 udelay(200);
1616 }
1617 if (j != tries) {
1618 I915_WRITE(fdi_rx_iir_reg,
1619 temp | FDI_RX_SYMBOL_LOCK);
1620 DRM_DEBUG("train 2 ok 1!\n");
1621 } else
1622 DRM_DEBUG("train 2 fail\n");
1623 } else {
1624 I915_WRITE(fdi_rx_iir_reg,
1625 temp | FDI_RX_SYMBOL_LOCK);
1626 DRM_DEBUG("train 2 ok 2!\n");
1627 }
1628 DRM_DEBUG("train done\n");
1629
1630 /* set transcoder timing */
1631 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1632 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1633 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1634
1635 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1636 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1637 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1638
1639 /* enable PCH transcoder */
1640 temp = I915_READ(transconf_reg);
1641 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1642 I915_READ(transconf_reg);
1643
1644 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1645 ;
1646
1647 /* enable normal */
1648
1649 temp = I915_READ(fdi_tx_reg);
1650 temp &= ~FDI_LINK_TRAIN_NONE;
1651 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1652 FDI_TX_ENHANCE_FRAME_ENABLE);
1653 I915_READ(fdi_tx_reg);
1654
1655 temp = I915_READ(fdi_rx_reg);
1656 temp &= ~FDI_LINK_TRAIN_NONE;
1657 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1658 FDI_RX_ENHANCE_FRAME_ENABLE);
1659 I915_READ(fdi_rx_reg);
1660
1661 /* wait one idle pattern time */
1662 udelay(100);
1663
1664 }
1665
1666 intel_crtc_load_lut(crtc);
1667
1668 break;
1669 case DRM_MODE_DPMS_OFF:
1670 DRM_DEBUG("crtc %d dpms off\n", pipe);
1671
1672 i915_disable_vga(dev);
1673
1674 /* Disable display plane */
1675 temp = I915_READ(dspcntr_reg);
1676 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1677 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1678 /* Flush the plane changes */
1679 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1680 I915_READ(dspbase_reg);
1681 }
1682
1683 /* disable cpu pipe, disable after all planes disabled */
1684 temp = I915_READ(pipeconf_reg);
1685 if ((temp & PIPEACONF_ENABLE) != 0) {
1686 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1687 I915_READ(pipeconf_reg);
1688 n = 0;
1689 /* wait for cpu pipe off, pipe state */
1690 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1691 n++;
1692 if (n < 60) {
1693 udelay(500);
1694 continue;
1695 } else {
1696 DRM_DEBUG("pipe %d off delay\n", pipe);
1697 break;
1698 }
1699 }
1700 } else
1701 DRM_DEBUG("crtc %d is disabled\n", pipe);
1702
1703 if (HAS_eDP) {
1704 igdng_disable_pll_edp(crtc);
1705 }
1706
1707 /* disable CPU FDI tx and PCH FDI rx */
1708 temp = I915_READ(fdi_tx_reg);
1709 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1710 I915_READ(fdi_tx_reg);
1711
1712 temp = I915_READ(fdi_rx_reg);
1713 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1714 I915_READ(fdi_rx_reg);
1715
1716 udelay(100);
1717
1718 /* still set train pattern 1 */
1719 temp = I915_READ(fdi_tx_reg);
1720 temp &= ~FDI_LINK_TRAIN_NONE;
1721 temp |= FDI_LINK_TRAIN_PATTERN_1;
1722 I915_WRITE(fdi_tx_reg, temp);
1723
1724 temp = I915_READ(fdi_rx_reg);
1725 temp &= ~FDI_LINK_TRAIN_NONE;
1726 temp |= FDI_LINK_TRAIN_PATTERN_1;
1727 I915_WRITE(fdi_rx_reg, temp);
1728
1729 udelay(100);
1730
1731 /* disable PCH transcoder */
1732 temp = I915_READ(transconf_reg);
1733 if ((temp & TRANS_ENABLE) != 0) {
1734 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1735 I915_READ(transconf_reg);
1736 n = 0;
1737 /* wait for PCH transcoder off, transcoder state */
1738 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1739 n++;
1740 if (n < 60) {
1741 udelay(500);
1742 continue;
1743 } else {
1744 DRM_DEBUG("transcoder %d off delay\n", pipe);
1745 break;
1746 }
1747 }
1748 }
1749
1750 /* disable PCH DPLL */
1751 temp = I915_READ(pch_dpll_reg);
1752 if ((temp & DPLL_VCO_ENABLE) != 0) {
1753 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1754 I915_READ(pch_dpll_reg);
1755 }
1756
1757 temp = I915_READ(fdi_rx_reg);
1758 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1759 temp &= ~FDI_SEL_PCDCLK;
1760 temp &= ~FDI_RX_PLL_ENABLE;
1761 I915_WRITE(fdi_rx_reg, temp);
1762 I915_READ(fdi_rx_reg);
1763 }
1764
1765 /* Disable CPU FDI TX PLL */
1766 temp = I915_READ(fdi_tx_reg);
1767 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1768 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1769 I915_READ(fdi_tx_reg);
1770 udelay(100);
1771 }
1772
1773 /* Disable PF */
1774 temp = I915_READ(pf_ctl_reg);
1775 if ((temp & PF_ENABLE) != 0) {
1776 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1777 I915_READ(pf_ctl_reg);
1778 }
1779 I915_WRITE(pf_win_size, 0);
1780
1781 /* Wait for the clocks to turn off. */
1782 udelay(150);
1783 break;
1784 }
1785 }
1786
1787 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1788 {
1789 struct drm_device *dev = crtc->dev;
1790 struct drm_i915_private *dev_priv = dev->dev_private;
1791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1792 int pipe = intel_crtc->pipe;
1793 int plane = intel_crtc->plane;
1794 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1795 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1796 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1797 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1798 u32 temp;
1799
1800 /* XXX: When our outputs are all unaware of DPMS modes other than off
1801 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1802 */
1803 switch (mode) {
1804 case DRM_MODE_DPMS_ON:
1805 case DRM_MODE_DPMS_STANDBY:
1806 case DRM_MODE_DPMS_SUSPEND:
1807 intel_update_watermarks(dev);
1808
1809 /* Enable the DPLL */
1810 temp = I915_READ(dpll_reg);
1811 if ((temp & DPLL_VCO_ENABLE) == 0) {
1812 I915_WRITE(dpll_reg, temp);
1813 I915_READ(dpll_reg);
1814 /* Wait for the clocks to stabilize. */
1815 udelay(150);
1816 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1817 I915_READ(dpll_reg);
1818 /* Wait for the clocks to stabilize. */
1819 udelay(150);
1820 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1821 I915_READ(dpll_reg);
1822 /* Wait for the clocks to stabilize. */
1823 udelay(150);
1824 }
1825
1826 /* Enable the pipe */
1827 temp = I915_READ(pipeconf_reg);
1828 if ((temp & PIPEACONF_ENABLE) == 0)
1829 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1830
1831 /* Enable the plane */
1832 temp = I915_READ(dspcntr_reg);
1833 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1834 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1835 /* Flush the plane changes */
1836 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1837 }
1838
1839 intel_crtc_load_lut(crtc);
1840
1841 if ((IS_I965G(dev) || plane == 0))
1842 intel_update_fbc(crtc, &crtc->mode);
1843
1844 /* Give the overlay scaler a chance to enable if it's on this pipe */
1845 //intel_crtc_dpms_video(crtc, true); TODO
1846 break;
1847 case DRM_MODE_DPMS_OFF:
1848 intel_update_watermarks(dev);
1849 /* Give the overlay scaler a chance to disable if it's on this pipe */
1850 //intel_crtc_dpms_video(crtc, FALSE); TODO
1851
1852 if (dev_priv->cfb_plane == plane &&
1853 dev_priv->display.disable_fbc)
1854 dev_priv->display.disable_fbc(dev);
1855
1856 /* Disable the VGA plane that we never use */
1857 i915_disable_vga(dev);
1858
1859 /* Disable display plane */
1860 temp = I915_READ(dspcntr_reg);
1861 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1862 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1863 /* Flush the plane changes */
1864 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1865 I915_READ(dspbase_reg);
1866 }
1867
1868 if (!IS_I9XX(dev)) {
1869 /* Wait for vblank for the disable to take effect */
1870 intel_wait_for_vblank(dev);
1871 }
1872
1873 /* Next, disable display pipes */
1874 temp = I915_READ(pipeconf_reg);
1875 if ((temp & PIPEACONF_ENABLE) != 0) {
1876 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1877 I915_READ(pipeconf_reg);
1878 }
1879
1880 /* Wait for vblank for the disable to take effect. */
1881 intel_wait_for_vblank(dev);
1882
1883 temp = I915_READ(dpll_reg);
1884 if ((temp & DPLL_VCO_ENABLE) != 0) {
1885 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1886 I915_READ(dpll_reg);
1887 }
1888
1889 /* Wait for the clocks to turn off. */
1890 udelay(150);
1891 break;
1892 }
1893 }
1894
1895 /**
1896 * Sets the power management mode of the pipe and plane.
1897 *
1898 * This code should probably grow support for turning the cursor off and back
1899 * on appropriately at the same time as we're turning the pipe off/on.
1900 */
1901 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1902 {
1903 struct drm_device *dev = crtc->dev;
1904 struct drm_i915_private *dev_priv = dev->dev_private;
1905 struct drm_i915_master_private *master_priv;
1906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1907 int pipe = intel_crtc->pipe;
1908 bool enabled;
1909
1910 dev_priv->display.dpms(crtc, mode);
1911
1912 intel_crtc->dpms_mode = mode;
1913
1914 if (!dev->primary->master)
1915 return;
1916
1917 master_priv = dev->primary->master->driver_priv;
1918 if (!master_priv->sarea_priv)
1919 return;
1920
1921 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1922
1923 switch (pipe) {
1924 case 0:
1925 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1926 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1927 break;
1928 case 1:
1929 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1930 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1931 break;
1932 default:
1933 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1934 break;
1935 }
1936 }
1937
1938 static void intel_crtc_prepare (struct drm_crtc *crtc)
1939 {
1940 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1941 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1942 }
1943
1944 static void intel_crtc_commit (struct drm_crtc *crtc)
1945 {
1946 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1947 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1948 }
1949
1950 void intel_encoder_prepare (struct drm_encoder *encoder)
1951 {
1952 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1953 /* lvds has its own version of prepare see intel_lvds_prepare */
1954 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1955 }
1956
1957 void intel_encoder_commit (struct drm_encoder *encoder)
1958 {
1959 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1960 /* lvds has its own version of commit see intel_lvds_commit */
1961 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1962 }
1963
1964 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1965 struct drm_display_mode *mode,
1966 struct drm_display_mode *adjusted_mode)
1967 {
1968 struct drm_device *dev = crtc->dev;
1969 if (IS_IGDNG(dev)) {
1970 /* FDI link clock is fixed at 2.7G */
1971 if (mode->clock * 3 > 27000 * 4)
1972 return MODE_CLOCK_HIGH;
1973 }
1974 return true;
1975 }
1976
1977 static int i945_get_display_clock_speed(struct drm_device *dev)
1978 {
1979 return 400000;
1980 }
1981
1982 static int i915_get_display_clock_speed(struct drm_device *dev)
1983 {
1984 return 333000;
1985 }
1986
1987 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
1988 {
1989 return 200000;
1990 }
1991
1992 static int i915gm_get_display_clock_speed(struct drm_device *dev)
1993 {
1994 u16 gcfgc = 0;
1995
1996 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1997
1998 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1999 return 133000;
2000 else {
2001 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2002 case GC_DISPLAY_CLOCK_333_MHZ:
2003 return 333000;
2004 default:
2005 case GC_DISPLAY_CLOCK_190_200_MHZ:
2006 return 190000;
2007 }
2008 }
2009 }
2010
2011 static int i865_get_display_clock_speed(struct drm_device *dev)
2012 {
2013 return 266000;
2014 }
2015
2016 static int i855_get_display_clock_speed(struct drm_device *dev)
2017 {
2018 u16 hpllcc = 0;
2019 /* Assume that the hardware is in the high speed state. This
2020 * should be the default.
2021 */
2022 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2023 case GC_CLOCK_133_200:
2024 case GC_CLOCK_100_200:
2025 return 200000;
2026 case GC_CLOCK_166_250:
2027 return 250000;
2028 case GC_CLOCK_100_133:
2029 return 133000;
2030 }
2031
2032 /* Shouldn't happen */
2033 return 0;
2034 }
2035
2036 static int i830_get_display_clock_speed(struct drm_device *dev)
2037 {
2038 return 133000;
2039 }
2040
2041 /**
2042 * Return the pipe currently connected to the panel fitter,
2043 * or -1 if the panel fitter is not present or not in use
2044 */
2045 static int intel_panel_fitter_pipe (struct drm_device *dev)
2046 {
2047 struct drm_i915_private *dev_priv = dev->dev_private;
2048 u32 pfit_control;
2049
2050 /* i830 doesn't have a panel fitter */
2051 if (IS_I830(dev))
2052 return -1;
2053
2054 pfit_control = I915_READ(PFIT_CONTROL);
2055
2056 /* See if the panel fitter is in use */
2057 if ((pfit_control & PFIT_ENABLE) == 0)
2058 return -1;
2059
2060 /* 965 can place panel fitter on either pipe */
2061 if (IS_I965G(dev))
2062 return (pfit_control >> 29) & 0x3;
2063
2064 /* older chips can only use pipe 1 */
2065 return 1;
2066 }
2067
2068 struct fdi_m_n {
2069 u32 tu;
2070 u32 gmch_m;
2071 u32 gmch_n;
2072 u32 link_m;
2073 u32 link_n;
2074 };
2075
2076 static void
2077 fdi_reduce_ratio(u32 *num, u32 *den)
2078 {
2079 while (*num > 0xffffff || *den > 0xffffff) {
2080 *num >>= 1;
2081 *den >>= 1;
2082 }
2083 }
2084
2085 #define DATA_N 0x800000
2086 #define LINK_N 0x80000
2087
2088 static void
2089 igdng_compute_m_n(int bits_per_pixel, int nlanes,
2090 int pixel_clock, int link_clock,
2091 struct fdi_m_n *m_n)
2092 {
2093 u64 temp;
2094
2095 m_n->tu = 64; /* default size */
2096
2097 temp = (u64) DATA_N * pixel_clock;
2098 temp = div_u64(temp, link_clock);
2099 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2100 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2101 m_n->gmch_n = DATA_N;
2102 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2103
2104 temp = (u64) LINK_N * pixel_clock;
2105 m_n->link_m = div_u64(temp, link_clock);
2106 m_n->link_n = LINK_N;
2107 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2108 }
2109
2110
2111 struct intel_watermark_params {
2112 unsigned long fifo_size;
2113 unsigned long max_wm;
2114 unsigned long default_wm;
2115 unsigned long guard_size;
2116 unsigned long cacheline_size;
2117 };
2118
2119 /* IGD has different values for various configs */
2120 static struct intel_watermark_params igd_display_wm = {
2121 IGD_DISPLAY_FIFO,
2122 IGD_MAX_WM,
2123 IGD_DFT_WM,
2124 IGD_GUARD_WM,
2125 IGD_FIFO_LINE_SIZE
2126 };
2127 static struct intel_watermark_params igd_display_hplloff_wm = {
2128 IGD_DISPLAY_FIFO,
2129 IGD_MAX_WM,
2130 IGD_DFT_HPLLOFF_WM,
2131 IGD_GUARD_WM,
2132 IGD_FIFO_LINE_SIZE
2133 };
2134 static struct intel_watermark_params igd_cursor_wm = {
2135 IGD_CURSOR_FIFO,
2136 IGD_CURSOR_MAX_WM,
2137 IGD_CURSOR_DFT_WM,
2138 IGD_CURSOR_GUARD_WM,
2139 IGD_FIFO_LINE_SIZE,
2140 };
2141 static struct intel_watermark_params igd_cursor_hplloff_wm = {
2142 IGD_CURSOR_FIFO,
2143 IGD_CURSOR_MAX_WM,
2144 IGD_CURSOR_DFT_WM,
2145 IGD_CURSOR_GUARD_WM,
2146 IGD_FIFO_LINE_SIZE
2147 };
2148 static struct intel_watermark_params g4x_wm_info = {
2149 G4X_FIFO_SIZE,
2150 G4X_MAX_WM,
2151 G4X_MAX_WM,
2152 2,
2153 G4X_FIFO_LINE_SIZE,
2154 };
2155 static struct intel_watermark_params i945_wm_info = {
2156 I945_FIFO_SIZE,
2157 I915_MAX_WM,
2158 1,
2159 2,
2160 I915_FIFO_LINE_SIZE
2161 };
2162 static struct intel_watermark_params i915_wm_info = {
2163 I915_FIFO_SIZE,
2164 I915_MAX_WM,
2165 1,
2166 2,
2167 I915_FIFO_LINE_SIZE
2168 };
2169 static struct intel_watermark_params i855_wm_info = {
2170 I855GM_FIFO_SIZE,
2171 I915_MAX_WM,
2172 1,
2173 2,
2174 I830_FIFO_LINE_SIZE
2175 };
2176 static struct intel_watermark_params i830_wm_info = {
2177 I830_FIFO_SIZE,
2178 I915_MAX_WM,
2179 1,
2180 2,
2181 I830_FIFO_LINE_SIZE
2182 };
2183
2184 /**
2185 * intel_calculate_wm - calculate watermark level
2186 * @clock_in_khz: pixel clock
2187 * @wm: chip FIFO params
2188 * @pixel_size: display pixel size
2189 * @latency_ns: memory latency for the platform
2190 *
2191 * Calculate the watermark level (the level at which the display plane will
2192 * start fetching from memory again). Each chip has a different display
2193 * FIFO size and allocation, so the caller needs to figure that out and pass
2194 * in the correct intel_watermark_params structure.
2195 *
2196 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2197 * on the pixel size. When it reaches the watermark level, it'll start
2198 * fetching FIFO line sized based chunks from memory until the FIFO fills
2199 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2200 * will occur, and a display engine hang could result.
2201 */
2202 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2203 struct intel_watermark_params *wm,
2204 int pixel_size,
2205 unsigned long latency_ns)
2206 {
2207 long entries_required, wm_size;
2208
2209 /*
2210 * Note: we need to make sure we don't overflow for various clock &
2211 * latency values.
2212 * clocks go from a few thousand to several hundred thousand.
2213 * latency is usually a few thousand
2214 */
2215 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2216 1000;
2217 entries_required /= wm->cacheline_size;
2218
2219 DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
2220
2221 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2222
2223 DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
2224
2225 /* Don't promote wm_size to unsigned... */
2226 if (wm_size > (long)wm->max_wm)
2227 wm_size = wm->max_wm;
2228 if (wm_size <= 0)
2229 wm_size = wm->default_wm;
2230 return wm_size;
2231 }
2232
2233 struct cxsr_latency {
2234 int is_desktop;
2235 unsigned long fsb_freq;
2236 unsigned long mem_freq;
2237 unsigned long display_sr;
2238 unsigned long display_hpll_disable;
2239 unsigned long cursor_sr;
2240 unsigned long cursor_hpll_disable;
2241 };
2242
2243 static struct cxsr_latency cxsr_latency_table[] = {
2244 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2245 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2246 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2247
2248 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2249 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2250 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2251
2252 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2253 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2254 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2255
2256 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2257 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2258 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2259
2260 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2261 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2262 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2263
2264 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2265 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2266 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2267 };
2268
2269 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2270 int mem)
2271 {
2272 int i;
2273 struct cxsr_latency *latency;
2274
2275 if (fsb == 0 || mem == 0)
2276 return NULL;
2277
2278 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2279 latency = &cxsr_latency_table[i];
2280 if (is_desktop == latency->is_desktop &&
2281 fsb == latency->fsb_freq && mem == latency->mem_freq)
2282 return latency;
2283 }
2284
2285 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2286
2287 return NULL;
2288 }
2289
2290 static void igd_disable_cxsr(struct drm_device *dev)
2291 {
2292 struct drm_i915_private *dev_priv = dev->dev_private;
2293 u32 reg;
2294
2295 /* deactivate cxsr */
2296 reg = I915_READ(DSPFW3);
2297 reg &= ~(IGD_SELF_REFRESH_EN);
2298 I915_WRITE(DSPFW3, reg);
2299 DRM_INFO("Big FIFO is disabled\n");
2300 }
2301
2302 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2303 int pixel_size)
2304 {
2305 struct drm_i915_private *dev_priv = dev->dev_private;
2306 u32 reg;
2307 unsigned long wm;
2308 struct cxsr_latency *latency;
2309
2310 latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2311 dev_priv->mem_freq);
2312 if (!latency) {
2313 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2314 igd_disable_cxsr(dev);
2315 return;
2316 }
2317
2318 /* Display SR */
2319 wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2320 latency->display_sr);
2321 reg = I915_READ(DSPFW1);
2322 reg &= 0x7fffff;
2323 reg |= wm << 23;
2324 I915_WRITE(DSPFW1, reg);
2325 DRM_DEBUG("DSPFW1 register is %x\n", reg);
2326
2327 /* cursor SR */
2328 wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2329 latency->cursor_sr);
2330 reg = I915_READ(DSPFW3);
2331 reg &= ~(0x3f << 24);
2332 reg |= (wm & 0x3f) << 24;
2333 I915_WRITE(DSPFW3, reg);
2334
2335 /* Display HPLL off SR */
2336 wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2337 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2338 reg = I915_READ(DSPFW3);
2339 reg &= 0xfffffe00;
2340 reg |= wm & 0x1ff;
2341 I915_WRITE(DSPFW3, reg);
2342
2343 /* cursor HPLL off SR */
2344 wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2345 latency->cursor_hpll_disable);
2346 reg = I915_READ(DSPFW3);
2347 reg &= ~(0x3f << 16);
2348 reg |= (wm & 0x3f) << 16;
2349 I915_WRITE(DSPFW3, reg);
2350 DRM_DEBUG("DSPFW3 register is %x\n", reg);
2351
2352 /* activate cxsr */
2353 reg = I915_READ(DSPFW3);
2354 reg |= IGD_SELF_REFRESH_EN;
2355 I915_WRITE(DSPFW3, reg);
2356
2357 DRM_INFO("Big FIFO is enabled\n");
2358
2359 return;
2360 }
2361
2362 /*
2363 * Latency for FIFO fetches is dependent on several factors:
2364 * - memory configuration (speed, channels)
2365 * - chipset
2366 * - current MCH state
2367 * It can be fairly high in some situations, so here we assume a fairly
2368 * pessimal value. It's a tradeoff between extra memory fetches (if we
2369 * set this value too high, the FIFO will fetch frequently to stay full)
2370 * and power consumption (set it too low to save power and we might see
2371 * FIFO underruns and display "flicker").
2372 *
2373 * A value of 5us seems to be a good balance; safe for very low end
2374 * platforms but not overly aggressive on lower latency configs.
2375 */
2376 const static int latency_ns = 5000;
2377
2378 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2379 {
2380 struct drm_i915_private *dev_priv = dev->dev_private;
2381 uint32_t dsparb = I915_READ(DSPARB);
2382 int size;
2383
2384 if (plane == 0)
2385 size = dsparb & 0x7f;
2386 else
2387 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2388 (dsparb & 0x7f);
2389
2390 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2391 size);
2392
2393 return size;
2394 }
2395
2396 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2397 {
2398 struct drm_i915_private *dev_priv = dev->dev_private;
2399 uint32_t dsparb = I915_READ(DSPARB);
2400 int size;
2401
2402 if (plane == 0)
2403 size = dsparb & 0x1ff;
2404 else
2405 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2406 (dsparb & 0x1ff);
2407 size >>= 1; /* Convert to cachelines */
2408
2409 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2410 size);
2411
2412 return size;
2413 }
2414
2415 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2416 {
2417 struct drm_i915_private *dev_priv = dev->dev_private;
2418 uint32_t dsparb = I915_READ(DSPARB);
2419 int size;
2420
2421 size = dsparb & 0x7f;
2422 size >>= 2; /* Convert to cachelines */
2423
2424 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2425 size);
2426
2427 return size;
2428 }
2429
2430 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2431 {
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 uint32_t dsparb = I915_READ(DSPARB);
2434 int size;
2435
2436 size = dsparb & 0x7f;
2437 size >>= 1; /* Convert to cachelines */
2438
2439 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2440 size);
2441
2442 return size;
2443 }
2444
2445 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2446 int planeb_clock, int sr_hdisplay, int pixel_size)
2447 {
2448 struct drm_i915_private *dev_priv = dev->dev_private;
2449 int total_size, cacheline_size;
2450 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2451 struct intel_watermark_params planea_params, planeb_params;
2452 unsigned long line_time_us;
2453 int sr_clock, sr_entries = 0, entries_required;
2454
2455 /* Create copies of the base settings for each pipe */
2456 planea_params = planeb_params = g4x_wm_info;
2457
2458 /* Grab a couple of global values before we overwrite them */
2459 total_size = planea_params.fifo_size;
2460 cacheline_size = planea_params.cacheline_size;
2461
2462 /*
2463 * Note: we need to make sure we don't overflow for various clock &
2464 * latency values.
2465 * clocks go from a few thousand to several hundred thousand.
2466 * latency is usually a few thousand
2467 */
2468 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2469 1000;
2470 entries_required /= G4X_FIFO_LINE_SIZE;
2471 planea_wm = entries_required + planea_params.guard_size;
2472
2473 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2474 1000;
2475 entries_required /= G4X_FIFO_LINE_SIZE;
2476 planeb_wm = entries_required + planeb_params.guard_size;
2477
2478 cursora_wm = cursorb_wm = 16;
2479 cursor_sr = 32;
2480
2481 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2482
2483 /* Calc sr entries for one plane configs */
2484 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2485 /* self-refresh has much higher latency */
2486 const static int sr_latency_ns = 12000;
2487
2488 sr_clock = planea_clock ? planea_clock : planeb_clock;
2489 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2490
2491 /* Use ns/us then divide to preserve precision */
2492 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2493 pixel_size * sr_hdisplay) / 1000;
2494 sr_entries = roundup(sr_entries / cacheline_size, 1);
2495 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2496 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2497 }
2498
2499 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2500 planea_wm, planeb_wm, sr_entries);
2501
2502 planea_wm &= 0x3f;
2503 planeb_wm &= 0x3f;
2504
2505 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2506 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2507 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2508 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2509 (cursora_wm << DSPFW_CURSORA_SHIFT));
2510 /* HPLL off in SR has some issues on G4x... disable it */
2511 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2512 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2513 }
2514
2515 static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
2516 int unused3, int unused4)
2517 {
2518 struct drm_i915_private *dev_priv = dev->dev_private;
2519
2520 DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2521
2522 /* 965 has limitations... */
2523 I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
2524 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2525 }
2526
2527 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2528 int planeb_clock, int sr_hdisplay, int pixel_size)
2529 {
2530 struct drm_i915_private *dev_priv = dev->dev_private;
2531 uint32_t fwater_lo;
2532 uint32_t fwater_hi;
2533 int total_size, cacheline_size, cwm, srwm = 1;
2534 int planea_wm, planeb_wm;
2535 struct intel_watermark_params planea_params, planeb_params;
2536 unsigned long line_time_us;
2537 int sr_clock, sr_entries = 0;
2538
2539 /* Create copies of the base settings for each pipe */
2540 if (IS_I965GM(dev) || IS_I945GM(dev))
2541 planea_params = planeb_params = i945_wm_info;
2542 else if (IS_I9XX(dev))
2543 planea_params = planeb_params = i915_wm_info;
2544 else
2545 planea_params = planeb_params = i855_wm_info;
2546
2547 /* Grab a couple of global values before we overwrite them */
2548 total_size = planea_params.fifo_size;
2549 cacheline_size = planea_params.cacheline_size;
2550
2551 /* Update per-plane FIFO sizes */
2552 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2553 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2554
2555 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2556 pixel_size, latency_ns);
2557 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2558 pixel_size, latency_ns);
2559 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2560
2561 /*
2562 * Overlay gets an aggressive default since video jitter is bad.
2563 */
2564 cwm = 2;
2565
2566 /* Calc sr entries for one plane configs */
2567 if (HAS_FW_BLC(dev) && sr_hdisplay &&
2568 (!planea_clock || !planeb_clock)) {
2569 /* self-refresh has much higher latency */
2570 const static int sr_latency_ns = 6000;
2571
2572 sr_clock = planea_clock ? planea_clock : planeb_clock;
2573 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2574
2575 /* Use ns/us then divide to preserve precision */
2576 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2577 pixel_size * sr_hdisplay) / 1000;
2578 sr_entries = roundup(sr_entries / cacheline_size, 1);
2579 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2580 srwm = total_size - sr_entries;
2581 if (srwm < 0)
2582 srwm = 1;
2583 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2584 }
2585
2586 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2587 planea_wm, planeb_wm, cwm, srwm);
2588
2589 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2590 fwater_hi = (cwm & 0x1f);
2591
2592 /* Set request length to 8 cachelines per fetch */
2593 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2594 fwater_hi = fwater_hi | (1 << 8);
2595
2596 I915_WRITE(FW_BLC, fwater_lo);
2597 I915_WRITE(FW_BLC2, fwater_hi);
2598 }
2599
2600 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2601 int unused2, int pixel_size)
2602 {
2603 struct drm_i915_private *dev_priv = dev->dev_private;
2604 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2605 int planea_wm;
2606
2607 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2608
2609 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2610 pixel_size, latency_ns);
2611 fwater_lo |= (3<<8) | planea_wm;
2612
2613 DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
2614
2615 I915_WRITE(FW_BLC, fwater_lo);
2616 }
2617
2618 /**
2619 * intel_update_watermarks - update FIFO watermark values based on current modes
2620 *
2621 * Calculate watermark values for the various WM regs based on current mode
2622 * and plane configuration.
2623 *
2624 * There are several cases to deal with here:
2625 * - normal (i.e. non-self-refresh)
2626 * - self-refresh (SR) mode
2627 * - lines are large relative to FIFO size (buffer can hold up to 2)
2628 * - lines are small relative to FIFO size (buffer can hold more than 2
2629 * lines), so need to account for TLB latency
2630 *
2631 * The normal calculation is:
2632 * watermark = dotclock * bytes per pixel * latency
2633 * where latency is platform & configuration dependent (we assume pessimal
2634 * values here).
2635 *
2636 * The SR calculation is:
2637 * watermark = (trunc(latency/line time)+1) * surface width *
2638 * bytes per pixel
2639 * where
2640 * line time = htotal / dotclock
2641 * and latency is assumed to be high, as above.
2642 *
2643 * The final value programmed to the register should always be rounded up,
2644 * and include an extra 2 entries to account for clock crossings.
2645 *
2646 * We don't use the sprite, so we can ignore that. And on Crestline we have
2647 * to set the non-SR watermarks to 8.
2648 */
2649 static void intel_update_watermarks(struct drm_device *dev)
2650 {
2651 struct drm_i915_private *dev_priv = dev->dev_private;
2652 struct drm_crtc *crtc;
2653 struct intel_crtc *intel_crtc;
2654 int sr_hdisplay = 0;
2655 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2656 int enabled = 0, pixel_size = 0;
2657
2658 if (!dev_priv->display.update_wm)
2659 return;
2660
2661 /* Get the clock config from both planes */
2662 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2663 intel_crtc = to_intel_crtc(crtc);
2664 if (crtc->enabled) {
2665 enabled++;
2666 if (intel_crtc->plane == 0) {
2667 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2668 intel_crtc->pipe, crtc->mode.clock);
2669 planea_clock = crtc->mode.clock;
2670 } else {
2671 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2672 intel_crtc->pipe, crtc->mode.clock);
2673 planeb_clock = crtc->mode.clock;
2674 }
2675 sr_hdisplay = crtc->mode.hdisplay;
2676 sr_clock = crtc->mode.clock;
2677 if (crtc->fb)
2678 pixel_size = crtc->fb->bits_per_pixel / 8;
2679 else
2680 pixel_size = 4; /* by default */
2681 }
2682 }
2683
2684 if (enabled <= 0)
2685 return;
2686
2687 /* Single plane configs can enable self refresh */
2688 if (enabled == 1 && IS_IGD(dev))
2689 igd_enable_cxsr(dev, sr_clock, pixel_size);
2690 else if (IS_IGD(dev))
2691 igd_disable_cxsr(dev);
2692
2693 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2694 sr_hdisplay, pixel_size);
2695 }
2696
2697 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2698 struct drm_display_mode *mode,
2699 struct drm_display_mode *adjusted_mode,
2700 int x, int y,
2701 struct drm_framebuffer *old_fb)
2702 {
2703 struct drm_device *dev = crtc->dev;
2704 struct drm_i915_private *dev_priv = dev->dev_private;
2705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2706 int pipe = intel_crtc->pipe;
2707 int plane = intel_crtc->plane;
2708 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2709 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2710 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2711 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2712 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2713 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2714 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2715 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2716 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2717 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2718 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2719 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2720 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2721 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2722 int refclk, num_outputs = 0;
2723 intel_clock_t clock, reduced_clock;
2724 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2725 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2726 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2727 bool is_edp = false;
2728 struct drm_mode_config *mode_config = &dev->mode_config;
2729 struct drm_connector *connector;
2730 const intel_limit_t *limit;
2731 int ret;
2732 struct fdi_m_n m_n = {0};
2733 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2734 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2735 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2736 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2737 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2738 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2739 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2740 int lvds_reg = LVDS;
2741 u32 temp;
2742 int sdvo_pixel_multiply;
2743 int target_clock;
2744
2745 drm_vblank_pre_modeset(dev, pipe);
2746
2747 list_for_each_entry(connector, &mode_config->connector_list, head) {
2748 struct intel_output *intel_output = to_intel_output(connector);
2749
2750 if (!connector->encoder || connector->encoder->crtc != crtc)
2751 continue;
2752
2753 switch (intel_output->type) {
2754 case INTEL_OUTPUT_LVDS:
2755 is_lvds = true;
2756 break;
2757 case INTEL_OUTPUT_SDVO:
2758 case INTEL_OUTPUT_HDMI:
2759 is_sdvo = true;
2760 if (intel_output->needs_tv_clock)
2761 is_tv = true;
2762 break;
2763 case INTEL_OUTPUT_DVO:
2764 is_dvo = true;
2765 break;
2766 case INTEL_OUTPUT_TVOUT:
2767 is_tv = true;
2768 break;
2769 case INTEL_OUTPUT_ANALOG:
2770 is_crt = true;
2771 break;
2772 case INTEL_OUTPUT_DISPLAYPORT:
2773 is_dp = true;
2774 break;
2775 case INTEL_OUTPUT_EDP:
2776 is_edp = true;
2777 break;
2778 }
2779
2780 num_outputs++;
2781 }
2782
2783 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2784 refclk = dev_priv->lvds_ssc_freq * 1000;
2785 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2786 } else if (IS_I9XX(dev)) {
2787 refclk = 96000;
2788 if (IS_IGDNG(dev))
2789 refclk = 120000; /* 120Mhz refclk */
2790 } else {
2791 refclk = 48000;
2792 }
2793
2794
2795 /*
2796 * Returns a set of divisors for the desired target clock with the given
2797 * refclk, or FALSE. The returned values represent the clock equation:
2798 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2799 */
2800 limit = intel_limit(crtc);
2801 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2802 if (!ok) {
2803 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2804 drm_vblank_post_modeset(dev, pipe);
2805 return -EINVAL;
2806 }
2807
2808 if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
2809 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2810 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2811 (adjusted_mode->clock*3/4),
2812 refclk,
2813 &reduced_clock);
2814 }
2815
2816 /* SDVO TV has fixed PLL values depend on its clock range,
2817 this mirrors vbios setting. */
2818 if (is_sdvo && is_tv) {
2819 if (adjusted_mode->clock >= 100000
2820 && adjusted_mode->clock < 140500) {
2821 clock.p1 = 2;
2822 clock.p2 = 10;
2823 clock.n = 3;
2824 clock.m1 = 16;
2825 clock.m2 = 8;
2826 } else if (adjusted_mode->clock >= 140500
2827 && adjusted_mode->clock <= 200000) {
2828 clock.p1 = 1;
2829 clock.p2 = 10;
2830 clock.n = 6;
2831 clock.m1 = 12;
2832 clock.m2 = 8;
2833 }
2834 }
2835
2836 /* FDI link */
2837 if (IS_IGDNG(dev)) {
2838 int lane, link_bw, bpp;
2839 /* eDP doesn't require FDI link, so just set DP M/N
2840 according to current link config */
2841 if (is_edp) {
2842 struct drm_connector *edp;
2843 target_clock = mode->clock;
2844 edp = intel_pipe_get_output(crtc);
2845 intel_edp_link_config(to_intel_output(edp),
2846 &lane, &link_bw);
2847 } else {
2848 /* DP over FDI requires target mode clock
2849 instead of link clock */
2850 if (is_dp)
2851 target_clock = mode->clock;
2852 else
2853 target_clock = adjusted_mode->clock;
2854 lane = 4;
2855 link_bw = 270000;
2856 }
2857
2858 /* determine panel color depth */
2859 temp = I915_READ(pipeconf_reg);
2860
2861 switch (temp & PIPE_BPC_MASK) {
2862 case PIPE_8BPC:
2863 bpp = 24;
2864 break;
2865 case PIPE_10BPC:
2866 bpp = 30;
2867 break;
2868 case PIPE_6BPC:
2869 bpp = 18;
2870 break;
2871 case PIPE_12BPC:
2872 bpp = 36;
2873 break;
2874 default:
2875 DRM_ERROR("unknown pipe bpc value\n");
2876 bpp = 24;
2877 }
2878
2879 igdng_compute_m_n(bpp, lane, target_clock,
2880 link_bw, &m_n);
2881 }
2882
2883 /* Ironlake: try to setup display ref clock before DPLL
2884 * enabling. This is only under driver's control after
2885 * PCH B stepping, previous chipset stepping should be
2886 * ignoring this setting.
2887 */
2888 if (IS_IGDNG(dev)) {
2889 temp = I915_READ(PCH_DREF_CONTROL);
2890 /* Always enable nonspread source */
2891 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2892 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
2893 I915_WRITE(PCH_DREF_CONTROL, temp);
2894 POSTING_READ(PCH_DREF_CONTROL);
2895
2896 temp &= ~DREF_SSC_SOURCE_MASK;
2897 temp |= DREF_SSC_SOURCE_ENABLE;
2898 I915_WRITE(PCH_DREF_CONTROL, temp);
2899 POSTING_READ(PCH_DREF_CONTROL);
2900
2901 udelay(200);
2902
2903 if (is_edp) {
2904 if (dev_priv->lvds_use_ssc) {
2905 temp |= DREF_SSC1_ENABLE;
2906 I915_WRITE(PCH_DREF_CONTROL, temp);
2907 POSTING_READ(PCH_DREF_CONTROL);
2908
2909 udelay(200);
2910
2911 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2912 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2913 I915_WRITE(PCH_DREF_CONTROL, temp);
2914 POSTING_READ(PCH_DREF_CONTROL);
2915 } else {
2916 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2917 I915_WRITE(PCH_DREF_CONTROL, temp);
2918 POSTING_READ(PCH_DREF_CONTROL);
2919 }
2920 }
2921 }
2922
2923 if (IS_IGD(dev)) {
2924 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2925 if (has_reduced_clock)
2926 fp2 = (1 << reduced_clock.n) << 16 |
2927 reduced_clock.m1 << 8 | reduced_clock.m2;
2928 } else {
2929 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2930 if (has_reduced_clock)
2931 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
2932 reduced_clock.m2;
2933 }
2934
2935 if (!IS_IGDNG(dev))
2936 dpll = DPLL_VGA_MODE_DIS;
2937
2938 if (IS_I9XX(dev)) {
2939 if (is_lvds)
2940 dpll |= DPLLB_MODE_LVDS;
2941 else
2942 dpll |= DPLLB_MODE_DAC_SERIAL;
2943 if (is_sdvo) {
2944 dpll |= DPLL_DVO_HIGH_SPEED;
2945 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2946 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2947 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2948 else if (IS_IGDNG(dev))
2949 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2950 }
2951 if (is_dp)
2952 dpll |= DPLL_DVO_HIGH_SPEED;
2953
2954 /* compute bitmask from p1 value */
2955 if (IS_IGD(dev))
2956 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2957 else {
2958 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2959 /* also FPA1 */
2960 if (IS_IGDNG(dev))
2961 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2962 if (IS_G4X(dev) && has_reduced_clock)
2963 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2964 }
2965 switch (clock.p2) {
2966 case 5:
2967 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2968 break;
2969 case 7:
2970 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2971 break;
2972 case 10:
2973 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2974 break;
2975 case 14:
2976 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2977 break;
2978 }
2979 if (IS_I965G(dev) && !IS_IGDNG(dev))
2980 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2981 } else {
2982 if (is_lvds) {
2983 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2984 } else {
2985 if (clock.p1 == 2)
2986 dpll |= PLL_P1_DIVIDE_BY_TWO;
2987 else
2988 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2989 if (clock.p2 == 4)
2990 dpll |= PLL_P2_DIVIDE_BY_4;
2991 }
2992 }
2993
2994 if (is_sdvo && is_tv)
2995 dpll |= PLL_REF_INPUT_TVCLKINBC;
2996 else if (is_tv)
2997 /* XXX: just matching BIOS for now */
2998 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
2999 dpll |= 3;
3000 else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3001 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3002 else
3003 dpll |= PLL_REF_INPUT_DREFCLK;
3004
3005 /* setup pipeconf */
3006 pipeconf = I915_READ(pipeconf_reg);
3007
3008 /* Set up the display plane register */
3009 dspcntr = DISPPLANE_GAMMA_ENABLE;
3010
3011 /* IGDNG's plane is forced to pipe, bit 24 is to
3012 enable color space conversion */
3013 if (!IS_IGDNG(dev)) {
3014 if (pipe == 0)
3015 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3016 else
3017 dspcntr |= DISPPLANE_SEL_PIPE_B;
3018 }
3019
3020 if (pipe == 0 && !IS_I965G(dev)) {
3021 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3022 * core speed.
3023 *
3024 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3025 * pipe == 0 check?
3026 */
3027 if (mode->clock >
3028 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3029 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3030 else
3031 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3032 }
3033
3034 dspcntr |= DISPLAY_PLANE_ENABLE;
3035 pipeconf |= PIPEACONF_ENABLE;
3036 dpll |= DPLL_VCO_ENABLE;
3037
3038
3039 /* Disable the panel fitter if it was on our pipe */
3040 if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
3041 I915_WRITE(PFIT_CONTROL, 0);
3042
3043 DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3044 drm_mode_debug_printmodeline(mode);
3045
3046 /* assign to IGDNG registers */
3047 if (IS_IGDNG(dev)) {
3048 fp_reg = pch_fp_reg;
3049 dpll_reg = pch_dpll_reg;
3050 }
3051
3052 if (is_edp) {
3053 igdng_disable_pll_edp(crtc);
3054 } else if ((dpll & DPLL_VCO_ENABLE)) {
3055 I915_WRITE(fp_reg, fp);
3056 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3057 I915_READ(dpll_reg);
3058 udelay(150);
3059 }
3060
3061 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3062 * This is an exception to the general rule that mode_set doesn't turn
3063 * things on.
3064 */
3065 if (is_lvds) {
3066 u32 lvds;
3067
3068 if (IS_IGDNG(dev))
3069 lvds_reg = PCH_LVDS;
3070
3071 lvds = I915_READ(lvds_reg);
3072 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3073 /* set the corresponsding LVDS_BORDER bit */
3074 lvds |= dev_priv->lvds_border_bits;
3075 /* Set the B0-B3 data pairs corresponding to whether we're going to
3076 * set the DPLLs for dual-channel mode or not.
3077 */
3078 if (clock.p2 == 7)
3079 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3080 else
3081 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3082
3083 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3084 * appropriately here, but we need to look more thoroughly into how
3085 * panels behave in the two modes.
3086 */
3087
3088 I915_WRITE(lvds_reg, lvds);
3089 I915_READ(lvds_reg);
3090 }
3091 if (is_dp)
3092 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3093
3094 if (!is_edp) {
3095 I915_WRITE(fp_reg, fp);
3096 I915_WRITE(dpll_reg, dpll);
3097 I915_READ(dpll_reg);
3098 /* Wait for the clocks to stabilize. */
3099 udelay(150);
3100
3101 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
3102 if (is_sdvo) {
3103 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3104 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3105 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3106 } else
3107 I915_WRITE(dpll_md_reg, 0);
3108 } else {
3109 /* write it again -- the BIOS does, after all */
3110 I915_WRITE(dpll_reg, dpll);
3111 }
3112 I915_READ(dpll_reg);
3113 /* Wait for the clocks to stabilize. */
3114 udelay(150);
3115 }
3116
3117 if (is_lvds && has_reduced_clock && i915_powersave) {
3118 I915_WRITE(fp_reg + 4, fp2);
3119 intel_crtc->lowfreq_avail = true;
3120 if (HAS_PIPE_CXSR(dev)) {
3121 DRM_DEBUG("enabling CxSR downclocking\n");
3122 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3123 }
3124 } else {
3125 I915_WRITE(fp_reg + 4, fp);
3126 intel_crtc->lowfreq_avail = false;
3127 if (HAS_PIPE_CXSR(dev)) {
3128 DRM_DEBUG("disabling CxSR downclocking\n");
3129 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3130 }
3131 }
3132
3133 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3134 ((adjusted_mode->crtc_htotal - 1) << 16));
3135 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3136 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3137 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3138 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3139 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3140 ((adjusted_mode->crtc_vtotal - 1) << 16));
3141 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3142 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3143 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3144 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3145 /* pipesrc and dspsize control the size that is scaled from, which should
3146 * always be the user's requested size.
3147 */
3148 if (!IS_IGDNG(dev)) {
3149 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3150 (mode->hdisplay - 1));
3151 I915_WRITE(dsppos_reg, 0);
3152 }
3153 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3154
3155 if (IS_IGDNG(dev)) {
3156 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3157 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3158 I915_WRITE(link_m1_reg, m_n.link_m);
3159 I915_WRITE(link_n1_reg, m_n.link_n);
3160
3161 if (is_edp) {
3162 igdng_set_pll_edp(crtc, adjusted_mode->clock);
3163 } else {
3164 /* enable FDI RX PLL too */
3165 temp = I915_READ(fdi_rx_reg);
3166 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3167 udelay(200);
3168 }
3169 }
3170
3171 I915_WRITE(pipeconf_reg, pipeconf);
3172 I915_READ(pipeconf_reg);
3173
3174 intel_wait_for_vblank(dev);
3175
3176 if (IS_IGDNG(dev)) {
3177 /* enable address swizzle for tiling buffer */
3178 temp = I915_READ(DISP_ARB_CTL);
3179 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3180 }
3181
3182 I915_WRITE(dspcntr_reg, dspcntr);
3183
3184 /* Flush the plane changes */
3185 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3186
3187 if ((IS_I965G(dev) || plane == 0))
3188 intel_update_fbc(crtc, &crtc->mode);
3189
3190 intel_update_watermarks(dev);
3191
3192 drm_vblank_post_modeset(dev, pipe);
3193
3194 return ret;
3195 }
3196
3197 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3198 void intel_crtc_load_lut(struct drm_crtc *crtc)
3199 {
3200 struct drm_device *dev = crtc->dev;
3201 struct drm_i915_private *dev_priv = dev->dev_private;
3202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3203 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3204 int i;
3205
3206 /* The clocks have to be on to load the palette. */
3207 if (!crtc->enabled)
3208 return;
3209
3210 /* use legacy palette for IGDNG */
3211 if (IS_IGDNG(dev))
3212 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3213 LGC_PALETTE_B;
3214
3215 for (i = 0; i < 256; i++) {
3216 I915_WRITE(palreg + 4 * i,
3217 (intel_crtc->lut_r[i] << 16) |
3218 (intel_crtc->lut_g[i] << 8) |
3219 intel_crtc->lut_b[i]);
3220 }
3221 }
3222
3223 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3224 struct drm_file *file_priv,
3225 uint32_t handle,
3226 uint32_t width, uint32_t height)
3227 {
3228 struct drm_device *dev = crtc->dev;
3229 struct drm_i915_private *dev_priv = dev->dev_private;
3230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3231 struct drm_gem_object *bo;
3232 struct drm_i915_gem_object *obj_priv;
3233 int pipe = intel_crtc->pipe;
3234 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3235 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3236 uint32_t temp = I915_READ(control);
3237 size_t addr;
3238 int ret;
3239
3240 DRM_DEBUG("\n");
3241
3242 /* if we want to turn off the cursor ignore width and height */
3243 if (!handle) {
3244 DRM_DEBUG("cursor off\n");
3245 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3246 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3247 temp |= CURSOR_MODE_DISABLE;
3248 } else {
3249 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3250 }
3251 addr = 0;
3252 bo = NULL;
3253 mutex_lock(&dev->struct_mutex);
3254 goto finish;
3255 }
3256
3257 /* Currently we only support 64x64 cursors */
3258 if (width != 64 || height != 64) {
3259 DRM_ERROR("we currently only support 64x64 cursors\n");
3260 return -EINVAL;
3261 }
3262
3263 bo = drm_gem_object_lookup(dev, file_priv, handle);
3264 if (!bo)
3265 return -ENOENT;
3266
3267 obj_priv = bo->driver_private;
3268
3269 if (bo->size < width * height * 4) {
3270 DRM_ERROR("buffer is to small\n");
3271 ret = -ENOMEM;
3272 goto fail;
3273 }
3274
3275 /* we only need to pin inside GTT if cursor is non-phy */
3276 mutex_lock(&dev->struct_mutex);
3277 if (!dev_priv->cursor_needs_physical) {
3278 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3279 if (ret) {
3280 DRM_ERROR("failed to pin cursor bo\n");
3281 goto fail_locked;
3282 }
3283 addr = obj_priv->gtt_offset;
3284 } else {
3285 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3286 if (ret) {
3287 DRM_ERROR("failed to attach phys object\n");
3288 goto fail_locked;
3289 }
3290 addr = obj_priv->phys_obj->handle->busaddr;
3291 }
3292
3293 if (!IS_I9XX(dev))
3294 I915_WRITE(CURSIZE, (height << 12) | width);
3295
3296 /* Hooray for CUR*CNTR differences */
3297 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3298 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3299 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3300 temp |= (pipe << 28); /* Connect to correct pipe */
3301 } else {
3302 temp &= ~(CURSOR_FORMAT_MASK);
3303 temp |= CURSOR_ENABLE;
3304 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3305 }
3306
3307 finish:
3308 I915_WRITE(control, temp);
3309 I915_WRITE(base, addr);
3310
3311 if (intel_crtc->cursor_bo) {
3312 if (dev_priv->cursor_needs_physical) {
3313 if (intel_crtc->cursor_bo != bo)
3314 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3315 } else
3316 i915_gem_object_unpin(intel_crtc->cursor_bo);
3317 drm_gem_object_unreference(intel_crtc->cursor_bo);
3318 }
3319
3320 mutex_unlock(&dev->struct_mutex);
3321
3322 intel_crtc->cursor_addr = addr;
3323 intel_crtc->cursor_bo = bo;
3324
3325 return 0;
3326 fail:
3327 mutex_lock(&dev->struct_mutex);
3328 fail_locked:
3329 drm_gem_object_unreference(bo);
3330 mutex_unlock(&dev->struct_mutex);
3331 return ret;
3332 }
3333
3334 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3335 {
3336 struct drm_device *dev = crtc->dev;
3337 struct drm_i915_private *dev_priv = dev->dev_private;
3338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3339 struct intel_framebuffer *intel_fb;
3340 int pipe = intel_crtc->pipe;
3341 uint32_t temp = 0;
3342 uint32_t adder;
3343
3344 if (crtc->fb) {
3345 intel_fb = to_intel_framebuffer(crtc->fb);
3346 intel_mark_busy(dev, intel_fb->obj);
3347 }
3348
3349 if (x < 0) {
3350 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3351 x = -x;
3352 }
3353 if (y < 0) {
3354 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3355 y = -y;
3356 }
3357
3358 temp |= x << CURSOR_X_SHIFT;
3359 temp |= y << CURSOR_Y_SHIFT;
3360
3361 adder = intel_crtc->cursor_addr;
3362 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3363 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3364
3365 return 0;
3366 }
3367
3368 /** Sets the color ramps on behalf of RandR */
3369 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3370 u16 blue, int regno)
3371 {
3372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3373
3374 intel_crtc->lut_r[regno] = red >> 8;
3375 intel_crtc->lut_g[regno] = green >> 8;
3376 intel_crtc->lut_b[regno] = blue >> 8;
3377 }
3378
3379 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3380 u16 *blue, int regno)
3381 {
3382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3383
3384 *red = intel_crtc->lut_r[regno] << 8;
3385 *green = intel_crtc->lut_g[regno] << 8;
3386 *blue = intel_crtc->lut_b[regno] << 8;
3387 }
3388
3389 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3390 u16 *blue, uint32_t size)
3391 {
3392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3393 int i;
3394
3395 if (size != 256)
3396 return;
3397
3398 for (i = 0; i < 256; i++) {
3399 intel_crtc->lut_r[i] = red[i] >> 8;
3400 intel_crtc->lut_g[i] = green[i] >> 8;
3401 intel_crtc->lut_b[i] = blue[i] >> 8;
3402 }
3403
3404 intel_crtc_load_lut(crtc);
3405 }
3406
3407 /**
3408 * Get a pipe with a simple mode set on it for doing load-based monitor
3409 * detection.
3410 *
3411 * It will be up to the load-detect code to adjust the pipe as appropriate for
3412 * its requirements. The pipe will be connected to no other outputs.
3413 *
3414 * Currently this code will only succeed if there is a pipe with no outputs
3415 * configured for it. In the future, it could choose to temporarily disable
3416 * some outputs to free up a pipe for its use.
3417 *
3418 * \return crtc, or NULL if no pipes are available.
3419 */
3420
3421 /* VESA 640x480x72Hz mode to set on the pipe */
3422 static struct drm_display_mode load_detect_mode = {
3423 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3424 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3425 };
3426
3427 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3428 struct drm_display_mode *mode,
3429 int *dpms_mode)
3430 {
3431 struct intel_crtc *intel_crtc;
3432 struct drm_crtc *possible_crtc;
3433 struct drm_crtc *supported_crtc =NULL;
3434 struct drm_encoder *encoder = &intel_output->enc;
3435 struct drm_crtc *crtc = NULL;
3436 struct drm_device *dev = encoder->dev;
3437 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3438 struct drm_crtc_helper_funcs *crtc_funcs;
3439 int i = -1;
3440
3441 /*
3442 * Algorithm gets a little messy:
3443 * - if the connector already has an assigned crtc, use it (but make
3444 * sure it's on first)
3445 * - try to find the first unused crtc that can drive this connector,
3446 * and use that if we find one
3447 * - if there are no unused crtcs available, try to use the first
3448 * one we found that supports the connector
3449 */
3450
3451 /* See if we already have a CRTC for this connector */
3452 if (encoder->crtc) {
3453 crtc = encoder->crtc;
3454 /* Make sure the crtc and connector are running */
3455 intel_crtc = to_intel_crtc(crtc);
3456 *dpms_mode = intel_crtc->dpms_mode;
3457 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3458 crtc_funcs = crtc->helper_private;
3459 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3460 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3461 }
3462 return crtc;
3463 }
3464
3465 /* Find an unused one (if possible) */
3466 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3467 i++;
3468 if (!(encoder->possible_crtcs & (1 << i)))
3469 continue;
3470 if (!possible_crtc->enabled) {
3471 crtc = possible_crtc;
3472 break;
3473 }
3474 if (!supported_crtc)
3475 supported_crtc = possible_crtc;
3476 }
3477
3478 /*
3479 * If we didn't find an unused CRTC, don't use any.
3480 */
3481 if (!crtc) {
3482 return NULL;
3483 }
3484
3485 encoder->crtc = crtc;
3486 intel_output->base.encoder = encoder;
3487 intel_output->load_detect_temp = true;
3488
3489 intel_crtc = to_intel_crtc(crtc);
3490 *dpms_mode = intel_crtc->dpms_mode;
3491
3492 if (!crtc->enabled) {
3493 if (!mode)
3494 mode = &load_detect_mode;
3495 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3496 } else {
3497 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3498 crtc_funcs = crtc->helper_private;
3499 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3500 }
3501
3502 /* Add this connector to the crtc */
3503 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3504 encoder_funcs->commit(encoder);
3505 }
3506 /* let the connector get through one full cycle before testing */
3507 intel_wait_for_vblank(dev);
3508
3509 return crtc;
3510 }
3511
3512 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3513 {
3514 struct drm_encoder *encoder = &intel_output->enc;
3515 struct drm_device *dev = encoder->dev;
3516 struct drm_crtc *crtc = encoder->crtc;
3517 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3518 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3519
3520 if (intel_output->load_detect_temp) {
3521 encoder->crtc = NULL;
3522 intel_output->base.encoder = NULL;
3523 intel_output->load_detect_temp = false;
3524 crtc->enabled = drm_helper_crtc_in_use(crtc);
3525 drm_helper_disable_unused_functions(dev);
3526 }
3527
3528 /* Switch crtc and output back off if necessary */
3529 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3530 if (encoder->crtc == crtc)
3531 encoder_funcs->dpms(encoder, dpms_mode);
3532 crtc_funcs->dpms(crtc, dpms_mode);
3533 }
3534 }
3535
3536 /* Returns the clock of the currently programmed mode of the given pipe. */
3537 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3538 {
3539 struct drm_i915_private *dev_priv = dev->dev_private;
3540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3541 int pipe = intel_crtc->pipe;
3542 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3543 u32 fp;
3544 intel_clock_t clock;
3545
3546 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3547 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3548 else
3549 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3550
3551 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3552 if (IS_IGD(dev)) {
3553 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3554 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3555 } else {
3556 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3557 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3558 }
3559
3560 if (IS_I9XX(dev)) {
3561 if (IS_IGD(dev))
3562 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3563 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3564 else
3565 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3566 DPLL_FPA01_P1_POST_DIV_SHIFT);
3567
3568 switch (dpll & DPLL_MODE_MASK) {
3569 case DPLLB_MODE_DAC_SERIAL:
3570 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3571 5 : 10;
3572 break;
3573 case DPLLB_MODE_LVDS:
3574 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3575 7 : 14;
3576 break;
3577 default:
3578 DRM_DEBUG("Unknown DPLL mode %08x in programmed "
3579 "mode\n", (int)(dpll & DPLL_MODE_MASK));
3580 return 0;
3581 }
3582
3583 /* XXX: Handle the 100Mhz refclk */
3584 intel_clock(dev, 96000, &clock);
3585 } else {
3586 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3587
3588 if (is_lvds) {
3589 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3590 DPLL_FPA01_P1_POST_DIV_SHIFT);
3591 clock.p2 = 14;
3592
3593 if ((dpll & PLL_REF_INPUT_MASK) ==
3594 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3595 /* XXX: might not be 66MHz */
3596 intel_clock(dev, 66000, &clock);
3597 } else
3598 intel_clock(dev, 48000, &clock);
3599 } else {
3600 if (dpll & PLL_P1_DIVIDE_BY_TWO)
3601 clock.p1 = 2;
3602 else {
3603 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3604 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3605 }
3606 if (dpll & PLL_P2_DIVIDE_BY_4)
3607 clock.p2 = 4;
3608 else
3609 clock.p2 = 2;
3610
3611 intel_clock(dev, 48000, &clock);
3612 }
3613 }
3614
3615 /* XXX: It would be nice to validate the clocks, but we can't reuse
3616 * i830PllIsValid() because it relies on the xf86_config connector
3617 * configuration being accurate, which it isn't necessarily.
3618 */
3619
3620 return clock.dot;
3621 }
3622
3623 /** Returns the currently programmed mode of the given pipe. */
3624 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3625 struct drm_crtc *crtc)
3626 {
3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629 int pipe = intel_crtc->pipe;
3630 struct drm_display_mode *mode;
3631 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3632 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3633 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3634 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3635
3636 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3637 if (!mode)
3638 return NULL;
3639
3640 mode->clock = intel_crtc_clock_get(dev, crtc);
3641 mode->hdisplay = (htot & 0xffff) + 1;
3642 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3643 mode->hsync_start = (hsync & 0xffff) + 1;
3644 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3645 mode->vdisplay = (vtot & 0xffff) + 1;
3646 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3647 mode->vsync_start = (vsync & 0xffff) + 1;
3648 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3649
3650 drm_mode_set_name(mode);
3651 drm_mode_set_crtcinfo(mode, 0);
3652
3653 return mode;
3654 }
3655
3656 #define GPU_IDLE_TIMEOUT 500 /* ms */
3657
3658 /* When this timer fires, we've been idle for awhile */
3659 static void intel_gpu_idle_timer(unsigned long arg)
3660 {
3661 struct drm_device *dev = (struct drm_device *)arg;
3662 drm_i915_private_t *dev_priv = dev->dev_private;
3663
3664 DRM_DEBUG("idle timer fired, downclocking\n");
3665
3666 dev_priv->busy = false;
3667
3668 queue_work(dev_priv->wq, &dev_priv->idle_work);
3669 }
3670
3671 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3672 {
3673 drm_i915_private_t *dev_priv = dev->dev_private;
3674
3675 if (IS_IGDNG(dev))
3676 return;
3677
3678 if (!dev_priv->render_reclock_avail) {
3679 DRM_DEBUG("not reclocking render clock\n");
3680 return;
3681 }
3682
3683 /* Restore render clock frequency to original value */
3684 if (IS_G4X(dev) || IS_I9XX(dev))
3685 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3686 else if (IS_I85X(dev))
3687 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3688 DRM_DEBUG("increasing render clock frequency\n");
3689
3690 /* Schedule downclock */
3691 if (schedule)
3692 mod_timer(&dev_priv->idle_timer, jiffies +
3693 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3694 }
3695
3696 void intel_decrease_renderclock(struct drm_device *dev)
3697 {
3698 drm_i915_private_t *dev_priv = dev->dev_private;
3699
3700 if (IS_IGDNG(dev))
3701 return;
3702
3703 if (!dev_priv->render_reclock_avail) {
3704 DRM_DEBUG("not reclocking render clock\n");
3705 return;
3706 }
3707
3708 if (IS_G4X(dev)) {
3709 u16 gcfgc;
3710
3711 /* Adjust render clock... */
3712 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3713
3714 /* Down to minimum... */
3715 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3716 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3717
3718 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3719 } else if (IS_I965G(dev)) {
3720 u16 gcfgc;
3721
3722 /* Adjust render clock... */
3723 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3724
3725 /* Down to minimum... */
3726 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3727 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3728
3729 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3730 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3731 u16 gcfgc;
3732
3733 /* Adjust render clock... */
3734 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3735
3736 /* Down to minimum... */
3737 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3738 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3739
3740 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3741 } else if (IS_I915G(dev)) {
3742 u16 gcfgc;
3743
3744 /* Adjust render clock... */
3745 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3746
3747 /* Down to minimum... */
3748 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3749 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3750
3751 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3752 } else if (IS_I85X(dev)) {
3753 u16 hpllcc;
3754
3755 /* Adjust render clock... */
3756 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3757
3758 /* Up to maximum... */
3759 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3760 hpllcc |= GC_CLOCK_133_200;
3761
3762 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3763 }
3764 DRM_DEBUG("decreasing render clock frequency\n");
3765 }
3766
3767 /* Note that no increase function is needed for this - increase_renderclock()
3768 * will also rewrite these bits
3769 */
3770 void intel_decrease_displayclock(struct drm_device *dev)
3771 {
3772 if (IS_IGDNG(dev))
3773 return;
3774
3775 if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3776 IS_I915GM(dev)) {
3777 u16 gcfgc;
3778
3779 /* Adjust render clock... */
3780 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3781
3782 /* Down to minimum... */
3783 gcfgc &= ~0xf0;
3784 gcfgc |= 0x80;
3785
3786 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3787 }
3788 }
3789
3790 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3791
3792 static void intel_crtc_idle_timer(unsigned long arg)
3793 {
3794 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3795 struct drm_crtc *crtc = &intel_crtc->base;
3796 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3797
3798 DRM_DEBUG("idle timer fired, downclocking\n");
3799
3800 intel_crtc->busy = false;
3801
3802 queue_work(dev_priv->wq, &dev_priv->idle_work);
3803 }
3804
3805 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3806 {
3807 struct drm_device *dev = crtc->dev;
3808 drm_i915_private_t *dev_priv = dev->dev_private;
3809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3810 int pipe = intel_crtc->pipe;
3811 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3812 int dpll = I915_READ(dpll_reg);
3813
3814 if (IS_IGDNG(dev))
3815 return;
3816
3817 if (!dev_priv->lvds_downclock_avail)
3818 return;
3819
3820 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3821 DRM_DEBUG("upclocking LVDS\n");
3822
3823 /* Unlock panel regs */
3824 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3825
3826 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3827 I915_WRITE(dpll_reg, dpll);
3828 dpll = I915_READ(dpll_reg);
3829 intel_wait_for_vblank(dev);
3830 dpll = I915_READ(dpll_reg);
3831 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3832 DRM_DEBUG("failed to upclock LVDS!\n");
3833
3834 /* ...and lock them again */
3835 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3836 }
3837
3838 /* Schedule downclock */
3839 if (schedule)
3840 mod_timer(&intel_crtc->idle_timer, jiffies +
3841 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3842 }
3843
3844 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3845 {
3846 struct drm_device *dev = crtc->dev;
3847 drm_i915_private_t *dev_priv = dev->dev_private;
3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849 int pipe = intel_crtc->pipe;
3850 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3851 int dpll = I915_READ(dpll_reg);
3852
3853 if (IS_IGDNG(dev))
3854 return;
3855
3856 if (!dev_priv->lvds_downclock_avail)
3857 return;
3858
3859 /*
3860 * Since this is called by a timer, we should never get here in
3861 * the manual case.
3862 */
3863 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3864 DRM_DEBUG("downclocking LVDS\n");
3865
3866 /* Unlock panel regs */
3867 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3868
3869 dpll |= DISPLAY_RATE_SELECT_FPA1;
3870 I915_WRITE(dpll_reg, dpll);
3871 dpll = I915_READ(dpll_reg);
3872 intel_wait_for_vblank(dev);
3873 dpll = I915_READ(dpll_reg);
3874 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3875 DRM_DEBUG("failed to downclock LVDS!\n");
3876
3877 /* ...and lock them again */
3878 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3879 }
3880
3881 }
3882
3883 /**
3884 * intel_idle_update - adjust clocks for idleness
3885 * @work: work struct
3886 *
3887 * Either the GPU or display (or both) went idle. Check the busy status
3888 * here and adjust the CRTC and GPU clocks as necessary.
3889 */
3890 static void intel_idle_update(struct work_struct *work)
3891 {
3892 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3893 idle_work);
3894 struct drm_device *dev = dev_priv->dev;
3895 struct drm_crtc *crtc;
3896 struct intel_crtc *intel_crtc;
3897
3898 if (!i915_powersave)
3899 return;
3900
3901 mutex_lock(&dev->struct_mutex);
3902
3903 /* GPU isn't processing, downclock it. */
3904 if (!dev_priv->busy) {
3905 intel_decrease_renderclock(dev);
3906 intel_decrease_displayclock(dev);
3907 }
3908
3909 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3910 /* Skip inactive CRTCs */
3911 if (!crtc->fb)
3912 continue;
3913
3914 intel_crtc = to_intel_crtc(crtc);
3915 if (!intel_crtc->busy)
3916 intel_decrease_pllclock(crtc);
3917 }
3918
3919 mutex_unlock(&dev->struct_mutex);
3920 }
3921
3922 /**
3923 * intel_mark_busy - mark the GPU and possibly the display busy
3924 * @dev: drm device
3925 * @obj: object we're operating on
3926 *
3927 * Callers can use this function to indicate that the GPU is busy processing
3928 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
3929 * buffer), we'll also mark the display as busy, so we know to increase its
3930 * clock frequency.
3931 */
3932 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3933 {
3934 drm_i915_private_t *dev_priv = dev->dev_private;
3935 struct drm_crtc *crtc = NULL;
3936 struct intel_framebuffer *intel_fb;
3937 struct intel_crtc *intel_crtc;
3938
3939 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3940 return;
3941
3942 dev_priv->busy = true;
3943 intel_increase_renderclock(dev, true);
3944
3945 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3946 if (!crtc->fb)
3947 continue;
3948
3949 intel_crtc = to_intel_crtc(crtc);
3950 intel_fb = to_intel_framebuffer(crtc->fb);
3951 if (intel_fb->obj == obj) {
3952 if (!intel_crtc->busy) {
3953 /* Non-busy -> busy, upclock */
3954 intel_increase_pllclock(crtc, true);
3955 intel_crtc->busy = true;
3956 } else {
3957 /* Busy -> busy, put off timer */
3958 mod_timer(&intel_crtc->idle_timer, jiffies +
3959 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3960 }
3961 }
3962 }
3963 }
3964
3965 static void intel_crtc_destroy(struct drm_crtc *crtc)
3966 {
3967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3968
3969 drm_crtc_cleanup(crtc);
3970 kfree(intel_crtc);
3971 }
3972
3973 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
3974 .dpms = intel_crtc_dpms,
3975 .mode_fixup = intel_crtc_mode_fixup,
3976 .mode_set = intel_crtc_mode_set,
3977 .mode_set_base = intel_pipe_set_base,
3978 .prepare = intel_crtc_prepare,
3979 .commit = intel_crtc_commit,
3980 .load_lut = intel_crtc_load_lut,
3981 };
3982
3983 static const struct drm_crtc_funcs intel_crtc_funcs = {
3984 .cursor_set = intel_crtc_cursor_set,
3985 .cursor_move = intel_crtc_cursor_move,
3986 .gamma_set = intel_crtc_gamma_set,
3987 .set_config = drm_crtc_helper_set_config,
3988 .destroy = intel_crtc_destroy,
3989 };
3990
3991
3992 static void intel_crtc_init(struct drm_device *dev, int pipe)
3993 {
3994 struct intel_crtc *intel_crtc;
3995 int i;
3996
3997 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
3998 if (intel_crtc == NULL)
3999 return;
4000
4001 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4002
4003 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4004 intel_crtc->pipe = pipe;
4005 intel_crtc->plane = pipe;
4006 for (i = 0; i < 256; i++) {
4007 intel_crtc->lut_r[i] = i;
4008 intel_crtc->lut_g[i] = i;
4009 intel_crtc->lut_b[i] = i;
4010 }
4011
4012 /* Swap pipes & planes for FBC on pre-965 */
4013 intel_crtc->pipe = pipe;
4014 intel_crtc->plane = pipe;
4015 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4016 DRM_DEBUG("swapping pipes & planes for FBC\n");
4017 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4018 }
4019
4020 intel_crtc->cursor_addr = 0;
4021 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4022 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4023
4024 intel_crtc->busy = false;
4025
4026 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4027 (unsigned long)intel_crtc);
4028 }
4029
4030 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4031 struct drm_file *file_priv)
4032 {
4033 drm_i915_private_t *dev_priv = dev->dev_private;
4034 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4035 struct drm_mode_object *drmmode_obj;
4036 struct intel_crtc *crtc;
4037
4038 if (!dev_priv) {
4039 DRM_ERROR("called with no initialization\n");
4040 return -EINVAL;
4041 }
4042
4043 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4044 DRM_MODE_OBJECT_CRTC);
4045
4046 if (!drmmode_obj) {
4047 DRM_ERROR("no such CRTC id\n");
4048 return -EINVAL;
4049 }
4050
4051 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4052 pipe_from_crtc_id->pipe = crtc->pipe;
4053
4054 return 0;
4055 }
4056
4057 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4058 {
4059 struct drm_crtc *crtc = NULL;
4060
4061 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4063 if (intel_crtc->pipe == pipe)
4064 break;
4065 }
4066 return crtc;
4067 }
4068
4069 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4070 {
4071 int index_mask = 0;
4072 struct drm_connector *connector;
4073 int entry = 0;
4074
4075 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4076 struct intel_output *intel_output = to_intel_output(connector);
4077 if (type_mask & intel_output->clone_mask)
4078 index_mask |= (1 << entry);
4079 entry++;
4080 }
4081 return index_mask;
4082 }
4083
4084
4085 static void intel_setup_outputs(struct drm_device *dev)
4086 {
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088 struct drm_connector *connector;
4089
4090 intel_crt_init(dev);
4091
4092 /* Set up integrated LVDS */
4093 if (IS_MOBILE(dev) && !IS_I830(dev))
4094 intel_lvds_init(dev);
4095
4096 if (IS_IGDNG(dev)) {
4097 int found;
4098
4099 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4100 intel_dp_init(dev, DP_A);
4101
4102 if (I915_READ(HDMIB) & PORT_DETECTED) {
4103 /* check SDVOB */
4104 /* found = intel_sdvo_init(dev, HDMIB); */
4105 found = 0;
4106 if (!found)
4107 intel_hdmi_init(dev, HDMIB);
4108 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4109 intel_dp_init(dev, PCH_DP_B);
4110 }
4111
4112 if (I915_READ(HDMIC) & PORT_DETECTED)
4113 intel_hdmi_init(dev, HDMIC);
4114
4115 if (I915_READ(HDMID) & PORT_DETECTED)
4116 intel_hdmi_init(dev, HDMID);
4117
4118 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4119 intel_dp_init(dev, PCH_DP_C);
4120
4121 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4122 intel_dp_init(dev, PCH_DP_D);
4123
4124 } else if (IS_I9XX(dev)) {
4125 bool found = false;
4126
4127 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4128 found = intel_sdvo_init(dev, SDVOB);
4129 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
4130 intel_hdmi_init(dev, SDVOB);
4131
4132 if (!found && SUPPORTS_INTEGRATED_DP(dev))
4133 intel_dp_init(dev, DP_B);
4134 }
4135
4136 /* Before G4X SDVOC doesn't have its own detect register */
4137
4138 if (I915_READ(SDVOB) & SDVO_DETECTED)
4139 found = intel_sdvo_init(dev, SDVOC);
4140
4141 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4142
4143 if (SUPPORTS_INTEGRATED_HDMI(dev))
4144 intel_hdmi_init(dev, SDVOC);
4145 if (SUPPORTS_INTEGRATED_DP(dev))
4146 intel_dp_init(dev, DP_C);
4147 }
4148
4149 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
4150 intel_dp_init(dev, DP_D);
4151 } else
4152 intel_dvo_init(dev);
4153
4154 if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
4155 intel_tv_init(dev);
4156
4157 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4158 struct intel_output *intel_output = to_intel_output(connector);
4159 struct drm_encoder *encoder = &intel_output->enc;
4160
4161 encoder->possible_crtcs = intel_output->crtc_mask;
4162 encoder->possible_clones = intel_connector_clones(dev,
4163 intel_output->clone_mask);
4164 }
4165 }
4166
4167 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4168 {
4169 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4170 struct drm_device *dev = fb->dev;
4171
4172 if (fb->fbdev)
4173 intelfb_remove(dev, fb);
4174
4175 drm_framebuffer_cleanup(fb);
4176 mutex_lock(&dev->struct_mutex);
4177 drm_gem_object_unreference(intel_fb->obj);
4178 mutex_unlock(&dev->struct_mutex);
4179
4180 kfree(intel_fb);
4181 }
4182
4183 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4184 struct drm_file *file_priv,
4185 unsigned int *handle)
4186 {
4187 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4188 struct drm_gem_object *object = intel_fb->obj;
4189
4190 return drm_gem_handle_create(file_priv, object, handle);
4191 }
4192
4193 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4194 .destroy = intel_user_framebuffer_destroy,
4195 .create_handle = intel_user_framebuffer_create_handle,
4196 };
4197
4198 int intel_framebuffer_create(struct drm_device *dev,
4199 struct drm_mode_fb_cmd *mode_cmd,
4200 struct drm_framebuffer **fb,
4201 struct drm_gem_object *obj)
4202 {
4203 struct intel_framebuffer *intel_fb;
4204 int ret;
4205
4206 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4207 if (!intel_fb)
4208 return -ENOMEM;
4209
4210 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4211 if (ret) {
4212 DRM_ERROR("framebuffer init failed %d\n", ret);
4213 return ret;
4214 }
4215
4216 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4217
4218 intel_fb->obj = obj;
4219
4220 *fb = &intel_fb->base;
4221
4222 return 0;
4223 }
4224
4225
4226 static struct drm_framebuffer *
4227 intel_user_framebuffer_create(struct drm_device *dev,
4228 struct drm_file *filp,
4229 struct drm_mode_fb_cmd *mode_cmd)
4230 {
4231 struct drm_gem_object *obj;
4232 struct drm_framebuffer *fb;
4233 int ret;
4234
4235 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4236 if (!obj)
4237 return NULL;
4238
4239 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4240 if (ret) {
4241 mutex_lock(&dev->struct_mutex);
4242 drm_gem_object_unreference(obj);
4243 mutex_unlock(&dev->struct_mutex);
4244 return NULL;
4245 }
4246
4247 return fb;
4248 }
4249
4250 static const struct drm_mode_config_funcs intel_mode_funcs = {
4251 .fb_create = intel_user_framebuffer_create,
4252 .fb_changed = intelfb_probe,
4253 };
4254
4255 void intel_init_clock_gating(struct drm_device *dev)
4256 {
4257 struct drm_i915_private *dev_priv = dev->dev_private;
4258
4259 /*
4260 * Disable clock gating reported to work incorrectly according to the
4261 * specs, but enable as much else as we can.
4262 */
4263 if (IS_IGDNG(dev)) {
4264 return;
4265 } else if (IS_G4X(dev)) {
4266 uint32_t dspclk_gate;
4267 I915_WRITE(RENCLK_GATE_D1, 0);
4268 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4269 GS_UNIT_CLOCK_GATE_DISABLE |
4270 CL_UNIT_CLOCK_GATE_DISABLE);
4271 I915_WRITE(RAMCLK_GATE_D, 0);
4272 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4273 OVRUNIT_CLOCK_GATE_DISABLE |
4274 OVCUNIT_CLOCK_GATE_DISABLE;
4275 if (IS_GM45(dev))
4276 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4277 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4278 } else if (IS_I965GM(dev)) {
4279 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4280 I915_WRITE(RENCLK_GATE_D2, 0);
4281 I915_WRITE(DSPCLK_GATE_D, 0);
4282 I915_WRITE(RAMCLK_GATE_D, 0);
4283 I915_WRITE16(DEUC, 0);
4284 } else if (IS_I965G(dev)) {
4285 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4286 I965_RCC_CLOCK_GATE_DISABLE |
4287 I965_RCPB_CLOCK_GATE_DISABLE |
4288 I965_ISC_CLOCK_GATE_DISABLE |
4289 I965_FBC_CLOCK_GATE_DISABLE);
4290 I915_WRITE(RENCLK_GATE_D2, 0);
4291 } else if (IS_I9XX(dev)) {
4292 u32 dstate = I915_READ(D_STATE);
4293
4294 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4295 DSTATE_DOT_CLOCK_GATING;
4296 I915_WRITE(D_STATE, dstate);
4297 } else if (IS_I855(dev) || IS_I865G(dev)) {
4298 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4299 } else if (IS_I830(dev)) {
4300 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4301 }
4302 }
4303
4304 /* Set up chip specific display functions */
4305 static void intel_init_display(struct drm_device *dev)
4306 {
4307 struct drm_i915_private *dev_priv = dev->dev_private;
4308
4309 /* We always want a DPMS function */
4310 if (IS_IGDNG(dev))
4311 dev_priv->display.dpms = igdng_crtc_dpms;
4312 else
4313 dev_priv->display.dpms = i9xx_crtc_dpms;
4314
4315 /* Only mobile has FBC, leave pointers NULL for other chips */
4316 if (IS_MOBILE(dev)) {
4317 if (IS_GM45(dev)) {
4318 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4319 dev_priv->display.enable_fbc = g4x_enable_fbc;
4320 dev_priv->display.disable_fbc = g4x_disable_fbc;
4321 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4322 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4323 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4324 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4325 }
4326 /* 855GM needs testing */
4327 }
4328
4329 /* Returns the core display clock speed */
4330 if (IS_I945G(dev))
4331 dev_priv->display.get_display_clock_speed =
4332 i945_get_display_clock_speed;
4333 else if (IS_I915G(dev))
4334 dev_priv->display.get_display_clock_speed =
4335 i915_get_display_clock_speed;
4336 else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
4337 dev_priv->display.get_display_clock_speed =
4338 i9xx_misc_get_display_clock_speed;
4339 else if (IS_I915GM(dev))
4340 dev_priv->display.get_display_clock_speed =
4341 i915gm_get_display_clock_speed;
4342 else if (IS_I865G(dev))
4343 dev_priv->display.get_display_clock_speed =
4344 i865_get_display_clock_speed;
4345 else if (IS_I855(dev))
4346 dev_priv->display.get_display_clock_speed =
4347 i855_get_display_clock_speed;
4348 else /* 852, 830 */
4349 dev_priv->display.get_display_clock_speed =
4350 i830_get_display_clock_speed;
4351
4352 /* For FIFO watermark updates */
4353 if (IS_IGDNG(dev))
4354 dev_priv->display.update_wm = NULL;
4355 else if (IS_G4X(dev))
4356 dev_priv->display.update_wm = g4x_update_wm;
4357 else if (IS_I965G(dev))
4358 dev_priv->display.update_wm = i965_update_wm;
4359 else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4360 dev_priv->display.update_wm = i9xx_update_wm;
4361 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4362 } else {
4363 if (IS_I85X(dev))
4364 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4365 else if (IS_845G(dev))
4366 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4367 else
4368 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4369 dev_priv->display.update_wm = i830_update_wm;
4370 }
4371 }
4372
4373 void intel_modeset_init(struct drm_device *dev)
4374 {
4375 struct drm_i915_private *dev_priv = dev->dev_private;
4376 int num_pipe;
4377 int i;
4378
4379 drm_mode_config_init(dev);
4380
4381 dev->mode_config.min_width = 0;
4382 dev->mode_config.min_height = 0;
4383
4384 dev->mode_config.funcs = (void *)&intel_mode_funcs;
4385
4386 intel_init_display(dev);
4387
4388 if (IS_I965G(dev)) {
4389 dev->mode_config.max_width = 8192;
4390 dev->mode_config.max_height = 8192;
4391 } else if (IS_I9XX(dev)) {
4392 dev->mode_config.max_width = 4096;
4393 dev->mode_config.max_height = 4096;
4394 } else {
4395 dev->mode_config.max_width = 2048;
4396 dev->mode_config.max_height = 2048;
4397 }
4398
4399 /* set memory base */
4400 if (IS_I9XX(dev))
4401 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4402 else
4403 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4404
4405 if (IS_MOBILE(dev) || IS_I9XX(dev))
4406 num_pipe = 2;
4407 else
4408 num_pipe = 1;
4409 DRM_DEBUG("%d display pipe%s available.\n",
4410 num_pipe, num_pipe > 1 ? "s" : "");
4411
4412 if (IS_I85X(dev))
4413 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4414 else if (IS_I9XX(dev) || IS_G4X(dev))
4415 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4416
4417 for (i = 0; i < num_pipe; i++) {
4418 intel_crtc_init(dev, i);
4419 }
4420
4421 intel_setup_outputs(dev);
4422
4423 intel_init_clock_gating(dev);
4424
4425 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4426 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4427 (unsigned long)dev);
4428 }
4429
4430 void intel_modeset_cleanup(struct drm_device *dev)
4431 {
4432 struct drm_i915_private *dev_priv = dev->dev_private;
4433 struct drm_crtc *crtc;
4434 struct intel_crtc *intel_crtc;
4435
4436 mutex_lock(&dev->struct_mutex);
4437
4438 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4439 /* Skip inactive CRTCs */
4440 if (!crtc->fb)
4441 continue;
4442
4443 intel_crtc = to_intel_crtc(crtc);
4444 intel_increase_pllclock(crtc, false);
4445 del_timer_sync(&intel_crtc->idle_timer);
4446 }
4447
4448 intel_increase_renderclock(dev, false);
4449 del_timer_sync(&dev_priv->idle_timer);
4450
4451 mutex_unlock(&dev->struct_mutex);
4452
4453 if (dev_priv->display.disable_fbc)
4454 dev_priv->display.disable_fbc(dev);
4455
4456 drm_mode_config_cleanup(dev);
4457 }
4458
4459
4460 /* current intel driver doesn't take advantage of encoders
4461 always give back the encoder for the connector
4462 */
4463 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4464 {
4465 struct intel_output *intel_output = to_intel_output(connector);
4466
4467 return &intel_output->enc;
4468 }
4469
4470 /*
4471 * set vga decode state - true == enable VGA decode
4472 */
4473 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4474 {
4475 struct drm_i915_private *dev_priv = dev->dev_private;
4476 u16 gmch_ctrl;
4477
4478 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4479 if (state)
4480 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4481 else
4482 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4483 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4484 return 0;
4485 }
Linux with added FPC-III support