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x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / radeon_atombios.c
blob2ed88a820935fd26c0877e061b9bc82505535e26
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 /* from radeon_encoder.c */
34 extern uint32_t
35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
38 extern void
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42 /* from radeon_connector.c */
43 extern void
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info,
50 uint16_t connector_object_id);
51
52 /* from radeon_legacy_encoder.c */
53 extern void
54 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
55 uint32_t supported_device);
56
57 union atom_supported_devices {
58 struct _ATOM_SUPPORTED_DEVICES_INFO info;
59 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
61 };
62
63 static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
64 *dev, uint8_t id)
65 {
66 struct radeon_device *rdev = dev->dev_private;
67 struct atom_context *ctx = rdev->mode_info.atom_context;
68 ATOM_GPIO_I2C_ASSIGMENT gpio;
69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
72 uint16_t data_offset;
73
74 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
75 i2c.valid = false;
76
77 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
78
79 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
80
81 gpio = i2c_info->asGPIO_Info[id];
82
83 i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
84 i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
85 i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
86 i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
87 i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
88 i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
89 i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
90 i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
91 i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
92 i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
93 i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
94 i2c.put_data_mask = (1 << gpio.ucDataEnShift);
95 i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
96 i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
97 i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
98 i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
99 i2c.valid = true;
100
101 return i2c;
102 }
103
104 static bool radeon_atom_apply_quirks(struct drm_device *dev,
105 uint32_t supported_device,
106 int *connector_type,
107 struct radeon_i2c_bus_rec *i2c_bus,
108 uint16_t *line_mux)
109 {
110
111 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
112 if ((dev->pdev->device == 0x791e) &&
113 (dev->pdev->subsystem_vendor == 0x1043) &&
114 (dev->pdev->subsystem_device == 0x826d)) {
115 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
116 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
117 *connector_type = DRM_MODE_CONNECTOR_DVID;
118 }
119
120 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
121 if ((dev->pdev->device == 0x7941) &&
122 (dev->pdev->subsystem_vendor == 0x147b) &&
123 (dev->pdev->subsystem_device == 0x2412)) {
124 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
125 return false;
126 }
127
128 /* Falcon NW laptop lists vga ddc line for LVDS */
129 if ((dev->pdev->device == 0x5653) &&
130 (dev->pdev->subsystem_vendor == 0x1462) &&
131 (dev->pdev->subsystem_device == 0x0291)) {
132 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
133 i2c_bus->valid = false;
134 *line_mux = 53;
135 }
136 }
137
138 /* Funky macbooks */
139 if ((dev->pdev->device == 0x71C5) &&
140 (dev->pdev->subsystem_vendor == 0x106b) &&
141 (dev->pdev->subsystem_device == 0x0080)) {
142 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
143 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
144 return false;
145 }
146
147 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
148 if ((dev->pdev->device == 0x9598) &&
149 (dev->pdev->subsystem_vendor == 0x1043) &&
150 (dev->pdev->subsystem_device == 0x01da)) {
151 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
152 *connector_type = DRM_MODE_CONNECTOR_DVII;
153 }
154 }
155
156 /* ASUS HD 3450 board lists the DVI port as HDMI */
157 if ((dev->pdev->device == 0x95C5) &&
158 (dev->pdev->subsystem_vendor == 0x1043) &&
159 (dev->pdev->subsystem_device == 0x01e2)) {
160 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
161 *connector_type = DRM_MODE_CONNECTOR_DVII;
162 }
163 }
164
165 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
166 * HDMI + VGA reporting as HDMI
167 */
168 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
169 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
170 *connector_type = DRM_MODE_CONNECTOR_VGA;
171 *line_mux = 0;
172 }
173 }
174
175 return true;
176 }
177
178 const int supported_devices_connector_convert[] = {
179 DRM_MODE_CONNECTOR_Unknown,
180 DRM_MODE_CONNECTOR_VGA,
181 DRM_MODE_CONNECTOR_DVII,
182 DRM_MODE_CONNECTOR_DVID,
183 DRM_MODE_CONNECTOR_DVIA,
184 DRM_MODE_CONNECTOR_SVIDEO,
185 DRM_MODE_CONNECTOR_Composite,
186 DRM_MODE_CONNECTOR_LVDS,
187 DRM_MODE_CONNECTOR_Unknown,
188 DRM_MODE_CONNECTOR_Unknown,
189 DRM_MODE_CONNECTOR_HDMIA,
190 DRM_MODE_CONNECTOR_HDMIB,
191 DRM_MODE_CONNECTOR_Unknown,
192 DRM_MODE_CONNECTOR_Unknown,
193 DRM_MODE_CONNECTOR_9PinDIN,
194 DRM_MODE_CONNECTOR_DisplayPort
195 };
196
197 const uint16_t supported_devices_connector_object_id_convert[] = {
198 CONNECTOR_OBJECT_ID_NONE,
199 CONNECTOR_OBJECT_ID_VGA,
200 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
201 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
202 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
203 CONNECTOR_OBJECT_ID_COMPOSITE,
204 CONNECTOR_OBJECT_ID_SVIDEO,
205 CONNECTOR_OBJECT_ID_LVDS,
206 CONNECTOR_OBJECT_ID_9PIN_DIN,
207 CONNECTOR_OBJECT_ID_9PIN_DIN,
208 CONNECTOR_OBJECT_ID_DISPLAYPORT,
209 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
210 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
211 CONNECTOR_OBJECT_ID_SVIDEO
212 };
213
214 const int object_connector_convert[] = {
215 DRM_MODE_CONNECTOR_Unknown,
216 DRM_MODE_CONNECTOR_DVII,
217 DRM_MODE_CONNECTOR_DVII,
218 DRM_MODE_CONNECTOR_DVID,
219 DRM_MODE_CONNECTOR_DVID,
220 DRM_MODE_CONNECTOR_VGA,
221 DRM_MODE_CONNECTOR_Composite,
222 DRM_MODE_CONNECTOR_SVIDEO,
223 DRM_MODE_CONNECTOR_Unknown,
224 DRM_MODE_CONNECTOR_Unknown,
225 DRM_MODE_CONNECTOR_9PinDIN,
226 DRM_MODE_CONNECTOR_Unknown,
227 DRM_MODE_CONNECTOR_HDMIA,
228 DRM_MODE_CONNECTOR_HDMIB,
229 DRM_MODE_CONNECTOR_LVDS,
230 DRM_MODE_CONNECTOR_9PinDIN,
231 DRM_MODE_CONNECTOR_Unknown,
232 DRM_MODE_CONNECTOR_Unknown,
233 DRM_MODE_CONNECTOR_Unknown,
234 DRM_MODE_CONNECTOR_DisplayPort
235 };
236
237 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
238 {
239 struct radeon_device *rdev = dev->dev_private;
240 struct radeon_mode_info *mode_info = &rdev->mode_info;
241 struct atom_context *ctx = mode_info->atom_context;
242 int index = GetIndexIntoMasterTable(DATA, Object_Header);
243 uint16_t size, data_offset;
244 uint8_t frev, crev, line_mux = 0;
245 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
246 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
247 ATOM_OBJECT_HEADER *obj_header;
248 int i, j, path_size, device_support;
249 int connector_type;
250 uint16_t igp_lane_info, conn_id, connector_object_id;
251 bool linkb;
252 struct radeon_i2c_bus_rec ddc_bus;
253
254 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
255
256 if (data_offset == 0)
257 return false;
258
259 if (crev < 2)
260 return false;
261
262 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
263 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
264 (ctx->bios + data_offset +
265 le16_to_cpu(obj_header->usDisplayPathTableOffset));
266 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
267 (ctx->bios + data_offset +
268 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
269 device_support = le16_to_cpu(obj_header->usDeviceSupport);
270
271 path_size = 0;
272 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
273 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
274 ATOM_DISPLAY_OBJECT_PATH *path;
275 addr += path_size;
276 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
277 path_size += le16_to_cpu(path->usSize);
278 linkb = false;
279
280 if (device_support & le16_to_cpu(path->usDeviceTag)) {
281 uint8_t con_obj_id, con_obj_num, con_obj_type;
282
283 con_obj_id =
284 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
285 >> OBJECT_ID_SHIFT;
286 con_obj_num =
287 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
288 >> ENUM_ID_SHIFT;
289 con_obj_type =
290 (le16_to_cpu(path->usConnObjectId) &
291 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
292
293 /* TODO CV support */
294 if (le16_to_cpu(path->usDeviceTag) ==
295 ATOM_DEVICE_CV_SUPPORT)
296 continue;
297
298 /* IGP chips */
299 if ((rdev->flags & RADEON_IS_IGP) &&
300 (con_obj_id ==
301 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
302 uint16_t igp_offset = 0;
303 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
304
305 index =
306 GetIndexIntoMasterTable(DATA,
307 IntegratedSystemInfo);
308
309 atom_parse_data_header(ctx, index, &size, &frev,
310 &crev, &igp_offset);
311
312 if (crev >= 2) {
313 igp_obj =
314 (ATOM_INTEGRATED_SYSTEM_INFO_V2
315 *) (ctx->bios + igp_offset);
316
317 if (igp_obj) {
318 uint32_t slot_config, ct;
319
320 if (con_obj_num == 1)
321 slot_config =
322 igp_obj->
323 ulDDISlot1Config;
324 else
325 slot_config =
326 igp_obj->
327 ulDDISlot2Config;
328
329 ct = (slot_config >> 16) & 0xff;
330 connector_type =
331 object_connector_convert
332 [ct];
333 connector_object_id = ct;
334 igp_lane_info =
335 slot_config & 0xffff;
336 } else
337 continue;
338 } else
339 continue;
340 } else {
341 igp_lane_info = 0;
342 connector_type =
343 object_connector_convert[con_obj_id];
344 connector_object_id = con_obj_id;
345 }
346
347 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
348 continue;
349
350 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
351 j++) {
352 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
353
354 enc_obj_id =
355 (le16_to_cpu(path->usGraphicObjIds[j]) &
356 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
357 enc_obj_num =
358 (le16_to_cpu(path->usGraphicObjIds[j]) &
359 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
360 enc_obj_type =
361 (le16_to_cpu(path->usGraphicObjIds[j]) &
362 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
363
364 /* FIXME: add support for router objects */
365 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
366 if (enc_obj_num == 2)
367 linkb = true;
368 else
369 linkb = false;
370
371 radeon_add_atom_encoder(dev,
372 enc_obj_id,
373 le16_to_cpu
374 (path->
375 usDeviceTag));
376
377 }
378 }
379
380 /* look up gpio for ddc */
381 if ((le16_to_cpu(path->usDeviceTag) &
382 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
383 == 0) {
384 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
385 if (le16_to_cpu(path->usConnObjectId) ==
386 le16_to_cpu(con_obj->asObjects[j].
387 usObjectID)) {
388 ATOM_COMMON_RECORD_HEADER
389 *record =
390 (ATOM_COMMON_RECORD_HEADER
391 *)
392 (ctx->bios + data_offset +
393 le16_to_cpu(con_obj->
394 asObjects[j].
395 usRecordOffset));
396 ATOM_I2C_RECORD *i2c_record;
397
398 while (record->ucRecordType > 0
399 && record->
400 ucRecordType <=
401 ATOM_MAX_OBJECT_RECORD_NUMBER) {
402 switch (record->
403 ucRecordType) {
404 case ATOM_I2C_RECORD_TYPE:
405 i2c_record =
406 (ATOM_I2C_RECORD
407 *) record;
408 line_mux =
409 i2c_record->
410 sucI2cId.
411 bfI2C_LineMux;
412 break;
413 }
414 record =
415 (ATOM_COMMON_RECORD_HEADER
416 *) ((char *)record
417 +
418 record->
419 ucRecordSize);
420 }
421 break;
422 }
423 }
424 } else
425 line_mux = 0;
426
427 if ((le16_to_cpu(path->usDeviceTag) ==
428 ATOM_DEVICE_TV1_SUPPORT)
429 || (le16_to_cpu(path->usDeviceTag) ==
430 ATOM_DEVICE_TV2_SUPPORT)
431 || (le16_to_cpu(path->usDeviceTag) ==
432 ATOM_DEVICE_CV_SUPPORT))
433 ddc_bus.valid = false;
434 else
435 ddc_bus = radeon_lookup_gpio(dev, line_mux);
436
437 conn_id = le16_to_cpu(path->usConnObjectId);
438
439 if (!radeon_atom_apply_quirks
440 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
441 &ddc_bus, &conn_id))
442 continue;
443
444 radeon_add_atom_connector(dev,
445 conn_id,
446 le16_to_cpu(path->
447 usDeviceTag),
448 connector_type, &ddc_bus,
449 linkb, igp_lane_info,
450 connector_object_id);
451
452 }
453 }
454
455 radeon_link_encoder_connector(dev);
456
457 return true;
458 }
459
460 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
461 int connector_type,
462 uint16_t devices)
463 {
464 struct radeon_device *rdev = dev->dev_private;
465
466 if (rdev->flags & RADEON_IS_IGP) {
467 return supported_devices_connector_object_id_convert
468 [connector_type];
469 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
470 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
471 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
472 struct radeon_mode_info *mode_info = &rdev->mode_info;
473 struct atom_context *ctx = mode_info->atom_context;
474 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
475 uint16_t size, data_offset;
476 uint8_t frev, crev;
477 ATOM_XTMDS_INFO *xtmds;
478
479 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
480 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
481
482 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
483 if (connector_type == DRM_MODE_CONNECTOR_DVII)
484 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
485 else
486 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
487 } else {
488 if (connector_type == DRM_MODE_CONNECTOR_DVII)
489 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
490 else
491 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
492 }
493 } else {
494 return supported_devices_connector_object_id_convert
495 [connector_type];
496 }
497 }
498
499 struct bios_connector {
500 bool valid;
501 uint16_t line_mux;
502 uint16_t devices;
503 int connector_type;
504 struct radeon_i2c_bus_rec ddc_bus;
505 };
506
507 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
508 drm_device
509 *dev)
510 {
511 struct radeon_device *rdev = dev->dev_private;
512 struct radeon_mode_info *mode_info = &rdev->mode_info;
513 struct atom_context *ctx = mode_info->atom_context;
514 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
515 uint16_t size, data_offset;
516 uint8_t frev, crev;
517 uint16_t device_support;
518 uint8_t dac;
519 union atom_supported_devices *supported_devices;
520 int i, j;
521 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
522
523 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
524
525 supported_devices =
526 (union atom_supported_devices *)(ctx->bios + data_offset);
527
528 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
529
530 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
531 ATOM_CONNECTOR_INFO_I2C ci =
532 supported_devices->info.asConnInfo[i];
533
534 bios_connectors[i].valid = false;
535
536 if (!(device_support & (1 << i))) {
537 continue;
538 }
539
540 if (i == ATOM_DEVICE_CV_INDEX) {
541 DRM_DEBUG("Skipping Component Video\n");
542 continue;
543 }
544
545 bios_connectors[i].connector_type =
546 supported_devices_connector_convert[ci.sucConnectorInfo.
547 sbfAccess.
548 bfConnectorType];
549
550 if (bios_connectors[i].connector_type ==
551 DRM_MODE_CONNECTOR_Unknown)
552 continue;
553
554 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
555
556 if ((rdev->family == CHIP_RS690) ||
557 (rdev->family == CHIP_RS740)) {
558 if ((i == ATOM_DEVICE_DFP2_INDEX)
559 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
560 bios_connectors[i].line_mux =
561 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
562 else if ((i == ATOM_DEVICE_DFP3_INDEX)
563 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
564 bios_connectors[i].line_mux =
565 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
566 else
567 bios_connectors[i].line_mux =
568 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
569 } else
570 bios_connectors[i].line_mux =
571 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
572
573 /* give tv unique connector ids */
574 if (i == ATOM_DEVICE_TV1_INDEX) {
575 bios_connectors[i].ddc_bus.valid = false;
576 bios_connectors[i].line_mux = 50;
577 } else if (i == ATOM_DEVICE_TV2_INDEX) {
578 bios_connectors[i].ddc_bus.valid = false;
579 bios_connectors[i].line_mux = 51;
580 } else if (i == ATOM_DEVICE_CV_INDEX) {
581 bios_connectors[i].ddc_bus.valid = false;
582 bios_connectors[i].line_mux = 52;
583 } else
584 bios_connectors[i].ddc_bus =
585 radeon_lookup_gpio(dev,
586 bios_connectors[i].line_mux);
587
588 /* Always set the connector type to VGA for CRT1/CRT2. if they are
589 * shared with a DVI port, we'll pick up the DVI connector when we
590 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
591 */
592 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
593 bios_connectors[i].connector_type =
594 DRM_MODE_CONNECTOR_VGA;
595
596 if (!radeon_atom_apply_quirks
597 (dev, (1 << i), &bios_connectors[i].connector_type,
598 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux))
599 continue;
600
601 bios_connectors[i].valid = true;
602 bios_connectors[i].devices = (1 << i);
603
604 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
605 radeon_add_atom_encoder(dev,
606 radeon_get_encoder_id(dev,
607 (1 << i),
608 dac),
609 (1 << i));
610 else
611 radeon_add_legacy_encoder(dev,
612 radeon_get_encoder_id(dev,
613 (1 <<
614 i),
615 dac),
616 (1 << i));
617 }
618
619 /* combine shared connectors */
620 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
621 if (bios_connectors[i].valid) {
622 for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
623 if (bios_connectors[j].valid && (i != j)) {
624 if (bios_connectors[i].line_mux ==
625 bios_connectors[j].line_mux) {
626 if (((bios_connectors[i].
627 devices &
628 (ATOM_DEVICE_DFP_SUPPORT))
629 && (bios_connectors[j].
630 devices &
631 (ATOM_DEVICE_CRT_SUPPORT)))
632 ||
633 ((bios_connectors[j].
634 devices &
635 (ATOM_DEVICE_DFP_SUPPORT))
636 && (bios_connectors[i].
637 devices &
638 (ATOM_DEVICE_CRT_SUPPORT)))) {
639 bios_connectors[i].
640 devices |=
641 bios_connectors[j].
642 devices;
643 bios_connectors[i].
644 connector_type =
645 DRM_MODE_CONNECTOR_DVII;
646 bios_connectors[j].
647 valid = false;
648 }
649 }
650 }
651 }
652 }
653 }
654
655 /* add the connectors */
656 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
657 if (bios_connectors[i].valid) {
658 uint16_t connector_object_id =
659 atombios_get_connector_object_id(dev,
660 bios_connectors[i].connector_type,
661 bios_connectors[i].devices);
662 radeon_add_atom_connector(dev,
663 bios_connectors[i].line_mux,
664 bios_connectors[i].devices,
665 bios_connectors[i].
666 connector_type,
667 &bios_connectors[i].ddc_bus,
668 false, 0,
669 connector_object_id);
670 }
671 }
672
673 radeon_link_encoder_connector(dev);
674
675 return true;
676 }
677
678 union firmware_info {
679 ATOM_FIRMWARE_INFO info;
680 ATOM_FIRMWARE_INFO_V1_2 info_12;
681 ATOM_FIRMWARE_INFO_V1_3 info_13;
682 ATOM_FIRMWARE_INFO_V1_4 info_14;
683 };
684
685 bool radeon_atom_get_clock_info(struct drm_device *dev)
686 {
687 struct radeon_device *rdev = dev->dev_private;
688 struct radeon_mode_info *mode_info = &rdev->mode_info;
689 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
690 union firmware_info *firmware_info;
691 uint8_t frev, crev;
692 struct radeon_pll *p1pll = &rdev->clock.p1pll;
693 struct radeon_pll *p2pll = &rdev->clock.p2pll;
694 struct radeon_pll *spll = &rdev->clock.spll;
695 struct radeon_pll *mpll = &rdev->clock.mpll;
696 uint16_t data_offset;
697
698 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
699 &crev, &data_offset);
700
701 firmware_info =
702 (union firmware_info *)(mode_info->atom_context->bios +
703 data_offset);
704
705 if (firmware_info) {
706 /* pixel clocks */
707 p1pll->reference_freq =
708 le16_to_cpu(firmware_info->info.usReferenceClock);
709 p1pll->reference_div = 0;
710
711 if (crev < 2)
712 p1pll->pll_out_min =
713 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
714 else
715 p1pll->pll_out_min =
716 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
717 p1pll->pll_out_max =
718 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
719
720 if (p1pll->pll_out_min == 0) {
721 if (ASIC_IS_AVIVO(rdev))
722 p1pll->pll_out_min = 64800;
723 else
724 p1pll->pll_out_min = 20000;
725 } else if (p1pll->pll_out_min > 64800) {
726 /* Limiting the pll output range is a good thing generally as
727 * it limits the number of possible pll combinations for a given
728 * frequency presumably to the ones that work best on each card.
729 * However, certain duallink DVI monitors seem to like
730 * pll combinations that would be limited by this at least on
731 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
732 * family.
733 */
734 p1pll->pll_out_min = 64800;
735 }
736
737 p1pll->pll_in_min =
738 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
739 p1pll->pll_in_max =
740 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
741
742 *p2pll = *p1pll;
743
744 /* system clock */
745 spll->reference_freq =
746 le16_to_cpu(firmware_info->info.usReferenceClock);
747 spll->reference_div = 0;
748
749 spll->pll_out_min =
750 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
751 spll->pll_out_max =
752 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
753
754 /* ??? */
755 if (spll->pll_out_min == 0) {
756 if (ASIC_IS_AVIVO(rdev))
757 spll->pll_out_min = 64800;
758 else
759 spll->pll_out_min = 20000;
760 }
761
762 spll->pll_in_min =
763 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
764 spll->pll_in_max =
765 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
766
767 /* memory clock */
768 mpll->reference_freq =
769 le16_to_cpu(firmware_info->info.usReferenceClock);
770 mpll->reference_div = 0;
771
772 mpll->pll_out_min =
773 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
774 mpll->pll_out_max =
775 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
776
777 /* ??? */
778 if (mpll->pll_out_min == 0) {
779 if (ASIC_IS_AVIVO(rdev))
780 mpll->pll_out_min = 64800;
781 else
782 mpll->pll_out_min = 20000;
783 }
784
785 mpll->pll_in_min =
786 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
787 mpll->pll_in_max =
788 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
789
790 rdev->clock.default_sclk =
791 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
792 rdev->clock.default_mclk =
793 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
794
795 return true;
796 }
797 return false;
798 }
799
800 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
801 struct radeon_encoder_int_tmds *tmds)
802 {
803 struct drm_device *dev = encoder->base.dev;
804 struct radeon_device *rdev = dev->dev_private;
805 struct radeon_mode_info *mode_info = &rdev->mode_info;
806 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
807 uint16_t data_offset;
808 struct _ATOM_TMDS_INFO *tmds_info;
809 uint8_t frev, crev;
810 uint16_t maxfreq;
811 int i;
812
813 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
814 &crev, &data_offset);
815
816 tmds_info =
817 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
818 data_offset);
819
820 if (tmds_info) {
821 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
822 for (i = 0; i < 4; i++) {
823 tmds->tmds_pll[i].freq =
824 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
825 tmds->tmds_pll[i].value =
826 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
827 tmds->tmds_pll[i].value |=
828 (tmds_info->asMiscInfo[i].
829 ucPLL_VCO_Gain & 0x3f) << 6;
830 tmds->tmds_pll[i].value |=
831 (tmds_info->asMiscInfo[i].
832 ucPLL_DutyCycle & 0xf) << 12;
833 tmds->tmds_pll[i].value |=
834 (tmds_info->asMiscInfo[i].
835 ucPLL_VoltageSwing & 0xf) << 16;
836
837 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
838 tmds->tmds_pll[i].freq,
839 tmds->tmds_pll[i].value);
840
841 if (maxfreq == tmds->tmds_pll[i].freq) {
842 tmds->tmds_pll[i].freq = 0xffffffff;
843 break;
844 }
845 }
846 return true;
847 }
848 return false;
849 }
850
851 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
852 radeon_encoder
853 *encoder,
854 int id)
855 {
856 struct drm_device *dev = encoder->base.dev;
857 struct radeon_device *rdev = dev->dev_private;
858 struct radeon_mode_info *mode_info = &rdev->mode_info;
859 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
860 uint16_t data_offset;
861 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
862 uint8_t frev, crev;
863 struct radeon_atom_ss *ss = NULL;
864
865 if (id > ATOM_MAX_SS_ENTRY)
866 return NULL;
867
868 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
869 &crev, &data_offset);
870
871 ss_info =
872 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
873
874 if (ss_info) {
875 ss =
876 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
877
878 if (!ss)
879 return NULL;
880
881 ss->percentage = le16_to_cpu(ss_info->asSS_Info[id].usSpreadSpectrumPercentage);
882 ss->type = ss_info->asSS_Info[id].ucSpreadSpectrumType;
883 ss->step = ss_info->asSS_Info[id].ucSS_Step;
884 ss->delay = ss_info->asSS_Info[id].ucSS_Delay;
885 ss->range = ss_info->asSS_Info[id].ucSS_Range;
886 ss->refdiv = ss_info->asSS_Info[id].ucRecommendedRef_Div;
887 }
888 return ss;
889 }
890
891 union lvds_info {
892 struct _ATOM_LVDS_INFO info;
893 struct _ATOM_LVDS_INFO_V12 info_12;
894 };
895
896 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
897 radeon_encoder
898 *encoder)
899 {
900 struct drm_device *dev = encoder->base.dev;
901 struct radeon_device *rdev = dev->dev_private;
902 struct radeon_mode_info *mode_info = &rdev->mode_info;
903 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
904 uint16_t data_offset;
905 union lvds_info *lvds_info;
906 uint8_t frev, crev;
907 struct radeon_encoder_atom_dig *lvds = NULL;
908
909 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
910 &crev, &data_offset);
911
912 lvds_info =
913 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
914
915 if (lvds_info) {
916 lvds =
917 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
918
919 if (!lvds)
920 return NULL;
921
922 lvds->native_mode.clock =
923 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
924 lvds->native_mode.hdisplay =
925 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
926 lvds->native_mode.vdisplay =
927 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
928 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
929 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
930 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
931 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
932 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
933 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
934 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
935 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
936 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
937 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
938 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
939 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
940 lvds->panel_pwr_delay =
941 le16_to_cpu(lvds_info->info.usOffDelayInMs);
942 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
943 /* set crtc values */
944 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
945
946 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
947
948 encoder->native_mode = lvds->native_mode;
949 }
950 return lvds;
951 }
952
953 struct radeon_encoder_primary_dac *
954 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
955 {
956 struct drm_device *dev = encoder->base.dev;
957 struct radeon_device *rdev = dev->dev_private;
958 struct radeon_mode_info *mode_info = &rdev->mode_info;
959 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
960 uint16_t data_offset;
961 struct _COMPASSIONATE_DATA *dac_info;
962 uint8_t frev, crev;
963 uint8_t bg, dac;
964 struct radeon_encoder_primary_dac *p_dac = NULL;
965
966 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
967
968 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
969
970 if (dac_info) {
971 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
972
973 if (!p_dac)
974 return NULL;
975
976 bg = dac_info->ucDAC1_BG_Adjustment;
977 dac = dac_info->ucDAC1_DAC_Adjustment;
978 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
979
980 }
981 return p_dac;
982 }
983
984 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
985 struct drm_display_mode *mode)
986 {
987 struct radeon_mode_info *mode_info = &rdev->mode_info;
988 ATOM_ANALOG_TV_INFO *tv_info;
989 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
990 ATOM_DTD_FORMAT *dtd_timings;
991 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
992 u8 frev, crev;
993 u16 data_offset, misc;
994
995 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
996
997 switch (crev) {
998 case 1:
999 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1000 if (index > MAX_SUPPORTED_TV_TIMING)
1001 return false;
1002
1003 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1004 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1005 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1006 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1007 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1008
1009 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1010 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1011 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1012 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1013 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1014
1015 mode->flags = 0;
1016 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1017 if (misc & ATOM_VSYNC_POLARITY)
1018 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1019 if (misc & ATOM_HSYNC_POLARITY)
1020 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1021 if (misc & ATOM_COMPOSITESYNC)
1022 mode->flags |= DRM_MODE_FLAG_CSYNC;
1023 if (misc & ATOM_INTERLACE)
1024 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1025 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1026 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1027
1028 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1029
1030 if (index == 1) {
1031 /* PAL timings appear to have wrong values for totals */
1032 mode->crtc_htotal -= 1;
1033 mode->crtc_vtotal -= 1;
1034 }
1035 break;
1036 case 2:
1037 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1038 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1039 return false;
1040
1041 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1042 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1043 le16_to_cpu(dtd_timings->usHBlanking_Time);
1044 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1045 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1046 le16_to_cpu(dtd_timings->usHSyncOffset);
1047 mode->crtc_hsync_end = mode->crtc_hsync_start +
1048 le16_to_cpu(dtd_timings->usHSyncWidth);
1049
1050 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1051 le16_to_cpu(dtd_timings->usVBlanking_Time);
1052 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1053 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1054 le16_to_cpu(dtd_timings->usVSyncOffset);
1055 mode->crtc_vsync_end = mode->crtc_vsync_start +
1056 le16_to_cpu(dtd_timings->usVSyncWidth);
1057
1058 mode->flags = 0;
1059 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1060 if (misc & ATOM_VSYNC_POLARITY)
1061 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1062 if (misc & ATOM_HSYNC_POLARITY)
1063 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1064 if (misc & ATOM_COMPOSITESYNC)
1065 mode->flags |= DRM_MODE_FLAG_CSYNC;
1066 if (misc & ATOM_INTERLACE)
1067 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1068 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1069 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1070
1071 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1072 break;
1073 }
1074 return true;
1075 }
1076
1077 struct radeon_encoder_tv_dac *
1078 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1079 {
1080 struct drm_device *dev = encoder->base.dev;
1081 struct radeon_device *rdev = dev->dev_private;
1082 struct radeon_mode_info *mode_info = &rdev->mode_info;
1083 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1084 uint16_t data_offset;
1085 struct _COMPASSIONATE_DATA *dac_info;
1086 uint8_t frev, crev;
1087 uint8_t bg, dac;
1088 struct radeon_encoder_tv_dac *tv_dac = NULL;
1089
1090 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1091
1092 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1093
1094 if (dac_info) {
1095 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1096
1097 if (!tv_dac)
1098 return NULL;
1099
1100 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1101 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1102 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1103
1104 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1105 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1106 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1107
1108 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1109 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1110 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1111
1112 }
1113 return tv_dac;
1114 }
1115
1116 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1117 {
1118 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1119 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1120
1121 args.ucEnable = enable;
1122
1123 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1124 }
1125
1126 void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
1127 {
1128 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
1129 int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
1130
1131 args.ucEnable = enable;
1132
1133 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1134 }
1135
1136 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1137 {
1138 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1139 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1140
1141 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1142 return args.ulReturnEngineClock;
1143 }
1144
1145 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1146 {
1147 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1148 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1149
1150 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1151 return args.ulReturnMemoryClock;
1152 }
1153
1154 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1155 uint32_t eng_clock)
1156 {
1157 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1158 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1159
1160 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1161
1162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1163 }
1164
1165 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1166 uint32_t mem_clock)
1167 {
1168 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1169 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1170
1171 if (rdev->flags & RADEON_IS_IGP)
1172 return;
1173
1174 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1175
1176 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1177 }
1178
1179 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1180 {
1181 struct radeon_device *rdev = dev->dev_private;
1182 uint32_t bios_2_scratch, bios_6_scratch;
1183
1184 if (rdev->family >= CHIP_R600) {
1185 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1186 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1187 } else {
1188 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1189 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1190 }
1191
1192 /* let the bios control the backlight */
1193 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1194
1195 /* tell the bios not to handle mode switching */
1196 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1197
1198 if (rdev->family >= CHIP_R600) {
1199 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1200 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1201 } else {
1202 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1203 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1204 }
1205
1206 }
1207
1208 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1209 {
1210 uint32_t scratch_reg;
1211 int i;
1212
1213 if (rdev->family >= CHIP_R600)
1214 scratch_reg = R600_BIOS_0_SCRATCH;
1215 else
1216 scratch_reg = RADEON_BIOS_0_SCRATCH;
1217
1218 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1219 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1220 }
1221
1222 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1223 {
1224 uint32_t scratch_reg;
1225 int i;
1226
1227 if (rdev->family >= CHIP_R600)
1228 scratch_reg = R600_BIOS_0_SCRATCH;
1229 else
1230 scratch_reg = RADEON_BIOS_0_SCRATCH;
1231
1232 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1233 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1234 }
1235
1236 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1237 {
1238 struct drm_device *dev = encoder->dev;
1239 struct radeon_device *rdev = dev->dev_private;
1240 uint32_t bios_6_scratch;
1241
1242 if (rdev->family >= CHIP_R600)
1243 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1244 else
1245 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1246
1247 if (lock)
1248 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1249 else
1250 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1251
1252 if (rdev->family >= CHIP_R600)
1253 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1254 else
1255 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1256 }
1257
1258 /* at some point we may want to break this out into individual functions */
1259 void
1260 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1261 struct drm_encoder *encoder,
1262 bool connected)
1263 {
1264 struct drm_device *dev = connector->dev;
1265 struct radeon_device *rdev = dev->dev_private;
1266 struct radeon_connector *radeon_connector =
1267 to_radeon_connector(connector);
1268 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1269 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1270
1271 if (rdev->family >= CHIP_R600) {
1272 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1273 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1274 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1275 } else {
1276 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1277 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1278 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1279 }
1280
1281 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1282 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1283 if (connected) {
1284 DRM_DEBUG("TV1 connected\n");
1285 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1286 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1287 } else {
1288 DRM_DEBUG("TV1 disconnected\n");
1289 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1290 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1291 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1292 }
1293 }
1294 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1295 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1296 if (connected) {
1297 DRM_DEBUG("CV connected\n");
1298 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1299 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1300 } else {
1301 DRM_DEBUG("CV disconnected\n");
1302 bios_0_scratch &= ~ATOM_S0_CV_MASK;
1303 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1304 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1305 }
1306 }
1307 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1308 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1309 if (connected) {
1310 DRM_DEBUG("LCD1 connected\n");
1311 bios_0_scratch |= ATOM_S0_LCD1;
1312 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1313 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1314 } else {
1315 DRM_DEBUG("LCD1 disconnected\n");
1316 bios_0_scratch &= ~ATOM_S0_LCD1;
1317 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1318 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1319 }
1320 }
1321 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1322 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1323 if (connected) {
1324 DRM_DEBUG("CRT1 connected\n");
1325 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1326 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1327 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1328 } else {
1329 DRM_DEBUG("CRT1 disconnected\n");
1330 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1331 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1332 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1333 }
1334 }
1335 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1336 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1337 if (connected) {
1338 DRM_DEBUG("CRT2 connected\n");
1339 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1340 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1341 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1342 } else {
1343 DRM_DEBUG("CRT2 disconnected\n");
1344 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1345 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1346 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1347 }
1348 }
1349 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1350 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1351 if (connected) {
1352 DRM_DEBUG("DFP1 connected\n");
1353 bios_0_scratch |= ATOM_S0_DFP1;
1354 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1355 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1356 } else {
1357 DRM_DEBUG("DFP1 disconnected\n");
1358 bios_0_scratch &= ~ATOM_S0_DFP1;
1359 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1360 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1361 }
1362 }
1363 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1364 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1365 if (connected) {
1366 DRM_DEBUG("DFP2 connected\n");
1367 bios_0_scratch |= ATOM_S0_DFP2;
1368 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1369 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1370 } else {
1371 DRM_DEBUG("DFP2 disconnected\n");
1372 bios_0_scratch &= ~ATOM_S0_DFP2;
1373 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1374 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1375 }
1376 }
1377 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1378 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1379 if (connected) {
1380 DRM_DEBUG("DFP3 connected\n");
1381 bios_0_scratch |= ATOM_S0_DFP3;
1382 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1383 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1384 } else {
1385 DRM_DEBUG("DFP3 disconnected\n");
1386 bios_0_scratch &= ~ATOM_S0_DFP3;
1387 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1388 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1389 }
1390 }
1391 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1392 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1393 if (connected) {
1394 DRM_DEBUG("DFP4 connected\n");
1395 bios_0_scratch |= ATOM_S0_DFP4;
1396 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1397 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1398 } else {
1399 DRM_DEBUG("DFP4 disconnected\n");
1400 bios_0_scratch &= ~ATOM_S0_DFP4;
1401 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1402 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1403 }
1404 }
1405 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1406 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1407 if (connected) {
1408 DRM_DEBUG("DFP5 connected\n");
1409 bios_0_scratch |= ATOM_S0_DFP5;
1410 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1411 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1412 } else {
1413 DRM_DEBUG("DFP5 disconnected\n");
1414 bios_0_scratch &= ~ATOM_S0_DFP5;
1415 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1416 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1417 }
1418 }
1419
1420 if (rdev->family >= CHIP_R600) {
1421 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1422 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1423 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1424 } else {
1425 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1426 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1427 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1428 }
1429 }
1430
1431 void
1432 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1433 {
1434 struct drm_device *dev = encoder->dev;
1435 struct radeon_device *rdev = dev->dev_private;
1436 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1437 uint32_t bios_3_scratch;
1438
1439 if (rdev->family >= CHIP_R600)
1440 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1441 else
1442 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1443
1444 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1445 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1446 bios_3_scratch |= (crtc << 18);
1447 }
1448 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1449 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1450 bios_3_scratch |= (crtc << 24);
1451 }
1452 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1453 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1454 bios_3_scratch |= (crtc << 16);
1455 }
1456 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1457 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1458 bios_3_scratch |= (crtc << 20);
1459 }
1460 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1461 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1462 bios_3_scratch |= (crtc << 17);
1463 }
1464 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1465 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1466 bios_3_scratch |= (crtc << 19);
1467 }
1468 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1469 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1470 bios_3_scratch |= (crtc << 23);
1471 }
1472 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1473 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1474 bios_3_scratch |= (crtc << 25);
1475 }
1476
1477 if (rdev->family >= CHIP_R600)
1478 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1479 else
1480 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1481 }
1482
1483 void
1484 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1485 {
1486 struct drm_device *dev = encoder->dev;
1487 struct radeon_device *rdev = dev->dev_private;
1488 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1489 uint32_t bios_2_scratch;
1490
1491 if (rdev->family >= CHIP_R600)
1492 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1493 else
1494 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1495
1496 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1497 if (on)
1498 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1499 else
1500 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1501 }
1502 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1503 if (on)
1504 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1505 else
1506 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1507 }
1508 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1509 if (on)
1510 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1511 else
1512 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1513 }
1514 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1515 if (on)
1516 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1517 else
1518 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1519 }
1520 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1521 if (on)
1522 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1523 else
1524 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1525 }
1526 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1527 if (on)
1528 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1529 else
1530 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1531 }
1532 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1533 if (on)
1534 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1535 else
1536 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1537 }
1538 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1539 if (on)
1540 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1541 else
1542 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1543 }
1544 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1545 if (on)
1546 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1547 else
1548 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1549 }
1550 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1551 if (on)
1552 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1553 else
1554 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1555 }
1556
1557 if (rdev->family >= CHIP_R600)
1558 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1559 else
1560 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1561 }
Linux with added FPC-III support