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x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / rv515.c
blob7935f793bf629b8599644d242ddfbfcaf3a04cb6
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "rv515d.h"
31 #include "radeon.h"
32 #include "atom.h"
33 #include "rv515_reg_safe.h"
34
35 /* This files gather functions specifics to: rv515 */
36 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
37 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
38 void rv515_gpu_init(struct radeon_device *rdev);
39 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
40
41 void rv515_debugfs(struct radeon_device *rdev)
42 {
43 if (r100_debugfs_rbbm_init(rdev)) {
44 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
45 }
46 if (rv515_debugfs_pipes_info_init(rdev)) {
47 DRM_ERROR("Failed to register debugfs file for pipes !\n");
48 }
49 if (rv515_debugfs_ga_info_init(rdev)) {
50 DRM_ERROR("Failed to register debugfs file for pipes !\n");
51 }
52 }
53
54 void rv515_ring_start(struct radeon_device *rdev)
55 {
56 int r;
57
58 r = radeon_ring_lock(rdev, 64);
59 if (r) {
60 return;
61 }
62 radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
63 radeon_ring_write(rdev,
64 ISYNC_ANY2D_IDLE3D |
65 ISYNC_ANY3D_IDLE2D |
66 ISYNC_WAIT_IDLEGUI |
67 ISYNC_CPSCRATCH_IDLEGUI);
68 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
69 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
70 radeon_ring_write(rdev, PACKET0(0x170C, 0));
71 radeon_ring_write(rdev, 1 << 31);
72 radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
73 radeon_ring_write(rdev, 0);
74 radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
75 radeon_ring_write(rdev, 0);
76 radeon_ring_write(rdev, PACKET0(0x42C8, 0));
77 radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
78 radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
79 radeon_ring_write(rdev, 0);
80 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
81 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
82 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
83 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
84 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
85 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
86 radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
87 radeon_ring_write(rdev, 0);
88 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
89 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
90 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
91 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
92 radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
93 radeon_ring_write(rdev,
94 ((6 << MS_X0_SHIFT) |
95 (6 << MS_Y0_SHIFT) |
96 (6 << MS_X1_SHIFT) |
97 (6 << MS_Y1_SHIFT) |
98 (6 << MS_X2_SHIFT) |
99 (6 << MS_Y2_SHIFT) |
100 (6 << MSBD0_Y_SHIFT) |
101 (6 << MSBD0_X_SHIFT)));
102 radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
103 radeon_ring_write(rdev,
104 ((6 << MS_X3_SHIFT) |
105 (6 << MS_Y3_SHIFT) |
106 (6 << MS_X4_SHIFT) |
107 (6 << MS_Y4_SHIFT) |
108 (6 << MS_X5_SHIFT) |
109 (6 << MS_Y5_SHIFT) |
110 (6 << MSBD1_SHIFT)));
111 radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
112 radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
113 radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
114 radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
115 radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
116 radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
117 radeon_ring_write(rdev, PACKET0(0x20C8, 0));
118 radeon_ring_write(rdev, 0);
119 radeon_ring_unlock_commit(rdev);
120 }
121
122 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
123 {
124 unsigned i;
125 uint32_t tmp;
126
127 for (i = 0; i < rdev->usec_timeout; i++) {
128 /* read MC_STATUS */
129 tmp = RREG32_MC(MC_STATUS);
130 if (tmp & MC_STATUS_IDLE) {
131 return 0;
132 }
133 DRM_UDELAY(1);
134 }
135 return -1;
136 }
137
138 void rv515_vga_render_disable(struct radeon_device *rdev)
139 {
140 WREG32(R_000330_D1VGA_CONTROL, 0);
141 WREG32(R_000338_D2VGA_CONTROL, 0);
142 WREG32(R_000300_VGA_RENDER_CONTROL,
143 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
144 }
145
146 void rv515_gpu_init(struct radeon_device *rdev)
147 {
148 unsigned pipe_select_current, gb_pipe_select, tmp;
149
150 r100_hdp_reset(rdev);
151 r100_rb2d_reset(rdev);
152
153 if (r100_gui_wait_for_idle(rdev)) {
154 printk(KERN_WARNING "Failed to wait GUI idle while "
155 "reseting GPU. Bad things might happen.\n");
156 }
157
158 rv515_vga_render_disable(rdev);
159
160 r420_pipes_init(rdev);
161 gb_pipe_select = RREG32(0x402C);
162 tmp = RREG32(0x170C);
163 pipe_select_current = (tmp >> 2) & 3;
164 tmp = (1 << pipe_select_current) |
165 (((gb_pipe_select >> 8) & 0xF) << 4);
166 WREG32_PLL(0x000D, tmp);
167 if (r100_gui_wait_for_idle(rdev)) {
168 printk(KERN_WARNING "Failed to wait GUI idle while "
169 "reseting GPU. Bad things might happen.\n");
170 }
171 if (rv515_mc_wait_for_idle(rdev)) {
172 printk(KERN_WARNING "Failed to wait MC idle while "
173 "programming pipes. Bad things might happen.\n");
174 }
175 }
176
177 int rv515_ga_reset(struct radeon_device *rdev)
178 {
179 uint32_t tmp;
180 bool reinit_cp;
181 int i;
182
183 reinit_cp = rdev->cp.ready;
184 rdev->cp.ready = false;
185 for (i = 0; i < rdev->usec_timeout; i++) {
186 WREG32(CP_CSQ_MODE, 0);
187 WREG32(CP_CSQ_CNTL, 0);
188 WREG32(RBBM_SOFT_RESET, 0x32005);
189 (void)RREG32(RBBM_SOFT_RESET);
190 udelay(200);
191 WREG32(RBBM_SOFT_RESET, 0);
192 /* Wait to prevent race in RBBM_STATUS */
193 mdelay(1);
194 tmp = RREG32(RBBM_STATUS);
195 if (tmp & ((1 << 20) | (1 << 26))) {
196 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
197 /* GA still busy soft reset it */
198 WREG32(0x429C, 0x200);
199 WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
200 WREG32(0x43E0, 0);
201 WREG32(0x43E4, 0);
202 WREG32(0x24AC, 0);
203 }
204 /* Wait to prevent race in RBBM_STATUS */
205 mdelay(1);
206 tmp = RREG32(RBBM_STATUS);
207 if (!(tmp & ((1 << 20) | (1 << 26)))) {
208 break;
209 }
210 }
211 for (i = 0; i < rdev->usec_timeout; i++) {
212 tmp = RREG32(RBBM_STATUS);
213 if (!(tmp & ((1 << 20) | (1 << 26)))) {
214 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
215 tmp);
216 DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
217 DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
218 DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
219 if (reinit_cp) {
220 return r100_cp_init(rdev, rdev->cp.ring_size);
221 }
222 return 0;
223 }
224 DRM_UDELAY(1);
225 }
226 tmp = RREG32(RBBM_STATUS);
227 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
228 return -1;
229 }
230
231 int rv515_gpu_reset(struct radeon_device *rdev)
232 {
233 uint32_t status;
234
235 /* reset order likely matter */
236 status = RREG32(RBBM_STATUS);
237 /* reset HDP */
238 r100_hdp_reset(rdev);
239 /* reset rb2d */
240 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
241 r100_rb2d_reset(rdev);
242 }
243 /* reset GA */
244 if (status & ((1 << 20) | (1 << 26))) {
245 rv515_ga_reset(rdev);
246 }
247 /* reset CP */
248 status = RREG32(RBBM_STATUS);
249 if (status & (1 << 16)) {
250 r100_cp_reset(rdev);
251 }
252 /* Check if GPU is idle */
253 status = RREG32(RBBM_STATUS);
254 if (status & (1 << 31)) {
255 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
256 return -1;
257 }
258 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
259 return 0;
260 }
261
262 static void rv515_vram_get_type(struct radeon_device *rdev)
263 {
264 uint32_t tmp;
265
266 rdev->mc.vram_width = 128;
267 rdev->mc.vram_is_ddr = true;
268 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
269 switch (tmp) {
270 case 0:
271 rdev->mc.vram_width = 64;
272 break;
273 case 1:
274 rdev->mc.vram_width = 128;
275 break;
276 default:
277 rdev->mc.vram_width = 128;
278 break;
279 }
280 }
281
282 void rv515_vram_info(struct radeon_device *rdev)
283 {
284 fixed20_12 a;
285
286 rv515_vram_get_type(rdev);
287
288 r100_vram_init_sizes(rdev);
289 /* FIXME: we should enforce default clock in case GPU is not in
290 * default setup
291 */
292 a.full = rfixed_const(100);
293 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
294 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
295 }
296
297 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
298 {
299 uint32_t r;
300
301 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
302 r = RREG32(MC_IND_DATA);
303 WREG32(MC_IND_INDEX, 0);
304 return r;
305 }
306
307 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
308 {
309 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
310 WREG32(MC_IND_DATA, (v));
311 WREG32(MC_IND_INDEX, 0);
312 }
313
314 #if defined(CONFIG_DEBUG_FS)
315 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
316 {
317 struct drm_info_node *node = (struct drm_info_node *) m->private;
318 struct drm_device *dev = node->minor->dev;
319 struct radeon_device *rdev = dev->dev_private;
320 uint32_t tmp;
321
322 tmp = RREG32(GB_PIPE_SELECT);
323 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
324 tmp = RREG32(SU_REG_DEST);
325 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
326 tmp = RREG32(GB_TILE_CONFIG);
327 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
328 tmp = RREG32(DST_PIPE_CONFIG);
329 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
330 return 0;
331 }
332
333 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
334 {
335 struct drm_info_node *node = (struct drm_info_node *) m->private;
336 struct drm_device *dev = node->minor->dev;
337 struct radeon_device *rdev = dev->dev_private;
338 uint32_t tmp;
339
340 tmp = RREG32(0x2140);
341 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
342 radeon_gpu_reset(rdev);
343 tmp = RREG32(0x425C);
344 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
345 return 0;
346 }
347
348 static struct drm_info_list rv515_pipes_info_list[] = {
349 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
350 };
351
352 static struct drm_info_list rv515_ga_info_list[] = {
353 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
354 };
355 #endif
356
357 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
358 {
359 #if defined(CONFIG_DEBUG_FS)
360 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
361 #else
362 return 0;
363 #endif
364 }
365
366 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
367 {
368 #if defined(CONFIG_DEBUG_FS)
369 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
370 #else
371 return 0;
372 #endif
373 }
374
375 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
376 {
377 save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
378 save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
379 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
380 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
381 save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
382 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
383
384 /* Stop all video */
385 WREG32(R_000330_D1VGA_CONTROL, 0);
386 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
387 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
388 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
389 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
390 WREG32(R_006080_D1CRTC_CONTROL, 0);
391 WREG32(R_006880_D2CRTC_CONTROL, 0);
392 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
393 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
394 }
395
396 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
397 {
398 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
399 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
400 WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
401 WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
402 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
403 /* Unlock host access */
404 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
405 mdelay(1);
406 /* Restore video state */
407 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
408 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
409 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
410 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
411 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
412 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
413 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
414 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
415 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
416 }
417
418 void rv515_mc_program(struct radeon_device *rdev)
419 {
420 struct rv515_mc_save save;
421
422 /* Stops all mc clients */
423 rv515_mc_stop(rdev, &save);
424
425 /* Wait for mc idle */
426 if (rv515_mc_wait_for_idle(rdev))
427 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
428 /* Write VRAM size in case we are limiting it */
429 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
430 /* Program MC, should be a 32bits limited address space */
431 WREG32_MC(R_000001_MC_FB_LOCATION,
432 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
433 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
434 WREG32(R_000134_HDP_FB_LOCATION,
435 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
436 if (rdev->flags & RADEON_IS_AGP) {
437 WREG32_MC(R_000002_MC_AGP_LOCATION,
438 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
439 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
440 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
441 WREG32_MC(R_000004_MC_AGP_BASE_2,
442 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
443 } else {
444 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
445 WREG32_MC(R_000003_MC_AGP_BASE, 0);
446 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
447 }
448
449 rv515_mc_resume(rdev, &save);
450 }
451
452 void rv515_clock_startup(struct radeon_device *rdev)
453 {
454 if (radeon_dynclks != -1 && radeon_dynclks)
455 radeon_atom_set_clock_gating(rdev, 1);
456 /* We need to force on some of the block */
457 WREG32_PLL(R_00000F_CP_DYN_CNTL,
458 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
459 WREG32_PLL(R_000011_E2_DYN_CNTL,
460 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
461 WREG32_PLL(R_000013_IDCT_DYN_CNTL,
462 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
463 }
464
465 static int rv515_startup(struct radeon_device *rdev)
466 {
467 int r;
468
469 rv515_mc_program(rdev);
470 /* Resume clock */
471 rv515_clock_startup(rdev);
472 /* Initialize GPU configuration (# pipes, ...) */
473 rv515_gpu_init(rdev);
474 /* Initialize GART (initialize after TTM so we can allocate
475 * memory through TTM but finalize after TTM) */
476 if (rdev->flags & RADEON_IS_PCIE) {
477 r = rv370_pcie_gart_enable(rdev);
478 if (r)
479 return r;
480 }
481 /* Enable IRQ */
482 rdev->irq.sw_int = true;
483 rs600_irq_set(rdev);
484 /* 1M ring buffer */
485 r = r100_cp_init(rdev, 1024 * 1024);
486 if (r) {
487 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
488 return r;
489 }
490 r = r100_wb_init(rdev);
491 if (r)
492 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
493 r = r100_ib_init(rdev);
494 if (r) {
495 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
496 return r;
497 }
498 return 0;
499 }
500
501 int rv515_resume(struct radeon_device *rdev)
502 {
503 /* Make sur GART are not working */
504 if (rdev->flags & RADEON_IS_PCIE)
505 rv370_pcie_gart_disable(rdev);
506 /* Resume clock before doing reset */
507 rv515_clock_startup(rdev);
508 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
509 if (radeon_gpu_reset(rdev)) {
510 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
511 RREG32(R_000E40_RBBM_STATUS),
512 RREG32(R_0007C0_CP_STAT));
513 }
514 /* post */
515 atom_asic_init(rdev->mode_info.atom_context);
516 /* Resume clock after posting */
517 rv515_clock_startup(rdev);
518 return rv515_startup(rdev);
519 }
520
521 int rv515_suspend(struct radeon_device *rdev)
522 {
523 r100_cp_disable(rdev);
524 r100_wb_disable(rdev);
525 rs600_irq_disable(rdev);
526 if (rdev->flags & RADEON_IS_PCIE)
527 rv370_pcie_gart_disable(rdev);
528 return 0;
529 }
530
531 void rv515_set_safe_registers(struct radeon_device *rdev)
532 {
533 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
534 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
535 }
536
537 void rv515_fini(struct radeon_device *rdev)
538 {
539 rv515_suspend(rdev);
540 r100_cp_fini(rdev);
541 r100_wb_fini(rdev);
542 r100_ib_fini(rdev);
543 radeon_gem_fini(rdev);
544 rv370_pcie_gart_fini(rdev);
545 radeon_agp_fini(rdev);
546 radeon_irq_kms_fini(rdev);
547 radeon_fence_driver_fini(rdev);
548 radeon_object_fini(rdev);
549 radeon_atombios_fini(rdev);
550 kfree(rdev->bios);
551 rdev->bios = NULL;
552 }
553
554 int rv515_init(struct radeon_device *rdev)
555 {
556 int r;
557
558 /* Initialize scratch registers */
559 radeon_scratch_init(rdev);
560 /* Initialize surface registers */
561 radeon_surface_init(rdev);
562 /* TODO: disable VGA need to use VGA request */
563 /* BIOS*/
564 if (!radeon_get_bios(rdev)) {
565 if (ASIC_IS_AVIVO(rdev))
566 return -EINVAL;
567 }
568 if (rdev->is_atom_bios) {
569 r = radeon_atombios_init(rdev);
570 if (r)
571 return r;
572 } else {
573 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
574 return -EINVAL;
575 }
576 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
577 if (radeon_gpu_reset(rdev)) {
578 dev_warn(rdev->dev,
579 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
580 RREG32(R_000E40_RBBM_STATUS),
581 RREG32(R_0007C0_CP_STAT));
582 }
583 /* check if cards are posted or not */
584 if (!radeon_card_posted(rdev) && rdev->bios) {
585 DRM_INFO("GPU not posted. posting now...\n");
586 atom_asic_init(rdev->mode_info.atom_context);
587 }
588 /* Initialize clocks */
589 radeon_get_clock_info(rdev->ddev);
590 /* Initialize power management */
591 radeon_pm_init(rdev);
592 /* Get vram informations */
593 rv515_vram_info(rdev);
594 /* Initialize memory controller (also test AGP) */
595 r = r420_mc_init(rdev);
596 if (r)
597 return r;
598 rv515_debugfs(rdev);
599 /* Fence driver */
600 r = radeon_fence_driver_init(rdev);
601 if (r)
602 return r;
603 r = radeon_irq_kms_init(rdev);
604 if (r)
605 return r;
606 /* Memory manager */
607 r = radeon_object_init(rdev);
608 if (r)
609 return r;
610 r = rv370_pcie_gart_init(rdev);
611 if (r)
612 return r;
613 rv515_set_safe_registers(rdev);
614 rdev->accel_working = true;
615 r = rv515_startup(rdev);
616 if (r) {
617 /* Somethings want wront with the accel init stop accel */
618 dev_err(rdev->dev, "Disabling GPU acceleration\n");
619 rv515_suspend(rdev);
620 r100_cp_fini(rdev);
621 r100_wb_fini(rdev);
622 r100_ib_fini(rdev);
623 rv370_pcie_gart_fini(rdev);
624 radeon_agp_fini(rdev);
625 radeon_irq_kms_fini(rdev);
626 rdev->accel_working = false;
627 }
628 return 0;
629 }
630
631 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
632 {
633 int index_reg = 0x6578 + crtc->crtc_offset;
634 int data_reg = 0x657c + crtc->crtc_offset;
635
636 WREG32(0x659C + crtc->crtc_offset, 0x0);
637 WREG32(0x6594 + crtc->crtc_offset, 0x705);
638 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
639 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
640 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
641 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
642 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
643 WREG32(index_reg, 0x0);
644 WREG32(data_reg, 0x841880A8);
645 WREG32(index_reg, 0x1);
646 WREG32(data_reg, 0x84208680);
647 WREG32(index_reg, 0x2);
648 WREG32(data_reg, 0xBFF880B0);
649 WREG32(index_reg, 0x100);
650 WREG32(data_reg, 0x83D88088);
651 WREG32(index_reg, 0x101);
652 WREG32(data_reg, 0x84608680);
653 WREG32(index_reg, 0x102);
654 WREG32(data_reg, 0xBFF080D0);
655 WREG32(index_reg, 0x200);
656 WREG32(data_reg, 0x83988068);
657 WREG32(index_reg, 0x201);
658 WREG32(data_reg, 0x84A08680);
659 WREG32(index_reg, 0x202);
660 WREG32(data_reg, 0xBFF080F8);
661 WREG32(index_reg, 0x300);
662 WREG32(data_reg, 0x83588058);
663 WREG32(index_reg, 0x301);
664 WREG32(data_reg, 0x84E08660);
665 WREG32(index_reg, 0x302);
666 WREG32(data_reg, 0xBFF88120);
667 WREG32(index_reg, 0x400);
668 WREG32(data_reg, 0x83188040);
669 WREG32(index_reg, 0x401);
670 WREG32(data_reg, 0x85008660);
671 WREG32(index_reg, 0x402);
672 WREG32(data_reg, 0xBFF88150);
673 WREG32(index_reg, 0x500);
674 WREG32(data_reg, 0x82D88030);
675 WREG32(index_reg, 0x501);
676 WREG32(data_reg, 0x85408640);
677 WREG32(index_reg, 0x502);
678 WREG32(data_reg, 0xBFF88180);
679 WREG32(index_reg, 0x600);
680 WREG32(data_reg, 0x82A08018);
681 WREG32(index_reg, 0x601);
682 WREG32(data_reg, 0x85808620);
683 WREG32(index_reg, 0x602);
684 WREG32(data_reg, 0xBFF081B8);
685 WREG32(index_reg, 0x700);
686 WREG32(data_reg, 0x82608010);
687 WREG32(index_reg, 0x701);
688 WREG32(data_reg, 0x85A08600);
689 WREG32(index_reg, 0x702);
690 WREG32(data_reg, 0x800081F0);
691 WREG32(index_reg, 0x800);
692 WREG32(data_reg, 0x8228BFF8);
693 WREG32(index_reg, 0x801);
694 WREG32(data_reg, 0x85E085E0);
695 WREG32(index_reg, 0x802);
696 WREG32(data_reg, 0xBFF88228);
697 WREG32(index_reg, 0x10000);
698 WREG32(data_reg, 0x82A8BF00);
699 WREG32(index_reg, 0x10001);
700 WREG32(data_reg, 0x82A08CC0);
701 WREG32(index_reg, 0x10002);
702 WREG32(data_reg, 0x8008BEF8);
703 WREG32(index_reg, 0x10100);
704 WREG32(data_reg, 0x81F0BF28);
705 WREG32(index_reg, 0x10101);
706 WREG32(data_reg, 0x83608CA0);
707 WREG32(index_reg, 0x10102);
708 WREG32(data_reg, 0x8018BED0);
709 WREG32(index_reg, 0x10200);
710 WREG32(data_reg, 0x8148BF38);
711 WREG32(index_reg, 0x10201);
712 WREG32(data_reg, 0x84408C80);
713 WREG32(index_reg, 0x10202);
714 WREG32(data_reg, 0x8008BEB8);
715 WREG32(index_reg, 0x10300);
716 WREG32(data_reg, 0x80B0BF78);
717 WREG32(index_reg, 0x10301);
718 WREG32(data_reg, 0x85008C20);
719 WREG32(index_reg, 0x10302);
720 WREG32(data_reg, 0x8020BEA0);
721 WREG32(index_reg, 0x10400);
722 WREG32(data_reg, 0x8028BF90);
723 WREG32(index_reg, 0x10401);
724 WREG32(data_reg, 0x85E08BC0);
725 WREG32(index_reg, 0x10402);
726 WREG32(data_reg, 0x8018BE90);
727 WREG32(index_reg, 0x10500);
728 WREG32(data_reg, 0xBFB8BFB0);
729 WREG32(index_reg, 0x10501);
730 WREG32(data_reg, 0x86C08B40);
731 WREG32(index_reg, 0x10502);
732 WREG32(data_reg, 0x8010BE90);
733 WREG32(index_reg, 0x10600);
734 WREG32(data_reg, 0xBF58BFC8);
735 WREG32(index_reg, 0x10601);
736 WREG32(data_reg, 0x87A08AA0);
737 WREG32(index_reg, 0x10602);
738 WREG32(data_reg, 0x8010BE98);
739 WREG32(index_reg, 0x10700);
740 WREG32(data_reg, 0xBF10BFF0);
741 WREG32(index_reg, 0x10701);
742 WREG32(data_reg, 0x886089E0);
743 WREG32(index_reg, 0x10702);
744 WREG32(data_reg, 0x8018BEB0);
745 WREG32(index_reg, 0x10800);
746 WREG32(data_reg, 0xBED8BFE8);
747 WREG32(index_reg, 0x10801);
748 WREG32(data_reg, 0x89408940);
749 WREG32(index_reg, 0x10802);
750 WREG32(data_reg, 0xBFE8BED8);
751 WREG32(index_reg, 0x20000);
752 WREG32(data_reg, 0x80008000);
753 WREG32(index_reg, 0x20001);
754 WREG32(data_reg, 0x90008000);
755 WREG32(index_reg, 0x20002);
756 WREG32(data_reg, 0x80008000);
757 WREG32(index_reg, 0x20003);
758 WREG32(data_reg, 0x80008000);
759 WREG32(index_reg, 0x20100);
760 WREG32(data_reg, 0x80108000);
761 WREG32(index_reg, 0x20101);
762 WREG32(data_reg, 0x8FE0BF70);
763 WREG32(index_reg, 0x20102);
764 WREG32(data_reg, 0xBFE880C0);
765 WREG32(index_reg, 0x20103);
766 WREG32(data_reg, 0x80008000);
767 WREG32(index_reg, 0x20200);
768 WREG32(data_reg, 0x8018BFF8);
769 WREG32(index_reg, 0x20201);
770 WREG32(data_reg, 0x8F80BF08);
771 WREG32(index_reg, 0x20202);
772 WREG32(data_reg, 0xBFD081A0);
773 WREG32(index_reg, 0x20203);
774 WREG32(data_reg, 0xBFF88000);
775 WREG32(index_reg, 0x20300);
776 WREG32(data_reg, 0x80188000);
777 WREG32(index_reg, 0x20301);
778 WREG32(data_reg, 0x8EE0BEC0);
779 WREG32(index_reg, 0x20302);
780 WREG32(data_reg, 0xBFB082A0);
781 WREG32(index_reg, 0x20303);
782 WREG32(data_reg, 0x80008000);
783 WREG32(index_reg, 0x20400);
784 WREG32(data_reg, 0x80188000);
785 WREG32(index_reg, 0x20401);
786 WREG32(data_reg, 0x8E00BEA0);
787 WREG32(index_reg, 0x20402);
788 WREG32(data_reg, 0xBF8883C0);
789 WREG32(index_reg, 0x20403);
790 WREG32(data_reg, 0x80008000);
791 WREG32(index_reg, 0x20500);
792 WREG32(data_reg, 0x80188000);
793 WREG32(index_reg, 0x20501);
794 WREG32(data_reg, 0x8D00BE90);
795 WREG32(index_reg, 0x20502);
796 WREG32(data_reg, 0xBF588500);
797 WREG32(index_reg, 0x20503);
798 WREG32(data_reg, 0x80008008);
799 WREG32(index_reg, 0x20600);
800 WREG32(data_reg, 0x80188000);
801 WREG32(index_reg, 0x20601);
802 WREG32(data_reg, 0x8BC0BE98);
803 WREG32(index_reg, 0x20602);
804 WREG32(data_reg, 0xBF308660);
805 WREG32(index_reg, 0x20603);
806 WREG32(data_reg, 0x80008008);
807 WREG32(index_reg, 0x20700);
808 WREG32(data_reg, 0x80108000);
809 WREG32(index_reg, 0x20701);
810 WREG32(data_reg, 0x8A80BEB0);
811 WREG32(index_reg, 0x20702);
812 WREG32(data_reg, 0xBF0087C0);
813 WREG32(index_reg, 0x20703);
814 WREG32(data_reg, 0x80008008);
815 WREG32(index_reg, 0x20800);
816 WREG32(data_reg, 0x80108000);
817 WREG32(index_reg, 0x20801);
818 WREG32(data_reg, 0x8920BED0);
819 WREG32(index_reg, 0x20802);
820 WREG32(data_reg, 0xBED08920);
821 WREG32(index_reg, 0x20803);
822 WREG32(data_reg, 0x80008010);
823 WREG32(index_reg, 0x30000);
824 WREG32(data_reg, 0x90008000);
825 WREG32(index_reg, 0x30001);
826 WREG32(data_reg, 0x80008000);
827 WREG32(index_reg, 0x30100);
828 WREG32(data_reg, 0x8FE0BF90);
829 WREG32(index_reg, 0x30101);
830 WREG32(data_reg, 0xBFF880A0);
831 WREG32(index_reg, 0x30200);
832 WREG32(data_reg, 0x8F60BF40);
833 WREG32(index_reg, 0x30201);
834 WREG32(data_reg, 0xBFE88180);
835 WREG32(index_reg, 0x30300);
836 WREG32(data_reg, 0x8EC0BF00);
837 WREG32(index_reg, 0x30301);
838 WREG32(data_reg, 0xBFC88280);
839 WREG32(index_reg, 0x30400);
840 WREG32(data_reg, 0x8DE0BEE0);
841 WREG32(index_reg, 0x30401);
842 WREG32(data_reg, 0xBFA083A0);
843 WREG32(index_reg, 0x30500);
844 WREG32(data_reg, 0x8CE0BED0);
845 WREG32(index_reg, 0x30501);
846 WREG32(data_reg, 0xBF7884E0);
847 WREG32(index_reg, 0x30600);
848 WREG32(data_reg, 0x8BA0BED8);
849 WREG32(index_reg, 0x30601);
850 WREG32(data_reg, 0xBF508640);
851 WREG32(index_reg, 0x30700);
852 WREG32(data_reg, 0x8A60BEE8);
853 WREG32(index_reg, 0x30701);
854 WREG32(data_reg, 0xBF2087A0);
855 WREG32(index_reg, 0x30800);
856 WREG32(data_reg, 0x8900BF00);
857 WREG32(index_reg, 0x30801);
858 WREG32(data_reg, 0xBF008900);
859 }
860
861 struct rv515_watermark {
862 u32 lb_request_fifo_depth;
863 fixed20_12 num_line_pair;
864 fixed20_12 estimated_width;
865 fixed20_12 worst_case_latency;
866 fixed20_12 consumption_rate;
867 fixed20_12 active_time;
868 fixed20_12 dbpp;
869 fixed20_12 priority_mark_max;
870 fixed20_12 priority_mark;
871 fixed20_12 sclk;
872 };
873
874 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
875 struct radeon_crtc *crtc,
876 struct rv515_watermark *wm)
877 {
878 struct drm_display_mode *mode = &crtc->base.mode;
879 fixed20_12 a, b, c;
880 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
881 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
882
883 if (!crtc->base.enabled) {
884 /* FIXME: wouldn't it better to set priority mark to maximum */
885 wm->lb_request_fifo_depth = 4;
886 return;
887 }
888
889 if (crtc->vsc.full > rfixed_const(2))
890 wm->num_line_pair.full = rfixed_const(2);
891 else
892 wm->num_line_pair.full = rfixed_const(1);
893
894 b.full = rfixed_const(mode->crtc_hdisplay);
895 c.full = rfixed_const(256);
896 a.full = rfixed_mul(wm->num_line_pair, b);
897 request_fifo_depth.full = rfixed_div(a, c);
898 if (a.full < rfixed_const(4)) {
899 wm->lb_request_fifo_depth = 4;
900 } else {
901 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
902 }
903
904 /* Determine consumption rate
905 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
906 * vtaps = number of vertical taps,
907 * vsc = vertical scaling ratio, defined as source/destination
908 * hsc = horizontal scaling ration, defined as source/destination
909 */
910 a.full = rfixed_const(mode->clock);
911 b.full = rfixed_const(1000);
912 a.full = rfixed_div(a, b);
913 pclk.full = rfixed_div(b, a);
914 if (crtc->rmx_type != RMX_OFF) {
915 b.full = rfixed_const(2);
916 if (crtc->vsc.full > b.full)
917 b.full = crtc->vsc.full;
918 b.full = rfixed_mul(b, crtc->hsc);
919 c.full = rfixed_const(2);
920 b.full = rfixed_div(b, c);
921 consumption_time.full = rfixed_div(pclk, b);
922 } else {
923 consumption_time.full = pclk.full;
924 }
925 a.full = rfixed_const(1);
926 wm->consumption_rate.full = rfixed_div(a, consumption_time);
927
928
929 /* Determine line time
930 * LineTime = total time for one line of displayhtotal
931 * LineTime = total number of horizontal pixels
932 * pclk = pixel clock period(ns)
933 */
934 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
935 line_time.full = rfixed_mul(a, pclk);
936
937 /* Determine active time
938 * ActiveTime = time of active region of display within one line,
939 * hactive = total number of horizontal active pixels
940 * htotal = total number of horizontal pixels
941 */
942 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
943 b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
944 wm->active_time.full = rfixed_mul(line_time, b);
945 wm->active_time.full = rfixed_div(wm->active_time, a);
946
947 /* Determine chunk time
948 * ChunkTime = the time it takes the DCP to send one chunk of data
949 * to the LB which consists of pipeline delay and inter chunk gap
950 * sclk = system clock(Mhz)
951 */
952 a.full = rfixed_const(600 * 1000);
953 chunk_time.full = rfixed_div(a, rdev->pm.sclk);
954 read_delay_latency.full = rfixed_const(1000);
955
956 /* Determine the worst case latency
957 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
958 * WorstCaseLatency = worst case time from urgent to when the MC starts
959 * to return data
960 * READ_DELAY_IDLE_MAX = constant of 1us
961 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
962 * which consists of pipeline delay and inter chunk gap
963 */
964 if (rfixed_trunc(wm->num_line_pair) > 1) {
965 a.full = rfixed_const(3);
966 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
967 wm->worst_case_latency.full += read_delay_latency.full;
968 } else {
969 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
970 }
971
972 /* Determine the tolerable latency
973 * TolerableLatency = Any given request has only 1 line time
974 * for the data to be returned
975 * LBRequestFifoDepth = Number of chunk requests the LB can
976 * put into the request FIFO for a display
977 * LineTime = total time for one line of display
978 * ChunkTime = the time it takes the DCP to send one chunk
979 * of data to the LB which consists of
980 * pipeline delay and inter chunk gap
981 */
982 if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
983 tolerable_latency.full = line_time.full;
984 } else {
985 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
986 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
987 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
988 tolerable_latency.full = line_time.full - tolerable_latency.full;
989 }
990 /* We assume worst case 32bits (4 bytes) */
991 wm->dbpp.full = rfixed_const(2 * 16);
992
993 /* Determine the maximum priority mark
994 * width = viewport width in pixels
995 */
996 a.full = rfixed_const(16);
997 wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
998 wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
999
1000 /* Determine estimated width */
1001 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1002 estimated_width.full = rfixed_div(estimated_width, consumption_time);
1003 if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1004 wm->priority_mark.full = rfixed_const(10);
1005 } else {
1006 a.full = rfixed_const(16);
1007 wm->priority_mark.full = rfixed_div(estimated_width, a);
1008 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1009 }
1010 }
1011
1012 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1013 {
1014 struct drm_display_mode *mode0 = NULL;
1015 struct drm_display_mode *mode1 = NULL;
1016 struct rv515_watermark wm0;
1017 struct rv515_watermark wm1;
1018 u32 tmp;
1019 fixed20_12 priority_mark02, priority_mark12, fill_rate;
1020 fixed20_12 a, b;
1021
1022 if (rdev->mode_info.crtcs[0]->base.enabled)
1023 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1024 if (rdev->mode_info.crtcs[1]->base.enabled)
1025 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1026 rs690_line_buffer_adjust(rdev, mode0, mode1);
1027
1028 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
1029 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
1030
1031 tmp = wm0.lb_request_fifo_depth;
1032 tmp |= wm1.lb_request_fifo_depth << 16;
1033 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1034
1035 if (mode0 && mode1) {
1036 if (rfixed_trunc(wm0.dbpp) > 64)
1037 a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
1038 else
1039 a.full = wm0.num_line_pair.full;
1040 if (rfixed_trunc(wm1.dbpp) > 64)
1041 b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
1042 else
1043 b.full = wm1.num_line_pair.full;
1044 a.full += b.full;
1045 fill_rate.full = rfixed_div(wm0.sclk, a);
1046 if (wm0.consumption_rate.full > fill_rate.full) {
1047 b.full = wm0.consumption_rate.full - fill_rate.full;
1048 b.full = rfixed_mul(b, wm0.active_time);
1049 a.full = rfixed_const(16);
1050 b.full = rfixed_div(b, a);
1051 a.full = rfixed_mul(wm0.worst_case_latency,
1052 wm0.consumption_rate);
1053 priority_mark02.full = a.full + b.full;
1054 } else {
1055 a.full = rfixed_mul(wm0.worst_case_latency,
1056 wm0.consumption_rate);
1057 b.full = rfixed_const(16 * 1000);
1058 priority_mark02.full = rfixed_div(a, b);
1059 }
1060 if (wm1.consumption_rate.full > fill_rate.full) {
1061 b.full = wm1.consumption_rate.full - fill_rate.full;
1062 b.full = rfixed_mul(b, wm1.active_time);
1063 a.full = rfixed_const(16);
1064 b.full = rfixed_div(b, a);
1065 a.full = rfixed_mul(wm1.worst_case_latency,
1066 wm1.consumption_rate);
1067 priority_mark12.full = a.full + b.full;
1068 } else {
1069 a.full = rfixed_mul(wm1.worst_case_latency,
1070 wm1.consumption_rate);
1071 b.full = rfixed_const(16 * 1000);
1072 priority_mark12.full = rfixed_div(a, b);
1073 }
1074 if (wm0.priority_mark.full > priority_mark02.full)
1075 priority_mark02.full = wm0.priority_mark.full;
1076 if (rfixed_trunc(priority_mark02) < 0)
1077 priority_mark02.full = 0;
1078 if (wm0.priority_mark_max.full > priority_mark02.full)
1079 priority_mark02.full = wm0.priority_mark_max.full;
1080 if (wm1.priority_mark.full > priority_mark12.full)
1081 priority_mark12.full = wm1.priority_mark.full;
1082 if (rfixed_trunc(priority_mark12) < 0)
1083 priority_mark12.full = 0;
1084 if (wm1.priority_mark_max.full > priority_mark12.full)
1085 priority_mark12.full = wm1.priority_mark_max.full;
1086 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
1087 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
1088 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
1089 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
1090 } else if (mode0) {
1091 if (rfixed_trunc(wm0.dbpp) > 64)
1092 a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
1093 else
1094 a.full = wm0.num_line_pair.full;
1095 fill_rate.full = rfixed_div(wm0.sclk, a);
1096 if (wm0.consumption_rate.full > fill_rate.full) {
1097 b.full = wm0.consumption_rate.full - fill_rate.full;
1098 b.full = rfixed_mul(b, wm0.active_time);
1099 a.full = rfixed_const(16);
1100 b.full = rfixed_div(b, a);
1101 a.full = rfixed_mul(wm0.worst_case_latency,
1102 wm0.consumption_rate);
1103 priority_mark02.full = a.full + b.full;
1104 } else {
1105 a.full = rfixed_mul(wm0.worst_case_latency,
1106 wm0.consumption_rate);
1107 b.full = rfixed_const(16);
1108 priority_mark02.full = rfixed_div(a, b);
1109 }
1110 if (wm0.priority_mark.full > priority_mark02.full)
1111 priority_mark02.full = wm0.priority_mark.full;
1112 if (rfixed_trunc(priority_mark02) < 0)
1113 priority_mark02.full = 0;
1114 if (wm0.priority_mark_max.full > priority_mark02.full)
1115 priority_mark02.full = wm0.priority_mark_max.full;
1116 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
1117 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
1118 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1119 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1120 } else {
1121 if (rfixed_trunc(wm1.dbpp) > 64)
1122 a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
1123 else
1124 a.full = wm1.num_line_pair.full;
1125 fill_rate.full = rfixed_div(wm1.sclk, a);
1126 if (wm1.consumption_rate.full > fill_rate.full) {
1127 b.full = wm1.consumption_rate.full - fill_rate.full;
1128 b.full = rfixed_mul(b, wm1.active_time);
1129 a.full = rfixed_const(16);
1130 b.full = rfixed_div(b, a);
1131 a.full = rfixed_mul(wm1.worst_case_latency,
1132 wm1.consumption_rate);
1133 priority_mark12.full = a.full + b.full;
1134 } else {
1135 a.full = rfixed_mul(wm1.worst_case_latency,
1136 wm1.consumption_rate);
1137 b.full = rfixed_const(16 * 1000);
1138 priority_mark12.full = rfixed_div(a, b);
1139 }
1140 if (wm1.priority_mark.full > priority_mark12.full)
1141 priority_mark12.full = wm1.priority_mark.full;
1142 if (rfixed_trunc(priority_mark12) < 0)
1143 priority_mark12.full = 0;
1144 if (wm1.priority_mark_max.full > priority_mark12.full)
1145 priority_mark12.full = wm1.priority_mark_max.full;
1146 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1147 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1148 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
1149 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
1150 }
1151 }
1152
1153 void rv515_bandwidth_update(struct radeon_device *rdev)
1154 {
1155 uint32_t tmp;
1156 struct drm_display_mode *mode0 = NULL;
1157 struct drm_display_mode *mode1 = NULL;
1158
1159 if (rdev->mode_info.crtcs[0]->base.enabled)
1160 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1161 if (rdev->mode_info.crtcs[1]->base.enabled)
1162 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1163 /*
1164 * Set display0/1 priority up in the memory controller for
1165 * modes if the user specifies HIGH for displaypriority
1166 * option.
1167 */
1168 if (rdev->disp_priority == 2) {
1169 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1170 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1171 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1172 if (mode1)
1173 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1174 if (mode0)
1175 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1176 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1177 }
1178 rv515_bandwidth_avivo_update(rdev);
1179 }
Linux with added FPC-III support