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x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / ieee1394 / video1394.c
blob949064a05675cbb766cded13fc2bba78a680ad49
1 /*
2 * video1394.c - video driver for OHCI 1394 boards
3 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
4 * Peter Schlaile <udbz@rz.uni-karlsruhe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 * NOTES:
21 *
22 * ioctl return codes:
23 * EFAULT is only for invalid address for the argp
24 * EINVAL for out of range values
25 * EBUSY when trying to use an already used resource
26 * ESRCH when trying to free/stop a not used resource
27 * EAGAIN for resource allocation failure that could perhaps succeed later
28 * ENOTTY for unsupported ioctl request
29 *
30 */
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
35 #include <linux/interrupt.h>
36 #include <linux/wait.h>
37 #include <linux/errno.h>
38 #include <linux/module.h>
39 #include <linux/init.h>
40 #include <linux/pci.h>
41 #include <linux/fs.h>
42 #include <linux/poll.h>
43 #include <linux/delay.h>
44 #include <linux/bitops.h>
45 #include <linux/types.h>
46 #include <linux/vmalloc.h>
47 #include <linux/timex.h>
48 #include <linux/mm.h>
49 #include <linux/compat.h>
50 #include <linux/cdev.h>
51
52 #include "dma.h"
53 #include "highlevel.h"
54 #include "hosts.h"
55 #include "ieee1394.h"
56 #include "ieee1394_core.h"
57 #include "ieee1394_hotplug.h"
58 #include "ieee1394_types.h"
59 #include "nodemgr.h"
60 #include "ohci1394.h"
61 #include "video1394.h"
62
63 #define ISO_CHANNELS 64
64
65 struct it_dma_prg {
66 struct dma_cmd begin;
67 quadlet_t data[4];
68 struct dma_cmd end;
69 quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
70 };
71
72 struct dma_iso_ctx {
73 struct ti_ohci *ohci;
74 int type; /* OHCI_ISO_TRANSMIT or OHCI_ISO_RECEIVE */
75 struct ohci1394_iso_tasklet iso_tasklet;
76 int channel;
77 int ctx;
78 int last_buffer;
79 int * next_buffer; /* For ISO Transmit of video packets
80 to write the correct SYT field
81 into the next block */
82 unsigned int num_desc;
83 unsigned int buf_size;
84 unsigned int frame_size;
85 unsigned int packet_size;
86 unsigned int left_size;
87 unsigned int nb_cmd;
88
89 struct dma_region dma;
90
91 struct dma_prog_region *prg_reg;
92
93 struct dma_cmd **ir_prg;
94 struct it_dma_prg **it_prg;
95
96 unsigned int *buffer_status;
97 unsigned int *buffer_prg_assignment;
98 struct timeval *buffer_time; /* time when the buffer was received */
99 unsigned int *last_used_cmd; /* For ISO Transmit with
100 variable sized packets only ! */
101 int ctrlClear;
102 int ctrlSet;
103 int cmdPtr;
104 int ctxMatch;
105 wait_queue_head_t waitq;
106 spinlock_t lock;
107 unsigned int syt_offset;
108 int flags;
109
110 struct list_head link;
111 };
112
113
114 struct file_ctx {
115 struct ti_ohci *ohci;
116 struct list_head context_list;
117 struct dma_iso_ctx *current_ctx;
118 };
119
120 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
121 #define VIDEO1394_DEBUG
122 #endif
123
124 #ifdef DBGMSG
125 #undef DBGMSG
126 #endif
127
128 #ifdef VIDEO1394_DEBUG
129 #define DBGMSG(card, fmt, args...) \
130 printk(KERN_INFO "video1394_%d: " fmt "\n" , card , ## args)
131 #else
132 #define DBGMSG(card, fmt, args...) do {} while (0)
133 #endif
134
135 /* print general (card independent) information */
136 #define PRINT_G(level, fmt, args...) \
137 printk(level "video1394: " fmt "\n" , ## args)
138
139 /* print card specific information */
140 #define PRINT(level, card, fmt, args...) \
141 printk(level "video1394_%d: " fmt "\n" , card , ## args)
142
143 static void wakeup_dma_ir_ctx(unsigned long l);
144 static void wakeup_dma_it_ctx(unsigned long l);
145
146 static struct hpsb_highlevel video1394_highlevel;
147
148 static int free_dma_iso_ctx(struct dma_iso_ctx *d)
149 {
150 int i;
151
152 DBGMSG(d->ohci->host->id, "Freeing dma_iso_ctx %d", d->ctx);
153
154 ohci1394_stop_context(d->ohci, d->ctrlClear, NULL);
155 if (d->iso_tasklet.link.next != NULL)
156 ohci1394_unregister_iso_tasklet(d->ohci, &d->iso_tasklet);
157
158 dma_region_free(&d->dma);
159
160 if (d->prg_reg) {
161 for (i = 0; i < d->num_desc; i++)
162 dma_prog_region_free(&d->prg_reg[i]);
163 kfree(d->prg_reg);
164 }
165
166 kfree(d->ir_prg);
167 kfree(d->it_prg);
168 kfree(d->buffer_status);
169 kfree(d->buffer_prg_assignment);
170 kfree(d->buffer_time);
171 kfree(d->last_used_cmd);
172 kfree(d->next_buffer);
173 list_del(&d->link);
174 kfree(d);
175
176 return 0;
177 }
178
179 static struct dma_iso_ctx *
180 alloc_dma_iso_ctx(struct ti_ohci *ohci, int type, int num_desc,
181 int buf_size, int channel, unsigned int packet_size)
182 {
183 struct dma_iso_ctx *d;
184 int i;
185
186 d = kzalloc(sizeof(*d), GFP_KERNEL);
187 if (!d) {
188 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma_iso_ctx");
189 return NULL;
190 }
191
192 d->ohci = ohci;
193 d->type = type;
194 d->channel = channel;
195 d->num_desc = num_desc;
196 d->frame_size = buf_size;
197 d->buf_size = PAGE_ALIGN(buf_size);
198 d->last_buffer = -1;
199 INIT_LIST_HEAD(&d->link);
200 init_waitqueue_head(&d->waitq);
201
202 /* Init the regions for easy cleanup */
203 dma_region_init(&d->dma);
204
205 if (dma_region_alloc(&d->dma, (d->num_desc - 1) * d->buf_size, ohci->dev,
206 PCI_DMA_BIDIRECTIONAL)) {
207 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma buffer");
208 free_dma_iso_ctx(d);
209 return NULL;
210 }
211
212 if (type == OHCI_ISO_RECEIVE)
213 ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
214 wakeup_dma_ir_ctx,
215 (unsigned long) d);
216 else
217 ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
218 wakeup_dma_it_ctx,
219 (unsigned long) d);
220
221 if (ohci1394_register_iso_tasklet(ohci, &d->iso_tasklet) < 0) {
222 PRINT(KERN_ERR, ohci->host->id, "no free iso %s contexts",
223 type == OHCI_ISO_RECEIVE ? "receive" : "transmit");
224 free_dma_iso_ctx(d);
225 return NULL;
226 }
227 d->ctx = d->iso_tasklet.context;
228
229 d->prg_reg = kmalloc(d->num_desc * sizeof(*d->prg_reg), GFP_KERNEL);
230 if (!d->prg_reg) {
231 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate ir prg regs");
232 free_dma_iso_ctx(d);
233 return NULL;
234 }
235 /* Makes for easier cleanup */
236 for (i = 0; i < d->num_desc; i++)
237 dma_prog_region_init(&d->prg_reg[i]);
238
239 if (type == OHCI_ISO_RECEIVE) {
240 d->ctrlSet = OHCI1394_IsoRcvContextControlSet+32*d->ctx;
241 d->ctrlClear = OHCI1394_IsoRcvContextControlClear+32*d->ctx;
242 d->cmdPtr = OHCI1394_IsoRcvCommandPtr+32*d->ctx;
243 d->ctxMatch = OHCI1394_IsoRcvContextMatch+32*d->ctx;
244
245 d->ir_prg = kzalloc(d->num_desc * sizeof(*d->ir_prg),
246 GFP_KERNEL);
247
248 if (!d->ir_prg) {
249 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
250 free_dma_iso_ctx(d);
251 return NULL;
252 }
253
254 d->nb_cmd = d->buf_size / PAGE_SIZE + 1;
255 d->left_size = (d->frame_size % PAGE_SIZE) ?
256 d->frame_size % PAGE_SIZE : PAGE_SIZE;
257
258 for (i = 0;i < d->num_desc; i++) {
259 if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
260 sizeof(struct dma_cmd), ohci->dev)) {
261 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
262 free_dma_iso_ctx(d);
263 return NULL;
264 }
265 d->ir_prg[i] = (struct dma_cmd *)d->prg_reg[i].kvirt;
266 }
267
268 } else { /* OHCI_ISO_TRANSMIT */
269 d->ctrlSet = OHCI1394_IsoXmitContextControlSet+16*d->ctx;
270 d->ctrlClear = OHCI1394_IsoXmitContextControlClear+16*d->ctx;
271 d->cmdPtr = OHCI1394_IsoXmitCommandPtr+16*d->ctx;
272
273 d->it_prg = kzalloc(d->num_desc * sizeof(*d->it_prg),
274 GFP_KERNEL);
275
276 if (!d->it_prg) {
277 PRINT(KERN_ERR, ohci->host->id,
278 "Failed to allocate dma it prg");
279 free_dma_iso_ctx(d);
280 return NULL;
281 }
282
283 d->packet_size = packet_size;
284
285 if (PAGE_SIZE % packet_size || packet_size>4096) {
286 PRINT(KERN_ERR, ohci->host->id,
287 "Packet size %d (page_size: %ld) "
288 "not yet supported\n",
289 packet_size, PAGE_SIZE);
290 free_dma_iso_ctx(d);
291 return NULL;
292 }
293
294 d->nb_cmd = d->frame_size / d->packet_size;
295 if (d->frame_size % d->packet_size) {
296 d->nb_cmd++;
297 d->left_size = d->frame_size % d->packet_size;
298 } else
299 d->left_size = d->packet_size;
300
301 for (i = 0; i < d->num_desc; i++) {
302 if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
303 sizeof(struct it_dma_prg), ohci->dev)) {
304 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma it prg");
305 free_dma_iso_ctx(d);
306 return NULL;
307 }
308 d->it_prg[i] = (struct it_dma_prg *)d->prg_reg[i].kvirt;
309 }
310 }
311
312 d->buffer_status =
313 kzalloc(d->num_desc * sizeof(*d->buffer_status), GFP_KERNEL);
314 d->buffer_prg_assignment =
315 kzalloc(d->num_desc * sizeof(*d->buffer_prg_assignment), GFP_KERNEL);
316 d->buffer_time =
317 kzalloc(d->num_desc * sizeof(*d->buffer_time), GFP_KERNEL);
318 d->last_used_cmd =
319 kzalloc(d->num_desc * sizeof(*d->last_used_cmd), GFP_KERNEL);
320 d->next_buffer =
321 kzalloc(d->num_desc * sizeof(*d->next_buffer), GFP_KERNEL);
322
323 if (!d->buffer_status || !d->buffer_prg_assignment || !d->buffer_time ||
324 !d->last_used_cmd || !d->next_buffer) {
325 PRINT(KERN_ERR, ohci->host->id,
326 "Failed to allocate dma_iso_ctx member");
327 free_dma_iso_ctx(d);
328 return NULL;
329 }
330
331 spin_lock_init(&d->lock);
332
333 DBGMSG(ohci->host->id, "Iso %s DMA: %d buffers "
334 "of size %d allocated for a frame size %d, each with %d prgs",
335 (type == OHCI_ISO_RECEIVE) ? "receive" : "transmit",
336 d->num_desc - 1, d->buf_size, d->frame_size, d->nb_cmd);
337
338 return d;
339 }
340
341 static void reset_ir_status(struct dma_iso_ctx *d, int n)
342 {
343 int i;
344 d->ir_prg[n][0].status = cpu_to_le32(4);
345 d->ir_prg[n][1].status = cpu_to_le32(PAGE_SIZE-4);
346 for (i = 2; i < d->nb_cmd - 1; i++)
347 d->ir_prg[n][i].status = cpu_to_le32(PAGE_SIZE);
348 d->ir_prg[n][i].status = cpu_to_le32(d->left_size);
349 }
350
351 static void reprogram_dma_ir_prg(struct dma_iso_ctx *d, int n, int buffer, int flags)
352 {
353 struct dma_cmd *ir_prg = d->ir_prg[n];
354 unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size;
355 int i;
356
357 d->buffer_prg_assignment[n] = buffer;
358
359 ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
360 (unsigned long)d->dma.kvirt));
361 ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
362 (buf + 4) - (unsigned long)d->dma.kvirt));
363
364 for (i=2;i<d->nb_cmd-1;i++) {
365 ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
366 (buf+(i-1)*PAGE_SIZE) -
367 (unsigned long)d->dma.kvirt));
368 }
369
370 ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
371 DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
372 ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
373 (buf+(i-1)*PAGE_SIZE) - (unsigned long)d->dma.kvirt));
374 }
375
376 static void initialize_dma_ir_prg(struct dma_iso_ctx *d, int n, int flags)
377 {
378 struct dma_cmd *ir_prg = d->ir_prg[n];
379 struct dma_prog_region *ir_reg = &d->prg_reg[n];
380 unsigned long buf = (unsigned long)d->dma.kvirt;
381 int i;
382
383 /* the first descriptor will read only 4 bytes */
384 ir_prg[0].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
385 DMA_CTL_BRANCH | 4);
386
387 /* set the sync flag */
388 if (flags & VIDEO1394_SYNC_FRAMES)
389 ir_prg[0].control |= cpu_to_le32(DMA_CTL_WAIT);
390
391 ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
392 (unsigned long)d->dma.kvirt));
393 ir_prg[0].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
394 1 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
395
396 /* If there is *not* only one DMA page per frame (hence, d->nb_cmd==2) */
397 if (d->nb_cmd > 2) {
398 /* The second descriptor will read PAGE_SIZE-4 bytes */
399 ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
400 DMA_CTL_BRANCH | (PAGE_SIZE-4));
401 ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf + 4) -
402 (unsigned long)d->dma.kvirt));
403 ir_prg[1].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
404 2 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
405
406 for (i = 2; i < d->nb_cmd - 1; i++) {
407 ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
408 DMA_CTL_BRANCH | PAGE_SIZE);
409 ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
410 (buf+(i-1)*PAGE_SIZE) -
411 (unsigned long)d->dma.kvirt));
412
413 ir_prg[i].branchAddress =
414 cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
415 (i + 1) * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
416 }
417
418 /* The last descriptor will generate an interrupt */
419 ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
420 DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
421 ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
422 (buf+(i-1)*PAGE_SIZE) -
423 (unsigned long)d->dma.kvirt));
424 } else {
425 /* Only one DMA page is used. Read d->left_size immediately and */
426 /* generate an interrupt as this is also the last page. */
427 ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
428 DMA_CTL_IRQ | DMA_CTL_BRANCH | (d->left_size-4));
429 ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
430 (buf + 4) - (unsigned long)d->dma.kvirt));
431 }
432 }
433
434 static void initialize_dma_ir_ctx(struct dma_iso_ctx *d, int tag, int flags)
435 {
436 struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
437 int i;
438
439 d->flags = flags;
440
441 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
442
443 for (i=0;i<d->num_desc;i++) {
444 initialize_dma_ir_prg(d, i, flags);
445 reset_ir_status(d, i);
446 }
447
448 /* reset the ctrl register */
449 reg_write(ohci, d->ctrlClear, 0xf0000000);
450
451 /* Set bufferFill */
452 reg_write(ohci, d->ctrlSet, 0x80000000);
453
454 /* Set isoch header */
455 if (flags & VIDEO1394_INCLUDE_ISO_HEADERS)
456 reg_write(ohci, d->ctrlSet, 0x40000000);
457
458 /* Set the context match register to match on all tags,
459 sync for sync tag, and listen to d->channel */
460 reg_write(ohci, d->ctxMatch, 0xf0000000|((tag&0xf)<<8)|d->channel);
461
462 /* Set up isoRecvIntMask to generate interrupts */
463 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1<<d->ctx);
464 }
465
466 /* find which context is listening to this channel */
467 static struct dma_iso_ctx *
468 find_ctx(struct list_head *list, int type, int channel)
469 {
470 struct dma_iso_ctx *ctx;
471
472 list_for_each_entry(ctx, list, link) {
473 if (ctx->type == type && ctx->channel == channel)
474 return ctx;
475 }
476
477 return NULL;
478 }
479
480 static void wakeup_dma_ir_ctx(unsigned long l)
481 {
482 struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
483 int i;
484
485 spin_lock(&d->lock);
486
487 for (i = 0; i < d->num_desc; i++) {
488 if (d->ir_prg[i][d->nb_cmd-1].status & cpu_to_le32(0xFFFF0000)) {
489 reset_ir_status(d, i);
490 d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY;
491 do_gettimeofday(&d->buffer_time[d->buffer_prg_assignment[i]]);
492 dma_region_sync_for_cpu(&d->dma,
493 d->buffer_prg_assignment[i] * d->buf_size,
494 d->buf_size);
495 }
496 }
497
498 spin_unlock(&d->lock);
499
500 if (waitqueue_active(&d->waitq))
501 wake_up_interruptible(&d->waitq);
502 }
503
504 static inline void put_timestamp(struct ti_ohci *ohci, struct dma_iso_ctx * d,
505 int n)
506 {
507 unsigned char* buf = d->dma.kvirt + n * d->buf_size;
508 u32 cycleTimer;
509 u32 timeStamp;
510
511 if (n == -1) {
512 return;
513 }
514
515 cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
516
517 timeStamp = ((cycleTimer & 0x0fff) + d->syt_offset); /* 11059 = 450 us */
518 timeStamp = (timeStamp % 3072 + ((timeStamp / 3072) << 12)
519 + (cycleTimer & 0xf000)) & 0xffff;
520
521 buf[6] = timeStamp >> 8;
522 buf[7] = timeStamp & 0xff;
523
524 /* if first packet is empty packet, then put timestamp into the next full one too */
525 if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
526 buf += d->packet_size;
527 buf[6] = timeStamp >> 8;
528 buf[7] = timeStamp & 0xff;
529 }
530
531 /* do the next buffer frame too in case of irq latency */
532 n = d->next_buffer[n];
533 if (n == -1) {
534 return;
535 }
536 buf = d->dma.kvirt + n * d->buf_size;
537
538 timeStamp += (d->last_used_cmd[n] << 12) & 0xffff;
539
540 buf[6] = timeStamp >> 8;
541 buf[7] = timeStamp & 0xff;
542
543 /* if first packet is empty packet, then put timestamp into the next full one too */
544 if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
545 buf += d->packet_size;
546 buf[6] = timeStamp >> 8;
547 buf[7] = timeStamp & 0xff;
548 }
549
550 #if 0
551 printk("curr: %d, next: %d, cycleTimer: %08x timeStamp: %08x\n",
552 curr, n, cycleTimer, timeStamp);
553 #endif
554 }
555
556 static void wakeup_dma_it_ctx(unsigned long l)
557 {
558 struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
559 struct ti_ohci *ohci = d->ohci;
560 int i;
561
562 spin_lock(&d->lock);
563
564 for (i = 0; i < d->num_desc; i++) {
565 if (d->it_prg[i][d->last_used_cmd[i]].end.status &
566 cpu_to_le32(0xFFFF0000)) {
567 int next = d->next_buffer[i];
568 put_timestamp(ohci, d, next);
569 d->it_prg[i][d->last_used_cmd[i]].end.status = 0;
570 d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY;
571 }
572 }
573
574 spin_unlock(&d->lock);
575
576 if (waitqueue_active(&d->waitq))
577 wake_up_interruptible(&d->waitq);
578 }
579
580 static void reprogram_dma_it_prg(struct dma_iso_ctx *d, int n, int buffer)
581 {
582 struct it_dma_prg *it_prg = d->it_prg[n];
583 unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size;
584 int i;
585
586 d->buffer_prg_assignment[n] = buffer;
587 for (i=0;i<d->nb_cmd;i++) {
588 it_prg[i].end.address =
589 cpu_to_le32(dma_region_offset_to_bus(&d->dma,
590 (buf+i*d->packet_size) - (unsigned long)d->dma.kvirt));
591 }
592 }
593
594 static void initialize_dma_it_prg(struct dma_iso_ctx *d, int n, int sync_tag)
595 {
596 struct it_dma_prg *it_prg = d->it_prg[n];
597 struct dma_prog_region *it_reg = &d->prg_reg[n];
598 unsigned long buf = (unsigned long)d->dma.kvirt;
599 int i;
600 d->last_used_cmd[n] = d->nb_cmd - 1;
601 for (i=0;i<d->nb_cmd;i++) {
602
603 it_prg[i].begin.control = cpu_to_le32(DMA_CTL_OUTPUT_MORE |
604 DMA_CTL_IMMEDIATE | 8) ;
605 it_prg[i].begin.address = 0;
606
607 it_prg[i].begin.status = 0;
608
609 it_prg[i].data[0] = cpu_to_le32(
610 (IEEE1394_SPEED_100 << 16)
611 | (/* tag */ 1 << 14)
612 | (d->channel << 8)
613 | (TCODE_ISO_DATA << 4));
614 if (i==0) it_prg[i].data[0] |= cpu_to_le32(sync_tag);
615 it_prg[i].data[1] = cpu_to_le32(d->packet_size << 16);
616 it_prg[i].data[2] = 0;
617 it_prg[i].data[3] = 0;
618
619 it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST |
620 DMA_CTL_BRANCH);
621 it_prg[i].end.address =
622 cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf+i*d->packet_size) -
623 (unsigned long)d->dma.kvirt));
624
625 if (i<d->nb_cmd-1) {
626 it_prg[i].end.control |= cpu_to_le32(d->packet_size);
627 it_prg[i].begin.branchAddress =
628 cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
629 sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
630 it_prg[i].end.branchAddress =
631 cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
632 sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
633 } else {
634 /* the last prg generates an interrupt */
635 it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
636 DMA_CTL_IRQ | d->left_size);
637 /* the last prg doesn't branch */
638 it_prg[i].begin.branchAddress = 0;
639 it_prg[i].end.branchAddress = 0;
640 }
641 it_prg[i].end.status = 0;
642 }
643 }
644
645 static void initialize_dma_it_prg_var_packet_queue(
646 struct dma_iso_ctx *d, int n, unsigned int * packet_sizes,
647 struct ti_ohci *ohci)
648 {
649 struct it_dma_prg *it_prg = d->it_prg[n];
650 struct dma_prog_region *it_reg = &d->prg_reg[n];
651 int i;
652
653 #if 0
654 if (n != -1) {
655 put_timestamp(ohci, d, n);
656 }
657 #endif
658 d->last_used_cmd[n] = d->nb_cmd - 1;
659
660 for (i = 0; i < d->nb_cmd; i++) {
661 unsigned int size;
662 if (packet_sizes[i] > d->packet_size) {
663 size = d->packet_size;
664 } else {
665 size = packet_sizes[i];
666 }
667 it_prg[i].data[1] = cpu_to_le32(size << 16);
668 it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST | DMA_CTL_BRANCH);
669
670 if (i < d->nb_cmd-1 && packet_sizes[i+1] != 0) {
671 it_prg[i].end.control |= cpu_to_le32(size);
672 it_prg[i].begin.branchAddress =
673 cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
674 sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
675 it_prg[i].end.branchAddress =
676 cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
677 sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
678 } else {
679 /* the last prg generates an interrupt */
680 it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
681 DMA_CTL_IRQ | size);
682 /* the last prg doesn't branch */
683 it_prg[i].begin.branchAddress = 0;
684 it_prg[i].end.branchAddress = 0;
685 d->last_used_cmd[n] = i;
686 break;
687 }
688 }
689 }
690
691 static void initialize_dma_it_ctx(struct dma_iso_ctx *d, int sync_tag,
692 unsigned int syt_offset, int flags)
693 {
694 struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
695 int i;
696
697 d->flags = flags;
698 d->syt_offset = (syt_offset == 0 ? 11000 : syt_offset);
699
700 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
701
702 for (i=0;i<d->num_desc;i++)
703 initialize_dma_it_prg(d, i, sync_tag);
704
705 /* Set up isoRecvIntMask to generate interrupts */
706 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1<<d->ctx);
707 }
708
709 static inline unsigned video1394_buffer_state(struct dma_iso_ctx *d,
710 unsigned int buffer)
711 {
712 unsigned long flags;
713 unsigned int ret;
714 spin_lock_irqsave(&d->lock, flags);
715 ret = d->buffer_status[buffer];
716 spin_unlock_irqrestore(&d->lock, flags);
717 return ret;
718 }
719
720 static long video1394_ioctl(struct file *file,
721 unsigned int cmd, unsigned long arg)
722 {
723 struct file_ctx *ctx = (struct file_ctx *)file->private_data;
724 struct ti_ohci *ohci = ctx->ohci;
725 unsigned long flags;
726 void __user *argp = (void __user *)arg;
727
728 switch(cmd)
729 {
730 case VIDEO1394_IOC_LISTEN_CHANNEL:
731 case VIDEO1394_IOC_TALK_CHANNEL:
732 {
733 struct video1394_mmap v;
734 u64 mask;
735 struct dma_iso_ctx *d;
736 int i;
737
738 if (copy_from_user(&v, argp, sizeof(v)))
739 return -EFAULT;
740
741 /* if channel < 0, find lowest available one */
742 if (v.channel < 0) {
743 mask = (u64)0x1;
744 for (i=0; ; i++) {
745 if (i == ISO_CHANNELS) {
746 PRINT(KERN_ERR, ohci->host->id,
747 "No free channel found");
748 return -EAGAIN;
749 }
750 if (!(ohci->ISO_channel_usage & mask)) {
751 v.channel = i;
752 PRINT(KERN_INFO, ohci->host->id, "Found free channel %d", i);
753 break;
754 }
755 mask = mask << 1;
756 }
757 } else if (v.channel >= ISO_CHANNELS) {
758 PRINT(KERN_ERR, ohci->host->id,
759 "Iso channel %d out of bounds", v.channel);
760 return -EINVAL;
761 } else {
762 mask = (u64)0x1<<v.channel;
763 }
764 DBGMSG(ohci->host->id, "mask: %08X%08X usage: %08X%08X\n",
765 (u32)(mask>>32),(u32)(mask&0xffffffff),
766 (u32)(ohci->ISO_channel_usage>>32),
767 (u32)(ohci->ISO_channel_usage&0xffffffff));
768 if (ohci->ISO_channel_usage & mask) {
769 PRINT(KERN_ERR, ohci->host->id,
770 "Channel %d is already taken", v.channel);
771 return -EBUSY;
772 }
773
774 if (v.buf_size == 0 || v.buf_size > VIDEO1394_MAX_SIZE) {
775 PRINT(KERN_ERR, ohci->host->id,
776 "Invalid %d length buffer requested",v.buf_size);
777 return -EINVAL;
778 }
779
780 if (v.nb_buffers == 0 || v.nb_buffers > VIDEO1394_MAX_SIZE) {
781 PRINT(KERN_ERR, ohci->host->id,
782 "Invalid %d buffers requested",v.nb_buffers);
783 return -EINVAL;
784 }
785
786 if (v.nb_buffers * v.buf_size > VIDEO1394_MAX_SIZE) {
787 PRINT(KERN_ERR, ohci->host->id,
788 "%d buffers of size %d bytes is too big",
789 v.nb_buffers, v.buf_size);
790 return -EINVAL;
791 }
792
793 if (cmd == VIDEO1394_IOC_LISTEN_CHANNEL) {
794 d = alloc_dma_iso_ctx(ohci, OHCI_ISO_RECEIVE,
795 v.nb_buffers + 1, v.buf_size,
796 v.channel, 0);
797
798 if (d == NULL) {
799 PRINT(KERN_ERR, ohci->host->id,
800 "Couldn't allocate ir context");
801 return -EAGAIN;
802 }
803 initialize_dma_ir_ctx(d, v.sync_tag, v.flags);
804
805 ctx->current_ctx = d;
806
807 v.buf_size = d->buf_size;
808 list_add_tail(&d->link, &ctx->context_list);
809
810 DBGMSG(ohci->host->id,
811 "iso context %d listen on channel %d",
812 d->ctx, v.channel);
813 }
814 else {
815 d = alloc_dma_iso_ctx(ohci, OHCI_ISO_TRANSMIT,
816 v.nb_buffers + 1, v.buf_size,
817 v.channel, v.packet_size);
818
819 if (d == NULL) {
820 PRINT(KERN_ERR, ohci->host->id,
821 "Couldn't allocate it context");
822 return -EAGAIN;
823 }
824 initialize_dma_it_ctx(d, v.sync_tag,
825 v.syt_offset, v.flags);
826
827 ctx->current_ctx = d;
828
829 v.buf_size = d->buf_size;
830
831 list_add_tail(&d->link, &ctx->context_list);
832
833 DBGMSG(ohci->host->id,
834 "Iso context %d talk on channel %d", d->ctx,
835 v.channel);
836 }
837
838 if (copy_to_user(argp, &v, sizeof(v))) {
839 /* FIXME : free allocated dma resources */
840 return -EFAULT;
841 }
842
843 ohci->ISO_channel_usage |= mask;
844
845 return 0;
846 }
847 case VIDEO1394_IOC_UNLISTEN_CHANNEL:
848 case VIDEO1394_IOC_UNTALK_CHANNEL:
849 {
850 int channel;
851 u64 mask;
852 struct dma_iso_ctx *d;
853
854 if (copy_from_user(&channel, argp, sizeof(int)))
855 return -EFAULT;
856
857 if (channel < 0 || channel >= ISO_CHANNELS) {
858 PRINT(KERN_ERR, ohci->host->id,
859 "Iso channel %d out of bound", channel);
860 return -EINVAL;
861 }
862 mask = (u64)0x1<<channel;
863 if (!(ohci->ISO_channel_usage & mask)) {
864 PRINT(KERN_ERR, ohci->host->id,
865 "Channel %d is not being used", channel);
866 return -ESRCH;
867 }
868
869 /* Mark this channel as unused */
870 ohci->ISO_channel_usage &= ~mask;
871
872 if (cmd == VIDEO1394_IOC_UNLISTEN_CHANNEL)
873 d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, channel);
874 else
875 d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, channel);
876
877 if (d == NULL) return -ESRCH;
878 DBGMSG(ohci->host->id, "Iso context %d "
879 "stop talking on channel %d", d->ctx, channel);
880 free_dma_iso_ctx(d);
881
882 return 0;
883 }
884 case VIDEO1394_IOC_LISTEN_QUEUE_BUFFER:
885 {
886 struct video1394_wait v;
887 struct dma_iso_ctx *d;
888 int next_prg;
889
890 if (unlikely(copy_from_user(&v, argp, sizeof(v))))
891 return -EFAULT;
892
893 d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
894 if (unlikely(d == NULL))
895 return -EFAULT;
896
897 if (unlikely(v.buffer >= d->num_desc - 1)) {
898 PRINT(KERN_ERR, ohci->host->id,
899 "Buffer %d out of range",v.buffer);
900 return -EINVAL;
901 }
902
903 spin_lock_irqsave(&d->lock,flags);
904
905 if (unlikely(d->buffer_status[v.buffer]==VIDEO1394_BUFFER_QUEUED)) {
906 PRINT(KERN_ERR, ohci->host->id,
907 "Buffer %d is already used",v.buffer);
908 spin_unlock_irqrestore(&d->lock,flags);
909 return -EBUSY;
910 }
911
912 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
913
914 next_prg = (d->last_buffer + 1) % d->num_desc;
915 if (d->last_buffer>=0)
916 d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress =
917 cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0)
918 & 0xfffffff0) | 0x1);
919
920 d->last_buffer = next_prg;
921 reprogram_dma_ir_prg(d, d->last_buffer, v.buffer, d->flags);
922
923 d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress = 0;
924
925 spin_unlock_irqrestore(&d->lock,flags);
926
927 if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
928 {
929 DBGMSG(ohci->host->id, "Starting iso DMA ctx=%d",d->ctx);
930
931 /* Tell the controller where the first program is */
932 reg_write(ohci, d->cmdPtr,
933 dma_prog_region_offset_to_bus(&d->prg_reg[d->last_buffer], 0) | 0x1);
934
935 /* Run IR context */
936 reg_write(ohci, d->ctrlSet, 0x8000);
937 }
938 else {
939 /* Wake up dma context if necessary */
940 if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
941 DBGMSG(ohci->host->id,
942 "Waking up iso dma ctx=%d", d->ctx);
943 reg_write(ohci, d->ctrlSet, 0x1000);
944 }
945 }
946 return 0;
947
948 }
949 case VIDEO1394_IOC_LISTEN_WAIT_BUFFER:
950 case VIDEO1394_IOC_LISTEN_POLL_BUFFER:
951 {
952 struct video1394_wait v;
953 struct dma_iso_ctx *d;
954 int i = 0;
955
956 if (unlikely(copy_from_user(&v, argp, sizeof(v))))
957 return -EFAULT;
958
959 d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
960 if (unlikely(d == NULL))
961 return -EFAULT;
962
963 if (unlikely(v.buffer > d->num_desc - 1)) {
964 PRINT(KERN_ERR, ohci->host->id,
965 "Buffer %d out of range",v.buffer);
966 return -EINVAL;
967 }
968
969 /*
970 * I change the way it works so that it returns
971 * the last received frame.
972 */
973 spin_lock_irqsave(&d->lock, flags);
974 switch(d->buffer_status[v.buffer]) {
975 case VIDEO1394_BUFFER_READY:
976 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
977 break;
978 case VIDEO1394_BUFFER_QUEUED:
979 if (cmd == VIDEO1394_IOC_LISTEN_POLL_BUFFER) {
980 /* for polling, return error code EINTR */
981 spin_unlock_irqrestore(&d->lock, flags);
982 return -EINTR;
983 }
984
985 spin_unlock_irqrestore(&d->lock, flags);
986 wait_event_interruptible(d->waitq,
987 video1394_buffer_state(d, v.buffer) ==
988 VIDEO1394_BUFFER_READY);
989 if (signal_pending(current))
990 return -EINTR;
991 spin_lock_irqsave(&d->lock, flags);
992 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
993 break;
994 default:
995 PRINT(KERN_ERR, ohci->host->id,
996 "Buffer %d is not queued",v.buffer);
997 spin_unlock_irqrestore(&d->lock, flags);
998 return -ESRCH;
999 }
1000
1001 /* set time of buffer */
1002 v.filltime = d->buffer_time[v.buffer];
1003
1004 /*
1005 * Look ahead to see how many more buffers have been received
1006 */
1007 i=0;
1008 while (d->buffer_status[(v.buffer+1)%(d->num_desc - 1)]==
1009 VIDEO1394_BUFFER_READY) {
1010 v.buffer=(v.buffer+1)%(d->num_desc - 1);
1011 i++;
1012 }
1013 spin_unlock_irqrestore(&d->lock, flags);
1014
1015 v.buffer=i;
1016 if (unlikely(copy_to_user(argp, &v, sizeof(v))))
1017 return -EFAULT;
1018
1019 return 0;
1020 }
1021 case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
1022 {
1023 struct video1394_wait v;
1024 unsigned int *psizes = NULL;
1025 struct dma_iso_ctx *d;
1026 int next_prg;
1027
1028 if (copy_from_user(&v, argp, sizeof(v)))
1029 return -EFAULT;
1030
1031 d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
1032 if (d == NULL) return -EFAULT;
1033
1034 if (v.buffer >= d->num_desc - 1) {
1035 PRINT(KERN_ERR, ohci->host->id,
1036 "Buffer %d out of range",v.buffer);
1037 return -EINVAL;
1038 }
1039
1040 if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
1041 int buf_size = d->nb_cmd * sizeof(*psizes);
1042 struct video1394_queue_variable __user *p = argp;
1043 unsigned int __user *qv;
1044
1045 if (get_user(qv, &p->packet_sizes))
1046 return -EFAULT;
1047
1048 psizes = kmalloc(buf_size, GFP_KERNEL);
1049 if (!psizes)
1050 return -ENOMEM;
1051
1052 if (copy_from_user(psizes, qv, buf_size)) {
1053 kfree(psizes);
1054 return -EFAULT;
1055 }
1056 }
1057
1058 spin_lock_irqsave(&d->lock,flags);
1059
1060 /* last_buffer is last_prg */
1061 next_prg = (d->last_buffer + 1) % d->num_desc;
1062 if (d->buffer_status[v.buffer]!=VIDEO1394_BUFFER_FREE) {
1063 PRINT(KERN_ERR, ohci->host->id,
1064 "Buffer %d is already used",v.buffer);
1065 spin_unlock_irqrestore(&d->lock,flags);
1066 kfree(psizes);
1067 return -EBUSY;
1068 }
1069
1070 if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
1071 initialize_dma_it_prg_var_packet_queue(
1072 d, next_prg, psizes, ohci);
1073 }
1074
1075 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
1076
1077 if (d->last_buffer >= 0) {
1078 d->it_prg[d->last_buffer]
1079 [ d->last_used_cmd[d->last_buffer] ].end.branchAddress =
1080 cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg],
1081 0) & 0xfffffff0) | 0x3);
1082
1083 d->it_prg[d->last_buffer]
1084 [ d->last_used_cmd[d->last_buffer] ].begin.branchAddress =
1085 cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg],
1086 0) & 0xfffffff0) | 0x3);
1087 d->next_buffer[d->last_buffer] = (v.buffer + 1) % (d->num_desc - 1);
1088 }
1089 d->last_buffer = next_prg;
1090 reprogram_dma_it_prg(d, d->last_buffer, v.buffer);
1091 d->next_buffer[d->last_buffer] = -1;
1092
1093 d->it_prg[d->last_buffer][d->last_used_cmd[d->last_buffer]].end.branchAddress = 0;
1094
1095 spin_unlock_irqrestore(&d->lock,flags);
1096
1097 if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
1098 {
1099 DBGMSG(ohci->host->id, "Starting iso transmit DMA ctx=%d",
1100 d->ctx);
1101 put_timestamp(ohci, d, d->last_buffer);
1102 dma_region_sync_for_device(&d->dma,
1103 v.buffer * d->buf_size, d->buf_size);
1104
1105 /* Tell the controller where the first program is */
1106 reg_write(ohci, d->cmdPtr,
1107 dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0) | 0x3);
1108
1109 /* Run IT context */
1110 reg_write(ohci, d->ctrlSet, 0x8000);
1111 }
1112 else {
1113 /* Wake up dma context if necessary */
1114 if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
1115 DBGMSG(ohci->host->id,
1116 "Waking up iso transmit dma ctx=%d",
1117 d->ctx);
1118 put_timestamp(ohci, d, d->last_buffer);
1119 dma_region_sync_for_device(&d->dma,
1120 v.buffer * d->buf_size, d->buf_size);
1121
1122 reg_write(ohci, d->ctrlSet, 0x1000);
1123 }
1124 }
1125
1126 kfree(psizes);
1127 return 0;
1128
1129 }
1130 case VIDEO1394_IOC_TALK_WAIT_BUFFER:
1131 {
1132 struct video1394_wait v;
1133 struct dma_iso_ctx *d;
1134
1135 if (copy_from_user(&v, argp, sizeof(v)))
1136 return -EFAULT;
1137
1138 d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
1139 if (d == NULL) return -EFAULT;
1140
1141 if (v.buffer >= d->num_desc - 1) {
1142 PRINT(KERN_ERR, ohci->host->id,
1143 "Buffer %d out of range",v.buffer);
1144 return -EINVAL;
1145 }
1146
1147 switch(d->buffer_status[v.buffer]) {
1148 case VIDEO1394_BUFFER_READY:
1149 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
1150 return 0;
1151 case VIDEO1394_BUFFER_QUEUED:
1152 wait_event_interruptible(d->waitq,
1153 (d->buffer_status[v.buffer] == VIDEO1394_BUFFER_READY));
1154 if (signal_pending(current))
1155 return -EINTR;
1156 d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
1157 return 0;
1158 default:
1159 PRINT(KERN_ERR, ohci->host->id,
1160 "Buffer %d is not queued",v.buffer);
1161 return -ESRCH;
1162 }
1163 }
1164 default:
1165 return -ENOTTY;
1166 }
1167 }
1168
1169 /*
1170 * This maps the vmalloced and reserved buffer to user space.
1171 *
1172 * FIXME:
1173 * - PAGE_READONLY should suffice!?
1174 * - remap_pfn_range is kind of inefficient for page by page remapping.
1175 * But e.g. pte_alloc() does not work in modules ... :-(
1176 */
1177
1178 static int video1394_mmap(struct file *file, struct vm_area_struct *vma)
1179 {
1180 struct file_ctx *ctx = (struct file_ctx *)file->private_data;
1181
1182 if (ctx->current_ctx == NULL) {
1183 PRINT(KERN_ERR, ctx->ohci->host->id,
1184 "Current iso context not set");
1185 return -EINVAL;
1186 }
1187
1188 return dma_region_mmap(&ctx->current_ctx->dma, file, vma);
1189 }
1190
1191 static unsigned int video1394_poll(struct file *file, poll_table *pt)
1192 {
1193 struct file_ctx *ctx;
1194 unsigned int mask = 0;
1195 unsigned long flags;
1196 struct dma_iso_ctx *d;
1197 int i;
1198
1199 ctx = file->private_data;
1200 d = ctx->current_ctx;
1201 if (d == NULL) {
1202 PRINT(KERN_ERR, ctx->ohci->host->id,
1203 "Current iso context not set");
1204 return POLLERR;
1205 }
1206
1207 poll_wait(file, &d->waitq, pt);
1208
1209 spin_lock_irqsave(&d->lock, flags);
1210 for (i = 0; i < d->num_desc; i++) {
1211 if (d->buffer_status[i] == VIDEO1394_BUFFER_READY) {
1212 mask |= POLLIN | POLLRDNORM;
1213 break;
1214 }
1215 }
1216 spin_unlock_irqrestore(&d->lock, flags);
1217
1218 return mask;
1219 }
1220
1221 static int video1394_open(struct inode *inode, struct file *file)
1222 {
1223 int i = ieee1394_file_to_instance(file);
1224 struct ti_ohci *ohci;
1225 struct file_ctx *ctx;
1226
1227 ohci = hpsb_get_hostinfo_bykey(&video1394_highlevel, i);
1228 if (ohci == NULL)
1229 return -EIO;
1230
1231 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
1232 if (!ctx) {
1233 PRINT(KERN_ERR, ohci->host->id, "Cannot malloc file_ctx");
1234 return -ENOMEM;
1235 }
1236
1237 ctx->ohci = ohci;
1238 INIT_LIST_HEAD(&ctx->context_list);
1239 ctx->current_ctx = NULL;
1240 file->private_data = ctx;
1241
1242 return 0;
1243 }
1244
1245 static int video1394_release(struct inode *inode, struct file *file)
1246 {
1247 struct file_ctx *ctx = (struct file_ctx *)file->private_data;
1248 struct ti_ohci *ohci = ctx->ohci;
1249 struct list_head *lh, *next;
1250 u64 mask;
1251
1252 list_for_each_safe(lh, next, &ctx->context_list) {
1253 struct dma_iso_ctx *d;
1254 d = list_entry(lh, struct dma_iso_ctx, link);
1255 mask = (u64) 1 << d->channel;
1256
1257 if (!(ohci->ISO_channel_usage & mask))
1258 PRINT(KERN_ERR, ohci->host->id, "On release: Channel %d "
1259 "is not being used", d->channel);
1260 else
1261 ohci->ISO_channel_usage &= ~mask;
1262 DBGMSG(ohci->host->id, "On release: Iso %s context "
1263 "%d stop listening on channel %d",
1264 d->type == OHCI_ISO_RECEIVE ? "receive" : "transmit",
1265 d->ctx, d->channel);
1266 free_dma_iso_ctx(d);
1267 }
1268
1269 kfree(ctx);
1270 file->private_data = NULL;
1271
1272 return 0;
1273 }
1274
1275 #ifdef CONFIG_COMPAT
1276 static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg);
1277 #endif
1278
1279 static struct cdev video1394_cdev;
1280 static const struct file_operations video1394_fops=
1281 {
1282 .owner = THIS_MODULE,
1283 .unlocked_ioctl = video1394_ioctl,
1284 #ifdef CONFIG_COMPAT
1285 .compat_ioctl = video1394_compat_ioctl,
1286 #endif
1287 .poll = video1394_poll,
1288 .mmap = video1394_mmap,
1289 .open = video1394_open,
1290 .release = video1394_release
1291 };
1292
1293 /*** HOTPLUG STUFF **********************************************************/
1294 /*
1295 * Export information about protocols/devices supported by this driver.
1296 */
1297 #ifdef MODULE
1298 static const struct ieee1394_device_id video1394_id_table[] = {
1299 {
1300 .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
1301 .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
1302 .version = CAMERA_SW_VERSION_ENTRY & 0xffffff
1303 },
1304 {
1305 .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
1306 .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
1307 .version = (CAMERA_SW_VERSION_ENTRY + 1) & 0xffffff
1308 },
1309 {
1310 .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
1311 .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
1312 .version = (CAMERA_SW_VERSION_ENTRY + 2) & 0xffffff
1313 },
1314 { }
1315 };
1316
1317 MODULE_DEVICE_TABLE(ieee1394, video1394_id_table);
1318 #endif /* MODULE */
1319
1320 static struct hpsb_protocol_driver video1394_driver = {
1321 .name = VIDEO1394_DRIVER_NAME,
1322 };
1323
1324
1325 static void video1394_add_host (struct hpsb_host *host)
1326 {
1327 struct ti_ohci *ohci;
1328 int minor;
1329
1330 /* We only work with the OHCI-1394 driver */
1331 if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME))
1332 return;
1333
1334 ohci = (struct ti_ohci *)host->hostdata;
1335
1336 if (!hpsb_create_hostinfo(&video1394_highlevel, host, 0)) {
1337 PRINT(KERN_ERR, ohci->host->id, "Cannot allocate hostinfo");
1338 return;
1339 }
1340
1341 hpsb_set_hostinfo(&video1394_highlevel, host, ohci);
1342 hpsb_set_hostinfo_key(&video1394_highlevel, host, ohci->host->id);
1343
1344 minor = IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id;
1345 device_create(hpsb_protocol_class, NULL, MKDEV(IEEE1394_MAJOR, minor),
1346 NULL, "%s-%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
1347 }
1348
1349
1350 static void video1394_remove_host (struct hpsb_host *host)
1351 {
1352 struct ti_ohci *ohci = hpsb_get_hostinfo(&video1394_highlevel, host);
1353
1354 if (ohci)
1355 device_destroy(hpsb_protocol_class, MKDEV(IEEE1394_MAJOR,
1356 IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id));
1357 return;
1358 }
1359
1360
1361 static struct hpsb_highlevel video1394_highlevel = {
1362 .name = VIDEO1394_DRIVER_NAME,
1363 .add_host = video1394_add_host,
1364 .remove_host = video1394_remove_host,
1365 };
1366
1367 MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
1368 MODULE_DESCRIPTION("driver for digital video on OHCI board");
1369 MODULE_SUPPORTED_DEVICE(VIDEO1394_DRIVER_NAME);
1370 MODULE_LICENSE("GPL");
1371
1372 #ifdef CONFIG_COMPAT
1373
1374 #define VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER \
1375 _IOW ('#', 0x12, struct video1394_wait32)
1376 #define VIDEO1394_IOC32_LISTEN_WAIT_BUFFER \
1377 _IOWR('#', 0x13, struct video1394_wait32)
1378 #define VIDEO1394_IOC32_TALK_WAIT_BUFFER \
1379 _IOW ('#', 0x17, struct video1394_wait32)
1380 #define VIDEO1394_IOC32_LISTEN_POLL_BUFFER \
1381 _IOWR('#', 0x18, struct video1394_wait32)
1382
1383 struct video1394_wait32 {
1384 u32 channel;
1385 u32 buffer;
1386 struct compat_timeval filltime;
1387 };
1388
1389 static int video1394_wr_wait32(struct file *file, unsigned int cmd, unsigned long arg)
1390 {
1391 struct video1394_wait32 __user *argp = (void __user *)arg;
1392 struct video1394_wait32 wait32;
1393 struct video1394_wait wait;
1394 mm_segment_t old_fs;
1395 int ret;
1396
1397 if (copy_from_user(&wait32, argp, sizeof(wait32)))
1398 return -EFAULT;
1399
1400 wait.channel = wait32.channel;
1401 wait.buffer = wait32.buffer;
1402 wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
1403 wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
1404
1405 old_fs = get_fs();
1406 set_fs(KERNEL_DS);
1407 if (cmd == VIDEO1394_IOC32_LISTEN_WAIT_BUFFER)
1408 ret = video1394_ioctl(file,
1409 VIDEO1394_IOC_LISTEN_WAIT_BUFFER,
1410 (unsigned long) &wait);
1411 else
1412 ret = video1394_ioctl(file,
1413 VIDEO1394_IOC_LISTEN_POLL_BUFFER,
1414 (unsigned long) &wait);
1415 set_fs(old_fs);
1416
1417 if (!ret) {
1418 wait32.channel = wait.channel;
1419 wait32.buffer = wait.buffer;
1420 wait32.filltime.tv_sec = (int)wait.filltime.tv_sec;
1421 wait32.filltime.tv_usec = (int)wait.filltime.tv_usec;
1422
1423 if (copy_to_user(argp, &wait32, sizeof(wait32)))
1424 ret = -EFAULT;
1425 }
1426
1427 return ret;
1428 }
1429
1430 static int video1394_w_wait32(struct file *file, unsigned int cmd, unsigned long arg)
1431 {
1432 struct video1394_wait32 wait32;
1433 struct video1394_wait wait;
1434 mm_segment_t old_fs;
1435 int ret;
1436
1437 if (copy_from_user(&wait32, (void __user *)arg, sizeof(wait32)))
1438 return -EFAULT;
1439
1440 wait.channel = wait32.channel;
1441 wait.buffer = wait32.buffer;
1442 wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
1443 wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
1444
1445 old_fs = get_fs();
1446 set_fs(KERNEL_DS);
1447 if (cmd == VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER)
1448 ret = video1394_ioctl(file,
1449 VIDEO1394_IOC_LISTEN_QUEUE_BUFFER,
1450 (unsigned long) &wait);
1451 else
1452 ret = video1394_ioctl(file,
1453 VIDEO1394_IOC_TALK_WAIT_BUFFER,
1454 (unsigned long) &wait);
1455 set_fs(old_fs);
1456
1457 return ret;
1458 }
1459
1460 static int video1394_queue_buf32(struct file *file, unsigned int cmd, unsigned long arg)
1461 {
1462 return -EFAULT; /* ??? was there before. */
1463
1464 return video1394_ioctl(file,
1465 VIDEO1394_IOC_TALK_QUEUE_BUFFER, arg);
1466 }
1467
1468 static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg)
1469 {
1470 switch (cmd) {
1471 case VIDEO1394_IOC_LISTEN_CHANNEL:
1472 case VIDEO1394_IOC_UNLISTEN_CHANNEL:
1473 case VIDEO1394_IOC_TALK_CHANNEL:
1474 case VIDEO1394_IOC_UNTALK_CHANNEL:
1475 return video1394_ioctl(f, cmd, arg);
1476
1477 case VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER:
1478 return video1394_w_wait32(f, cmd, arg);
1479 case VIDEO1394_IOC32_LISTEN_WAIT_BUFFER:
1480 return video1394_wr_wait32(f, cmd, arg);
1481 case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
1482 return video1394_queue_buf32(f, cmd, arg);
1483 case VIDEO1394_IOC32_TALK_WAIT_BUFFER:
1484 return video1394_w_wait32(f, cmd, arg);
1485 case VIDEO1394_IOC32_LISTEN_POLL_BUFFER:
1486 return video1394_wr_wait32(f, cmd, arg);
1487 default:
1488 return -ENOIOCTLCMD;
1489 }
1490 }
1491
1492 #endif /* CONFIG_COMPAT */
1493
1494 static void __exit video1394_exit_module (void)
1495 {
1496 hpsb_unregister_protocol(&video1394_driver);
1497 hpsb_unregister_highlevel(&video1394_highlevel);
1498 cdev_del(&video1394_cdev);
1499 PRINT_G(KERN_INFO, "Removed " VIDEO1394_DRIVER_NAME " module");
1500 }
1501
1502 static int __init video1394_init_module (void)
1503 {
1504 int ret;
1505
1506 hpsb_init_highlevel(&video1394_highlevel);
1507
1508 cdev_init(&video1394_cdev, &video1394_fops);
1509 video1394_cdev.owner = THIS_MODULE;
1510 ret = cdev_add(&video1394_cdev, IEEE1394_VIDEO1394_DEV, 16);
1511 if (ret) {
1512 PRINT_G(KERN_ERR, "video1394: unable to get minor device block");
1513 return ret;
1514 }
1515
1516 hpsb_register_highlevel(&video1394_highlevel);
1517
1518 ret = hpsb_register_protocol(&video1394_driver);
1519 if (ret) {
1520 PRINT_G(KERN_ERR, "video1394: failed to register protocol");
1521 hpsb_unregister_highlevel(&video1394_highlevel);
1522 cdev_del(&video1394_cdev);
1523 return ret;
1524 }
1525
1526 PRINT_G(KERN_INFO, "Installed " VIDEO1394_DRIVER_NAME " module");
1527 return 0;
1528 }
1529
1530
1531 module_init(video1394_init_module);
1532 module_exit(video1394_exit_module);
Linux with added FPC-III support