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x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / infiniband / hw / nes / nes_utils.c
blob9687c397ce1ac7480e36692a022d358258ae3c51
1 /*
2 * Copyright (c) 2006 - 2009 Intel-NE, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/ethtool.h>
39 #include <linux/mii.h>
40 #include <linux/if_vlan.h>
41 #include <linux/crc32.h>
42 #include <linux/in.h>
43 #include <linux/ip.h>
44 #include <linux/tcp.h>
45 #include <linux/init.h>
46
47 #include <asm/io.h>
48 #include <asm/irq.h>
49 #include <asm/byteorder.h>
50
51 #include "nes.h"
52
53
54
55 static u16 nes_read16_eeprom(void __iomem *addr, u16 offset);
56
57 u32 mh_detected;
58 u32 mh_pauses_sent;
59
60 /**
61 * nes_read_eeprom_values -
62 */
63 int nes_read_eeprom_values(struct nes_device *nesdev, struct nes_adapter *nesadapter)
64 {
65 u32 mac_addr_low;
66 u16 mac_addr_high;
67 u16 eeprom_data;
68 u16 eeprom_offset;
69 u16 next_section_address;
70 u16 sw_section_ver;
71 u8 major_ver = 0;
72 u8 minor_ver = 0;
73
74 /* TODO: deal with EEPROM endian issues */
75 if (nesadapter->firmware_eeprom_offset == 0) {
76 /* Read the EEPROM Parameters */
77 eeprom_data = nes_read16_eeprom(nesdev->regs, 0);
78 nes_debug(NES_DBG_HW, "EEPROM Offset 0 = 0x%04X\n", eeprom_data);
79 eeprom_offset = 2 + (((eeprom_data & 0x007f) << 3) <<
80 ((eeprom_data & 0x0080) >> 7));
81 nes_debug(NES_DBG_HW, "Firmware Offset = 0x%04X\n", eeprom_offset);
82 nesadapter->firmware_eeprom_offset = eeprom_offset;
83 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
84 if (eeprom_data != 0x5746) {
85 nes_debug(NES_DBG_HW, "Not a valid Firmware Image = 0x%04X\n", eeprom_data);
86 return -1;
87 }
88
89 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
90 nes_debug(NES_DBG_HW, "EEPROM Offset %u = 0x%04X\n",
91 eeprom_offset + 2, eeprom_data);
92 eeprom_offset += ((eeprom_data & 0x00ff) << 3) << ((eeprom_data & 0x0100) >> 8);
93 nes_debug(NES_DBG_HW, "Software Offset = 0x%04X\n", eeprom_offset);
94 nesadapter->software_eeprom_offset = eeprom_offset;
95 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
96 if (eeprom_data != 0x5753) {
97 printk("Not a valid Software Image = 0x%04X\n", eeprom_data);
98 return -1;
99 }
100 sw_section_ver = nes_read16_eeprom(nesdev->regs, nesadapter->software_eeprom_offset + 6);
101 nes_debug(NES_DBG_HW, "Software section version number = 0x%04X\n",
102 sw_section_ver);
103
104 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
105 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
106 eeprom_offset + 2, eeprom_data);
107 next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
108 ((eeprom_data & 0x0100) >> 8));
109 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
110 if (eeprom_data != 0x414d) {
111 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
112 eeprom_data);
113 goto no_fw_rev;
114 }
115 eeprom_offset = next_section_address;
116
117 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
118 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
119 eeprom_offset + 2, eeprom_data);
120 next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
121 ((eeprom_data & 0x0100) >> 8));
122 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
123 if (eeprom_data != 0x4f52) {
124 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x4f52 but was 0x%04X\n",
125 eeprom_data);
126 goto no_fw_rev;
127 }
128 eeprom_offset = next_section_address;
129
130 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
131 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
132 eeprom_offset + 2, eeprom_data);
133 next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
134 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
135 if (eeprom_data != 0x5746) {
136 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5746 but was 0x%04X\n",
137 eeprom_data);
138 goto no_fw_rev;
139 }
140 eeprom_offset = next_section_address;
141
142 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
143 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
144 eeprom_offset + 2, eeprom_data);
145 next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
146 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
147 if (eeprom_data != 0x5753) {
148 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5753 but was 0x%04X\n",
149 eeprom_data);
150 goto no_fw_rev;
151 }
152 eeprom_offset = next_section_address;
153
154 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
155 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
156 eeprom_offset + 2, eeprom_data);
157 next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
158 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
159 if (eeprom_data != 0x414d) {
160 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
161 eeprom_data);
162 goto no_fw_rev;
163 }
164 eeprom_offset = next_section_address;
165
166 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
167 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
168 eeprom_offset + 2, eeprom_data);
169 next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
170 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
171 if (eeprom_data != 0x464e) {
172 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x464e but was 0x%04X\n",
173 eeprom_data);
174 goto no_fw_rev;
175 }
176 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 8);
177 printk(PFX "Firmware version %u.%u\n", (u8)(eeprom_data>>8), (u8)eeprom_data);
178 major_ver = (u8)(eeprom_data >> 8);
179 minor_ver = (u8)(eeprom_data);
180
181 if (nes_drv_opt & NES_DRV_OPT_DISABLE_VIRT_WQ) {
182 nes_debug(NES_DBG_HW, "Virtual WQs have been disabled\n");
183 } else if (((major_ver == 2) && (minor_ver > 21)) || ((major_ver > 2) && (major_ver != 255))) {
184 nesadapter->virtwq = 1;
185 }
186 if (((major_ver == 3) && (minor_ver >= 16)) || (major_ver > 3))
187 nesadapter->send_term_ok = 1;
188
189 nesadapter->firmware_version = (((u32)(u8)(eeprom_data>>8)) << 16) +
190 (u32)((u8)eeprom_data);
191
192 no_fw_rev:
193 /* eeprom is valid */
194 eeprom_offset = nesadapter->software_eeprom_offset;
195 eeprom_offset += 8;
196 nesadapter->netdev_max = (u8)nes_read16_eeprom(nesdev->regs, eeprom_offset);
197 eeprom_offset += 2;
198 mac_addr_high = nes_read16_eeprom(nesdev->regs, eeprom_offset);
199 eeprom_offset += 2;
200 mac_addr_low = (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
201 eeprom_offset += 2;
202 mac_addr_low <<= 16;
203 mac_addr_low += (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
204 nes_debug(NES_DBG_HW, "Base MAC Address = 0x%04X%08X\n",
205 mac_addr_high, mac_addr_low);
206 nes_debug(NES_DBG_HW, "MAC Address count = %u\n", nesadapter->netdev_max);
207
208 nesadapter->mac_addr_low = mac_addr_low;
209 nesadapter->mac_addr_high = mac_addr_high;
210
211 /* Read the Phy Type array */
212 eeprom_offset += 10;
213 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
214 nesadapter->phy_type[0] = (u8)(eeprom_data >> 8);
215 nesadapter->phy_type[1] = (u8)eeprom_data;
216
217 /* Read the port array */
218 eeprom_offset += 2;
219 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
220 nesadapter->phy_type[2] = (u8)(eeprom_data >> 8);
221 nesadapter->phy_type[3] = (u8)eeprom_data;
222 /* port_count is set by soft reset reg */
223 nes_debug(NES_DBG_HW, "port_count = %u, port 0 -> %u, port 1 -> %u,"
224 " port 2 -> %u, port 3 -> %u\n",
225 nesadapter->port_count,
226 nesadapter->phy_type[0], nesadapter->phy_type[1],
227 nesadapter->phy_type[2], nesadapter->phy_type[3]);
228
229 /* Read PD config array */
230 eeprom_offset += 10;
231 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
232 nesadapter->pd_config_size[0] = eeprom_data;
233 eeprom_offset += 2;
234 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
235 nesadapter->pd_config_base[0] = eeprom_data;
236 nes_debug(NES_DBG_HW, "PD0 config, size=0x%04x, base=0x%04x\n",
237 nesadapter->pd_config_size[0], nesadapter->pd_config_base[0]);
238
239 eeprom_offset += 2;
240 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
241 nesadapter->pd_config_size[1] = eeprom_data;
242 eeprom_offset += 2;
243 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
244 nesadapter->pd_config_base[1] = eeprom_data;
245 nes_debug(NES_DBG_HW, "PD1 config, size=0x%04x, base=0x%04x\n",
246 nesadapter->pd_config_size[1], nesadapter->pd_config_base[1]);
247
248 eeprom_offset += 2;
249 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
250 nesadapter->pd_config_size[2] = eeprom_data;
251 eeprom_offset += 2;
252 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
253 nesadapter->pd_config_base[2] = eeprom_data;
254 nes_debug(NES_DBG_HW, "PD2 config, size=0x%04x, base=0x%04x\n",
255 nesadapter->pd_config_size[2], nesadapter->pd_config_base[2]);
256
257 eeprom_offset += 2;
258 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
259 nesadapter->pd_config_size[3] = eeprom_data;
260 eeprom_offset += 2;
261 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
262 nesadapter->pd_config_base[3] = eeprom_data;
263 nes_debug(NES_DBG_HW, "PD3 config, size=0x%04x, base=0x%04x\n",
264 nesadapter->pd_config_size[3], nesadapter->pd_config_base[3]);
265
266 /* Read Rx Pool Size */
267 eeprom_offset += 22; /* 46 */
268 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
269 eeprom_offset += 2;
270 nesadapter->rx_pool_size = (((u32)eeprom_data) << 16) +
271 nes_read16_eeprom(nesdev->regs, eeprom_offset);
272 nes_debug(NES_DBG_HW, "rx_pool_size = 0x%08X\n", nesadapter->rx_pool_size);
273
274 eeprom_offset += 2;
275 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
276 eeprom_offset += 2;
277 nesadapter->tx_pool_size = (((u32)eeprom_data) << 16) +
278 nes_read16_eeprom(nesdev->regs, eeprom_offset);
279 nes_debug(NES_DBG_HW, "tx_pool_size = 0x%08X\n", nesadapter->tx_pool_size);
280
281 eeprom_offset += 2;
282 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
283 eeprom_offset += 2;
284 nesadapter->rx_threshold = (((u32)eeprom_data) << 16) +
285 nes_read16_eeprom(nesdev->regs, eeprom_offset);
286 nes_debug(NES_DBG_HW, "rx_threshold = 0x%08X\n", nesadapter->rx_threshold);
287
288 eeprom_offset += 2;
289 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
290 eeprom_offset += 2;
291 nesadapter->tcp_timer_core_clk_divisor = (((u32)eeprom_data) << 16) +
292 nes_read16_eeprom(nesdev->regs, eeprom_offset);
293 nes_debug(NES_DBG_HW, "tcp_timer_core_clk_divisor = 0x%08X\n",
294 nesadapter->tcp_timer_core_clk_divisor);
295
296 eeprom_offset += 2;
297 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
298 eeprom_offset += 2;
299 nesadapter->iwarp_config = (((u32)eeprom_data) << 16) +
300 nes_read16_eeprom(nesdev->regs, eeprom_offset);
301 nes_debug(NES_DBG_HW, "iwarp_config = 0x%08X\n", nesadapter->iwarp_config);
302
303 eeprom_offset += 2;
304 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
305 eeprom_offset += 2;
306 nesadapter->cm_config = (((u32)eeprom_data) << 16) +
307 nes_read16_eeprom(nesdev->regs, eeprom_offset);
308 nes_debug(NES_DBG_HW, "cm_config = 0x%08X\n", nesadapter->cm_config);
309
310 eeprom_offset += 2;
311 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
312 eeprom_offset += 2;
313 nesadapter->sws_timer_config = (((u32)eeprom_data) << 16) +
314 nes_read16_eeprom(nesdev->regs, eeprom_offset);
315 nes_debug(NES_DBG_HW, "sws_timer_config = 0x%08X\n", nesadapter->sws_timer_config);
316
317 eeprom_offset += 2;
318 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
319 eeprom_offset += 2;
320 nesadapter->tcp_config1 = (((u32)eeprom_data) << 16) +
321 nes_read16_eeprom(nesdev->regs, eeprom_offset);
322 nes_debug(NES_DBG_HW, "tcp_config1 = 0x%08X\n", nesadapter->tcp_config1);
323
324 eeprom_offset += 2;
325 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
326 eeprom_offset += 2;
327 nesadapter->wqm_wat = (((u32)eeprom_data) << 16) +
328 nes_read16_eeprom(nesdev->regs, eeprom_offset);
329 nes_debug(NES_DBG_HW, "wqm_wat = 0x%08X\n", nesadapter->wqm_wat);
330
331 eeprom_offset += 2;
332 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
333 eeprom_offset += 2;
334 nesadapter->core_clock = (((u32)eeprom_data) << 16) +
335 nes_read16_eeprom(nesdev->regs, eeprom_offset);
336 nes_debug(NES_DBG_HW, "core_clock = 0x%08X\n", nesadapter->core_clock);
337
338 if ((sw_section_ver) && (nesadapter->hw_rev != NE020_REV)) {
339 eeprom_offset += 2;
340 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
341 nesadapter->phy_index[0] = (eeprom_data & 0xff00)>>8;
342 nesadapter->phy_index[1] = eeprom_data & 0x00ff;
343 eeprom_offset += 2;
344 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
345 nesadapter->phy_index[2] = (eeprom_data & 0xff00)>>8;
346 nesadapter->phy_index[3] = eeprom_data & 0x00ff;
347 } else {
348 nesadapter->phy_index[0] = 4;
349 nesadapter->phy_index[1] = 5;
350 nesadapter->phy_index[2] = 6;
351 nesadapter->phy_index[3] = 7;
352 }
353 nes_debug(NES_DBG_HW, "Phy address map = 0 > %u, 1 > %u, 2 > %u, 3 > %u\n",
354 nesadapter->phy_index[0],nesadapter->phy_index[1],
355 nesadapter->phy_index[2],nesadapter->phy_index[3]);
356 }
357
358 return 0;
359 }
360
361
362 /**
363 * nes_read16_eeprom
364 */
365 static u16 nes_read16_eeprom(void __iomem *addr, u16 offset)
366 {
367 writel(NES_EEPROM_READ_REQUEST + (offset >> 1),
368 (void __iomem *)addr + NES_EEPROM_COMMAND);
369
370 do {
371 } while (readl((void __iomem *)addr + NES_EEPROM_COMMAND) &
372 NES_EEPROM_READ_REQUEST);
373
374 return readw((void __iomem *)addr + NES_EEPROM_DATA);
375 }
376
377
378 /**
379 * nes_write_1G_phy_reg
380 */
381 void nes_write_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 data)
382 {
383 struct nes_adapter *nesadapter = nesdev->nesadapter;
384 u32 u32temp;
385 u32 counter;
386 unsigned long flags;
387
388 spin_lock_irqsave(&nesadapter->phy_lock, flags);
389
390 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
391 0x50020000 | data | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
392 for (counter = 0; counter < 100 ; counter++) {
393 udelay(30);
394 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
395 if (u32temp & 1) {
396 /* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
397 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
398 break;
399 }
400 }
401 if (!(u32temp & 1))
402 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
403 u32temp);
404
405 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
406 }
407
408
409 /**
410 * nes_read_1G_phy_reg
411 * This routine only issues the read, the data must be read
412 * separately.
413 */
414 void nes_read_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 *data)
415 {
416 struct nes_adapter *nesadapter = nesdev->nesadapter;
417 u32 u32temp;
418 u32 counter;
419 unsigned long flags;
420
421 /* nes_debug(NES_DBG_PHY, "phy addr = %d, mac_index = %d\n",
422 phy_addr, nesdev->mac_index); */
423 spin_lock_irqsave(&nesadapter->phy_lock, flags);
424
425 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
426 0x60020000 | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
427 for (counter = 0; counter < 100 ; counter++) {
428 udelay(30);
429 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
430 if (u32temp & 1) {
431 /* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
432 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
433 break;
434 }
435 }
436 if (!(u32temp & 1)) {
437 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
438 u32temp);
439 *data = 0xffff;
440 } else {
441 *data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
442 }
443 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
444 }
445
446
447 /**
448 * nes_write_10G_phy_reg
449 */
450 void nes_write_10G_phy_reg(struct nes_device *nesdev, u16 phy_addr, u8 dev_addr, u16 phy_reg,
451 u16 data)
452 {
453 u32 port_addr;
454 u32 u32temp;
455 u32 counter;
456
457 port_addr = phy_addr;
458
459 /* set address */
460 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
461 0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
462 for (counter = 0; counter < 100 ; counter++) {
463 udelay(30);
464 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
465 if (u32temp & 1) {
466 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
467 break;
468 }
469 }
470 if (!(u32temp & 1))
471 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
472 u32temp);
473
474 /* set data */
475 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
476 0x10020000 | (u32)data | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
477 for (counter = 0; counter < 100 ; counter++) {
478 udelay(30);
479 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
480 if (u32temp & 1) {
481 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
482 break;
483 }
484 }
485 if (!(u32temp & 1))
486 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
487 u32temp);
488 }
489
490
491 /**
492 * nes_read_10G_phy_reg
493 * This routine only issues the read, the data must be read
494 * separately.
495 */
496 void nes_read_10G_phy_reg(struct nes_device *nesdev, u8 phy_addr, u8 dev_addr, u16 phy_reg)
497 {
498 u32 port_addr;
499 u32 u32temp;
500 u32 counter;
501
502 port_addr = phy_addr;
503
504 /* set address */
505 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
506 0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
507 for (counter = 0; counter < 100 ; counter++) {
508 udelay(30);
509 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
510 if (u32temp & 1) {
511 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
512 break;
513 }
514 }
515 if (!(u32temp & 1))
516 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
517 u32temp);
518
519 /* issue read */
520 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
521 0x30020000 | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
522 for (counter = 0; counter < 100 ; counter++) {
523 udelay(30);
524 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
525 if (u32temp & 1) {
526 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
527 break;
528 }
529 }
530 if (!(u32temp & 1))
531 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
532 u32temp);
533 }
534
535
536 /**
537 * nes_get_cqp_request
538 */
539 struct nes_cqp_request *nes_get_cqp_request(struct nes_device *nesdev)
540 {
541 unsigned long flags;
542 struct nes_cqp_request *cqp_request = NULL;
543
544 if (!list_empty(&nesdev->cqp_avail_reqs)) {
545 spin_lock_irqsave(&nesdev->cqp.lock, flags);
546 if (!list_empty(&nesdev->cqp_avail_reqs)) {
547 cqp_request = list_entry(nesdev->cqp_avail_reqs.next,
548 struct nes_cqp_request, list);
549 list_del_init(&cqp_request->list);
550 }
551 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
552 }
553 if (cqp_request == NULL) {
554 cqp_request = kzalloc(sizeof(struct nes_cqp_request), GFP_ATOMIC);
555 if (cqp_request) {
556 cqp_request->dynamic = 1;
557 INIT_LIST_HEAD(&cqp_request->list);
558 }
559 }
560
561 if (cqp_request) {
562 init_waitqueue_head(&cqp_request->waitq);
563 cqp_request->waiting = 0;
564 cqp_request->request_done = 0;
565 cqp_request->callback = 0;
566 init_waitqueue_head(&cqp_request->waitq);
567 nes_debug(NES_DBG_CQP, "Got cqp request %p from the available list \n",
568 cqp_request);
569 } else
570 printk(KERN_ERR PFX "%s: Could not allocated a CQP request.\n",
571 __func__);
572
573 return cqp_request;
574 }
575
576 void nes_free_cqp_request(struct nes_device *nesdev,
577 struct nes_cqp_request *cqp_request)
578 {
579 unsigned long flags;
580
581 nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X) freed.\n",
582 cqp_request,
583 le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX]) & 0x3f);
584
585 if (cqp_request->dynamic) {
586 kfree(cqp_request);
587 } else {
588 spin_lock_irqsave(&nesdev->cqp.lock, flags);
589 list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
590 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
591 }
592 }
593
594 void nes_put_cqp_request(struct nes_device *nesdev,
595 struct nes_cqp_request *cqp_request)
596 {
597 if (atomic_dec_and_test(&cqp_request->refcount))
598 nes_free_cqp_request(nesdev, cqp_request);
599 }
600
601 /**
602 * nes_post_cqp_request
603 */
604 void nes_post_cqp_request(struct nes_device *nesdev,
605 struct nes_cqp_request *cqp_request)
606 {
607 struct nes_hw_cqp_wqe *cqp_wqe;
608 unsigned long flags;
609 u32 cqp_head;
610 u64 u64temp;
611
612 spin_lock_irqsave(&nesdev->cqp.lock, flags);
613
614 if (((((nesdev->cqp.sq_tail+(nesdev->cqp.sq_size*2))-nesdev->cqp.sq_head) &
615 (nesdev->cqp.sq_size - 1)) != 1)
616 && (list_empty(&nesdev->cqp_pending_reqs))) {
617 cqp_head = nesdev->cqp.sq_head++;
618 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
619 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
620 memcpy(cqp_wqe, &cqp_request->cqp_wqe, sizeof(*cqp_wqe));
621 barrier();
622 u64temp = (unsigned long)cqp_request;
623 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_COMP_SCRATCH_LOW_IDX,
624 u64temp);
625 nes_debug(NES_DBG_CQP, "CQP request (opcode 0x%02X), line 1 = 0x%08X put on CQPs SQ,"
626 " request = %p, cqp_head = %u, cqp_tail = %u, cqp_size = %u,"
627 " waiting = %d, refcount = %d.\n",
628 le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f,
629 le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX]), cqp_request,
630 nesdev->cqp.sq_head, nesdev->cqp.sq_tail, nesdev->cqp.sq_size,
631 cqp_request->waiting, atomic_read(&cqp_request->refcount));
632 barrier();
633
634 /* Ring doorbell (1 WQEs) */
635 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x01800000 | nesdev->cqp.qp_id);
636
637 barrier();
638 } else {
639 nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X), line 1 = 0x%08X"
640 " put on the pending queue.\n",
641 cqp_request,
642 le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f,
643 le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_ID_IDX]));
644 list_add_tail(&cqp_request->list, &nesdev->cqp_pending_reqs);
645 }
646
647 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
648
649 return;
650 }
651
652
653 /**
654 * nes_arp_table
655 */
656 int nes_arp_table(struct nes_device *nesdev, u32 ip_addr, u8 *mac_addr, u32 action)
657 {
658 struct nes_adapter *nesadapter = nesdev->nesadapter;
659 int arp_index;
660 int err = 0;
661 __be32 tmp_addr;
662
663 for (arp_index = 0; (u32) arp_index < nesadapter->arp_table_size; arp_index++) {
664 if (nesadapter->arp_table[arp_index].ip_addr == ip_addr)
665 break;
666 }
667
668 if (action == NES_ARP_ADD) {
669 if (arp_index != nesadapter->arp_table_size) {
670 return -1;
671 }
672
673 arp_index = 0;
674 err = nes_alloc_resource(nesadapter, nesadapter->allocated_arps,
675 nesadapter->arp_table_size, (u32 *)&arp_index, &nesadapter->next_arp_index);
676 if (err) {
677 nes_debug(NES_DBG_NETDEV, "nes_alloc_resource returned error = %u\n", err);
678 return err;
679 }
680 nes_debug(NES_DBG_NETDEV, "ADD, arp_index=%d\n", arp_index);
681
682 nesadapter->arp_table[arp_index].ip_addr = ip_addr;
683 memcpy(nesadapter->arp_table[arp_index].mac_addr, mac_addr, ETH_ALEN);
684 return arp_index;
685 }
686
687 /* DELETE or RESOLVE */
688 if (arp_index == nesadapter->arp_table_size) {
689 tmp_addr = cpu_to_be32(ip_addr);
690 nes_debug(NES_DBG_NETDEV, "MAC for %pI4 not in ARP table - cannot %s\n",
691 &tmp_addr, action == NES_ARP_RESOLVE ? "resolve" : "delete");
692 return -1;
693 }
694
695 if (action == NES_ARP_RESOLVE) {
696 nes_debug(NES_DBG_NETDEV, "RESOLVE, arp_index=%d\n", arp_index);
697 return arp_index;
698 }
699
700 if (action == NES_ARP_DELETE) {
701 nes_debug(NES_DBG_NETDEV, "DELETE, arp_index=%d\n", arp_index);
702 nesadapter->arp_table[arp_index].ip_addr = 0;
703 memset(nesadapter->arp_table[arp_index].mac_addr, 0x00, ETH_ALEN);
704 nes_free_resource(nesadapter, nesadapter->allocated_arps, arp_index);
705 return arp_index;
706 }
707
708 return -1;
709 }
710
711
712 /**
713 * nes_mh_fix
714 */
715 void nes_mh_fix(unsigned long parm)
716 {
717 unsigned long flags;
718 struct nes_device *nesdev = (struct nes_device *)parm;
719 struct nes_adapter *nesadapter = nesdev->nesadapter;
720 struct nes_vnic *nesvnic;
721 u32 used_chunks_tx;
722 u32 temp_used_chunks_tx;
723 u32 temp_last_used_chunks_tx;
724 u32 used_chunks_mask;
725 u32 mac_tx_frames_low;
726 u32 mac_tx_frames_high;
727 u32 mac_tx_pauses;
728 u32 serdes_status;
729 u32 reset_value;
730 u32 tx_control;
731 u32 tx_config;
732 u32 tx_pause_quanta;
733 u32 rx_control;
734 u32 rx_config;
735 u32 mac_exact_match;
736 u32 mpp_debug;
737 u32 i=0;
738 u32 chunks_tx_progress = 0;
739
740 spin_lock_irqsave(&nesadapter->phy_lock, flags);
741 if ((nesadapter->mac_sw_state[0] != NES_MAC_SW_IDLE) || (nesadapter->mac_link_down[0])) {
742 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
743 goto no_mh_work;
744 }
745 nesadapter->mac_sw_state[0] = NES_MAC_SW_MH;
746 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
747 do {
748 mac_tx_frames_low = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_LOW);
749 mac_tx_frames_high = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_HIGH);
750 mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
751 used_chunks_tx = nes_read_indexed(nesdev, NES_IDX_USED_CHUNKS_TX);
752 nesdev->mac_pause_frames_sent += mac_tx_pauses;
753 used_chunks_mask = 0;
754 temp_used_chunks_tx = used_chunks_tx;
755 temp_last_used_chunks_tx = nesdev->last_used_chunks_tx;
756
757 if (nesdev->netdev[0]) {
758 nesvnic = netdev_priv(nesdev->netdev[0]);
759 } else {
760 break;
761 }
762
763 for (i=0; i<4; i++) {
764 used_chunks_mask <<= 8;
765 if (nesvnic->qp_nic_index[i] != 0xff) {
766 used_chunks_mask |= 0xff;
767 if ((temp_used_chunks_tx&0xff)<(temp_last_used_chunks_tx&0xff)) {
768 chunks_tx_progress = 1;
769 }
770 }
771 temp_used_chunks_tx >>= 8;
772 temp_last_used_chunks_tx >>= 8;
773 }
774 if ((mac_tx_frames_low) || (mac_tx_frames_high) ||
775 (!(used_chunks_tx&used_chunks_mask)) ||
776 (!(nesdev->last_used_chunks_tx&used_chunks_mask)) ||
777 (chunks_tx_progress) ) {
778 nesdev->last_used_chunks_tx = used_chunks_tx;
779 break;
780 }
781 nesdev->last_used_chunks_tx = used_chunks_tx;
782 barrier();
783
784 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000005);
785 mh_pauses_sent++;
786 mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
787 if (mac_tx_pauses) {
788 nesdev->mac_pause_frames_sent += mac_tx_pauses;
789 break;
790 }
791
792 tx_control = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONTROL);
793 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
794 tx_pause_quanta = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA);
795 rx_control = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONTROL);
796 rx_config = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONFIG);
797 mac_exact_match = nes_read_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM);
798 mpp_debug = nes_read_indexed(nesdev, NES_IDX_MPP_DEBUG);
799
800 /* one last ditch effort to avoid a false positive */
801 mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
802 if (mac_tx_pauses) {
803 nesdev->last_mac_tx_pauses = nesdev->mac_pause_frames_sent;
804 nes_debug(NES_DBG_HW, "failsafe caught slow outbound pause\n");
805 break;
806 }
807 mh_detected++;
808
809 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000000);
810 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, 0x00000000);
811 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
812
813 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value | 0x0000001d);
814
815 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
816 & 0x00000040) != 0x00000040) && (i++ < 5000)) {
817 /* mdelay(1); */
818 }
819
820 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
821 serdes_status = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0);
822
823 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x000bdef7);
824 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE0, 0x9ce73000);
825 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE0, 0x0ff00000);
826 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET0, 0x00000000);
827 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS0, 0x00000000);
828 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0, 0x00000000);
829 if (nesadapter->OneG_Mode) {
830 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0182222);
831 } else {
832 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0042222);
833 }
834 serdes_status = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_STATUS0);
835 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000ff);
836
837 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, tx_control);
838 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
839 nes_write_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA, tx_pause_quanta);
840 nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONTROL, rx_control);
841 nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONFIG, rx_config);
842 nes_write_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM, mac_exact_match);
843 nes_write_indexed(nesdev, NES_IDX_MPP_DEBUG, mpp_debug);
844
845 } while (0);
846
847 nesadapter->mac_sw_state[0] = NES_MAC_SW_IDLE;
848 no_mh_work:
849 nesdev->nesadapter->mh_timer.expires = jiffies + (HZ/5);
850 add_timer(&nesdev->nesadapter->mh_timer);
851 }
852
853 /**
854 * nes_clc
855 */
856 void nes_clc(unsigned long parm)
857 {
858 unsigned long flags;
859 struct nes_device *nesdev = (struct nes_device *)parm;
860 struct nes_adapter *nesadapter = nesdev->nesadapter;
861
862 spin_lock_irqsave(&nesadapter->phy_lock, flags);
863 nesadapter->link_interrupt_count[0] = 0;
864 nesadapter->link_interrupt_count[1] = 0;
865 nesadapter->link_interrupt_count[2] = 0;
866 nesadapter->link_interrupt_count[3] = 0;
867 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
868
869 nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */
870 add_timer(&nesadapter->lc_timer);
871 }
872
873
874 /**
875 * nes_dump_mem
876 */
877 void nes_dump_mem(unsigned int dump_debug_level, void *addr, int length)
878 {
879 char xlate[] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
880 'a', 'b', 'c', 'd', 'e', 'f'};
881 char *ptr;
882 char hex_buf[80];
883 char ascii_buf[20];
884 int num_char;
885 int num_ascii;
886 int num_hex;
887
888 if (!(nes_debug_level & dump_debug_level)) {
889 return;
890 }
891
892 ptr = addr;
893 if (length > 0x100) {
894 nes_debug(dump_debug_level, "Length truncated from %x to %x\n", length, 0x100);
895 length = 0x100;
896 }
897 nes_debug(dump_debug_level, "Address=0x%p, length=0x%x (%d)\n", ptr, length, length);
898
899 memset(ascii_buf, 0, 20);
900 memset(hex_buf, 0, 80);
901
902 num_ascii = 0;
903 num_hex = 0;
904 for (num_char = 0; num_char < length; num_char++) {
905 if (num_ascii == 8) {
906 ascii_buf[num_ascii++] = ' ';
907 hex_buf[num_hex++] = '-';
908 hex_buf[num_hex++] = ' ';
909 }
910
911 if (*ptr < 0x20 || *ptr > 0x7e)
912 ascii_buf[num_ascii++] = '.';
913 else
914 ascii_buf[num_ascii++] = *ptr;
915 hex_buf[num_hex++] = xlate[((*ptr & 0xf0) >> 4)];
916 hex_buf[num_hex++] = xlate[*ptr & 0x0f];
917 hex_buf[num_hex++] = ' ';
918 ptr++;
919
920 if (num_ascii >= 17) {
921 /* output line and reset */
922 nes_debug(dump_debug_level, " %s | %s\n", hex_buf, ascii_buf);
923 memset(ascii_buf, 0, 20);
924 memset(hex_buf, 0, 80);
925 num_ascii = 0;
926 num_hex = 0;
927 }
928 }
929
930 /* output the rest */
931 if (num_ascii) {
932 while (num_ascii < 17) {
933 if (num_ascii == 8) {
934 hex_buf[num_hex++] = ' ';
935 hex_buf[num_hex++] = ' ';
936 }
937 hex_buf[num_hex++] = ' ';
938 hex_buf[num_hex++] = ' ';
939 hex_buf[num_hex++] = ' ';
940 num_ascii++;
941 }
942
943 nes_debug(dump_debug_level, " %s | %s\n", hex_buf, ascii_buf);
944 }
945 }
Linux with added FPC-III support