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x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / mfd / wm8350-core.c
blobba27c9dc1ad39284a04ebcb8e11c8b7fd3d8c67e
1 /*
2 * wm8350-core.c -- Device access for Wolfson WM8350
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Liam Girdwood, Mark Brown
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/bug.h>
19 #include <linux/device.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/workqueue.h>
23
24 #include <linux/mfd/wm8350/core.h>
25 #include <linux/mfd/wm8350/audio.h>
26 #include <linux/mfd/wm8350/comparator.h>
27 #include <linux/mfd/wm8350/gpio.h>
28 #include <linux/mfd/wm8350/pmic.h>
29 #include <linux/mfd/wm8350/rtc.h>
30 #include <linux/mfd/wm8350/supply.h>
31 #include <linux/mfd/wm8350/wdt.h>
32
33 #define WM8350_UNLOCK_KEY 0x0013
34 #define WM8350_LOCK_KEY 0x0000
35
36 #define WM8350_CLOCK_CONTROL_1 0x28
37 #define WM8350_AIF_TEST 0x74
38
39 /* debug */
40 #define WM8350_BUS_DEBUG 0
41 #if WM8350_BUS_DEBUG
42 #define dump(regs, src) do { \
43 int i_; \
44 u16 *src_ = src; \
45 printk(KERN_DEBUG); \
46 for (i_ = 0; i_ < regs; i_++) \
47 printk(" 0x%4.4x", *src_++); \
48 printk("\n"); \
49 } while (0);
50 #else
51 #define dump(bytes, src)
52 #endif
53
54 #define WM8350_LOCK_DEBUG 0
55 #if WM8350_LOCK_DEBUG
56 #define ldbg(format, arg...) printk(format, ## arg)
57 #else
58 #define ldbg(format, arg...)
59 #endif
60
61 /*
62 * WM8350 Device IO
63 */
64 static DEFINE_MUTEX(io_mutex);
65 static DEFINE_MUTEX(reg_lock_mutex);
66
67 /* Perform a physical read from the device.
68 */
69 static int wm8350_phys_read(struct wm8350 *wm8350, u8 reg, int num_regs,
70 u16 *dest)
71 {
72 int i, ret;
73 int bytes = num_regs * 2;
74
75 dev_dbg(wm8350->dev, "volatile read\n");
76 ret = wm8350->read_dev(wm8350, reg, bytes, (char *)dest);
77
78 for (i = reg; i < reg + num_regs; i++) {
79 /* Cache is CPU endian */
80 dest[i - reg] = be16_to_cpu(dest[i - reg]);
81
82 /* Mask out non-readable bits */
83 dest[i - reg] &= wm8350_reg_io_map[i].readable;
84 }
85
86 dump(num_regs, dest);
87
88 return ret;
89 }
90
91 static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest)
92 {
93 int i;
94 int end = reg + num_regs;
95 int ret = 0;
96 int bytes = num_regs * 2;
97
98 if (wm8350->read_dev == NULL)
99 return -ENODEV;
100
101 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
102 dev_err(wm8350->dev, "invalid reg %x\n",
103 reg + num_regs - 1);
104 return -EINVAL;
105 }
106
107 dev_dbg(wm8350->dev,
108 "%s R%d(0x%2.2x) %d regs\n", __func__, reg, reg, num_regs);
109
110 #if WM8350_BUS_DEBUG
111 /* we can _safely_ read any register, but warn if read not supported */
112 for (i = reg; i < end; i++) {
113 if (!wm8350_reg_io_map[i].readable)
114 dev_warn(wm8350->dev,
115 "reg R%d is not readable\n", i);
116 }
117 #endif
118
119 /* if any volatile registers are required, then read back all */
120 for (i = reg; i < end; i++)
121 if (wm8350_reg_io_map[i].vol)
122 return wm8350_phys_read(wm8350, reg, num_regs, dest);
123
124 /* no volatiles, then cache is good */
125 dev_dbg(wm8350->dev, "cache read\n");
126 memcpy(dest, &wm8350->reg_cache[reg], bytes);
127 dump(num_regs, dest);
128 return ret;
129 }
130
131 static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg)
132 {
133 if (reg == WM8350_SECURITY ||
134 wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY)
135 return 0;
136
137 if ((reg == WM8350_GPIO_CONFIGURATION_I_O) ||
138 (reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
139 reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
140 (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
141 reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
142 return 1;
143 return 0;
144 }
145
146 static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src)
147 {
148 int i;
149 int end = reg + num_regs;
150 int bytes = num_regs * 2;
151
152 if (wm8350->write_dev == NULL)
153 return -ENODEV;
154
155 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
156 dev_err(wm8350->dev, "invalid reg %x\n",
157 reg + num_regs - 1);
158 return -EINVAL;
159 }
160
161 /* it's generally not a good idea to write to RO or locked registers */
162 for (i = reg; i < end; i++) {
163 if (!wm8350_reg_io_map[i].writable) {
164 dev_err(wm8350->dev,
165 "attempted write to read only reg R%d\n", i);
166 return -EINVAL;
167 }
168
169 if (is_reg_locked(wm8350, i)) {
170 dev_err(wm8350->dev,
171 "attempted write to locked reg R%d\n", i);
172 return -EINVAL;
173 }
174
175 src[i - reg] &= wm8350_reg_io_map[i].writable;
176
177 wm8350->reg_cache[i] =
178 (wm8350->reg_cache[i] & ~wm8350_reg_io_map[i].writable)
179 | src[i - reg];
180
181 src[i - reg] = cpu_to_be16(src[i - reg]);
182 }
183
184 /* Actually write it out */
185 return wm8350->write_dev(wm8350, reg, bytes, (char *)src);
186 }
187
188 /*
189 * Safe read, modify, write methods
190 */
191 int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
192 {
193 u16 data;
194 int err;
195
196 mutex_lock(&io_mutex);
197 err = wm8350_read(wm8350, reg, 1, &data);
198 if (err) {
199 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
200 goto out;
201 }
202
203 data &= ~mask;
204 err = wm8350_write(wm8350, reg, 1, &data);
205 if (err)
206 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
207 out:
208 mutex_unlock(&io_mutex);
209 return err;
210 }
211 EXPORT_SYMBOL_GPL(wm8350_clear_bits);
212
213 int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
214 {
215 u16 data;
216 int err;
217
218 mutex_lock(&io_mutex);
219 err = wm8350_read(wm8350, reg, 1, &data);
220 if (err) {
221 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
222 goto out;
223 }
224
225 data |= mask;
226 err = wm8350_write(wm8350, reg, 1, &data);
227 if (err)
228 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
229 out:
230 mutex_unlock(&io_mutex);
231 return err;
232 }
233 EXPORT_SYMBOL_GPL(wm8350_set_bits);
234
235 u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
236 {
237 u16 data;
238 int err;
239
240 mutex_lock(&io_mutex);
241 err = wm8350_read(wm8350, reg, 1, &data);
242 if (err)
243 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
244
245 mutex_unlock(&io_mutex);
246 return data;
247 }
248 EXPORT_SYMBOL_GPL(wm8350_reg_read);
249
250 int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
251 {
252 int ret;
253 u16 data = val;
254
255 mutex_lock(&io_mutex);
256 ret = wm8350_write(wm8350, reg, 1, &data);
257 if (ret)
258 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
259 mutex_unlock(&io_mutex);
260 return ret;
261 }
262 EXPORT_SYMBOL_GPL(wm8350_reg_write);
263
264 int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
265 u16 *dest)
266 {
267 int err = 0;
268
269 mutex_lock(&io_mutex);
270 err = wm8350_read(wm8350, start_reg, regs, dest);
271 if (err)
272 dev_err(wm8350->dev, "block read starting from R%d failed\n",
273 start_reg);
274 mutex_unlock(&io_mutex);
275 return err;
276 }
277 EXPORT_SYMBOL_GPL(wm8350_block_read);
278
279 int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
280 u16 *src)
281 {
282 int ret = 0;
283
284 mutex_lock(&io_mutex);
285 ret = wm8350_write(wm8350, start_reg, regs, src);
286 if (ret)
287 dev_err(wm8350->dev, "block write starting at R%d failed\n",
288 start_reg);
289 mutex_unlock(&io_mutex);
290 return ret;
291 }
292 EXPORT_SYMBOL_GPL(wm8350_block_write);
293
294 /**
295 * wm8350_reg_lock()
296 *
297 * The WM8350 has a hardware lock which can be used to prevent writes to
298 * some registers (generally those which can cause particularly serious
299 * problems if misused). This function enables that lock.
300 */
301 int wm8350_reg_lock(struct wm8350 *wm8350)
302 {
303 u16 key = WM8350_LOCK_KEY;
304 int ret;
305
306 ldbg(__func__);
307 mutex_lock(&io_mutex);
308 ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
309 if (ret)
310 dev_err(wm8350->dev, "lock failed\n");
311 mutex_unlock(&io_mutex);
312 return ret;
313 }
314 EXPORT_SYMBOL_GPL(wm8350_reg_lock);
315
316 /**
317 * wm8350_reg_unlock()
318 *
319 * The WM8350 has a hardware lock which can be used to prevent writes to
320 * some registers (generally those which can cause particularly serious
321 * problems if misused). This function disables that lock so updates
322 * can be performed. For maximum safety this should be done only when
323 * required.
324 */
325 int wm8350_reg_unlock(struct wm8350 *wm8350)
326 {
327 u16 key = WM8350_UNLOCK_KEY;
328 int ret;
329
330 ldbg(__func__);
331 mutex_lock(&io_mutex);
332 ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
333 if (ret)
334 dev_err(wm8350->dev, "unlock failed\n");
335 mutex_unlock(&io_mutex);
336 return ret;
337 }
338 EXPORT_SYMBOL_GPL(wm8350_reg_unlock);
339
340 static void wm8350_irq_call_handler(struct wm8350 *wm8350, int irq)
341 {
342 mutex_lock(&wm8350->irq_mutex);
343
344 if (wm8350->irq[irq].handler)
345 wm8350->irq[irq].handler(wm8350, irq, wm8350->irq[irq].data);
346 else {
347 dev_err(wm8350->dev, "irq %d nobody cared. now masked.\n",
348 irq);
349 wm8350_mask_irq(wm8350, irq);
350 }
351
352 mutex_unlock(&wm8350->irq_mutex);
353 }
354
355 /*
356 * This is a threaded IRQ handler so can access I2C/SPI. Since all
357 * interrupts are clear on read the IRQ line will be reasserted and
358 * the physical IRQ will be handled again if another interrupt is
359 * asserted while we run - in the normal course of events this is a
360 * rare occurrence so we save I2C/SPI reads.
361 */
362 static irqreturn_t wm8350_irq(int irq, void *data)
363 {
364 struct wm8350 *wm8350 = data;
365 u16 level_one, status1, status2, comp;
366
367 /* TODO: Use block reads to improve performance? */
368 level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS)
369 & ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK);
370 status1 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_1)
371 & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_1_MASK);
372 status2 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_2)
373 & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_2_MASK);
374 comp = wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS)
375 & ~wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS_MASK);
376
377 /* over current */
378 if (level_one & WM8350_OC_INT) {
379 u16 oc;
380
381 oc = wm8350_reg_read(wm8350, WM8350_OVER_CURRENT_INT_STATUS);
382 oc &= ~wm8350_reg_read(wm8350,
383 WM8350_OVER_CURRENT_INT_STATUS_MASK);
384
385 if (oc & WM8350_OC_LS_EINT) /* limit switch */
386 wm8350_irq_call_handler(wm8350, WM8350_IRQ_OC_LS);
387 }
388
389 /* under voltage */
390 if (level_one & WM8350_UV_INT) {
391 u16 uv;
392
393 uv = wm8350_reg_read(wm8350, WM8350_UNDER_VOLTAGE_INT_STATUS);
394 uv &= ~wm8350_reg_read(wm8350,
395 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK);
396
397 if (uv & WM8350_UV_DC1_EINT)
398 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC1);
399 if (uv & WM8350_UV_DC2_EINT)
400 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC2);
401 if (uv & WM8350_UV_DC3_EINT)
402 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC3);
403 if (uv & WM8350_UV_DC4_EINT)
404 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC4);
405 if (uv & WM8350_UV_DC5_EINT)
406 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC5);
407 if (uv & WM8350_UV_DC6_EINT)
408 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC6);
409 if (uv & WM8350_UV_LDO1_EINT)
410 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO1);
411 if (uv & WM8350_UV_LDO2_EINT)
412 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO2);
413 if (uv & WM8350_UV_LDO3_EINT)
414 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO3);
415 if (uv & WM8350_UV_LDO4_EINT)
416 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO4);
417 }
418
419 /* charger, RTC */
420 if (status1) {
421 if (status1 & WM8350_CHG_BAT_HOT_EINT)
422 wm8350_irq_call_handler(wm8350,
423 WM8350_IRQ_CHG_BAT_HOT);
424 if (status1 & WM8350_CHG_BAT_COLD_EINT)
425 wm8350_irq_call_handler(wm8350,
426 WM8350_IRQ_CHG_BAT_COLD);
427 if (status1 & WM8350_CHG_BAT_FAIL_EINT)
428 wm8350_irq_call_handler(wm8350,
429 WM8350_IRQ_CHG_BAT_FAIL);
430 if (status1 & WM8350_CHG_TO_EINT)
431 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_TO);
432 if (status1 & WM8350_CHG_END_EINT)
433 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_END);
434 if (status1 & WM8350_CHG_START_EINT)
435 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_START);
436 if (status1 & WM8350_CHG_FAST_RDY_EINT)
437 wm8350_irq_call_handler(wm8350,
438 WM8350_IRQ_CHG_FAST_RDY);
439 if (status1 & WM8350_CHG_VBATT_LT_3P9_EINT)
440 wm8350_irq_call_handler(wm8350,
441 WM8350_IRQ_CHG_VBATT_LT_3P9);
442 if (status1 & WM8350_CHG_VBATT_LT_3P1_EINT)
443 wm8350_irq_call_handler(wm8350,
444 WM8350_IRQ_CHG_VBATT_LT_3P1);
445 if (status1 & WM8350_CHG_VBATT_LT_2P85_EINT)
446 wm8350_irq_call_handler(wm8350,
447 WM8350_IRQ_CHG_VBATT_LT_2P85);
448 if (status1 & WM8350_RTC_ALM_EINT)
449 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_ALM);
450 if (status1 & WM8350_RTC_SEC_EINT)
451 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_SEC);
452 if (status1 & WM8350_RTC_PER_EINT)
453 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_PER);
454 }
455
456 /* current sink, system, aux adc */
457 if (status2) {
458 if (status2 & WM8350_CS1_EINT)
459 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS1);
460 if (status2 & WM8350_CS2_EINT)
461 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS2);
462
463 if (status2 & WM8350_SYS_HYST_COMP_FAIL_EINT)
464 wm8350_irq_call_handler(wm8350,
465 WM8350_IRQ_SYS_HYST_COMP_FAIL);
466 if (status2 & WM8350_SYS_CHIP_GT115_EINT)
467 wm8350_irq_call_handler(wm8350,
468 WM8350_IRQ_SYS_CHIP_GT115);
469 if (status2 & WM8350_SYS_CHIP_GT140_EINT)
470 wm8350_irq_call_handler(wm8350,
471 WM8350_IRQ_SYS_CHIP_GT140);
472 if (status2 & WM8350_SYS_WDOG_TO_EINT)
473 wm8350_irq_call_handler(wm8350,
474 WM8350_IRQ_SYS_WDOG_TO);
475
476 if (status2 & WM8350_AUXADC_DATARDY_EINT)
477 wm8350_irq_call_handler(wm8350,
478 WM8350_IRQ_AUXADC_DATARDY);
479 if (status2 & WM8350_AUXADC_DCOMP4_EINT)
480 wm8350_irq_call_handler(wm8350,
481 WM8350_IRQ_AUXADC_DCOMP4);
482 if (status2 & WM8350_AUXADC_DCOMP3_EINT)
483 wm8350_irq_call_handler(wm8350,
484 WM8350_IRQ_AUXADC_DCOMP3);
485 if (status2 & WM8350_AUXADC_DCOMP2_EINT)
486 wm8350_irq_call_handler(wm8350,
487 WM8350_IRQ_AUXADC_DCOMP2);
488 if (status2 & WM8350_AUXADC_DCOMP1_EINT)
489 wm8350_irq_call_handler(wm8350,
490 WM8350_IRQ_AUXADC_DCOMP1);
491
492 if (status2 & WM8350_USB_LIMIT_EINT)
493 wm8350_irq_call_handler(wm8350, WM8350_IRQ_USB_LIMIT);
494 }
495
496 /* wake, codec, ext */
497 if (comp) {
498 if (comp & WM8350_WKUP_OFF_STATE_EINT)
499 wm8350_irq_call_handler(wm8350,
500 WM8350_IRQ_WKUP_OFF_STATE);
501 if (comp & WM8350_WKUP_HIB_STATE_EINT)
502 wm8350_irq_call_handler(wm8350,
503 WM8350_IRQ_WKUP_HIB_STATE);
504 if (comp & WM8350_WKUP_CONV_FAULT_EINT)
505 wm8350_irq_call_handler(wm8350,
506 WM8350_IRQ_WKUP_CONV_FAULT);
507 if (comp & WM8350_WKUP_WDOG_RST_EINT)
508 wm8350_irq_call_handler(wm8350,
509 WM8350_IRQ_WKUP_WDOG_RST);
510 if (comp & WM8350_WKUP_GP_PWR_ON_EINT)
511 wm8350_irq_call_handler(wm8350,
512 WM8350_IRQ_WKUP_GP_PWR_ON);
513 if (comp & WM8350_WKUP_ONKEY_EINT)
514 wm8350_irq_call_handler(wm8350, WM8350_IRQ_WKUP_ONKEY);
515 if (comp & WM8350_WKUP_GP_WAKEUP_EINT)
516 wm8350_irq_call_handler(wm8350,
517 WM8350_IRQ_WKUP_GP_WAKEUP);
518
519 if (comp & WM8350_CODEC_JCK_DET_L_EINT)
520 wm8350_irq_call_handler(wm8350,
521 WM8350_IRQ_CODEC_JCK_DET_L);
522 if (comp & WM8350_CODEC_JCK_DET_R_EINT)
523 wm8350_irq_call_handler(wm8350,
524 WM8350_IRQ_CODEC_JCK_DET_R);
525 if (comp & WM8350_CODEC_MICSCD_EINT)
526 wm8350_irq_call_handler(wm8350,
527 WM8350_IRQ_CODEC_MICSCD);
528 if (comp & WM8350_CODEC_MICD_EINT)
529 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CODEC_MICD);
530
531 if (comp & WM8350_EXT_USB_FB_EINT)
532 wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_USB_FB);
533 if (comp & WM8350_EXT_WALL_FB_EINT)
534 wm8350_irq_call_handler(wm8350,
535 WM8350_IRQ_EXT_WALL_FB);
536 if (comp & WM8350_EXT_BAT_FB_EINT)
537 wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_BAT_FB);
538 }
539
540 if (level_one & WM8350_GP_INT) {
541 int i;
542 u16 gpio;
543
544 gpio = wm8350_reg_read(wm8350, WM8350_GPIO_INT_STATUS);
545 gpio &= ~wm8350_reg_read(wm8350,
546 WM8350_GPIO_INT_STATUS_MASK);
547
548 for (i = 0; i < 12; i++) {
549 if (gpio & (1 << i))
550 wm8350_irq_call_handler(wm8350,
551 WM8350_IRQ_GPIO(i));
552 }
553 }
554
555 return IRQ_HANDLED;
556 }
557
558 int wm8350_register_irq(struct wm8350 *wm8350, int irq,
559 void (*handler) (struct wm8350 *, int, void *),
560 void *data)
561 {
562 if (irq < 0 || irq > WM8350_NUM_IRQ || !handler)
563 return -EINVAL;
564
565 if (wm8350->irq[irq].handler)
566 return -EBUSY;
567
568 mutex_lock(&wm8350->irq_mutex);
569 wm8350->irq[irq].handler = handler;
570 wm8350->irq[irq].data = data;
571 mutex_unlock(&wm8350->irq_mutex);
572
573 return 0;
574 }
575 EXPORT_SYMBOL_GPL(wm8350_register_irq);
576
577 int wm8350_free_irq(struct wm8350 *wm8350, int irq)
578 {
579 if (irq < 0 || irq > WM8350_NUM_IRQ)
580 return -EINVAL;
581
582 mutex_lock(&wm8350->irq_mutex);
583 wm8350->irq[irq].handler = NULL;
584 mutex_unlock(&wm8350->irq_mutex);
585 return 0;
586 }
587 EXPORT_SYMBOL_GPL(wm8350_free_irq);
588
589 int wm8350_mask_irq(struct wm8350 *wm8350, int irq)
590 {
591 switch (irq) {
592 case WM8350_IRQ_CHG_BAT_HOT:
593 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
594 WM8350_IM_CHG_BAT_HOT_EINT);
595 case WM8350_IRQ_CHG_BAT_COLD:
596 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
597 WM8350_IM_CHG_BAT_COLD_EINT);
598 case WM8350_IRQ_CHG_BAT_FAIL:
599 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
600 WM8350_IM_CHG_BAT_FAIL_EINT);
601 case WM8350_IRQ_CHG_TO:
602 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
603 WM8350_IM_CHG_TO_EINT);
604 case WM8350_IRQ_CHG_END:
605 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
606 WM8350_IM_CHG_END_EINT);
607 case WM8350_IRQ_CHG_START:
608 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
609 WM8350_IM_CHG_START_EINT);
610 case WM8350_IRQ_CHG_FAST_RDY:
611 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
612 WM8350_IM_CHG_FAST_RDY_EINT);
613 case WM8350_IRQ_RTC_PER:
614 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
615 WM8350_IM_RTC_PER_EINT);
616 case WM8350_IRQ_RTC_SEC:
617 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
618 WM8350_IM_RTC_SEC_EINT);
619 case WM8350_IRQ_RTC_ALM:
620 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
621 WM8350_IM_RTC_ALM_EINT);
622 case WM8350_IRQ_CHG_VBATT_LT_3P9:
623 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
624 WM8350_IM_CHG_VBATT_LT_3P9_EINT);
625 case WM8350_IRQ_CHG_VBATT_LT_3P1:
626 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
627 WM8350_IM_CHG_VBATT_LT_3P1_EINT);
628 case WM8350_IRQ_CHG_VBATT_LT_2P85:
629 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
630 WM8350_IM_CHG_VBATT_LT_2P85_EINT);
631 case WM8350_IRQ_CS1:
632 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
633 WM8350_IM_CS1_EINT);
634 case WM8350_IRQ_CS2:
635 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
636 WM8350_IM_CS2_EINT);
637 case WM8350_IRQ_USB_LIMIT:
638 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
639 WM8350_IM_USB_LIMIT_EINT);
640 case WM8350_IRQ_AUXADC_DATARDY:
641 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
642 WM8350_IM_AUXADC_DATARDY_EINT);
643 case WM8350_IRQ_AUXADC_DCOMP4:
644 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
645 WM8350_IM_AUXADC_DCOMP4_EINT);
646 case WM8350_IRQ_AUXADC_DCOMP3:
647 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
648 WM8350_IM_AUXADC_DCOMP3_EINT);
649 case WM8350_IRQ_AUXADC_DCOMP2:
650 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
651 WM8350_IM_AUXADC_DCOMP2_EINT);
652 case WM8350_IRQ_AUXADC_DCOMP1:
653 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
654 WM8350_IM_AUXADC_DCOMP1_EINT);
655 case WM8350_IRQ_SYS_HYST_COMP_FAIL:
656 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
657 WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
658 case WM8350_IRQ_SYS_CHIP_GT115:
659 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
660 WM8350_IM_SYS_CHIP_GT115_EINT);
661 case WM8350_IRQ_SYS_CHIP_GT140:
662 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
663 WM8350_IM_SYS_CHIP_GT140_EINT);
664 case WM8350_IRQ_SYS_WDOG_TO:
665 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
666 WM8350_IM_SYS_WDOG_TO_EINT);
667 case WM8350_IRQ_UV_LDO4:
668 return wm8350_set_bits(wm8350,
669 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
670 WM8350_IM_UV_LDO4_EINT);
671 case WM8350_IRQ_UV_LDO3:
672 return wm8350_set_bits(wm8350,
673 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
674 WM8350_IM_UV_LDO3_EINT);
675 case WM8350_IRQ_UV_LDO2:
676 return wm8350_set_bits(wm8350,
677 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
678 WM8350_IM_UV_LDO2_EINT);
679 case WM8350_IRQ_UV_LDO1:
680 return wm8350_set_bits(wm8350,
681 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
682 WM8350_IM_UV_LDO1_EINT);
683 case WM8350_IRQ_UV_DC6:
684 return wm8350_set_bits(wm8350,
685 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
686 WM8350_IM_UV_DC6_EINT);
687 case WM8350_IRQ_UV_DC5:
688 return wm8350_set_bits(wm8350,
689 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
690 WM8350_IM_UV_DC5_EINT);
691 case WM8350_IRQ_UV_DC4:
692 return wm8350_set_bits(wm8350,
693 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
694 WM8350_IM_UV_DC4_EINT);
695 case WM8350_IRQ_UV_DC3:
696 return wm8350_set_bits(wm8350,
697 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
698 WM8350_IM_UV_DC3_EINT);
699 case WM8350_IRQ_UV_DC2:
700 return wm8350_set_bits(wm8350,
701 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
702 WM8350_IM_UV_DC2_EINT);
703 case WM8350_IRQ_UV_DC1:
704 return wm8350_set_bits(wm8350,
705 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
706 WM8350_IM_UV_DC1_EINT);
707 case WM8350_IRQ_OC_LS:
708 return wm8350_set_bits(wm8350,
709 WM8350_OVER_CURRENT_INT_STATUS_MASK,
710 WM8350_IM_OC_LS_EINT);
711 case WM8350_IRQ_EXT_USB_FB:
712 return wm8350_set_bits(wm8350,
713 WM8350_COMPARATOR_INT_STATUS_MASK,
714 WM8350_IM_EXT_USB_FB_EINT);
715 case WM8350_IRQ_EXT_WALL_FB:
716 return wm8350_set_bits(wm8350,
717 WM8350_COMPARATOR_INT_STATUS_MASK,
718 WM8350_IM_EXT_WALL_FB_EINT);
719 case WM8350_IRQ_EXT_BAT_FB:
720 return wm8350_set_bits(wm8350,
721 WM8350_COMPARATOR_INT_STATUS_MASK,
722 WM8350_IM_EXT_BAT_FB_EINT);
723 case WM8350_IRQ_CODEC_JCK_DET_L:
724 return wm8350_set_bits(wm8350,
725 WM8350_COMPARATOR_INT_STATUS_MASK,
726 WM8350_IM_CODEC_JCK_DET_L_EINT);
727 case WM8350_IRQ_CODEC_JCK_DET_R:
728 return wm8350_set_bits(wm8350,
729 WM8350_COMPARATOR_INT_STATUS_MASK,
730 WM8350_IM_CODEC_JCK_DET_R_EINT);
731 case WM8350_IRQ_CODEC_MICSCD:
732 return wm8350_set_bits(wm8350,
733 WM8350_COMPARATOR_INT_STATUS_MASK,
734 WM8350_IM_CODEC_MICSCD_EINT);
735 case WM8350_IRQ_CODEC_MICD:
736 return wm8350_set_bits(wm8350,
737 WM8350_COMPARATOR_INT_STATUS_MASK,
738 WM8350_IM_CODEC_MICD_EINT);
739 case WM8350_IRQ_WKUP_OFF_STATE:
740 return wm8350_set_bits(wm8350,
741 WM8350_COMPARATOR_INT_STATUS_MASK,
742 WM8350_IM_WKUP_OFF_STATE_EINT);
743 case WM8350_IRQ_WKUP_HIB_STATE:
744 return wm8350_set_bits(wm8350,
745 WM8350_COMPARATOR_INT_STATUS_MASK,
746 WM8350_IM_WKUP_HIB_STATE_EINT);
747 case WM8350_IRQ_WKUP_CONV_FAULT:
748 return wm8350_set_bits(wm8350,
749 WM8350_COMPARATOR_INT_STATUS_MASK,
750 WM8350_IM_WKUP_CONV_FAULT_EINT);
751 case WM8350_IRQ_WKUP_WDOG_RST:
752 return wm8350_set_bits(wm8350,
753 WM8350_COMPARATOR_INT_STATUS_MASK,
754 WM8350_IM_WKUP_OFF_STATE_EINT);
755 case WM8350_IRQ_WKUP_GP_PWR_ON:
756 return wm8350_set_bits(wm8350,
757 WM8350_COMPARATOR_INT_STATUS_MASK,
758 WM8350_IM_WKUP_GP_PWR_ON_EINT);
759 case WM8350_IRQ_WKUP_ONKEY:
760 return wm8350_set_bits(wm8350,
761 WM8350_COMPARATOR_INT_STATUS_MASK,
762 WM8350_IM_WKUP_ONKEY_EINT);
763 case WM8350_IRQ_WKUP_GP_WAKEUP:
764 return wm8350_set_bits(wm8350,
765 WM8350_COMPARATOR_INT_STATUS_MASK,
766 WM8350_IM_WKUP_GP_WAKEUP_EINT);
767 case WM8350_IRQ_GPIO(0):
768 return wm8350_set_bits(wm8350,
769 WM8350_GPIO_INT_STATUS_MASK,
770 WM8350_IM_GP0_EINT);
771 case WM8350_IRQ_GPIO(1):
772 return wm8350_set_bits(wm8350,
773 WM8350_GPIO_INT_STATUS_MASK,
774 WM8350_IM_GP1_EINT);
775 case WM8350_IRQ_GPIO(2):
776 return wm8350_set_bits(wm8350,
777 WM8350_GPIO_INT_STATUS_MASK,
778 WM8350_IM_GP2_EINT);
779 case WM8350_IRQ_GPIO(3):
780 return wm8350_set_bits(wm8350,
781 WM8350_GPIO_INT_STATUS_MASK,
782 WM8350_IM_GP3_EINT);
783 case WM8350_IRQ_GPIO(4):
784 return wm8350_set_bits(wm8350,
785 WM8350_GPIO_INT_STATUS_MASK,
786 WM8350_IM_GP4_EINT);
787 case WM8350_IRQ_GPIO(5):
788 return wm8350_set_bits(wm8350,
789 WM8350_GPIO_INT_STATUS_MASK,
790 WM8350_IM_GP5_EINT);
791 case WM8350_IRQ_GPIO(6):
792 return wm8350_set_bits(wm8350,
793 WM8350_GPIO_INT_STATUS_MASK,
794 WM8350_IM_GP6_EINT);
795 case WM8350_IRQ_GPIO(7):
796 return wm8350_set_bits(wm8350,
797 WM8350_GPIO_INT_STATUS_MASK,
798 WM8350_IM_GP7_EINT);
799 case WM8350_IRQ_GPIO(8):
800 return wm8350_set_bits(wm8350,
801 WM8350_GPIO_INT_STATUS_MASK,
802 WM8350_IM_GP8_EINT);
803 case WM8350_IRQ_GPIO(9):
804 return wm8350_set_bits(wm8350,
805 WM8350_GPIO_INT_STATUS_MASK,
806 WM8350_IM_GP9_EINT);
807 case WM8350_IRQ_GPIO(10):
808 return wm8350_set_bits(wm8350,
809 WM8350_GPIO_INT_STATUS_MASK,
810 WM8350_IM_GP10_EINT);
811 case WM8350_IRQ_GPIO(11):
812 return wm8350_set_bits(wm8350,
813 WM8350_GPIO_INT_STATUS_MASK,
814 WM8350_IM_GP11_EINT);
815 case WM8350_IRQ_GPIO(12):
816 return wm8350_set_bits(wm8350,
817 WM8350_GPIO_INT_STATUS_MASK,
818 WM8350_IM_GP12_EINT);
819 default:
820 dev_warn(wm8350->dev, "Attempting to mask unknown IRQ %d\n",
821 irq);
822 return -EINVAL;
823 }
824 return 0;
825 }
826 EXPORT_SYMBOL_GPL(wm8350_mask_irq);
827
828 int wm8350_unmask_irq(struct wm8350 *wm8350, int irq)
829 {
830 switch (irq) {
831 case WM8350_IRQ_CHG_BAT_HOT:
832 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
833 WM8350_IM_CHG_BAT_HOT_EINT);
834 case WM8350_IRQ_CHG_BAT_COLD:
835 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
836 WM8350_IM_CHG_BAT_COLD_EINT);
837 case WM8350_IRQ_CHG_BAT_FAIL:
838 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
839 WM8350_IM_CHG_BAT_FAIL_EINT);
840 case WM8350_IRQ_CHG_TO:
841 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
842 WM8350_IM_CHG_TO_EINT);
843 case WM8350_IRQ_CHG_END:
844 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
845 WM8350_IM_CHG_END_EINT);
846 case WM8350_IRQ_CHG_START:
847 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
848 WM8350_IM_CHG_START_EINT);
849 case WM8350_IRQ_CHG_FAST_RDY:
850 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
851 WM8350_IM_CHG_FAST_RDY_EINT);
852 case WM8350_IRQ_RTC_PER:
853 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
854 WM8350_IM_RTC_PER_EINT);
855 case WM8350_IRQ_RTC_SEC:
856 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
857 WM8350_IM_RTC_SEC_EINT);
858 case WM8350_IRQ_RTC_ALM:
859 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
860 WM8350_IM_RTC_ALM_EINT);
861 case WM8350_IRQ_CHG_VBATT_LT_3P9:
862 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
863 WM8350_IM_CHG_VBATT_LT_3P9_EINT);
864 case WM8350_IRQ_CHG_VBATT_LT_3P1:
865 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
866 WM8350_IM_CHG_VBATT_LT_3P1_EINT);
867 case WM8350_IRQ_CHG_VBATT_LT_2P85:
868 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
869 WM8350_IM_CHG_VBATT_LT_2P85_EINT);
870 case WM8350_IRQ_CS1:
871 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
872 WM8350_IM_CS1_EINT);
873 case WM8350_IRQ_CS2:
874 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
875 WM8350_IM_CS2_EINT);
876 case WM8350_IRQ_USB_LIMIT:
877 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
878 WM8350_IM_USB_LIMIT_EINT);
879 case WM8350_IRQ_AUXADC_DATARDY:
880 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
881 WM8350_IM_AUXADC_DATARDY_EINT);
882 case WM8350_IRQ_AUXADC_DCOMP4:
883 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
884 WM8350_IM_AUXADC_DCOMP4_EINT);
885 case WM8350_IRQ_AUXADC_DCOMP3:
886 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
887 WM8350_IM_AUXADC_DCOMP3_EINT);
888 case WM8350_IRQ_AUXADC_DCOMP2:
889 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
890 WM8350_IM_AUXADC_DCOMP2_EINT);
891 case WM8350_IRQ_AUXADC_DCOMP1:
892 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
893 WM8350_IM_AUXADC_DCOMP1_EINT);
894 case WM8350_IRQ_SYS_HYST_COMP_FAIL:
895 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
896 WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
897 case WM8350_IRQ_SYS_CHIP_GT115:
898 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
899 WM8350_IM_SYS_CHIP_GT115_EINT);
900 case WM8350_IRQ_SYS_CHIP_GT140:
901 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
902 WM8350_IM_SYS_CHIP_GT140_EINT);
903 case WM8350_IRQ_SYS_WDOG_TO:
904 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
905 WM8350_IM_SYS_WDOG_TO_EINT);
906 case WM8350_IRQ_UV_LDO4:
907 return wm8350_clear_bits(wm8350,
908 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
909 WM8350_IM_UV_LDO4_EINT);
910 case WM8350_IRQ_UV_LDO3:
911 return wm8350_clear_bits(wm8350,
912 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
913 WM8350_IM_UV_LDO3_EINT);
914 case WM8350_IRQ_UV_LDO2:
915 return wm8350_clear_bits(wm8350,
916 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
917 WM8350_IM_UV_LDO2_EINT);
918 case WM8350_IRQ_UV_LDO1:
919 return wm8350_clear_bits(wm8350,
920 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
921 WM8350_IM_UV_LDO1_EINT);
922 case WM8350_IRQ_UV_DC6:
923 return wm8350_clear_bits(wm8350,
924 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
925 WM8350_IM_UV_DC6_EINT);
926 case WM8350_IRQ_UV_DC5:
927 return wm8350_clear_bits(wm8350,
928 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
929 WM8350_IM_UV_DC5_EINT);
930 case WM8350_IRQ_UV_DC4:
931 return wm8350_clear_bits(wm8350,
932 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
933 WM8350_IM_UV_DC4_EINT);
934 case WM8350_IRQ_UV_DC3:
935 return wm8350_clear_bits(wm8350,
936 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
937 WM8350_IM_UV_DC3_EINT);
938 case WM8350_IRQ_UV_DC2:
939 return wm8350_clear_bits(wm8350,
940 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
941 WM8350_IM_UV_DC2_EINT);
942 case WM8350_IRQ_UV_DC1:
943 return wm8350_clear_bits(wm8350,
944 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
945 WM8350_IM_UV_DC1_EINT);
946 case WM8350_IRQ_OC_LS:
947 return wm8350_clear_bits(wm8350,
948 WM8350_OVER_CURRENT_INT_STATUS_MASK,
949 WM8350_IM_OC_LS_EINT);
950 case WM8350_IRQ_EXT_USB_FB:
951 return wm8350_clear_bits(wm8350,
952 WM8350_COMPARATOR_INT_STATUS_MASK,
953 WM8350_IM_EXT_USB_FB_EINT);
954 case WM8350_IRQ_EXT_WALL_FB:
955 return wm8350_clear_bits(wm8350,
956 WM8350_COMPARATOR_INT_STATUS_MASK,
957 WM8350_IM_EXT_WALL_FB_EINT);
958 case WM8350_IRQ_EXT_BAT_FB:
959 return wm8350_clear_bits(wm8350,
960 WM8350_COMPARATOR_INT_STATUS_MASK,
961 WM8350_IM_EXT_BAT_FB_EINT);
962 case WM8350_IRQ_CODEC_JCK_DET_L:
963 return wm8350_clear_bits(wm8350,
964 WM8350_COMPARATOR_INT_STATUS_MASK,
965 WM8350_IM_CODEC_JCK_DET_L_EINT);
966 case WM8350_IRQ_CODEC_JCK_DET_R:
967 return wm8350_clear_bits(wm8350,
968 WM8350_COMPARATOR_INT_STATUS_MASK,
969 WM8350_IM_CODEC_JCK_DET_R_EINT);
970 case WM8350_IRQ_CODEC_MICSCD:
971 return wm8350_clear_bits(wm8350,
972 WM8350_COMPARATOR_INT_STATUS_MASK,
973 WM8350_IM_CODEC_MICSCD_EINT);
974 case WM8350_IRQ_CODEC_MICD:
975 return wm8350_clear_bits(wm8350,
976 WM8350_COMPARATOR_INT_STATUS_MASK,
977 WM8350_IM_CODEC_MICD_EINT);
978 case WM8350_IRQ_WKUP_OFF_STATE:
979 return wm8350_clear_bits(wm8350,
980 WM8350_COMPARATOR_INT_STATUS_MASK,
981 WM8350_IM_WKUP_OFF_STATE_EINT);
982 case WM8350_IRQ_WKUP_HIB_STATE:
983 return wm8350_clear_bits(wm8350,
984 WM8350_COMPARATOR_INT_STATUS_MASK,
985 WM8350_IM_WKUP_HIB_STATE_EINT);
986 case WM8350_IRQ_WKUP_CONV_FAULT:
987 return wm8350_clear_bits(wm8350,
988 WM8350_COMPARATOR_INT_STATUS_MASK,
989 WM8350_IM_WKUP_CONV_FAULT_EINT);
990 case WM8350_IRQ_WKUP_WDOG_RST:
991 return wm8350_clear_bits(wm8350,
992 WM8350_COMPARATOR_INT_STATUS_MASK,
993 WM8350_IM_WKUP_OFF_STATE_EINT);
994 case WM8350_IRQ_WKUP_GP_PWR_ON:
995 return wm8350_clear_bits(wm8350,
996 WM8350_COMPARATOR_INT_STATUS_MASK,
997 WM8350_IM_WKUP_GP_PWR_ON_EINT);
998 case WM8350_IRQ_WKUP_ONKEY:
999 return wm8350_clear_bits(wm8350,
1000 WM8350_COMPARATOR_INT_STATUS_MASK,
1001 WM8350_IM_WKUP_ONKEY_EINT);
1002 case WM8350_IRQ_WKUP_GP_WAKEUP:
1003 return wm8350_clear_bits(wm8350,
1004 WM8350_COMPARATOR_INT_STATUS_MASK,
1005 WM8350_IM_WKUP_GP_WAKEUP_EINT);
1006 case WM8350_IRQ_GPIO(0):
1007 return wm8350_clear_bits(wm8350,
1008 WM8350_GPIO_INT_STATUS_MASK,
1009 WM8350_IM_GP0_EINT);
1010 case WM8350_IRQ_GPIO(1):
1011 return wm8350_clear_bits(wm8350,
1012 WM8350_GPIO_INT_STATUS_MASK,
1013 WM8350_IM_GP1_EINT);
1014 case WM8350_IRQ_GPIO(2):
1015 return wm8350_clear_bits(wm8350,
1016 WM8350_GPIO_INT_STATUS_MASK,
1017 WM8350_IM_GP2_EINT);
1018 case WM8350_IRQ_GPIO(3):
1019 return wm8350_clear_bits(wm8350,
1020 WM8350_GPIO_INT_STATUS_MASK,
1021 WM8350_IM_GP3_EINT);
1022 case WM8350_IRQ_GPIO(4):
1023 return wm8350_clear_bits(wm8350,
1024 WM8350_GPIO_INT_STATUS_MASK,
1025 WM8350_IM_GP4_EINT);
1026 case WM8350_IRQ_GPIO(5):
1027 return wm8350_clear_bits(wm8350,
1028 WM8350_GPIO_INT_STATUS_MASK,
1029 WM8350_IM_GP5_EINT);
1030 case WM8350_IRQ_GPIO(6):
1031 return wm8350_clear_bits(wm8350,
1032 WM8350_GPIO_INT_STATUS_MASK,
1033 WM8350_IM_GP6_EINT);
1034 case WM8350_IRQ_GPIO(7):
1035 return wm8350_clear_bits(wm8350,
1036 WM8350_GPIO_INT_STATUS_MASK,
1037 WM8350_IM_GP7_EINT);
1038 case WM8350_IRQ_GPIO(8):
1039 return wm8350_clear_bits(wm8350,
1040 WM8350_GPIO_INT_STATUS_MASK,
1041 WM8350_IM_GP8_EINT);
1042 case WM8350_IRQ_GPIO(9):
1043 return wm8350_clear_bits(wm8350,
1044 WM8350_GPIO_INT_STATUS_MASK,
1045 WM8350_IM_GP9_EINT);
1046 case WM8350_IRQ_GPIO(10):
1047 return wm8350_clear_bits(wm8350,
1048 WM8350_GPIO_INT_STATUS_MASK,
1049 WM8350_IM_GP10_EINT);
1050 case WM8350_IRQ_GPIO(11):
1051 return wm8350_clear_bits(wm8350,
1052 WM8350_GPIO_INT_STATUS_MASK,
1053 WM8350_IM_GP11_EINT);
1054 case WM8350_IRQ_GPIO(12):
1055 return wm8350_clear_bits(wm8350,
1056 WM8350_GPIO_INT_STATUS_MASK,
1057 WM8350_IM_GP12_EINT);
1058 default:
1059 dev_warn(wm8350->dev, "Attempting to unmask unknown IRQ %d\n",
1060 irq);
1061 return -EINVAL;
1062 }
1063 return 0;
1064 }
1065 EXPORT_SYMBOL_GPL(wm8350_unmask_irq);
1066
1067 int wm8350_read_auxadc(struct wm8350 *wm8350, int channel, int scale, int vref)
1068 {
1069 u16 reg, result = 0;
1070 int tries = 5;
1071
1072 if (channel < WM8350_AUXADC_AUX1 || channel > WM8350_AUXADC_TEMP)
1073 return -EINVAL;
1074 if (channel >= WM8350_AUXADC_USB && channel <= WM8350_AUXADC_TEMP
1075 && (scale != 0 || vref != 0))
1076 return -EINVAL;
1077
1078 mutex_lock(&wm8350->auxadc_mutex);
1079
1080 /* Turn on the ADC */
1081 reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
1082 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5, reg | WM8350_AUXADC_ENA);
1083
1084 if (scale || vref) {
1085 reg = scale << 13;
1086 reg |= vref << 12;
1087 wm8350_reg_write(wm8350, WM8350_AUX1_READBACK + channel, reg);
1088 }
1089
1090 reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
1091 reg |= 1 << channel | WM8350_AUXADC_POLL;
1092 wm8350_reg_write(wm8350, WM8350_DIGITISER_CONTROL_1, reg);
1093
1094 do {
1095 schedule_timeout_interruptible(1);
1096 reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
1097 } while ((reg & WM8350_AUXADC_POLL) && --tries);
1098
1099 if (!tries)
1100 dev_err(wm8350->dev, "adc chn %d read timeout\n", channel);
1101 else
1102 result = wm8350_reg_read(wm8350,
1103 WM8350_AUX1_READBACK + channel);
1104
1105 /* Turn off the ADC */
1106 reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
1107 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5,
1108 reg & ~WM8350_AUXADC_ENA);
1109
1110 mutex_unlock(&wm8350->auxadc_mutex);
1111
1112 return result & WM8350_AUXADC_DATA1_MASK;
1113 }
1114 EXPORT_SYMBOL_GPL(wm8350_read_auxadc);
1115
1116 /*
1117 * Cache is always host endian.
1118 */
1119 static int wm8350_create_cache(struct wm8350 *wm8350, int type, int mode)
1120 {
1121 int i, ret = 0;
1122 u16 value;
1123 const u16 *reg_map;
1124
1125 switch (type) {
1126 case 0:
1127 switch (mode) {
1128 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
1129 case 0:
1130 reg_map = wm8350_mode0_defaults;
1131 break;
1132 #endif
1133 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
1134 case 1:
1135 reg_map = wm8350_mode1_defaults;
1136 break;
1137 #endif
1138 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
1139 case 2:
1140 reg_map = wm8350_mode2_defaults;
1141 break;
1142 #endif
1143 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
1144 case 3:
1145 reg_map = wm8350_mode3_defaults;
1146 break;
1147 #endif
1148 default:
1149 dev_err(wm8350->dev,
1150 "WM8350 configuration mode %d not supported\n",
1151 mode);
1152 return -EINVAL;
1153 }
1154 break;
1155
1156 case 1:
1157 switch (mode) {
1158 #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_0
1159 case 0:
1160 reg_map = wm8351_mode0_defaults;
1161 break;
1162 #endif
1163 #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_1
1164 case 1:
1165 reg_map = wm8351_mode1_defaults;
1166 break;
1167 #endif
1168 #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_2
1169 case 2:
1170 reg_map = wm8351_mode2_defaults;
1171 break;
1172 #endif
1173 #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_3
1174 case 3:
1175 reg_map = wm8351_mode3_defaults;
1176 break;
1177 #endif
1178 default:
1179 dev_err(wm8350->dev,
1180 "WM8351 configuration mode %d not supported\n",
1181 mode);
1182 return -EINVAL;
1183 }
1184 break;
1185
1186 case 2:
1187 switch (mode) {
1188 #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_0
1189 case 0:
1190 reg_map = wm8352_mode0_defaults;
1191 break;
1192 #endif
1193 #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_1
1194 case 1:
1195 reg_map = wm8352_mode1_defaults;
1196 break;
1197 #endif
1198 #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_2
1199 case 2:
1200 reg_map = wm8352_mode2_defaults;
1201 break;
1202 #endif
1203 #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_3
1204 case 3:
1205 reg_map = wm8352_mode3_defaults;
1206 break;
1207 #endif
1208 default:
1209 dev_err(wm8350->dev,
1210 "WM8352 configuration mode %d not supported\n",
1211 mode);
1212 return -EINVAL;
1213 }
1214 break;
1215
1216 default:
1217 dev_err(wm8350->dev,
1218 "WM835x configuration mode %d not supported\n",
1219 mode);
1220 return -EINVAL;
1221 }
1222
1223 wm8350->reg_cache =
1224 kmalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL);
1225 if (wm8350->reg_cache == NULL)
1226 return -ENOMEM;
1227
1228 /* Read the initial cache state back from the device - this is
1229 * a PMIC so the device many not be in a virgin state and we
1230 * can't rely on the silicon values.
1231 */
1232 ret = wm8350->read_dev(wm8350, 0,
1233 sizeof(u16) * (WM8350_MAX_REGISTER + 1),
1234 wm8350->reg_cache);
1235 if (ret < 0) {
1236 dev_err(wm8350->dev,
1237 "failed to read initial cache values\n");
1238 goto out;
1239 }
1240
1241 /* Mask out uncacheable/unreadable bits and the audio. */
1242 for (i = 0; i < WM8350_MAX_REGISTER; i++) {
1243 if (wm8350_reg_io_map[i].readable &&
1244 (i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) {
1245 value = be16_to_cpu(wm8350->reg_cache[i]);
1246 value &= wm8350_reg_io_map[i].readable;
1247 wm8350->reg_cache[i] = value;
1248 } else
1249 wm8350->reg_cache[i] = reg_map[i];
1250 }
1251
1252 out:
1253 return ret;
1254 }
1255
1256 /*
1257 * Register a client device. This is non-fatal since there is no need to
1258 * fail the entire device init due to a single platform device failing.
1259 */
1260 static void wm8350_client_dev_register(struct wm8350 *wm8350,
1261 const char *name,
1262 struct platform_device **pdev)
1263 {
1264 int ret;
1265
1266 *pdev = platform_device_alloc(name, -1);
1267 if (pdev == NULL) {
1268 dev_err(wm8350->dev, "Failed to allocate %s\n", name);
1269 return;
1270 }
1271
1272 (*pdev)->dev.parent = wm8350->dev;
1273 platform_set_drvdata(*pdev, wm8350);
1274 ret = platform_device_add(*pdev);
1275 if (ret != 0) {
1276 dev_err(wm8350->dev, "Failed to register %s: %d\n", name, ret);
1277 platform_device_put(*pdev);
1278 *pdev = NULL;
1279 }
1280 }
1281
1282 int wm8350_device_init(struct wm8350 *wm8350, int irq,
1283 struct wm8350_platform_data *pdata)
1284 {
1285 int ret;
1286 u16 id1, id2, mask_rev;
1287 u16 cust_id, mode, chip_rev;
1288
1289 /* get WM8350 revision and config mode */
1290 ret = wm8350->read_dev(wm8350, WM8350_RESET_ID, sizeof(id1), &id1);
1291 if (ret != 0) {
1292 dev_err(wm8350->dev, "Failed to read ID: %d\n", ret);
1293 goto err;
1294 }
1295
1296 ret = wm8350->read_dev(wm8350, WM8350_ID, sizeof(id2), &id2);
1297 if (ret != 0) {
1298 dev_err(wm8350->dev, "Failed to read ID: %d\n", ret);
1299 goto err;
1300 }
1301
1302 ret = wm8350->read_dev(wm8350, WM8350_REVISION, sizeof(mask_rev),
1303 &mask_rev);
1304 if (ret != 0) {
1305 dev_err(wm8350->dev, "Failed to read revision: %d\n", ret);
1306 goto err;
1307 }
1308
1309 id1 = be16_to_cpu(id1);
1310 id2 = be16_to_cpu(id2);
1311 mask_rev = be16_to_cpu(mask_rev);
1312
1313 if (id1 != 0x6143) {
1314 dev_err(wm8350->dev,
1315 "Device with ID %x is not a WM8350\n", id1);
1316 ret = -ENODEV;
1317 goto err;
1318 }
1319
1320 mode = id2 & WM8350_CONF_STS_MASK >> 10;
1321 cust_id = id2 & WM8350_CUST_ID_MASK;
1322 chip_rev = (id2 & WM8350_CHIP_REV_MASK) >> 12;
1323 dev_info(wm8350->dev,
1324 "CONF_STS %d, CUST_ID %d, MASK_REV %d, CHIP_REV %d\n",
1325 mode, cust_id, mask_rev, chip_rev);
1326
1327 if (cust_id != 0) {
1328 dev_err(wm8350->dev, "Unsupported CUST_ID\n");
1329 ret = -ENODEV;
1330 goto err;
1331 }
1332
1333 switch (mask_rev) {
1334 case 0:
1335 wm8350->pmic.max_dcdc = WM8350_DCDC_6;
1336 wm8350->pmic.max_isink = WM8350_ISINK_B;
1337
1338 switch (chip_rev) {
1339 case WM8350_REV_E:
1340 dev_info(wm8350->dev, "WM8350 Rev E\n");
1341 break;
1342 case WM8350_REV_F:
1343 dev_info(wm8350->dev, "WM8350 Rev F\n");
1344 break;
1345 case WM8350_REV_G:
1346 dev_info(wm8350->dev, "WM8350 Rev G\n");
1347 wm8350->power.rev_g_coeff = 1;
1348 break;
1349 case WM8350_REV_H:
1350 dev_info(wm8350->dev, "WM8350 Rev H\n");
1351 wm8350->power.rev_g_coeff = 1;
1352 break;
1353 default:
1354 /* For safety we refuse to run on unknown hardware */
1355 dev_err(wm8350->dev, "Unknown WM8350 CHIP_REV\n");
1356 ret = -ENODEV;
1357 goto err;
1358 }
1359 break;
1360
1361 case 1:
1362 wm8350->pmic.max_dcdc = WM8350_DCDC_4;
1363 wm8350->pmic.max_isink = WM8350_ISINK_A;
1364
1365 switch (chip_rev) {
1366 case 0:
1367 dev_info(wm8350->dev, "WM8351 Rev A\n");
1368 wm8350->power.rev_g_coeff = 1;
1369 break;
1370
1371 case 1:
1372 dev_info(wm8350->dev, "WM8351 Rev B\n");
1373 wm8350->power.rev_g_coeff = 1;
1374 break;
1375
1376 default:
1377 dev_err(wm8350->dev, "Unknown WM8351 CHIP_REV\n");
1378 ret = -ENODEV;
1379 goto err;
1380 }
1381 break;
1382
1383 case 2:
1384 wm8350->pmic.max_dcdc = WM8350_DCDC_6;
1385 wm8350->pmic.max_isink = WM8350_ISINK_B;
1386
1387 switch (chip_rev) {
1388 case 0:
1389 dev_info(wm8350->dev, "WM8352 Rev A\n");
1390 wm8350->power.rev_g_coeff = 1;
1391 break;
1392
1393 default:
1394 dev_err(wm8350->dev, "Unknown WM8352 CHIP_REV\n");
1395 ret = -ENODEV;
1396 goto err;
1397 }
1398 break;
1399
1400 default:
1401 dev_err(wm8350->dev, "Unknown MASK_REV\n");
1402 ret = -ENODEV;
1403 goto err;
1404 }
1405
1406 ret = wm8350_create_cache(wm8350, mask_rev, mode);
1407 if (ret < 0) {
1408 dev_err(wm8350->dev, "Failed to create register cache\n");
1409 return ret;
1410 }
1411
1412 wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0xFFFF);
1413 wm8350_reg_write(wm8350, WM8350_INT_STATUS_1_MASK, 0xFFFF);
1414 wm8350_reg_write(wm8350, WM8350_INT_STATUS_2_MASK, 0xFFFF);
1415 wm8350_reg_write(wm8350, WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 0xFFFF);
1416 wm8350_reg_write(wm8350, WM8350_GPIO_INT_STATUS_MASK, 0xFFFF);
1417 wm8350_reg_write(wm8350, WM8350_COMPARATOR_INT_STATUS_MASK, 0xFFFF);
1418
1419 mutex_init(&wm8350->auxadc_mutex);
1420 mutex_init(&wm8350->irq_mutex);
1421 if (irq) {
1422 int flags = IRQF_ONESHOT;
1423
1424 if (pdata && pdata->irq_high) {
1425 flags |= IRQF_TRIGGER_HIGH;
1426
1427 wm8350_set_bits(wm8350, WM8350_SYSTEM_CONTROL_1,
1428 WM8350_IRQ_POL);
1429 } else {
1430 flags |= IRQF_TRIGGER_LOW;
1431
1432 wm8350_clear_bits(wm8350, WM8350_SYSTEM_CONTROL_1,
1433 WM8350_IRQ_POL);
1434 }
1435
1436 ret = request_threaded_irq(irq, NULL, wm8350_irq, flags,
1437 "wm8350", wm8350);
1438 if (ret != 0) {
1439 dev_err(wm8350->dev, "Failed to request IRQ: %d\n",
1440 ret);
1441 goto err;
1442 }
1443 } else {
1444 dev_err(wm8350->dev, "No IRQ configured\n");
1445 goto err;
1446 }
1447 wm8350->chip_irq = irq;
1448
1449 if (pdata && pdata->init) {
1450 ret = pdata->init(wm8350);
1451 if (ret != 0) {
1452 dev_err(wm8350->dev, "Platform init() failed: %d\n",
1453 ret);
1454 goto err;
1455 }
1456 }
1457
1458 wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0);
1459
1460 wm8350_client_dev_register(wm8350, "wm8350-codec",
1461 &(wm8350->codec.pdev));
1462 wm8350_client_dev_register(wm8350, "wm8350-gpio",
1463 &(wm8350->gpio.pdev));
1464 wm8350_client_dev_register(wm8350, "wm8350-hwmon",
1465 &(wm8350->hwmon.pdev));
1466 wm8350_client_dev_register(wm8350, "wm8350-power",
1467 &(wm8350->power.pdev));
1468 wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev));
1469 wm8350_client_dev_register(wm8350, "wm8350-wdt", &(wm8350->wdt.pdev));
1470
1471 return 0;
1472
1473 err:
1474 kfree(wm8350->reg_cache);
1475 return ret;
1476 }
1477 EXPORT_SYMBOL_GPL(wm8350_device_init);
1478
1479 void wm8350_device_exit(struct wm8350 *wm8350)
1480 {
1481 int i;
1482
1483 for (i = 0; i < ARRAY_SIZE(wm8350->pmic.led); i++)
1484 platform_device_unregister(wm8350->pmic.led[i].pdev);
1485
1486 for (i = 0; i < ARRAY_SIZE(wm8350->pmic.pdev); i++)
1487 platform_device_unregister(wm8350->pmic.pdev[i]);
1488
1489 platform_device_unregister(wm8350->wdt.pdev);
1490 platform_device_unregister(wm8350->rtc.pdev);
1491 platform_device_unregister(wm8350->power.pdev);
1492 platform_device_unregister(wm8350->hwmon.pdev);
1493 platform_device_unregister(wm8350->gpio.pdev);
1494 platform_device_unregister(wm8350->codec.pdev);
1495
1496 free_irq(wm8350->chip_irq, wm8350);
1497 kfree(wm8350->reg_cache);
1498 }
1499 EXPORT_SYMBOL_GPL(wm8350_device_exit);
1500
1501 MODULE_DESCRIPTION("WM8350 AudioPlus PMIC core driver");
1502 MODULE_LICENSE("GPL");
Linux with added FPC-III support