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x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / net / e100.c
blob3c29a20b751e831fd4d338ec316535cc7e43c093
1 /*******************************************************************************
2
3 Intel PRO/100 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
97 * IV. Receive
98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
109 * In order to keep updates to the RFD link field from colliding with
110 * hardware writes to mark packets complete, we use the feature that
111 * hardware will not write to a size 0 descriptor and mark the previous
112 * packet as end-of-list (EL). After updating the link, we remove EL
113 * and only then restore the size such that hardware may use the
114 * previous-to-end RFD.
115 *
116 * Under typical operation, the receive unit (RU) is start once,
117 * and the controller happily fills RFDs as frames arrive. If
118 * replacement RFDs cannot be allocated, or the RU goes non-active,
119 * the RU must be restarted. Frame arrival generates an interrupt,
120 * and Rx indication and re-allocation happen in the same context,
121 * therefore no locking is required. A software-generated interrupt
122 * is generated from the watchdog to recover from a failed allocation
123 * scenario where all Rx resources have been indicated and none re-
124 * placed.
125 *
126 * V. Miscellaneous
127 *
128 * VLAN offloading of tagging, stripping and filtering is not
129 * supported, but driver will accommodate the extra 4-byte VLAN tag
130 * for processing by upper layers. Tx/Rx Checksum offloading is not
131 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
132 * not supported (hardware limitation).
133 *
134 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
135 *
136 * Thanks to JC (jchapman@katalix.com) for helping with
137 * testing/troubleshooting the development driver.
138 *
139 * TODO:
140 * o several entry points race with dev->close
141 * o check for tx-no-resources/stop Q races with tx clean/wake Q
142 *
143 * FIXES:
144 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
145 * - Stratus87247: protect MDI control register manipulations
146 * 2009/06/01 - Andreas Mohr <andi at lisas dot de>
147 * - add clean lowlevel I/O emulation for cards with MII-lacking PHYs
148 */
149
150 #include <linux/module.h>
151 #include <linux/moduleparam.h>
152 #include <linux/kernel.h>
153 #include <linux/types.h>
154 #include <linux/sched.h>
155 #include <linux/slab.h>
156 #include <linux/delay.h>
157 #include <linux/init.h>
158 #include <linux/pci.h>
159 #include <linux/dma-mapping.h>
160 #include <linux/netdevice.h>
161 #include <linux/etherdevice.h>
162 #include <linux/mii.h>
163 #include <linux/if_vlan.h>
164 #include <linux/skbuff.h>
165 #include <linux/ethtool.h>
166 #include <linux/string.h>
167 #include <linux/firmware.h>
168 #include <asm/unaligned.h>
169
170
171 #define DRV_NAME "e100"
172 #define DRV_EXT "-NAPI"
173 #define DRV_VERSION "3.5.24-k2"DRV_EXT
174 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
175 #define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
176 #define PFX DRV_NAME ": "
177
178 #define E100_WATCHDOG_PERIOD (2 * HZ)
179 #define E100_NAPI_WEIGHT 16
180
181 #define FIRMWARE_D101M "e100/d101m_ucode.bin"
182 #define FIRMWARE_D101S "e100/d101s_ucode.bin"
183 #define FIRMWARE_D102E "e100/d102e_ucode.bin"
184
185 MODULE_DESCRIPTION(DRV_DESCRIPTION);
186 MODULE_AUTHOR(DRV_COPYRIGHT);
187 MODULE_LICENSE("GPL");
188 MODULE_VERSION(DRV_VERSION);
189 MODULE_FIRMWARE(FIRMWARE_D101M);
190 MODULE_FIRMWARE(FIRMWARE_D101S);
191 MODULE_FIRMWARE(FIRMWARE_D102E);
192
193 static int debug = 3;
194 static int eeprom_bad_csum_allow = 0;
195 static int use_io = 0;
196 module_param(debug, int, 0);
197 module_param(eeprom_bad_csum_allow, int, 0);
198 module_param(use_io, int, 0);
199 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
200 MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
201 MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
202 #define DPRINTK(nlevel, klevel, fmt, args...) \
203 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
204 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
205 __func__ , ## args))
206
207 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
208 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
209 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
210 static struct pci_device_id e100_id_table[] = {
211 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
212 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
213 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
214 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
215 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
216 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
217 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
218 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
219 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
220 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
221 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
222 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
223 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
224 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
225 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
226 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
227 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
228 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
229 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
230 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
231 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
232 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
233 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
234 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
235 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
236 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
237 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
238 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
239 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
240 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
241 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
242 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
243 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
244 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
245 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
246 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
247 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
248 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
249 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
250 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
251 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
252 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
253 { 0, }
254 };
255 MODULE_DEVICE_TABLE(pci, e100_id_table);
256
257 enum mac {
258 mac_82557_D100_A = 0,
259 mac_82557_D100_B = 1,
260 mac_82557_D100_C = 2,
261 mac_82558_D101_A4 = 4,
262 mac_82558_D101_B0 = 5,
263 mac_82559_D101M = 8,
264 mac_82559_D101S = 9,
265 mac_82550_D102 = 12,
266 mac_82550_D102_C = 13,
267 mac_82551_E = 14,
268 mac_82551_F = 15,
269 mac_82551_10 = 16,
270 mac_unknown = 0xFF,
271 };
272
273 enum phy {
274 phy_100a = 0x000003E0,
275 phy_100c = 0x035002A8,
276 phy_82555_tx = 0x015002A8,
277 phy_nsc_tx = 0x5C002000,
278 phy_82562_et = 0x033002A8,
279 phy_82562_em = 0x032002A8,
280 phy_82562_ek = 0x031002A8,
281 phy_82562_eh = 0x017002A8,
282 phy_82552_v = 0xd061004d,
283 phy_unknown = 0xFFFFFFFF,
284 };
285
286 /* CSR (Control/Status Registers) */
287 struct csr {
288 struct {
289 u8 status;
290 u8 stat_ack;
291 u8 cmd_lo;
292 u8 cmd_hi;
293 u32 gen_ptr;
294 } scb;
295 u32 port;
296 u16 flash_ctrl;
297 u8 eeprom_ctrl_lo;
298 u8 eeprom_ctrl_hi;
299 u32 mdi_ctrl;
300 u32 rx_dma_count;
301 };
302
303 enum scb_status {
304 rus_no_res = 0x08,
305 rus_ready = 0x10,
306 rus_mask = 0x3C,
307 };
308
309 enum ru_state {
310 RU_SUSPENDED = 0,
311 RU_RUNNING = 1,
312 RU_UNINITIALIZED = -1,
313 };
314
315 enum scb_stat_ack {
316 stat_ack_not_ours = 0x00,
317 stat_ack_sw_gen = 0x04,
318 stat_ack_rnr = 0x10,
319 stat_ack_cu_idle = 0x20,
320 stat_ack_frame_rx = 0x40,
321 stat_ack_cu_cmd_done = 0x80,
322 stat_ack_not_present = 0xFF,
323 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
324 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
325 };
326
327 enum scb_cmd_hi {
328 irq_mask_none = 0x00,
329 irq_mask_all = 0x01,
330 irq_sw_gen = 0x02,
331 };
332
333 enum scb_cmd_lo {
334 cuc_nop = 0x00,
335 ruc_start = 0x01,
336 ruc_load_base = 0x06,
337 cuc_start = 0x10,
338 cuc_resume = 0x20,
339 cuc_dump_addr = 0x40,
340 cuc_dump_stats = 0x50,
341 cuc_load_base = 0x60,
342 cuc_dump_reset = 0x70,
343 };
344
345 enum cuc_dump {
346 cuc_dump_complete = 0x0000A005,
347 cuc_dump_reset_complete = 0x0000A007,
348 };
349
350 enum port {
351 software_reset = 0x0000,
352 selftest = 0x0001,
353 selective_reset = 0x0002,
354 };
355
356 enum eeprom_ctrl_lo {
357 eesk = 0x01,
358 eecs = 0x02,
359 eedi = 0x04,
360 eedo = 0x08,
361 };
362
363 enum mdi_ctrl {
364 mdi_write = 0x04000000,
365 mdi_read = 0x08000000,
366 mdi_ready = 0x10000000,
367 };
368
369 enum eeprom_op {
370 op_write = 0x05,
371 op_read = 0x06,
372 op_ewds = 0x10,
373 op_ewen = 0x13,
374 };
375
376 enum eeprom_offsets {
377 eeprom_cnfg_mdix = 0x03,
378 eeprom_phy_iface = 0x06,
379 eeprom_id = 0x0A,
380 eeprom_config_asf = 0x0D,
381 eeprom_smbus_addr = 0x90,
382 };
383
384 enum eeprom_cnfg_mdix {
385 eeprom_mdix_enabled = 0x0080,
386 };
387
388 enum eeprom_phy_iface {
389 NoSuchPhy = 0,
390 I82553AB,
391 I82553C,
392 I82503,
393 DP83840,
394 S80C240,
395 S80C24,
396 I82555,
397 DP83840A = 10,
398 };
399
400 enum eeprom_id {
401 eeprom_id_wol = 0x0020,
402 };
403
404 enum eeprom_config_asf {
405 eeprom_asf = 0x8000,
406 eeprom_gcl = 0x4000,
407 };
408
409 enum cb_status {
410 cb_complete = 0x8000,
411 cb_ok = 0x2000,
412 };
413
414 enum cb_command {
415 cb_nop = 0x0000,
416 cb_iaaddr = 0x0001,
417 cb_config = 0x0002,
418 cb_multi = 0x0003,
419 cb_tx = 0x0004,
420 cb_ucode = 0x0005,
421 cb_dump = 0x0006,
422 cb_tx_sf = 0x0008,
423 cb_cid = 0x1f00,
424 cb_i = 0x2000,
425 cb_s = 0x4000,
426 cb_el = 0x8000,
427 };
428
429 struct rfd {
430 __le16 status;
431 __le16 command;
432 __le32 link;
433 __le32 rbd;
434 __le16 actual_size;
435 __le16 size;
436 };
437
438 struct rx {
439 struct rx *next, *prev;
440 struct sk_buff *skb;
441 dma_addr_t dma_addr;
442 };
443
444 #if defined(__BIG_ENDIAN_BITFIELD)
445 #define X(a,b) b,a
446 #else
447 #define X(a,b) a,b
448 #endif
449 struct config {
450 /*0*/ u8 X(byte_count:6, pad0:2);
451 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
452 /*2*/ u8 adaptive_ifs;
453 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
454 term_write_cache_line:1), pad3:4);
455 /*4*/ u8 X(rx_dma_max_count:7, pad4:1);
456 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
457 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
458 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
459 rx_discard_overruns:1), rx_save_bad_frames:1);
460 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
461 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
462 tx_dynamic_tbd:1);
463 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
464 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
465 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
466 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
467 loopback:2);
468 /*11*/ u8 X(linear_priority:3, pad11:5);
469 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
470 /*13*/ u8 ip_addr_lo;
471 /*14*/ u8 ip_addr_hi;
472 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
473 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
474 pad15_2:1), crs_or_cdt:1);
475 /*16*/ u8 fc_delay_lo;
476 /*17*/ u8 fc_delay_hi;
477 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
478 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
479 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
480 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
481 full_duplex_force:1), full_duplex_pin:1);
482 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
483 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
484 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
485 u8 pad_d102[9];
486 };
487
488 #define E100_MAX_MULTICAST_ADDRS 64
489 struct multi {
490 __le16 count;
491 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
492 };
493
494 /* Important: keep total struct u32-aligned */
495 #define UCODE_SIZE 134
496 struct cb {
497 __le16 status;
498 __le16 command;
499 __le32 link;
500 union {
501 u8 iaaddr[ETH_ALEN];
502 __le32 ucode[UCODE_SIZE];
503 struct config config;
504 struct multi multi;
505 struct {
506 u32 tbd_array;
507 u16 tcb_byte_count;
508 u8 threshold;
509 u8 tbd_count;
510 struct {
511 __le32 buf_addr;
512 __le16 size;
513 u16 eol;
514 } tbd;
515 } tcb;
516 __le32 dump_buffer_addr;
517 } u;
518 struct cb *next, *prev;
519 dma_addr_t dma_addr;
520 struct sk_buff *skb;
521 };
522
523 enum loopback {
524 lb_none = 0, lb_mac = 1, lb_phy = 3,
525 };
526
527 struct stats {
528 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions,
529 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
530 tx_multiple_collisions, tx_total_collisions;
531 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
532 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
533 rx_short_frame_errors;
534 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
535 __le16 xmt_tco_frames, rcv_tco_frames;
536 __le32 complete;
537 };
538
539 struct mem {
540 struct {
541 u32 signature;
542 u32 result;
543 } selftest;
544 struct stats stats;
545 u8 dump_buf[596];
546 };
547
548 struct param_range {
549 u32 min;
550 u32 max;
551 u32 count;
552 };
553
554 struct params {
555 struct param_range rfds;
556 struct param_range cbs;
557 };
558
559 struct nic {
560 /* Begin: frequently used values: keep adjacent for cache effect */
561 u32 msg_enable ____cacheline_aligned;
562 struct net_device *netdev;
563 struct pci_dev *pdev;
564 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data);
565
566 struct rx *rxs ____cacheline_aligned;
567 struct rx *rx_to_use;
568 struct rx *rx_to_clean;
569 struct rfd blank_rfd;
570 enum ru_state ru_running;
571
572 spinlock_t cb_lock ____cacheline_aligned;
573 spinlock_t cmd_lock;
574 struct csr __iomem *csr;
575 enum scb_cmd_lo cuc_cmd;
576 unsigned int cbs_avail;
577 struct napi_struct napi;
578 struct cb *cbs;
579 struct cb *cb_to_use;
580 struct cb *cb_to_send;
581 struct cb *cb_to_clean;
582 __le16 tx_command;
583 /* End: frequently used values: keep adjacent for cache effect */
584
585 enum {
586 ich = (1 << 0),
587 promiscuous = (1 << 1),
588 multicast_all = (1 << 2),
589 wol_magic = (1 << 3),
590 ich_10h_workaround = (1 << 4),
591 } flags ____cacheline_aligned;
592
593 enum mac mac;
594 enum phy phy;
595 struct params params;
596 struct timer_list watchdog;
597 struct timer_list blink_timer;
598 struct mii_if_info mii;
599 struct work_struct tx_timeout_task;
600 enum loopback loopback;
601
602 struct mem *mem;
603 dma_addr_t dma_addr;
604
605 dma_addr_t cbs_dma_addr;
606 u8 adaptive_ifs;
607 u8 tx_threshold;
608 u32 tx_frames;
609 u32 tx_collisions;
610 u32 tx_deferred;
611 u32 tx_single_collisions;
612 u32 tx_multiple_collisions;
613 u32 tx_fc_pause;
614 u32 tx_tco_frames;
615
616 u32 rx_fc_pause;
617 u32 rx_fc_unsupported;
618 u32 rx_tco_frames;
619 u32 rx_over_length_errors;
620
621 u16 leds;
622 u16 eeprom_wc;
623 __le16 eeprom[256];
624 spinlock_t mdio_lock;
625 };
626
627 static inline void e100_write_flush(struct nic *nic)
628 {
629 /* Flush previous PCI writes through intermediate bridges
630 * by doing a benign read */
631 (void)ioread8(&nic->csr->scb.status);
632 }
633
634 static void e100_enable_irq(struct nic *nic)
635 {
636 unsigned long flags;
637
638 spin_lock_irqsave(&nic->cmd_lock, flags);
639 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
640 e100_write_flush(nic);
641 spin_unlock_irqrestore(&nic->cmd_lock, flags);
642 }
643
644 static void e100_disable_irq(struct nic *nic)
645 {
646 unsigned long flags;
647
648 spin_lock_irqsave(&nic->cmd_lock, flags);
649 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
650 e100_write_flush(nic);
651 spin_unlock_irqrestore(&nic->cmd_lock, flags);
652 }
653
654 static void e100_hw_reset(struct nic *nic)
655 {
656 /* Put CU and RU into idle with a selective reset to get
657 * device off of PCI bus */
658 iowrite32(selective_reset, &nic->csr->port);
659 e100_write_flush(nic); udelay(20);
660
661 /* Now fully reset device */
662 iowrite32(software_reset, &nic->csr->port);
663 e100_write_flush(nic); udelay(20);
664
665 /* Mask off our interrupt line - it's unmasked after reset */
666 e100_disable_irq(nic);
667 }
668
669 static int e100_self_test(struct nic *nic)
670 {
671 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
672
673 /* Passing the self-test is a pretty good indication
674 * that the device can DMA to/from host memory */
675
676 nic->mem->selftest.signature = 0;
677 nic->mem->selftest.result = 0xFFFFFFFF;
678
679 iowrite32(selftest | dma_addr, &nic->csr->port);
680 e100_write_flush(nic);
681 /* Wait 10 msec for self-test to complete */
682 msleep(10);
683
684 /* Interrupts are enabled after self-test */
685 e100_disable_irq(nic);
686
687 /* Check results of self-test */
688 if (nic->mem->selftest.result != 0) {
689 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
690 nic->mem->selftest.result);
691 return -ETIMEDOUT;
692 }
693 if (nic->mem->selftest.signature == 0) {
694 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
695 return -ETIMEDOUT;
696 }
697
698 return 0;
699 }
700
701 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)
702 {
703 u32 cmd_addr_data[3];
704 u8 ctrl;
705 int i, j;
706
707 /* Three cmds: write/erase enable, write data, write/erase disable */
708 cmd_addr_data[0] = op_ewen << (addr_len - 2);
709 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
710 le16_to_cpu(data);
711 cmd_addr_data[2] = op_ewds << (addr_len - 2);
712
713 /* Bit-bang cmds to write word to eeprom */
714 for (j = 0; j < 3; j++) {
715
716 /* Chip select */
717 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
718 e100_write_flush(nic); udelay(4);
719
720 for (i = 31; i >= 0; i--) {
721 ctrl = (cmd_addr_data[j] & (1 << i)) ?
722 eecs | eedi : eecs;
723 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
724 e100_write_flush(nic); udelay(4);
725
726 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
727 e100_write_flush(nic); udelay(4);
728 }
729 /* Wait 10 msec for cmd to complete */
730 msleep(10);
731
732 /* Chip deselect */
733 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
734 e100_write_flush(nic); udelay(4);
735 }
736 };
737
738 /* General technique stolen from the eepro100 driver - very clever */
739 static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
740 {
741 u32 cmd_addr_data;
742 u16 data = 0;
743 u8 ctrl;
744 int i;
745
746 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
747
748 /* Chip select */
749 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
750 e100_write_flush(nic); udelay(4);
751
752 /* Bit-bang to read word from eeprom */
753 for (i = 31; i >= 0; i--) {
754 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
755 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
756 e100_write_flush(nic); udelay(4);
757
758 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
759 e100_write_flush(nic); udelay(4);
760
761 /* Eeprom drives a dummy zero to EEDO after receiving
762 * complete address. Use this to adjust addr_len. */
763 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
764 if (!(ctrl & eedo) && i > 16) {
765 *addr_len -= (i - 16);
766 i = 17;
767 }
768
769 data = (data << 1) | (ctrl & eedo ? 1 : 0);
770 }
771
772 /* Chip deselect */
773 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
774 e100_write_flush(nic); udelay(4);
775
776 return cpu_to_le16(data);
777 };
778
779 /* Load entire EEPROM image into driver cache and validate checksum */
780 static int e100_eeprom_load(struct nic *nic)
781 {
782 u16 addr, addr_len = 8, checksum = 0;
783
784 /* Try reading with an 8-bit addr len to discover actual addr len */
785 e100_eeprom_read(nic, &addr_len, 0);
786 nic->eeprom_wc = 1 << addr_len;
787
788 for (addr = 0; addr < nic->eeprom_wc; addr++) {
789 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
790 if (addr < nic->eeprom_wc - 1)
791 checksum += le16_to_cpu(nic->eeprom[addr]);
792 }
793
794 /* The checksum, stored in the last word, is calculated such that
795 * the sum of words should be 0xBABA */
796 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {
797 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
798 if (!eeprom_bad_csum_allow)
799 return -EAGAIN;
800 }
801
802 return 0;
803 }
804
805 /* Save (portion of) driver EEPROM cache to device and update checksum */
806 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
807 {
808 u16 addr, addr_len = 8, checksum = 0;
809
810 /* Try reading with an 8-bit addr len to discover actual addr len */
811 e100_eeprom_read(nic, &addr_len, 0);
812 nic->eeprom_wc = 1 << addr_len;
813
814 if (start + count >= nic->eeprom_wc)
815 return -EINVAL;
816
817 for (addr = start; addr < start + count; addr++)
818 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
819
820 /* The checksum, stored in the last word, is calculated such that
821 * the sum of words should be 0xBABA */
822 for (addr = 0; addr < nic->eeprom_wc - 1; addr++)
823 checksum += le16_to_cpu(nic->eeprom[addr]);
824 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);
825 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
826 nic->eeprom[nic->eeprom_wc - 1]);
827
828 return 0;
829 }
830
831 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
832 #define E100_WAIT_SCB_FAST 20 /* delay like the old code */
833 static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
834 {
835 unsigned long flags;
836 unsigned int i;
837 int err = 0;
838
839 spin_lock_irqsave(&nic->cmd_lock, flags);
840
841 /* Previous command is accepted when SCB clears */
842 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
843 if (likely(!ioread8(&nic->csr->scb.cmd_lo)))
844 break;
845 cpu_relax();
846 if (unlikely(i > E100_WAIT_SCB_FAST))
847 udelay(5);
848 }
849 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
850 err = -EAGAIN;
851 goto err_unlock;
852 }
853
854 if (unlikely(cmd != cuc_resume))
855 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
856 iowrite8(cmd, &nic->csr->scb.cmd_lo);
857
858 err_unlock:
859 spin_unlock_irqrestore(&nic->cmd_lock, flags);
860
861 return err;
862 }
863
864 static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
865 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
866 {
867 struct cb *cb;
868 unsigned long flags;
869 int err = 0;
870
871 spin_lock_irqsave(&nic->cb_lock, flags);
872
873 if (unlikely(!nic->cbs_avail)) {
874 err = -ENOMEM;
875 goto err_unlock;
876 }
877
878 cb = nic->cb_to_use;
879 nic->cb_to_use = cb->next;
880 nic->cbs_avail--;
881 cb->skb = skb;
882
883 if (unlikely(!nic->cbs_avail))
884 err = -ENOSPC;
885
886 cb_prepare(nic, cb, skb);
887
888 /* Order is important otherwise we'll be in a race with h/w:
889 * set S-bit in current first, then clear S-bit in previous. */
890 cb->command |= cpu_to_le16(cb_s);
891 wmb();
892 cb->prev->command &= cpu_to_le16(~cb_s);
893
894 while (nic->cb_to_send != nic->cb_to_use) {
895 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
896 nic->cb_to_send->dma_addr))) {
897 /* Ok, here's where things get sticky. It's
898 * possible that we can't schedule the command
899 * because the controller is too busy, so
900 * let's just queue the command and try again
901 * when another command is scheduled. */
902 if (err == -ENOSPC) {
903 //request a reset
904 schedule_work(&nic->tx_timeout_task);
905 }
906 break;
907 } else {
908 nic->cuc_cmd = cuc_resume;
909 nic->cb_to_send = nic->cb_to_send->next;
910 }
911 }
912
913 err_unlock:
914 spin_unlock_irqrestore(&nic->cb_lock, flags);
915
916 return err;
917 }
918
919 static int mdio_read(struct net_device *netdev, int addr, int reg)
920 {
921 struct nic *nic = netdev_priv(netdev);
922 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0);
923 }
924
925 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
926 {
927 struct nic *nic = netdev_priv(netdev);
928
929 nic->mdio_ctrl(nic, addr, mdi_write, reg, data);
930 }
931
932 /* the standard mdio_ctrl() function for usual MII-compliant hardware */
933 static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
934 {
935 u32 data_out = 0;
936 unsigned int i;
937 unsigned long flags;
938
939
940 /*
941 * Stratus87247: we shouldn't be writing the MDI control
942 * register until the Ready bit shows True. Also, since
943 * manipulation of the MDI control registers is a multi-step
944 * procedure it should be done under lock.
945 */
946 spin_lock_irqsave(&nic->mdio_lock, flags);
947 for (i = 100; i; --i) {
948 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
949 break;
950 udelay(20);
951 }
952 if (unlikely(!i)) {
953 printk("e100.mdio_ctrl(%s) won't go Ready\n",
954 nic->netdev->name );
955 spin_unlock_irqrestore(&nic->mdio_lock, flags);
956 return 0; /* No way to indicate timeout error */
957 }
958 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
959
960 for (i = 0; i < 100; i++) {
961 udelay(20);
962 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
963 break;
964 }
965 spin_unlock_irqrestore(&nic->mdio_lock, flags);
966 DPRINTK(HW, DEBUG,
967 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
968 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
969 return (u16)data_out;
970 }
971
972 /* slightly tweaked mdio_ctrl() function for phy_82552_v specifics */
973 static u16 mdio_ctrl_phy_82552_v(struct nic *nic,
974 u32 addr,
975 u32 dir,
976 u32 reg,
977 u16 data)
978 {
979 if ((reg == MII_BMCR) && (dir == mdi_write)) {
980 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) {
981 u16 advert = mdio_read(nic->netdev, nic->mii.phy_id,
982 MII_ADVERTISE);
983
984 /*
985 * Workaround Si issue where sometimes the part will not
986 * autoneg to 100Mbps even when advertised.
987 */
988 if (advert & ADVERTISE_100FULL)
989 data |= BMCR_SPEED100 | BMCR_FULLDPLX;
990 else if (advert & ADVERTISE_100HALF)
991 data |= BMCR_SPEED100;
992 }
993 }
994 return mdio_ctrl_hw(nic, addr, dir, reg, data);
995 }
996
997 /* Fully software-emulated mdio_ctrl() function for cards without
998 * MII-compliant PHYs.
999 * For now, this is mainly geared towards 80c24 support; in case of further
1000 * requirements for other types (i82503, ...?) either extend this mechanism
1001 * or split it, whichever is cleaner.
1002 */
1003 static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic,
1004 u32 addr,
1005 u32 dir,
1006 u32 reg,
1007 u16 data)
1008 {
1009 /* might need to allocate a netdev_priv'ed register array eventually
1010 * to be able to record state changes, but for now
1011 * some fully hardcoded register handling ought to be ok I guess. */
1012
1013 if (dir == mdi_read) {
1014 switch (reg) {
1015 case MII_BMCR:
1016 /* Auto-negotiation, right? */
1017 return BMCR_ANENABLE |
1018 BMCR_FULLDPLX;
1019 case MII_BMSR:
1020 return BMSR_LSTATUS /* for mii_link_ok() */ |
1021 BMSR_ANEGCAPABLE |
1022 BMSR_10FULL;
1023 case MII_ADVERTISE:
1024 /* 80c24 is a "combo card" PHY, right? */
1025 return ADVERTISE_10HALF |
1026 ADVERTISE_10FULL;
1027 default:
1028 DPRINTK(HW, DEBUG,
1029 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1030 dir == mdi_read ? "READ" : "WRITE", addr, reg, data);
1031 return 0xFFFF;
1032 }
1033 } else {
1034 switch (reg) {
1035 default:
1036 DPRINTK(HW, DEBUG,
1037 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1038 dir == mdi_read ? "READ" : "WRITE", addr, reg, data);
1039 return 0xFFFF;
1040 }
1041 }
1042 }
1043 static inline int e100_phy_supports_mii(struct nic *nic)
1044 {
1045 /* for now, just check it by comparing whether we
1046 are using MII software emulation.
1047 */
1048 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated);
1049 }
1050
1051 static void e100_get_defaults(struct nic *nic)
1052 {
1053 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
1054 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1055
1056 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
1057 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
1058 if (nic->mac == mac_unknown)
1059 nic->mac = mac_82557_D100_A;
1060
1061 nic->params.rfds = rfds;
1062 nic->params.cbs = cbs;
1063
1064 /* Quadwords to DMA into FIFO before starting frame transmit */
1065 nic->tx_threshold = 0xE0;
1066
1067 /* no interrupt for every tx completion, delay = 256us if not 557 */
1068 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
1069 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1070
1071 /* Template for a freshly allocated RFD */
1072 nic->blank_rfd.command = 0;
1073 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);
1074 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
1075
1076 /* MII setup */
1077 nic->mii.phy_id_mask = 0x1F;
1078 nic->mii.reg_num_mask = 0x1F;
1079 nic->mii.dev = nic->netdev;
1080 nic->mii.mdio_read = mdio_read;
1081 nic->mii.mdio_write = mdio_write;
1082 }
1083
1084 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1085 {
1086 struct config *config = &cb->u.config;
1087 u8 *c = (u8 *)config;
1088
1089 cb->command = cpu_to_le16(cb_config);
1090
1091 memset(config, 0, sizeof(struct config));
1092
1093 config->byte_count = 0x16; /* bytes in this struct */
1094 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
1095 config->direct_rx_dma = 0x1; /* reserved */
1096 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
1097 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
1098 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
1099 config->tx_underrun_retry = 0x3; /* # of underrun retries */
1100 if (e100_phy_supports_mii(nic))
1101 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */
1102 config->pad10 = 0x6;
1103 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
1104 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
1105 config->ifs = 0x6; /* x16 = inter frame spacing */
1106 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
1107 config->pad15_1 = 0x1;
1108 config->pad15_2 = 0x1;
1109 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
1110 config->fc_delay_hi = 0x40; /* time delay for fc frame */
1111 config->tx_padding = 0x1; /* 1=pad short frames */
1112 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
1113 config->pad18 = 0x1;
1114 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
1115 config->pad20_1 = 0x1F;
1116 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1117 config->pad21_1 = 0x5;
1118
1119 config->adaptive_ifs = nic->adaptive_ifs;
1120 config->loopback = nic->loopback;
1121
1122 if (nic->mii.force_media && nic->mii.full_duplex)
1123 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1124
1125 if (nic->flags & promiscuous || nic->loopback) {
1126 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1127 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1128 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1129 }
1130
1131 if (nic->flags & multicast_all)
1132 config->multicast_all = 0x1; /* 1=accept, 0=no */
1133
1134 /* disable WoL when up */
1135 if (netif_running(nic->netdev) || !(nic->flags & wol_magic))
1136 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1137
1138 if (nic->mac >= mac_82558_D101_A4) {
1139 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1140 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1141 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1142 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
1143 if (nic->mac >= mac_82559_D101M) {
1144 config->tno_intr = 0x1; /* TCO stats enable */
1145 /* Enable TCO in extended config */
1146 if (nic->mac >= mac_82551_10) {
1147 config->byte_count = 0x20; /* extended bytes */
1148 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1149 }
1150 } else {
1151 config->standard_stat_counter = 0x0;
1152 }
1153 }
1154
1155 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1156 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1157 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1158 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1159 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1160 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1161 }
1162
1163 /*************************************************************************
1164 * CPUSaver parameters
1165 *
1166 * All CPUSaver parameters are 16-bit literals that are part of a
1167 * "move immediate value" instruction. By changing the value of
1168 * the literal in the instruction before the code is loaded, the
1169 * driver can change the algorithm.
1170 *
1171 * INTDELAY - This loads the dead-man timer with its initial value.
1172 * When this timer expires the interrupt is asserted, and the
1173 * timer is reset each time a new packet is received. (see
1174 * BUNDLEMAX below to set the limit on number of chained packets)
1175 * The current default is 0x600 or 1536. Experiments show that
1176 * the value should probably stay within the 0x200 - 0x1000.
1177 *
1178 * BUNDLEMAX -
1179 * This sets the maximum number of frames that will be bundled. In
1180 * some situations, such as the TCP windowing algorithm, it may be
1181 * better to limit the growth of the bundle size than let it go as
1182 * high as it can, because that could cause too much added latency.
1183 * The default is six, because this is the number of packets in the
1184 * default TCP window size. A value of 1 would make CPUSaver indicate
1185 * an interrupt for every frame received. If you do not want to put
1186 * a limit on the bundle size, set this value to xFFFF.
1187 *
1188 * BUNDLESMALL -
1189 * This contains a bit-mask describing the minimum size frame that
1190 * will be bundled. The default masks the lower 7 bits, which means
1191 * that any frame less than 128 bytes in length will not be bundled,
1192 * but will instead immediately generate an interrupt. This does
1193 * not affect the current bundle in any way. Any frame that is 128
1194 * bytes or large will be bundled normally. This feature is meant
1195 * to provide immediate indication of ACK frames in a TCP environment.
1196 * Customers were seeing poor performance when a machine with CPUSaver
1197 * enabled was sending but not receiving. The delay introduced when
1198 * the ACKs were received was enough to reduce total throughput, because
1199 * the sender would sit idle until the ACK was finally seen.
1200 *
1201 * The current default is 0xFF80, which masks out the lower 7 bits.
1202 * This means that any frame which is x7F (127) bytes or smaller
1203 * will cause an immediate interrupt. Because this value must be a
1204 * bit mask, there are only a few valid values that can be used. To
1205 * turn this feature off, the driver can write the value xFFFF to the
1206 * lower word of this instruction (in the same way that the other
1207 * parameters are used). Likewise, a value of 0xF800 (2047) would
1208 * cause an interrupt to be generated for every frame, because all
1209 * standard Ethernet frames are <= 2047 bytes in length.
1210 *************************************************************************/
1211
1212 /* if you wish to disable the ucode functionality, while maintaining the
1213 * workarounds it provides, set the following defines to:
1214 * BUNDLESMALL 0
1215 * BUNDLEMAX 1
1216 * INTDELAY 1
1217 */
1218 #define BUNDLESMALL 1
1219 #define BUNDLEMAX (u16)6
1220 #define INTDELAY (u16)1536 /* 0x600 */
1221
1222 /* Initialize firmware */
1223 static const struct firmware *e100_request_firmware(struct nic *nic)
1224 {
1225 const char *fw_name;
1226 const struct firmware *fw;
1227 u8 timer, bundle, min_size;
1228 int err;
1229
1230 /* do not load u-code for ICH devices */
1231 if (nic->flags & ich)
1232 return NULL;
1233
1234 /* Search for ucode match against h/w revision */
1235 if (nic->mac == mac_82559_D101M)
1236 fw_name = FIRMWARE_D101M;
1237 else if (nic->mac == mac_82559_D101S)
1238 fw_name = FIRMWARE_D101S;
1239 else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10)
1240 fw_name = FIRMWARE_D102E;
1241 else /* No ucode on other devices */
1242 return NULL;
1243
1244 err = request_firmware(&fw, fw_name, &nic->pdev->dev);
1245 if (err) {
1246 DPRINTK(PROBE, ERR, "Failed to load firmware \"%s\": %d\n",
1247 fw_name, err);
1248 return ERR_PTR(err);
1249 }
1250 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes
1251 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */
1252 if (fw->size != UCODE_SIZE * 4 + 3) {
1253 DPRINTK(PROBE, ERR, "Firmware \"%s\" has wrong size %zu\n",
1254 fw_name, fw->size);
1255 release_firmware(fw);
1256 return ERR_PTR(-EINVAL);
1257 }
1258
1259 /* Read timer, bundle and min_size from end of firmware blob */
1260 timer = fw->data[UCODE_SIZE * 4];
1261 bundle = fw->data[UCODE_SIZE * 4 + 1];
1262 min_size = fw->data[UCODE_SIZE * 4 + 2];
1263
1264 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE ||
1265 min_size >= UCODE_SIZE) {
1266 DPRINTK(PROBE, ERR,
1267 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n",
1268 fw_name, timer, bundle, min_size);
1269 release_firmware(fw);
1270 return ERR_PTR(-EINVAL);
1271 }
1272 /* OK, firmware is validated and ready to use... */
1273 return fw;
1274 }
1275
1276 static void e100_setup_ucode(struct nic *nic, struct cb *cb,
1277 struct sk_buff *skb)
1278 {
1279 const struct firmware *fw = (void *)skb;
1280 u8 timer, bundle, min_size;
1281
1282 /* It's not a real skb; we just abused the fact that e100_exec_cb
1283 will pass it through to here... */
1284 cb->skb = NULL;
1285
1286 /* firmware is stored as little endian already */
1287 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4);
1288
1289 /* Read timer, bundle and min_size from end of firmware blob */
1290 timer = fw->data[UCODE_SIZE * 4];
1291 bundle = fw->data[UCODE_SIZE * 4 + 1];
1292 min_size = fw->data[UCODE_SIZE * 4 + 2];
1293
1294 /* Insert user-tunable settings in cb->u.ucode */
1295 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000);
1296 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY);
1297 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000);
1298 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX);
1299 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000);
1300 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80);
1301
1302 cb->command = cpu_to_le16(cb_ucode | cb_el);
1303 }
1304
1305 static inline int e100_load_ucode_wait(struct nic *nic)
1306 {
1307 const struct firmware *fw;
1308 int err = 0, counter = 50;
1309 struct cb *cb = nic->cb_to_clean;
1310
1311 fw = e100_request_firmware(nic);
1312 /* If it's NULL, then no ucode is required */
1313 if (!fw || IS_ERR(fw))
1314 return PTR_ERR(fw);
1315
1316 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
1317 DPRINTK(PROBE,ERR, "ucode cmd failed with error %d\n", err);
1318
1319 /* must restart cuc */
1320 nic->cuc_cmd = cuc_start;
1321
1322 /* wait for completion */
1323 e100_write_flush(nic);
1324 udelay(10);
1325
1326 /* wait for possibly (ouch) 500ms */
1327 while (!(cb->status & cpu_to_le16(cb_complete))) {
1328 msleep(10);
1329 if (!--counter) break;
1330 }
1331
1332 /* ack any interrupts, something could have been set */
1333 iowrite8(~0, &nic->csr->scb.stat_ack);
1334
1335 /* if the command failed, or is not OK, notify and return */
1336 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1337 DPRINTK(PROBE,ERR, "ucode load failed\n");
1338 err = -EPERM;
1339 }
1340
1341 return err;
1342 }
1343
1344 static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1345 struct sk_buff *skb)
1346 {
1347 cb->command = cpu_to_le16(cb_iaaddr);
1348 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1349 }
1350
1351 static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1352 {
1353 cb->command = cpu_to_le16(cb_dump);
1354 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1355 offsetof(struct mem, dump_buf));
1356 }
1357
1358 static int e100_phy_check_without_mii(struct nic *nic)
1359 {
1360 u8 phy_type;
1361 int without_mii;
1362
1363 phy_type = (nic->eeprom[eeprom_phy_iface] >> 8) & 0x0f;
1364
1365 switch (phy_type) {
1366 case NoSuchPhy: /* Non-MII PHY; UNTESTED! */
1367 case I82503: /* Non-MII PHY; UNTESTED! */
1368 case S80C24: /* Non-MII PHY; tested and working */
1369 /* paragraph from the FreeBSD driver, "FXP_PHY_80C24":
1370 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
1371 * doesn't have a programming interface of any sort. The
1372 * media is sensed automatically based on how the link partner
1373 * is configured. This is, in essence, manual configuration.
1374 */
1375 DPRINTK(PROBE, INFO,
1376 "found MII-less i82503 or 80c24 or other PHY\n");
1377
1378 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated;
1379 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */
1380
1381 /* these might be needed for certain MII-less cards...
1382 * nic->flags |= ich;
1383 * nic->flags |= ich_10h_workaround; */
1384
1385 without_mii = 1;
1386 break;
1387 default:
1388 without_mii = 0;
1389 break;
1390 }
1391 return without_mii;
1392 }
1393
1394 #define NCONFIG_AUTO_SWITCH 0x0080
1395 #define MII_NSC_CONG MII_RESV1
1396 #define NSC_CONG_ENABLE 0x0100
1397 #define NSC_CONG_TXREADY 0x0400
1398 #define ADVERTISE_FC_SUPPORTED 0x0400
1399 static int e100_phy_init(struct nic *nic)
1400 {
1401 struct net_device *netdev = nic->netdev;
1402 u32 addr;
1403 u16 bmcr, stat, id_lo, id_hi, cong;
1404
1405 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1406 for (addr = 0; addr < 32; addr++) {
1407 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1408 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1409 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1410 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1411 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1412 break;
1413 }
1414 if (addr == 32) {
1415 /* uhoh, no PHY detected: check whether we seem to be some
1416 * weird, rare variant which is *known* to not have any MII.
1417 * But do this AFTER MII checking only, since this does
1418 * lookup of EEPROM values which may easily be unreliable. */
1419 if (e100_phy_check_without_mii(nic))
1420 return 0; /* simply return and hope for the best */
1421 else {
1422 /* for unknown cases log a fatal error */
1423 DPRINTK(HW, ERR,
1424 "Failed to locate any known PHY, aborting.\n");
1425 return -EAGAIN;
1426 }
1427 } else
1428 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1429
1430 /* Get phy ID */
1431 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1432 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1433 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1434 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1435
1436 /* Select the phy and isolate the rest */
1437 for (addr = 0; addr < 32; addr++) {
1438 if (addr != nic->mii.phy_id) {
1439 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1440 } else if (nic->phy != phy_82552_v) {
1441 bmcr = mdio_read(netdev, addr, MII_BMCR);
1442 mdio_write(netdev, addr, MII_BMCR,
1443 bmcr & ~BMCR_ISOLATE);
1444 }
1445 }
1446 /*
1447 * Workaround for 82552:
1448 * Clear the ISOLATE bit on selected phy_id last (mirrored on all
1449 * other phy_id's) using bmcr value from addr discovery loop above.
1450 */
1451 if (nic->phy == phy_82552_v)
1452 mdio_write(netdev, nic->mii.phy_id, MII_BMCR,
1453 bmcr & ~BMCR_ISOLATE);
1454
1455 /* Handle National tx phys */
1456 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1457 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1458 /* Disable congestion control */
1459 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1460 cong |= NSC_CONG_TXREADY;
1461 cong &= ~NSC_CONG_ENABLE;
1462 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1463 }
1464
1465 if (nic->phy == phy_82552_v) {
1466 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
1467
1468 /* assign special tweaked mdio_ctrl() function */
1469 nic->mdio_ctrl = mdio_ctrl_phy_82552_v;
1470
1471 /* Workaround Si not advertising flow-control during autoneg */
1472 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1473 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert);
1474
1475 /* Reset for the above changes to take effect */
1476 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1477 bmcr |= BMCR_RESET;
1478 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1479 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1480 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1481 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1482 /* enable/disable MDI/MDI-X auto-switching. */
1483 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1484 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1485 }
1486
1487 return 0;
1488 }
1489
1490 static int e100_hw_init(struct nic *nic)
1491 {
1492 int err;
1493
1494 e100_hw_reset(nic);
1495
1496 DPRINTK(HW, ERR, "e100_hw_init\n");
1497 if (!in_interrupt() && (err = e100_self_test(nic)))
1498 return err;
1499
1500 if ((err = e100_phy_init(nic)))
1501 return err;
1502 if ((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1503 return err;
1504 if ((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1505 return err;
1506 if ((err = e100_load_ucode_wait(nic)))
1507 return err;
1508 if ((err = e100_exec_cb(nic, NULL, e100_configure)))
1509 return err;
1510 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1511 return err;
1512 if ((err = e100_exec_cmd(nic, cuc_dump_addr,
1513 nic->dma_addr + offsetof(struct mem, stats))))
1514 return err;
1515 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1516 return err;
1517
1518 e100_disable_irq(nic);
1519
1520 return 0;
1521 }
1522
1523 static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1524 {
1525 struct net_device *netdev = nic->netdev;
1526 struct dev_mc_list *list = netdev->mc_list;
1527 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1528
1529 cb->command = cpu_to_le16(cb_multi);
1530 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1531 for (i = 0; list && i < count; i++, list = list->next)
1532 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1533 ETH_ALEN);
1534 }
1535
1536 static void e100_set_multicast_list(struct net_device *netdev)
1537 {
1538 struct nic *nic = netdev_priv(netdev);
1539
1540 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1541 netdev->mc_count, netdev->flags);
1542
1543 if (netdev->flags & IFF_PROMISC)
1544 nic->flags |= promiscuous;
1545 else
1546 nic->flags &= ~promiscuous;
1547
1548 if (netdev->flags & IFF_ALLMULTI ||
1549 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1550 nic->flags |= multicast_all;
1551 else
1552 nic->flags &= ~multicast_all;
1553
1554 e100_exec_cb(nic, NULL, e100_configure);
1555 e100_exec_cb(nic, NULL, e100_multi);
1556 }
1557
1558 static void e100_update_stats(struct nic *nic)
1559 {
1560 struct net_device *dev = nic->netdev;
1561 struct net_device_stats *ns = &dev->stats;
1562 struct stats *s = &nic->mem->stats;
1563 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1564 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames :
1565 &s->complete;
1566
1567 /* Device's stats reporting may take several microseconds to
1568 * complete, so we're always waiting for results of the
1569 * previous command. */
1570
1571 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) {
1572 *complete = 0;
1573 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1574 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1575 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1576 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1577 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1578 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1579 ns->collisions += nic->tx_collisions;
1580 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1581 le32_to_cpu(s->tx_lost_crs);
1582 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1583 nic->rx_over_length_errors;
1584 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1585 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1586 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1587 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1588 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1589 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1590 le32_to_cpu(s->rx_alignment_errors) +
1591 le32_to_cpu(s->rx_short_frame_errors) +
1592 le32_to_cpu(s->rx_cdt_errors);
1593 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1594 nic->tx_single_collisions +=
1595 le32_to_cpu(s->tx_single_collisions);
1596 nic->tx_multiple_collisions +=
1597 le32_to_cpu(s->tx_multiple_collisions);
1598 if (nic->mac >= mac_82558_D101_A4) {
1599 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1600 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1601 nic->rx_fc_unsupported +=
1602 le32_to_cpu(s->fc_rcv_unsupported);
1603 if (nic->mac >= mac_82559_D101M) {
1604 nic->tx_tco_frames +=
1605 le16_to_cpu(s->xmt_tco_frames);
1606 nic->rx_tco_frames +=
1607 le16_to_cpu(s->rcv_tco_frames);
1608 }
1609 }
1610 }
1611
1612
1613 if (e100_exec_cmd(nic, cuc_dump_reset, 0))
1614 DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n");
1615 }
1616
1617 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1618 {
1619 /* Adjust inter-frame-spacing (IFS) between two transmits if
1620 * we're getting collisions on a half-duplex connection. */
1621
1622 if (duplex == DUPLEX_HALF) {
1623 u32 prev = nic->adaptive_ifs;
1624 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1625
1626 if ((nic->tx_frames / 32 < nic->tx_collisions) &&
1627 (nic->tx_frames > min_frames)) {
1628 if (nic->adaptive_ifs < 60)
1629 nic->adaptive_ifs += 5;
1630 } else if (nic->tx_frames < min_frames) {
1631 if (nic->adaptive_ifs >= 5)
1632 nic->adaptive_ifs -= 5;
1633 }
1634 if (nic->adaptive_ifs != prev)
1635 e100_exec_cb(nic, NULL, e100_configure);
1636 }
1637 }
1638
1639 static void e100_watchdog(unsigned long data)
1640 {
1641 struct nic *nic = (struct nic *)data;
1642 struct ethtool_cmd cmd;
1643
1644 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1645
1646 /* mii library handles link maintenance tasks */
1647
1648 mii_ethtool_gset(&nic->mii, &cmd);
1649
1650 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1651 printk(KERN_INFO "e100: %s NIC Link is Up %s Mbps %s Duplex\n",
1652 nic->netdev->name,
1653 cmd.speed == SPEED_100 ? "100" : "10",
1654 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1655 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1656 printk(KERN_INFO "e100: %s NIC Link is Down\n",
1657 nic->netdev->name);
1658 }
1659
1660 mii_check_link(&nic->mii);
1661
1662 /* Software generated interrupt to recover from (rare) Rx
1663 * allocation failure.
1664 * Unfortunately have to use a spinlock to not re-enable interrupts
1665 * accidentally, due to hardware that shares a register between the
1666 * interrupt mask bit and the SW Interrupt generation bit */
1667 spin_lock_irq(&nic->cmd_lock);
1668 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1669 e100_write_flush(nic);
1670 spin_unlock_irq(&nic->cmd_lock);
1671
1672 e100_update_stats(nic);
1673 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1674
1675 if (nic->mac <= mac_82557_D100_C)
1676 /* Issue a multicast command to workaround a 557 lock up */
1677 e100_set_multicast_list(nic->netdev);
1678
1679 if (nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1680 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1681 nic->flags |= ich_10h_workaround;
1682 else
1683 nic->flags &= ~ich_10h_workaround;
1684
1685 mod_timer(&nic->watchdog,
1686 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1687 }
1688
1689 static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1690 struct sk_buff *skb)
1691 {
1692 cb->command = nic->tx_command;
1693 /* interrupt every 16 packets regardless of delay */
1694 if ((nic->cbs_avail & ~15) == nic->cbs_avail)
1695 cb->command |= cpu_to_le16(cb_i);
1696 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1697 cb->u.tcb.tcb_byte_count = 0;
1698 cb->u.tcb.threshold = nic->tx_threshold;
1699 cb->u.tcb.tbd_count = 1;
1700 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1701 skb->data, skb->len, PCI_DMA_TODEVICE));
1702 /* check for mapping failure? */
1703 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1704 }
1705
1706 static netdev_tx_t e100_xmit_frame(struct sk_buff *skb,
1707 struct net_device *netdev)
1708 {
1709 struct nic *nic = netdev_priv(netdev);
1710 int err;
1711
1712 if (nic->flags & ich_10h_workaround) {
1713 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1714 Issue a NOP command followed by a 1us delay before
1715 issuing the Tx command. */
1716 if (e100_exec_cmd(nic, cuc_nop, 0))
1717 DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n");
1718 udelay(1);
1719 }
1720
1721 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1722
1723 switch (err) {
1724 case -ENOSPC:
1725 /* We queued the skb, but now we're out of space. */
1726 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1727 netif_stop_queue(netdev);
1728 break;
1729 case -ENOMEM:
1730 /* This is a hard error - log it. */
1731 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1732 netif_stop_queue(netdev);
1733 return NETDEV_TX_BUSY;
1734 }
1735
1736 netdev->trans_start = jiffies;
1737 return NETDEV_TX_OK;
1738 }
1739
1740 static int e100_tx_clean(struct nic *nic)
1741 {
1742 struct net_device *dev = nic->netdev;
1743 struct cb *cb;
1744 int tx_cleaned = 0;
1745
1746 spin_lock(&nic->cb_lock);
1747
1748 /* Clean CBs marked complete */
1749 for (cb = nic->cb_to_clean;
1750 cb->status & cpu_to_le16(cb_complete);
1751 cb = nic->cb_to_clean = cb->next) {
1752 DPRINTK(TX_DONE, DEBUG, "cb[%d]->status = 0x%04X\n",
1753 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1754 cb->status);
1755
1756 if (likely(cb->skb != NULL)) {
1757 dev->stats.tx_packets++;
1758 dev->stats.tx_bytes += cb->skb->len;
1759
1760 pci_unmap_single(nic->pdev,
1761 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1762 le16_to_cpu(cb->u.tcb.tbd.size),
1763 PCI_DMA_TODEVICE);
1764 dev_kfree_skb_any(cb->skb);
1765 cb->skb = NULL;
1766 tx_cleaned = 1;
1767 }
1768 cb->status = 0;
1769 nic->cbs_avail++;
1770 }
1771
1772 spin_unlock(&nic->cb_lock);
1773
1774 /* Recover from running out of Tx resources in xmit_frame */
1775 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1776 netif_wake_queue(nic->netdev);
1777
1778 return tx_cleaned;
1779 }
1780
1781 static void e100_clean_cbs(struct nic *nic)
1782 {
1783 if (nic->cbs) {
1784 while (nic->cbs_avail != nic->params.cbs.count) {
1785 struct cb *cb = nic->cb_to_clean;
1786 if (cb->skb) {
1787 pci_unmap_single(nic->pdev,
1788 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1789 le16_to_cpu(cb->u.tcb.tbd.size),
1790 PCI_DMA_TODEVICE);
1791 dev_kfree_skb(cb->skb);
1792 }
1793 nic->cb_to_clean = nic->cb_to_clean->next;
1794 nic->cbs_avail++;
1795 }
1796 pci_free_consistent(nic->pdev,
1797 sizeof(struct cb) * nic->params.cbs.count,
1798 nic->cbs, nic->cbs_dma_addr);
1799 nic->cbs = NULL;
1800 nic->cbs_avail = 0;
1801 }
1802 nic->cuc_cmd = cuc_start;
1803 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1804 nic->cbs;
1805 }
1806
1807 static int e100_alloc_cbs(struct nic *nic)
1808 {
1809 struct cb *cb;
1810 unsigned int i, count = nic->params.cbs.count;
1811
1812 nic->cuc_cmd = cuc_start;
1813 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1814 nic->cbs_avail = 0;
1815
1816 nic->cbs = pci_alloc_consistent(nic->pdev,
1817 sizeof(struct cb) * count, &nic->cbs_dma_addr);
1818 if (!nic->cbs)
1819 return -ENOMEM;
1820
1821 for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
1822 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1823 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1824
1825 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1826 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1827 ((i+1) % count) * sizeof(struct cb));
1828 cb->skb = NULL;
1829 }
1830
1831 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1832 nic->cbs_avail = count;
1833
1834 return 0;
1835 }
1836
1837 static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1838 {
1839 if (!nic->rxs) return;
1840 if (RU_SUSPENDED != nic->ru_running) return;
1841
1842 /* handle init time starts */
1843 if (!rx) rx = nic->rxs;
1844
1845 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1846 if (rx->skb) {
1847 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1848 nic->ru_running = RU_RUNNING;
1849 }
1850 }
1851
1852 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1853 static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1854 {
1855 if (!(rx->skb = netdev_alloc_skb(nic->netdev, RFD_BUF_LEN + NET_IP_ALIGN)))
1856 return -ENOMEM;
1857
1858 /* Align, init, and map the RFD. */
1859 skb_reserve(rx->skb, NET_IP_ALIGN);
1860 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1861 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1862 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1863
1864 if (pci_dma_mapping_error(nic->pdev, rx->dma_addr)) {
1865 dev_kfree_skb_any(rx->skb);
1866 rx->skb = NULL;
1867 rx->dma_addr = 0;
1868 return -ENOMEM;
1869 }
1870
1871 /* Link the RFD to end of RFA by linking previous RFD to
1872 * this one. We are safe to touch the previous RFD because
1873 * it is protected by the before last buffer's el bit being set */
1874 if (rx->prev->skb) {
1875 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1876 put_unaligned_le32(rx->dma_addr, &prev_rfd->link);
1877 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1878 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1879 }
1880
1881 return 0;
1882 }
1883
1884 static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1885 unsigned int *work_done, unsigned int work_to_do)
1886 {
1887 struct net_device *dev = nic->netdev;
1888 struct sk_buff *skb = rx->skb;
1889 struct rfd *rfd = (struct rfd *)skb->data;
1890 u16 rfd_status, actual_size;
1891
1892 if (unlikely(work_done && *work_done >= work_to_do))
1893 return -EAGAIN;
1894
1895 /* Need to sync before taking a peek at cb_complete bit */
1896 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1897 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1898 rfd_status = le16_to_cpu(rfd->status);
1899
1900 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1901
1902 /* If data isn't ready, nothing to indicate */
1903 if (unlikely(!(rfd_status & cb_complete))) {
1904 /* If the next buffer has the el bit, but we think the receiver
1905 * is still running, check to see if it really stopped while
1906 * we had interrupts off.
1907 * This allows for a fast restart without re-enabling
1908 * interrupts */
1909 if ((le16_to_cpu(rfd->command) & cb_el) &&
1910 (RU_RUNNING == nic->ru_running))
1911
1912 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1913 nic->ru_running = RU_SUSPENDED;
1914 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
1915 sizeof(struct rfd),
1916 PCI_DMA_FROMDEVICE);
1917 return -ENODATA;
1918 }
1919
1920 /* Get actual data size */
1921 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1922 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1923 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1924
1925 /* Get data */
1926 pci_unmap_single(nic->pdev, rx->dma_addr,
1927 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1928
1929 /* If this buffer has the el bit, but we think the receiver
1930 * is still running, check to see if it really stopped while
1931 * we had interrupts off.
1932 * This allows for a fast restart without re-enabling interrupts.
1933 * This can happen when the RU sees the size change but also sees
1934 * the el bit set. */
1935 if ((le16_to_cpu(rfd->command) & cb_el) &&
1936 (RU_RUNNING == nic->ru_running)) {
1937
1938 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1939 nic->ru_running = RU_SUSPENDED;
1940 }
1941
1942 /* Pull off the RFD and put the actual data (minus eth hdr) */
1943 skb_reserve(skb, sizeof(struct rfd));
1944 skb_put(skb, actual_size);
1945 skb->protocol = eth_type_trans(skb, nic->netdev);
1946
1947 if (unlikely(!(rfd_status & cb_ok))) {
1948 /* Don't indicate if hardware indicates errors */
1949 dev_kfree_skb_any(skb);
1950 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1951 /* Don't indicate oversized frames */
1952 nic->rx_over_length_errors++;
1953 dev_kfree_skb_any(skb);
1954 } else {
1955 dev->stats.rx_packets++;
1956 dev->stats.rx_bytes += actual_size;
1957 netif_receive_skb(skb);
1958 if (work_done)
1959 (*work_done)++;
1960 }
1961
1962 rx->skb = NULL;
1963
1964 return 0;
1965 }
1966
1967 static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1968 unsigned int work_to_do)
1969 {
1970 struct rx *rx;
1971 int restart_required = 0, err = 0;
1972 struct rx *old_before_last_rx, *new_before_last_rx;
1973 struct rfd *old_before_last_rfd, *new_before_last_rfd;
1974
1975 /* Indicate newly arrived packets */
1976 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1977 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
1978 /* Hit quota or no more to clean */
1979 if (-EAGAIN == err || -ENODATA == err)
1980 break;
1981 }
1982
1983
1984 /* On EAGAIN, hit quota so have more work to do, restart once
1985 * cleanup is complete.
1986 * Else, are we already rnr? then pay attention!!! this ensures that
1987 * the state machine progression never allows a start with a
1988 * partially cleaned list, avoiding a race between hardware
1989 * and rx_to_clean when in NAPI mode */
1990 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
1991 restart_required = 1;
1992
1993 old_before_last_rx = nic->rx_to_use->prev->prev;
1994 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
1995
1996 /* Alloc new skbs to refill list */
1997 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1998 if (unlikely(e100_rx_alloc_skb(nic, rx)))
1999 break; /* Better luck next time (see watchdog) */
2000 }
2001
2002 new_before_last_rx = nic->rx_to_use->prev->prev;
2003 if (new_before_last_rx != old_before_last_rx) {
2004 /* Set the el-bit on the buffer that is before the last buffer.
2005 * This lets us update the next pointer on the last buffer
2006 * without worrying about hardware touching it.
2007 * We set the size to 0 to prevent hardware from touching this
2008 * buffer.
2009 * When the hardware hits the before last buffer with el-bit
2010 * and size of 0, it will RNR interrupt, the RUS will go into
2011 * the No Resources state. It will not complete nor write to
2012 * this buffer. */
2013 new_before_last_rfd =
2014 (struct rfd *)new_before_last_rx->skb->data;
2015 new_before_last_rfd->size = 0;
2016 new_before_last_rfd->command |= cpu_to_le16(cb_el);
2017 pci_dma_sync_single_for_device(nic->pdev,
2018 new_before_last_rx->dma_addr, sizeof(struct rfd),
2019 PCI_DMA_BIDIRECTIONAL);
2020
2021 /* Now that we have a new stopping point, we can clear the old
2022 * stopping point. We must sync twice to get the proper
2023 * ordering on the hardware side of things. */
2024 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
2025 pci_dma_sync_single_for_device(nic->pdev,
2026 old_before_last_rx->dma_addr, sizeof(struct rfd),
2027 PCI_DMA_BIDIRECTIONAL);
2028 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
2029 pci_dma_sync_single_for_device(nic->pdev,
2030 old_before_last_rx->dma_addr, sizeof(struct rfd),
2031 PCI_DMA_BIDIRECTIONAL);
2032 }
2033
2034 if (restart_required) {
2035 // ack the rnr?
2036 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);
2037 e100_start_receiver(nic, nic->rx_to_clean);
2038 if (work_done)
2039 (*work_done)++;
2040 }
2041 }
2042
2043 static void e100_rx_clean_list(struct nic *nic)
2044 {
2045 struct rx *rx;
2046 unsigned int i, count = nic->params.rfds.count;
2047
2048 nic->ru_running = RU_UNINITIALIZED;
2049
2050 if (nic->rxs) {
2051 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2052 if (rx->skb) {
2053 pci_unmap_single(nic->pdev, rx->dma_addr,
2054 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2055 dev_kfree_skb(rx->skb);
2056 }
2057 }
2058 kfree(nic->rxs);
2059 nic->rxs = NULL;
2060 }
2061
2062 nic->rx_to_use = nic->rx_to_clean = NULL;
2063 }
2064
2065 static int e100_rx_alloc_list(struct nic *nic)
2066 {
2067 struct rx *rx;
2068 unsigned int i, count = nic->params.rfds.count;
2069 struct rfd *before_last;
2070
2071 nic->rx_to_use = nic->rx_to_clean = NULL;
2072 nic->ru_running = RU_UNINITIALIZED;
2073
2074 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_ATOMIC)))
2075 return -ENOMEM;
2076
2077 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2078 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
2079 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
2080 if (e100_rx_alloc_skb(nic, rx)) {
2081 e100_rx_clean_list(nic);
2082 return -ENOMEM;
2083 }
2084 }
2085 /* Set the el-bit on the buffer that is before the last buffer.
2086 * This lets us update the next pointer on the last buffer without
2087 * worrying about hardware touching it.
2088 * We set the size to 0 to prevent hardware from touching this buffer.
2089 * When the hardware hits the before last buffer with el-bit and size
2090 * of 0, it will RNR interrupt, the RU will go into the No Resources
2091 * state. It will not complete nor write to this buffer. */
2092 rx = nic->rxs->prev->prev;
2093 before_last = (struct rfd *)rx->skb->data;
2094 before_last->command |= cpu_to_le16(cb_el);
2095 before_last->size = 0;
2096 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
2097 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
2098
2099 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
2100 nic->ru_running = RU_SUSPENDED;
2101
2102 return 0;
2103 }
2104
2105 static irqreturn_t e100_intr(int irq, void *dev_id)
2106 {
2107 struct net_device *netdev = dev_id;
2108 struct nic *nic = netdev_priv(netdev);
2109 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
2110
2111 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
2112
2113 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */
2114 stat_ack == stat_ack_not_present) /* Hardware is ejected */
2115 return IRQ_NONE;
2116
2117 /* Ack interrupt(s) */
2118 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
2119
2120 /* We hit Receive No Resource (RNR); restart RU after cleaning */
2121 if (stat_ack & stat_ack_rnr)
2122 nic->ru_running = RU_SUSPENDED;
2123
2124 if (likely(napi_schedule_prep(&nic->napi))) {
2125 e100_disable_irq(nic);
2126 __napi_schedule(&nic->napi);
2127 }
2128
2129 return IRQ_HANDLED;
2130 }
2131
2132 static int e100_poll(struct napi_struct *napi, int budget)
2133 {
2134 struct nic *nic = container_of(napi, struct nic, napi);
2135 unsigned int work_done = 0;
2136
2137 e100_rx_clean(nic, &work_done, budget);
2138 e100_tx_clean(nic);
2139
2140 /* If budget not fully consumed, exit the polling mode */
2141 if (work_done < budget) {
2142 napi_complete(napi);
2143 e100_enable_irq(nic);
2144 }
2145
2146 return work_done;
2147 }
2148
2149 #ifdef CONFIG_NET_POLL_CONTROLLER
2150 static void e100_netpoll(struct net_device *netdev)
2151 {
2152 struct nic *nic = netdev_priv(netdev);
2153
2154 e100_disable_irq(nic);
2155 e100_intr(nic->pdev->irq, netdev);
2156 e100_tx_clean(nic);
2157 e100_enable_irq(nic);
2158 }
2159 #endif
2160
2161 static int e100_set_mac_address(struct net_device *netdev, void *p)
2162 {
2163 struct nic *nic = netdev_priv(netdev);
2164 struct sockaddr *addr = p;
2165
2166 if (!is_valid_ether_addr(addr->sa_data))
2167 return -EADDRNOTAVAIL;
2168
2169 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2170 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2171
2172 return 0;
2173 }
2174
2175 static int e100_change_mtu(struct net_device *netdev, int new_mtu)
2176 {
2177 if (new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
2178 return -EINVAL;
2179 netdev->mtu = new_mtu;
2180 return 0;
2181 }
2182
2183 static int e100_asf(struct nic *nic)
2184 {
2185 /* ASF can be enabled from eeprom */
2186 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2187 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2188 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2189 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
2190 }
2191
2192 static int e100_up(struct nic *nic)
2193 {
2194 int err;
2195
2196 if ((err = e100_rx_alloc_list(nic)))
2197 return err;
2198 if ((err = e100_alloc_cbs(nic)))
2199 goto err_rx_clean_list;
2200 if ((err = e100_hw_init(nic)))
2201 goto err_clean_cbs;
2202 e100_set_multicast_list(nic->netdev);
2203 e100_start_receiver(nic, NULL);
2204 mod_timer(&nic->watchdog, jiffies);
2205 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
2206 nic->netdev->name, nic->netdev)))
2207 goto err_no_irq;
2208 netif_wake_queue(nic->netdev);
2209 napi_enable(&nic->napi);
2210 /* enable ints _after_ enabling poll, preventing a race between
2211 * disable ints+schedule */
2212 e100_enable_irq(nic);
2213 return 0;
2214
2215 err_no_irq:
2216 del_timer_sync(&nic->watchdog);
2217 err_clean_cbs:
2218 e100_clean_cbs(nic);
2219 err_rx_clean_list:
2220 e100_rx_clean_list(nic);
2221 return err;
2222 }
2223
2224 static void e100_down(struct nic *nic)
2225 {
2226 /* wait here for poll to complete */
2227 napi_disable(&nic->napi);
2228 netif_stop_queue(nic->netdev);
2229 e100_hw_reset(nic);
2230 free_irq(nic->pdev->irq, nic->netdev);
2231 del_timer_sync(&nic->watchdog);
2232 netif_carrier_off(nic->netdev);
2233 e100_clean_cbs(nic);
2234 e100_rx_clean_list(nic);
2235 }
2236
2237 static void e100_tx_timeout(struct net_device *netdev)
2238 {
2239 struct nic *nic = netdev_priv(netdev);
2240
2241 /* Reset outside of interrupt context, to avoid request_irq
2242 * in interrupt context */
2243 schedule_work(&nic->tx_timeout_task);
2244 }
2245
2246 static void e100_tx_timeout_task(struct work_struct *work)
2247 {
2248 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2249 struct net_device *netdev = nic->netdev;
2250
2251 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
2252 ioread8(&nic->csr->scb.status));
2253 e100_down(netdev_priv(netdev));
2254 e100_up(netdev_priv(netdev));
2255 }
2256
2257 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2258 {
2259 int err;
2260 struct sk_buff *skb;
2261
2262 /* Use driver resources to perform internal MAC or PHY
2263 * loopback test. A single packet is prepared and transmitted
2264 * in loopback mode, and the test passes if the received
2265 * packet compares byte-for-byte to the transmitted packet. */
2266
2267 if ((err = e100_rx_alloc_list(nic)))
2268 return err;
2269 if ((err = e100_alloc_cbs(nic)))
2270 goto err_clean_rx;
2271
2272 /* ICH PHY loopback is broken so do MAC loopback instead */
2273 if (nic->flags & ich && loopback_mode == lb_phy)
2274 loopback_mode = lb_mac;
2275
2276 nic->loopback = loopback_mode;
2277 if ((err = e100_hw_init(nic)))
2278 goto err_loopback_none;
2279
2280 if (loopback_mode == lb_phy)
2281 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2282 BMCR_LOOPBACK);
2283
2284 e100_start_receiver(nic, NULL);
2285
2286 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2287 err = -ENOMEM;
2288 goto err_loopback_none;
2289 }
2290 skb_put(skb, ETH_DATA_LEN);
2291 memset(skb->data, 0xFF, ETH_DATA_LEN);
2292 e100_xmit_frame(skb, nic->netdev);
2293
2294 msleep(10);
2295
2296 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
2297 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2298
2299 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2300 skb->data, ETH_DATA_LEN))
2301 err = -EAGAIN;
2302
2303 err_loopback_none:
2304 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2305 nic->loopback = lb_none;
2306 e100_clean_cbs(nic);
2307 e100_hw_reset(nic);
2308 err_clean_rx:
2309 e100_rx_clean_list(nic);
2310 return err;
2311 }
2312
2313 #define MII_LED_CONTROL 0x1B
2314 #define E100_82552_LED_OVERRIDE 0x19
2315 #define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */
2316 #define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */
2317 static void e100_blink_led(unsigned long data)
2318 {
2319 struct nic *nic = (struct nic *)data;
2320 enum led_state {
2321 led_on = 0x01,
2322 led_off = 0x04,
2323 led_on_559 = 0x05,
2324 led_on_557 = 0x07,
2325 };
2326 u16 led_reg = MII_LED_CONTROL;
2327
2328 if (nic->phy == phy_82552_v) {
2329 led_reg = E100_82552_LED_OVERRIDE;
2330
2331 nic->leds = (nic->leds == E100_82552_LED_ON) ?
2332 E100_82552_LED_OFF : E100_82552_LED_ON;
2333 } else {
2334 nic->leds = (nic->leds & led_on) ? led_off :
2335 (nic->mac < mac_82559_D101M) ? led_on_557 :
2336 led_on_559;
2337 }
2338 mdio_write(nic->netdev, nic->mii.phy_id, led_reg, nic->leds);
2339 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
2340 }
2341
2342 static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2343 {
2344 struct nic *nic = netdev_priv(netdev);
2345 return mii_ethtool_gset(&nic->mii, cmd);
2346 }
2347
2348 static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2349 {
2350 struct nic *nic = netdev_priv(netdev);
2351 int err;
2352
2353 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2354 err = mii_ethtool_sset(&nic->mii, cmd);
2355 e100_exec_cb(nic, NULL, e100_configure);
2356
2357 return err;
2358 }
2359
2360 static void e100_get_drvinfo(struct net_device *netdev,
2361 struct ethtool_drvinfo *info)
2362 {
2363 struct nic *nic = netdev_priv(netdev);
2364 strcpy(info->driver, DRV_NAME);
2365 strcpy(info->version, DRV_VERSION);
2366 strcpy(info->fw_version, "N/A");
2367 strcpy(info->bus_info, pci_name(nic->pdev));
2368 }
2369
2370 #define E100_PHY_REGS 0x1C
2371 static int e100_get_regs_len(struct net_device *netdev)
2372 {
2373 struct nic *nic = netdev_priv(netdev);
2374 return 1 + E100_PHY_REGS + sizeof(nic->mem->dump_buf);
2375 }
2376
2377 static void e100_get_regs(struct net_device *netdev,
2378 struct ethtool_regs *regs, void *p)
2379 {
2380 struct nic *nic = netdev_priv(netdev);
2381 u32 *buff = p;
2382 int i;
2383
2384 regs->version = (1 << 24) | nic->pdev->revision;
2385 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2386 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2387 ioread16(&nic->csr->scb.status);
2388 for (i = E100_PHY_REGS; i >= 0; i--)
2389 buff[1 + E100_PHY_REGS - i] =
2390 mdio_read(netdev, nic->mii.phy_id, i);
2391 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2392 e100_exec_cb(nic, NULL, e100_dump);
2393 msleep(10);
2394 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2395 sizeof(nic->mem->dump_buf));
2396 }
2397
2398 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2399 {
2400 struct nic *nic = netdev_priv(netdev);
2401 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2402 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2403 }
2404
2405 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2406 {
2407 struct nic *nic = netdev_priv(netdev);
2408
2409 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) ||
2410 !device_can_wakeup(&nic->pdev->dev))
2411 return -EOPNOTSUPP;
2412
2413 if (wol->wolopts)
2414 nic->flags |= wol_magic;
2415 else
2416 nic->flags &= ~wol_magic;
2417
2418 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts);
2419
2420 e100_exec_cb(nic, NULL, e100_configure);
2421
2422 return 0;
2423 }
2424
2425 static u32 e100_get_msglevel(struct net_device *netdev)
2426 {
2427 struct nic *nic = netdev_priv(netdev);
2428 return nic->msg_enable;
2429 }
2430
2431 static void e100_set_msglevel(struct net_device *netdev, u32 value)
2432 {
2433 struct nic *nic = netdev_priv(netdev);
2434 nic->msg_enable = value;
2435 }
2436
2437 static int e100_nway_reset(struct net_device *netdev)
2438 {
2439 struct nic *nic = netdev_priv(netdev);
2440 return mii_nway_restart(&nic->mii);
2441 }
2442
2443 static u32 e100_get_link(struct net_device *netdev)
2444 {
2445 struct nic *nic = netdev_priv(netdev);
2446 return mii_link_ok(&nic->mii);
2447 }
2448
2449 static int e100_get_eeprom_len(struct net_device *netdev)
2450 {
2451 struct nic *nic = netdev_priv(netdev);
2452 return nic->eeprom_wc << 1;
2453 }
2454
2455 #define E100_EEPROM_MAGIC 0x1234
2456 static int e100_get_eeprom(struct net_device *netdev,
2457 struct ethtool_eeprom *eeprom, u8 *bytes)
2458 {
2459 struct nic *nic = netdev_priv(netdev);
2460
2461 eeprom->magic = E100_EEPROM_MAGIC;
2462 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2463
2464 return 0;
2465 }
2466
2467 static int e100_set_eeprom(struct net_device *netdev,
2468 struct ethtool_eeprom *eeprom, u8 *bytes)
2469 {
2470 struct nic *nic = netdev_priv(netdev);
2471
2472 if (eeprom->magic != E100_EEPROM_MAGIC)
2473 return -EINVAL;
2474
2475 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2476
2477 return e100_eeprom_save(nic, eeprom->offset >> 1,
2478 (eeprom->len >> 1) + 1);
2479 }
2480
2481 static void e100_get_ringparam(struct net_device *netdev,
2482 struct ethtool_ringparam *ring)
2483 {
2484 struct nic *nic = netdev_priv(netdev);
2485 struct param_range *rfds = &nic->params.rfds;
2486 struct param_range *cbs = &nic->params.cbs;
2487
2488 ring->rx_max_pending = rfds->max;
2489 ring->tx_max_pending = cbs->max;
2490 ring->rx_mini_max_pending = 0;
2491 ring->rx_jumbo_max_pending = 0;
2492 ring->rx_pending = rfds->count;
2493 ring->tx_pending = cbs->count;
2494 ring->rx_mini_pending = 0;
2495 ring->rx_jumbo_pending = 0;
2496 }
2497
2498 static int e100_set_ringparam(struct net_device *netdev,
2499 struct ethtool_ringparam *ring)
2500 {
2501 struct nic *nic = netdev_priv(netdev);
2502 struct param_range *rfds = &nic->params.rfds;
2503 struct param_range *cbs = &nic->params.cbs;
2504
2505 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2506 return -EINVAL;
2507
2508 if (netif_running(netdev))
2509 e100_down(nic);
2510 rfds->count = max(ring->rx_pending, rfds->min);
2511 rfds->count = min(rfds->count, rfds->max);
2512 cbs->count = max(ring->tx_pending, cbs->min);
2513 cbs->count = min(cbs->count, cbs->max);
2514 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
2515 rfds->count, cbs->count);
2516 if (netif_running(netdev))
2517 e100_up(nic);
2518
2519 return 0;
2520 }
2521
2522 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2523 "Link test (on/offline)",
2524 "Eeprom test (on/offline)",
2525 "Self test (offline)",
2526 "Mac loopback (offline)",
2527 "Phy loopback (offline)",
2528 };
2529 #define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
2530
2531 static void e100_diag_test(struct net_device *netdev,
2532 struct ethtool_test *test, u64 *data)
2533 {
2534 struct ethtool_cmd cmd;
2535 struct nic *nic = netdev_priv(netdev);
2536 int i, err;
2537
2538 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2539 data[0] = !mii_link_ok(&nic->mii);
2540 data[1] = e100_eeprom_load(nic);
2541 if (test->flags & ETH_TEST_FL_OFFLINE) {
2542
2543 /* save speed, duplex & autoneg settings */
2544 err = mii_ethtool_gset(&nic->mii, &cmd);
2545
2546 if (netif_running(netdev))
2547 e100_down(nic);
2548 data[2] = e100_self_test(nic);
2549 data[3] = e100_loopback_test(nic, lb_mac);
2550 data[4] = e100_loopback_test(nic, lb_phy);
2551
2552 /* restore speed, duplex & autoneg settings */
2553 err = mii_ethtool_sset(&nic->mii, &cmd);
2554
2555 if (netif_running(netdev))
2556 e100_up(nic);
2557 }
2558 for (i = 0; i < E100_TEST_LEN; i++)
2559 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2560
2561 msleep_interruptible(4 * 1000);
2562 }
2563
2564 static int e100_phys_id(struct net_device *netdev, u32 data)
2565 {
2566 struct nic *nic = netdev_priv(netdev);
2567 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE :
2568 MII_LED_CONTROL;
2569
2570 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2571 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2572 mod_timer(&nic->blink_timer, jiffies);
2573 msleep_interruptible(data * 1000);
2574 del_timer_sync(&nic->blink_timer);
2575 mdio_write(netdev, nic->mii.phy_id, led_reg, 0);
2576
2577 return 0;
2578 }
2579
2580 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2581 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2582 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2583 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2584 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2585 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2586 "tx_heartbeat_errors", "tx_window_errors",
2587 /* device-specific stats */
2588 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2589 "tx_flow_control_pause", "rx_flow_control_pause",
2590 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2591 };
2592 #define E100_NET_STATS_LEN 21
2593 #define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
2594
2595 static int e100_get_sset_count(struct net_device *netdev, int sset)
2596 {
2597 switch (sset) {
2598 case ETH_SS_TEST:
2599 return E100_TEST_LEN;
2600 case ETH_SS_STATS:
2601 return E100_STATS_LEN;
2602 default:
2603 return -EOPNOTSUPP;
2604 }
2605 }
2606
2607 static void e100_get_ethtool_stats(struct net_device *netdev,
2608 struct ethtool_stats *stats, u64 *data)
2609 {
2610 struct nic *nic = netdev_priv(netdev);
2611 int i;
2612
2613 for (i = 0; i < E100_NET_STATS_LEN; i++)
2614 data[i] = ((unsigned long *)&netdev->stats)[i];
2615
2616 data[i++] = nic->tx_deferred;
2617 data[i++] = nic->tx_single_collisions;
2618 data[i++] = nic->tx_multiple_collisions;
2619 data[i++] = nic->tx_fc_pause;
2620 data[i++] = nic->rx_fc_pause;
2621 data[i++] = nic->rx_fc_unsupported;
2622 data[i++] = nic->tx_tco_frames;
2623 data[i++] = nic->rx_tco_frames;
2624 }
2625
2626 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2627 {
2628 switch (stringset) {
2629 case ETH_SS_TEST:
2630 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2631 break;
2632 case ETH_SS_STATS:
2633 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2634 break;
2635 }
2636 }
2637
2638 static const struct ethtool_ops e100_ethtool_ops = {
2639 .get_settings = e100_get_settings,
2640 .set_settings = e100_set_settings,
2641 .get_drvinfo = e100_get_drvinfo,
2642 .get_regs_len = e100_get_regs_len,
2643 .get_regs = e100_get_regs,
2644 .get_wol = e100_get_wol,
2645 .set_wol = e100_set_wol,
2646 .get_msglevel = e100_get_msglevel,
2647 .set_msglevel = e100_set_msglevel,
2648 .nway_reset = e100_nway_reset,
2649 .get_link = e100_get_link,
2650 .get_eeprom_len = e100_get_eeprom_len,
2651 .get_eeprom = e100_get_eeprom,
2652 .set_eeprom = e100_set_eeprom,
2653 .get_ringparam = e100_get_ringparam,
2654 .set_ringparam = e100_set_ringparam,
2655 .self_test = e100_diag_test,
2656 .get_strings = e100_get_strings,
2657 .phys_id = e100_phys_id,
2658 .get_ethtool_stats = e100_get_ethtool_stats,
2659 .get_sset_count = e100_get_sset_count,
2660 };
2661
2662 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2663 {
2664 struct nic *nic = netdev_priv(netdev);
2665
2666 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2667 }
2668
2669 static int e100_alloc(struct nic *nic)
2670 {
2671 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2672 &nic->dma_addr);
2673 return nic->mem ? 0 : -ENOMEM;
2674 }
2675
2676 static void e100_free(struct nic *nic)
2677 {
2678 if (nic->mem) {
2679 pci_free_consistent(nic->pdev, sizeof(struct mem),
2680 nic->mem, nic->dma_addr);
2681 nic->mem = NULL;
2682 }
2683 }
2684
2685 static int e100_open(struct net_device *netdev)
2686 {
2687 struct nic *nic = netdev_priv(netdev);
2688 int err = 0;
2689
2690 netif_carrier_off(netdev);
2691 if ((err = e100_up(nic)))
2692 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2693 return err;
2694 }
2695
2696 static int e100_close(struct net_device *netdev)
2697 {
2698 e100_down(netdev_priv(netdev));
2699 return 0;
2700 }
2701
2702 static const struct net_device_ops e100_netdev_ops = {
2703 .ndo_open = e100_open,
2704 .ndo_stop = e100_close,
2705 .ndo_start_xmit = e100_xmit_frame,
2706 .ndo_validate_addr = eth_validate_addr,
2707 .ndo_set_multicast_list = e100_set_multicast_list,
2708 .ndo_set_mac_address = e100_set_mac_address,
2709 .ndo_change_mtu = e100_change_mtu,
2710 .ndo_do_ioctl = e100_do_ioctl,
2711 .ndo_tx_timeout = e100_tx_timeout,
2712 #ifdef CONFIG_NET_POLL_CONTROLLER
2713 .ndo_poll_controller = e100_netpoll,
2714 #endif
2715 };
2716
2717 static int __devinit e100_probe(struct pci_dev *pdev,
2718 const struct pci_device_id *ent)
2719 {
2720 struct net_device *netdev;
2721 struct nic *nic;
2722 int err;
2723
2724 if (!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2725 if (((1 << debug) - 1) & NETIF_MSG_PROBE)
2726 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2727 return -ENOMEM;
2728 }
2729
2730 netdev->netdev_ops = &e100_netdev_ops;
2731 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2732 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2733 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2734
2735 nic = netdev_priv(netdev);
2736 netif_napi_add(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
2737 nic->netdev = netdev;
2738 nic->pdev = pdev;
2739 nic->msg_enable = (1 << debug) - 1;
2740 nic->mdio_ctrl = mdio_ctrl_hw;
2741 pci_set_drvdata(pdev, netdev);
2742
2743 if ((err = pci_enable_device(pdev))) {
2744 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2745 goto err_out_free_dev;
2746 }
2747
2748 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2749 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2750 "base address, aborting.\n");
2751 err = -ENODEV;
2752 goto err_out_disable_pdev;
2753 }
2754
2755 if ((err = pci_request_regions(pdev, DRV_NAME))) {
2756 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2757 goto err_out_disable_pdev;
2758 }
2759
2760 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
2761 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2762 goto err_out_free_res;
2763 }
2764
2765 SET_NETDEV_DEV(netdev, &pdev->dev);
2766
2767 if (use_io)
2768 DPRINTK(PROBE, INFO, "using i/o access mode\n");
2769
2770 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
2771 if (!nic->csr) {
2772 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2773 err = -ENOMEM;
2774 goto err_out_free_res;
2775 }
2776
2777 if (ent->driver_data)
2778 nic->flags |= ich;
2779 else
2780 nic->flags &= ~ich;
2781
2782 e100_get_defaults(nic);
2783
2784 /* locks must be initialized before calling hw_reset */
2785 spin_lock_init(&nic->cb_lock);
2786 spin_lock_init(&nic->cmd_lock);
2787 spin_lock_init(&nic->mdio_lock);
2788
2789 /* Reset the device before pci_set_master() in case device is in some
2790 * funky state and has an interrupt pending - hint: we don't have the
2791 * interrupt handler registered yet. */
2792 e100_hw_reset(nic);
2793
2794 pci_set_master(pdev);
2795
2796 init_timer(&nic->watchdog);
2797 nic->watchdog.function = e100_watchdog;
2798 nic->watchdog.data = (unsigned long)nic;
2799 init_timer(&nic->blink_timer);
2800 nic->blink_timer.function = e100_blink_led;
2801 nic->blink_timer.data = (unsigned long)nic;
2802
2803 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2804
2805 if ((err = e100_alloc(nic))) {
2806 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2807 goto err_out_iounmap;
2808 }
2809
2810 if ((err = e100_eeprom_load(nic)))
2811 goto err_out_free;
2812
2813 e100_phy_init(nic);
2814
2815 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2816 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
2817 if (!is_valid_ether_addr(netdev->perm_addr)) {
2818 if (!eeprom_bad_csum_allow) {
2819 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2820 "EEPROM, aborting.\n");
2821 err = -EAGAIN;
2822 goto err_out_free;
2823 } else {
2824 DPRINTK(PROBE, ERR, "Invalid MAC address from EEPROM, "
2825 "you MUST configure one.\n");
2826 }
2827 }
2828
2829 /* Wol magic packet can be enabled from eeprom */
2830 if ((nic->mac >= mac_82558_D101_A4) &&
2831 (nic->eeprom[eeprom_id] & eeprom_id_wol)) {
2832 nic->flags |= wol_magic;
2833 device_set_wakeup_enable(&pdev->dev, true);
2834 }
2835
2836 /* ack any pending wake events, disable PME */
2837 pci_pme_active(pdev, false);
2838
2839 strcpy(netdev->name, "eth%d");
2840 if ((err = register_netdev(netdev))) {
2841 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2842 goto err_out_free;
2843 }
2844
2845 DPRINTK(PROBE, INFO, "addr 0x%llx, irq %d, MAC addr %pM\n",
2846 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
2847 pdev->irq, netdev->dev_addr);
2848
2849 return 0;
2850
2851 err_out_free:
2852 e100_free(nic);
2853 err_out_iounmap:
2854 pci_iounmap(pdev, nic->csr);
2855 err_out_free_res:
2856 pci_release_regions(pdev);
2857 err_out_disable_pdev:
2858 pci_disable_device(pdev);
2859 err_out_free_dev:
2860 pci_set_drvdata(pdev, NULL);
2861 free_netdev(netdev);
2862 return err;
2863 }
2864
2865 static void __devexit e100_remove(struct pci_dev *pdev)
2866 {
2867 struct net_device *netdev = pci_get_drvdata(pdev);
2868
2869 if (netdev) {
2870 struct nic *nic = netdev_priv(netdev);
2871 unregister_netdev(netdev);
2872 e100_free(nic);
2873 pci_iounmap(pdev, nic->csr);
2874 free_netdev(netdev);
2875 pci_release_regions(pdev);
2876 pci_disable_device(pdev);
2877 pci_set_drvdata(pdev, NULL);
2878 }
2879 }
2880
2881 #define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */
2882 #define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */
2883 #define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */
2884 static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake)
2885 {
2886 struct net_device *netdev = pci_get_drvdata(pdev);
2887 struct nic *nic = netdev_priv(netdev);
2888
2889 if (netif_running(netdev))
2890 e100_down(nic);
2891 netif_device_detach(netdev);
2892
2893 pci_save_state(pdev);
2894
2895 if ((nic->flags & wol_magic) | e100_asf(nic)) {
2896 /* enable reverse auto-negotiation */
2897 if (nic->phy == phy_82552_v) {
2898 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2899 E100_82552_SMARTSPEED);
2900
2901 mdio_write(netdev, nic->mii.phy_id,
2902 E100_82552_SMARTSPEED, smartspeed |
2903 E100_82552_REV_ANEG | E100_82552_ANEG_NOW);
2904 }
2905 *enable_wake = true;
2906 } else {
2907 *enable_wake = false;
2908 }
2909
2910 pci_disable_device(pdev);
2911 }
2912
2913 static int __e100_power_off(struct pci_dev *pdev, bool wake)
2914 {
2915 if (wake)
2916 return pci_prepare_to_sleep(pdev);
2917
2918 pci_wake_from_d3(pdev, false);
2919 pci_set_power_state(pdev, PCI_D3hot);
2920
2921 return 0;
2922 }
2923
2924 #ifdef CONFIG_PM
2925 static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2926 {
2927 bool wake;
2928 __e100_shutdown(pdev, &wake);
2929 return __e100_power_off(pdev, wake);
2930 }
2931
2932 static int e100_resume(struct pci_dev *pdev)
2933 {
2934 struct net_device *netdev = pci_get_drvdata(pdev);
2935 struct nic *nic = netdev_priv(netdev);
2936
2937 pci_set_power_state(pdev, PCI_D0);
2938 pci_restore_state(pdev);
2939 /* ack any pending wake events, disable PME */
2940 pci_enable_wake(pdev, 0, 0);
2941
2942 /* disable reverse auto-negotiation */
2943 if (nic->phy == phy_82552_v) {
2944 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2945 E100_82552_SMARTSPEED);
2946
2947 mdio_write(netdev, nic->mii.phy_id,
2948 E100_82552_SMARTSPEED,
2949 smartspeed & ~(E100_82552_REV_ANEG));
2950 }
2951
2952 netif_device_attach(netdev);
2953 if (netif_running(netdev))
2954 e100_up(nic);
2955
2956 return 0;
2957 }
2958 #endif /* CONFIG_PM */
2959
2960 static void e100_shutdown(struct pci_dev *pdev)
2961 {
2962 bool wake;
2963 __e100_shutdown(pdev, &wake);
2964 if (system_state == SYSTEM_POWER_OFF)
2965 __e100_power_off(pdev, wake);
2966 }
2967
2968 /* ------------------ PCI Error Recovery infrastructure -------------- */
2969 /**
2970 * e100_io_error_detected - called when PCI error is detected.
2971 * @pdev: Pointer to PCI device
2972 * @state: The current pci connection state
2973 */
2974 static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2975 {
2976 struct net_device *netdev = pci_get_drvdata(pdev);
2977 struct nic *nic = netdev_priv(netdev);
2978
2979 netif_device_detach(netdev);
2980
2981 if (state == pci_channel_io_perm_failure)
2982 return PCI_ERS_RESULT_DISCONNECT;
2983
2984 if (netif_running(netdev))
2985 e100_down(nic);
2986 pci_disable_device(pdev);
2987
2988 /* Request a slot reset. */
2989 return PCI_ERS_RESULT_NEED_RESET;
2990 }
2991
2992 /**
2993 * e100_io_slot_reset - called after the pci bus has been reset.
2994 * @pdev: Pointer to PCI device
2995 *
2996 * Restart the card from scratch.
2997 */
2998 static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
2999 {
3000 struct net_device *netdev = pci_get_drvdata(pdev);
3001 struct nic *nic = netdev_priv(netdev);
3002
3003 if (pci_enable_device(pdev)) {
3004 printk(KERN_ERR "e100: Cannot re-enable PCI device after reset.\n");
3005 return PCI_ERS_RESULT_DISCONNECT;
3006 }
3007 pci_set_master(pdev);
3008
3009 /* Only one device per card can do a reset */
3010 if (0 != PCI_FUNC(pdev->devfn))
3011 return PCI_ERS_RESULT_RECOVERED;
3012 e100_hw_reset(nic);
3013 e100_phy_init(nic);
3014
3015 return PCI_ERS_RESULT_RECOVERED;
3016 }
3017
3018 /**
3019 * e100_io_resume - resume normal operations
3020 * @pdev: Pointer to PCI device
3021 *
3022 * Resume normal operations after an error recovery
3023 * sequence has been completed.
3024 */
3025 static void e100_io_resume(struct pci_dev *pdev)
3026 {
3027 struct net_device *netdev = pci_get_drvdata(pdev);
3028 struct nic *nic = netdev_priv(netdev);
3029
3030 /* ack any pending wake events, disable PME */
3031 pci_enable_wake(pdev, 0, 0);
3032
3033 netif_device_attach(netdev);
3034 if (netif_running(netdev)) {
3035 e100_open(netdev);
3036 mod_timer(&nic->watchdog, jiffies);
3037 }
3038 }
3039
3040 static struct pci_error_handlers e100_err_handler = {
3041 .error_detected = e100_io_error_detected,
3042 .slot_reset = e100_io_slot_reset,
3043 .resume = e100_io_resume,
3044 };
3045
3046 static struct pci_driver e100_driver = {
3047 .name = DRV_NAME,
3048 .id_table = e100_id_table,
3049 .probe = e100_probe,
3050 .remove = __devexit_p(e100_remove),
3051 #ifdef CONFIG_PM
3052 /* Power Management hooks */
3053 .suspend = e100_suspend,
3054 .resume = e100_resume,
3055 #endif
3056 .shutdown = e100_shutdown,
3057 .err_handler = &e100_err_handler,
3058 };
3059
3060 static int __init e100_init_module(void)
3061 {
3062 if (((1 << debug) - 1) & NETIF_MSG_DRV) {
3063 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
3064 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
3065 }
3066 return pci_register_driver(&e100_driver);
3067 }
3068
3069 static void __exit e100_cleanup_module(void)
3070 {
3071 pci_unregister_driver(&e100_driver);
3072 }
3073
3074 module_init(e100_init_module);
3075 module_exit(e100_cleanup_module);
Linux with added FPC-III support