?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / net / qlge / qlge.h
blobc2383adcd5275b4974f645c16c7032e80b5c06fc
1 /*
2 * QLogic QLA41xx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qlge for copyright and licensing details.
6 */
7 #ifndef _QLGE_H_
8 #define _QLGE_H_
9
10 #include <linux/pci.h>
11 #include <linux/netdevice.h>
12 #include <linux/rtnetlink.h>
13
14 /*
15 * General definitions...
16 */
17 #define DRV_NAME "qlge"
18 #define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver "
19 #define DRV_VERSION "v1.00.00-b3"
20
21 #define PFX "qlge: "
22 #define QPRINTK(qdev, nlevel, klevel, fmt, args...) \
23 do { \
24 if (!((qdev)->msg_enable & NETIF_MSG_##nlevel)) \
25 ; \
26 else \
27 dev_printk(KERN_##klevel, &((qdev)->pdev->dev), \
28 "%s: " fmt, __func__, ##args); \
29 } while (0)
30
31 #define WQ_ADDR_ALIGN 0x3 /* 4 byte alignment */
32
33 #define QLGE_VENDOR_ID 0x1077
34 #define QLGE_DEVICE_ID_8012 0x8012
35 #define QLGE_DEVICE_ID_8000 0x8000
36 #define MAX_CPUS 8
37 #define MAX_TX_RINGS MAX_CPUS
38 #define MAX_RX_RINGS ((MAX_CPUS * 2) + 1)
39
40 #define NUM_TX_RING_ENTRIES 256
41 #define NUM_RX_RING_ENTRIES 256
42
43 #define NUM_SMALL_BUFFERS 512
44 #define NUM_LARGE_BUFFERS 512
45 #define DB_PAGE_SIZE 4096
46
47 /* Calculate the number of (4k) pages required to
48 * contain a buffer queue of the given length.
49 */
50 #define MAX_DB_PAGES_PER_BQ(x) \
51 (((x * sizeof(u64)) / DB_PAGE_SIZE) + \
52 (((x * sizeof(u64)) % DB_PAGE_SIZE) ? 1 : 0))
53
54 #define RX_RING_SHADOW_SPACE (sizeof(u64) + \
55 MAX_DB_PAGES_PER_BQ(NUM_SMALL_BUFFERS) * sizeof(u64) + \
56 MAX_DB_PAGES_PER_BQ(NUM_LARGE_BUFFERS) * sizeof(u64))
57 #define SMALL_BUFFER_SIZE 256
58 #define LARGE_BUFFER_SIZE PAGE_SIZE
59 #define MAX_SPLIT_SIZE 1023
60 #define QLGE_SB_PAD 32
61
62 #define MAX_CQ 128
63 #define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */
64 #define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */
65 #define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2)
66 #define UDELAY_COUNT 3
67 #define UDELAY_DELAY 100
68
69
70 #define TX_DESC_PER_IOCB 8
71 /* The maximum number of frags we handle is based
72 * on PAGE_SIZE...
73 */
74 #if (PAGE_SHIFT == 12) || (PAGE_SHIFT == 13) /* 4k & 8k pages */
75 #define TX_DESC_PER_OAL ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2)
76 #else /* all other page sizes */
77 #define TX_DESC_PER_OAL 0
78 #endif
79
80 /* MPI test register definitions. This register
81 * is used for determining alternate NIC function's
82 * PCI->func number.
83 */
84 enum {
85 MPI_TEST_FUNC_PORT_CFG = 0x1002,
86 MPI_TEST_NIC1_FUNC_SHIFT = 1,
87 MPI_TEST_NIC2_FUNC_SHIFT = 5,
88 MPI_TEST_NIC_FUNC_MASK = 0x00000007,
89 };
90
91 /*
92 * Processor Address Register (PROC_ADDR) bit definitions.
93 */
94 enum {
95
96 /* Misc. stuff */
97 MAILBOX_COUNT = 16,
98 MAILBOX_TIMEOUT = 5,
99
100 PROC_ADDR_RDY = (1 << 31),
101 PROC_ADDR_R = (1 << 30),
102 PROC_ADDR_ERR = (1 << 29),
103 PROC_ADDR_DA = (1 << 28),
104 PROC_ADDR_FUNC0_MBI = 0x00001180,
105 PROC_ADDR_FUNC0_MBO = (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT),
106 PROC_ADDR_FUNC0_CTL = 0x000011a1,
107 PROC_ADDR_FUNC2_MBI = 0x00001280,
108 PROC_ADDR_FUNC2_MBO = (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT),
109 PROC_ADDR_FUNC2_CTL = 0x000012a1,
110 PROC_ADDR_MPI_RISC = 0x00000000,
111 PROC_ADDR_MDE = 0x00010000,
112 PROC_ADDR_REGBLOCK = 0x00020000,
113 PROC_ADDR_RISC_REG = 0x00030000,
114 };
115
116 /*
117 * System Register (SYS) bit definitions.
118 */
119 enum {
120 SYS_EFE = (1 << 0),
121 SYS_FAE = (1 << 1),
122 SYS_MDC = (1 << 2),
123 SYS_DST = (1 << 3),
124 SYS_DWC = (1 << 4),
125 SYS_EVW = (1 << 5),
126 SYS_OMP_DLY_MASK = 0x3f000000,
127 /*
128 * There are no values defined as of edit #15.
129 */
130 SYS_ODI = (1 << 14),
131 };
132
133 /*
134 * Reset/Failover Register (RST_FO) bit definitions.
135 */
136 enum {
137 RST_FO_TFO = (1 << 0),
138 RST_FO_RR_MASK = 0x00060000,
139 RST_FO_RR_CQ_CAM = 0x00000000,
140 RST_FO_RR_DROP = 0x00000002,
141 RST_FO_RR_DQ = 0x00000004,
142 RST_FO_RR_RCV_FUNC_CQ = 0x00000006,
143 RST_FO_FRB = (1 << 12),
144 RST_FO_MOP = (1 << 13),
145 RST_FO_REG = (1 << 14),
146 RST_FO_FR = (1 << 15),
147 };
148
149 /*
150 * Function Specific Control Register (FSC) bit definitions.
151 */
152 enum {
153 FSC_DBRST_MASK = 0x00070000,
154 FSC_DBRST_256 = 0x00000000,
155 FSC_DBRST_512 = 0x00000001,
156 FSC_DBRST_768 = 0x00000002,
157 FSC_DBRST_1024 = 0x00000003,
158 FSC_DBL_MASK = 0x00180000,
159 FSC_DBL_DBRST = 0x00000000,
160 FSC_DBL_MAX_PLD = 0x00000008,
161 FSC_DBL_MAX_BRST = 0x00000010,
162 FSC_DBL_128_BYTES = 0x00000018,
163 FSC_EC = (1 << 5),
164 FSC_EPC_MASK = 0x00c00000,
165 FSC_EPC_INBOUND = (1 << 6),
166 FSC_EPC_OUTBOUND = (1 << 7),
167 FSC_VM_PAGESIZE_MASK = 0x07000000,
168 FSC_VM_PAGE_2K = 0x00000100,
169 FSC_VM_PAGE_4K = 0x00000200,
170 FSC_VM_PAGE_8K = 0x00000300,
171 FSC_VM_PAGE_64K = 0x00000600,
172 FSC_SH = (1 << 11),
173 FSC_DSB = (1 << 12),
174 FSC_STE = (1 << 13),
175 FSC_FE = (1 << 15),
176 };
177
178 /*
179 * Host Command Status Register (CSR) bit definitions.
180 */
181 enum {
182 CSR_ERR_STS_MASK = 0x0000003f,
183 /*
184 * There are no valued defined as of edit #15.
185 */
186 CSR_RR = (1 << 8),
187 CSR_HRI = (1 << 9),
188 CSR_RP = (1 << 10),
189 CSR_CMD_PARM_SHIFT = 22,
190 CSR_CMD_NOP = 0x00000000,
191 CSR_CMD_SET_RST = 0x10000000,
192 CSR_CMD_CLR_RST = 0x20000000,
193 CSR_CMD_SET_PAUSE = 0x30000000,
194 CSR_CMD_CLR_PAUSE = 0x40000000,
195 CSR_CMD_SET_H2R_INT = 0x50000000,
196 CSR_CMD_CLR_H2R_INT = 0x60000000,
197 CSR_CMD_PAR_EN = 0x70000000,
198 CSR_CMD_SET_BAD_PAR = 0x80000000,
199 CSR_CMD_CLR_BAD_PAR = 0x90000000,
200 CSR_CMD_CLR_R2PCI_INT = 0xa0000000,
201 };
202
203 /*
204 * Configuration Register (CFG) bit definitions.
205 */
206 enum {
207 CFG_LRQ = (1 << 0),
208 CFG_DRQ = (1 << 1),
209 CFG_LR = (1 << 2),
210 CFG_DR = (1 << 3),
211 CFG_LE = (1 << 5),
212 CFG_LCQ = (1 << 6),
213 CFG_DCQ = (1 << 7),
214 CFG_Q_SHIFT = 8,
215 CFG_Q_MASK = 0x7f000000,
216 };
217
218 /*
219 * Status Register (STS) bit definitions.
220 */
221 enum {
222 STS_FE = (1 << 0),
223 STS_PI = (1 << 1),
224 STS_PL0 = (1 << 2),
225 STS_PL1 = (1 << 3),
226 STS_PI0 = (1 << 4),
227 STS_PI1 = (1 << 5),
228 STS_FUNC_ID_MASK = 0x000000c0,
229 STS_FUNC_ID_SHIFT = 6,
230 STS_F0E = (1 << 8),
231 STS_F1E = (1 << 9),
232 STS_F2E = (1 << 10),
233 STS_F3E = (1 << 11),
234 STS_NFE = (1 << 12),
235 };
236
237 /*
238 * Interrupt Enable Register (INTR_EN) bit definitions.
239 */
240 enum {
241 INTR_EN_INTR_MASK = 0x007f0000,
242 INTR_EN_TYPE_MASK = 0x03000000,
243 INTR_EN_TYPE_ENABLE = 0x00000100,
244 INTR_EN_TYPE_DISABLE = 0x00000200,
245 INTR_EN_TYPE_READ = 0x00000300,
246 INTR_EN_IHD = (1 << 13),
247 INTR_EN_IHD_MASK = (INTR_EN_IHD << 16),
248 INTR_EN_EI = (1 << 14),
249 INTR_EN_EN = (1 << 15),
250 };
251
252 /*
253 * Interrupt Mask Register (INTR_MASK) bit definitions.
254 */
255 enum {
256 INTR_MASK_PI = (1 << 0),
257 INTR_MASK_HL0 = (1 << 1),
258 INTR_MASK_LH0 = (1 << 2),
259 INTR_MASK_HL1 = (1 << 3),
260 INTR_MASK_LH1 = (1 << 4),
261 INTR_MASK_SE = (1 << 5),
262 INTR_MASK_LSC = (1 << 6),
263 INTR_MASK_MC = (1 << 7),
264 INTR_MASK_LINK_IRQS = INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC,
265 };
266
267 /*
268 * Register (REV_ID) bit definitions.
269 */
270 enum {
271 REV_ID_MASK = 0x0000000f,
272 REV_ID_NICROLL_SHIFT = 0,
273 REV_ID_NICREV_SHIFT = 4,
274 REV_ID_XGROLL_SHIFT = 8,
275 REV_ID_XGREV_SHIFT = 12,
276 REV_ID_CHIPREV_SHIFT = 28,
277 };
278
279 /*
280 * Force ECC Error Register (FRC_ECC_ERR) bit definitions.
281 */
282 enum {
283 FRC_ECC_ERR_VW = (1 << 12),
284 FRC_ECC_ERR_VB = (1 << 13),
285 FRC_ECC_ERR_NI = (1 << 14),
286 FRC_ECC_ERR_NO = (1 << 15),
287 FRC_ECC_PFE_SHIFT = 16,
288 FRC_ECC_ERR_DO = (1 << 18),
289 FRC_ECC_P14 = (1 << 19),
290 };
291
292 /*
293 * Error Status Register (ERR_STS) bit definitions.
294 */
295 enum {
296 ERR_STS_NOF = (1 << 0),
297 ERR_STS_NIF = (1 << 1),
298 ERR_STS_DRP = (1 << 2),
299 ERR_STS_XGP = (1 << 3),
300 ERR_STS_FOU = (1 << 4),
301 ERR_STS_FOC = (1 << 5),
302 ERR_STS_FOF = (1 << 6),
303 ERR_STS_FIU = (1 << 7),
304 ERR_STS_FIC = (1 << 8),
305 ERR_STS_FIF = (1 << 9),
306 ERR_STS_MOF = (1 << 10),
307 ERR_STS_TA = (1 << 11),
308 ERR_STS_MA = (1 << 12),
309 ERR_STS_MPE = (1 << 13),
310 ERR_STS_SCE = (1 << 14),
311 ERR_STS_STE = (1 << 15),
312 ERR_STS_FOW = (1 << 16),
313 ERR_STS_UE = (1 << 17),
314 ERR_STS_MCH = (1 << 26),
315 ERR_STS_LOC_SHIFT = 27,
316 };
317
318 /*
319 * RAM Debug Address Register (RAM_DBG_ADDR) bit definitions.
320 */
321 enum {
322 RAM_DBG_ADDR_FW = (1 << 30),
323 RAM_DBG_ADDR_FR = (1 << 31),
324 };
325
326 /*
327 * Semaphore Register (SEM) bit definitions.
328 */
329 enum {
330 /*
331 * Example:
332 * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)
333 */
334 SEM_CLEAR = 0,
335 SEM_SET = 1,
336 SEM_FORCE = 3,
337 SEM_XGMAC0_SHIFT = 0,
338 SEM_XGMAC1_SHIFT = 2,
339 SEM_ICB_SHIFT = 4,
340 SEM_MAC_ADDR_SHIFT = 6,
341 SEM_FLASH_SHIFT = 8,
342 SEM_PROBE_SHIFT = 10,
343 SEM_RT_IDX_SHIFT = 12,
344 SEM_PROC_REG_SHIFT = 14,
345 SEM_XGMAC0_MASK = 0x00030000,
346 SEM_XGMAC1_MASK = 0x000c0000,
347 SEM_ICB_MASK = 0x00300000,
348 SEM_MAC_ADDR_MASK = 0x00c00000,
349 SEM_FLASH_MASK = 0x03000000,
350 SEM_PROBE_MASK = 0x0c000000,
351 SEM_RT_IDX_MASK = 0x30000000,
352 SEM_PROC_REG_MASK = 0xc0000000,
353 };
354
355 /*
356 * 10G MAC Address Register (XGMAC_ADDR) bit definitions.
357 */
358 enum {
359 XGMAC_ADDR_RDY = (1 << 31),
360 XGMAC_ADDR_R = (1 << 30),
361 XGMAC_ADDR_XME = (1 << 29),
362
363 /* XGMAC control registers */
364 PAUSE_SRC_LO = 0x00000100,
365 PAUSE_SRC_HI = 0x00000104,
366 GLOBAL_CFG = 0x00000108,
367 GLOBAL_CFG_RESET = (1 << 0),
368 GLOBAL_CFG_JUMBO = (1 << 6),
369 GLOBAL_CFG_TX_STAT_EN = (1 << 10),
370 GLOBAL_CFG_RX_STAT_EN = (1 << 11),
371 TX_CFG = 0x0000010c,
372 TX_CFG_RESET = (1 << 0),
373 TX_CFG_EN = (1 << 1),
374 TX_CFG_PREAM = (1 << 2),
375 RX_CFG = 0x00000110,
376 RX_CFG_RESET = (1 << 0),
377 RX_CFG_EN = (1 << 1),
378 RX_CFG_PREAM = (1 << 2),
379 FLOW_CTL = 0x0000011c,
380 PAUSE_OPCODE = 0x00000120,
381 PAUSE_TIMER = 0x00000124,
382 PAUSE_FRM_DEST_LO = 0x00000128,
383 PAUSE_FRM_DEST_HI = 0x0000012c,
384 MAC_TX_PARAMS = 0x00000134,
385 MAC_TX_PARAMS_JUMBO = (1 << 31),
386 MAC_TX_PARAMS_SIZE_SHIFT = 16,
387 MAC_RX_PARAMS = 0x00000138,
388 MAC_SYS_INT = 0x00000144,
389 MAC_SYS_INT_MASK = 0x00000148,
390 MAC_MGMT_INT = 0x0000014c,
391 MAC_MGMT_IN_MASK = 0x00000150,
392 EXT_ARB_MODE = 0x000001fc,
393
394 /* XGMAC TX statistics registers */
395 TX_PKTS = 0x00000200,
396 TX_BYTES = 0x00000208,
397 TX_MCAST_PKTS = 0x00000210,
398 TX_BCAST_PKTS = 0x00000218,
399 TX_UCAST_PKTS = 0x00000220,
400 TX_CTL_PKTS = 0x00000228,
401 TX_PAUSE_PKTS = 0x00000230,
402 TX_64_PKT = 0x00000238,
403 TX_65_TO_127_PKT = 0x00000240,
404 TX_128_TO_255_PKT = 0x00000248,
405 TX_256_511_PKT = 0x00000250,
406 TX_512_TO_1023_PKT = 0x00000258,
407 TX_1024_TO_1518_PKT = 0x00000260,
408 TX_1519_TO_MAX_PKT = 0x00000268,
409 TX_UNDERSIZE_PKT = 0x00000270,
410 TX_OVERSIZE_PKT = 0x00000278,
411
412 /* XGMAC statistics control registers */
413 RX_HALF_FULL_DET = 0x000002a0,
414 TX_HALF_FULL_DET = 0x000002a4,
415 RX_OVERFLOW_DET = 0x000002a8,
416 TX_OVERFLOW_DET = 0x000002ac,
417 RX_HALF_FULL_MASK = 0x000002b0,
418 TX_HALF_FULL_MASK = 0x000002b4,
419 RX_OVERFLOW_MASK = 0x000002b8,
420 TX_OVERFLOW_MASK = 0x000002bc,
421 STAT_CNT_CTL = 0x000002c0,
422 STAT_CNT_CTL_CLEAR_TX = (1 << 0),
423 STAT_CNT_CTL_CLEAR_RX = (1 << 1),
424 AUX_RX_HALF_FULL_DET = 0x000002d0,
425 AUX_TX_HALF_FULL_DET = 0x000002d4,
426 AUX_RX_OVERFLOW_DET = 0x000002d8,
427 AUX_TX_OVERFLOW_DET = 0x000002dc,
428 AUX_RX_HALF_FULL_MASK = 0x000002f0,
429 AUX_TX_HALF_FULL_MASK = 0x000002f4,
430 AUX_RX_OVERFLOW_MASK = 0x000002f8,
431 AUX_TX_OVERFLOW_MASK = 0x000002fc,
432
433 /* XGMAC RX statistics registers */
434 RX_BYTES = 0x00000300,
435 RX_BYTES_OK = 0x00000308,
436 RX_PKTS = 0x00000310,
437 RX_PKTS_OK = 0x00000318,
438 RX_BCAST_PKTS = 0x00000320,
439 RX_MCAST_PKTS = 0x00000328,
440 RX_UCAST_PKTS = 0x00000330,
441 RX_UNDERSIZE_PKTS = 0x00000338,
442 RX_OVERSIZE_PKTS = 0x00000340,
443 RX_JABBER_PKTS = 0x00000348,
444 RX_UNDERSIZE_FCERR_PKTS = 0x00000350,
445 RX_DROP_EVENTS = 0x00000358,
446 RX_FCERR_PKTS = 0x00000360,
447 RX_ALIGN_ERR = 0x00000368,
448 RX_SYMBOL_ERR = 0x00000370,
449 RX_MAC_ERR = 0x00000378,
450 RX_CTL_PKTS = 0x00000380,
451 RX_PAUSE_PKTS = 0x00000388,
452 RX_64_PKTS = 0x00000390,
453 RX_65_TO_127_PKTS = 0x00000398,
454 RX_128_255_PKTS = 0x000003a0,
455 RX_256_511_PKTS = 0x000003a8,
456 RX_512_TO_1023_PKTS = 0x000003b0,
457 RX_1024_TO_1518_PKTS = 0x000003b8,
458 RX_1519_TO_MAX_PKTS = 0x000003c0,
459 RX_LEN_ERR_PKTS = 0x000003c8,
460
461 /* XGMAC MDIO control registers */
462 MDIO_TX_DATA = 0x00000400,
463 MDIO_RX_DATA = 0x00000410,
464 MDIO_CMD = 0x00000420,
465 MDIO_PHY_ADDR = 0x00000430,
466 MDIO_PORT = 0x00000440,
467 MDIO_STATUS = 0x00000450,
468
469 /* XGMAC AUX statistics registers */
470 };
471
472 /*
473 * Enhanced Transmission Schedule Registers (NIC_ETS,CNA_ETS) bit definitions.
474 */
475 enum {
476 ETS_QUEUE_SHIFT = 29,
477 ETS_REF = (1 << 26),
478 ETS_RS = (1 << 27),
479 ETS_P = (1 << 28),
480 ETS_FC_COS_SHIFT = 23,
481 };
482
483 /*
484 * Flash Address Register (FLASH_ADDR) bit definitions.
485 */
486 enum {
487 FLASH_ADDR_RDY = (1 << 31),
488 FLASH_ADDR_R = (1 << 30),
489 FLASH_ADDR_ERR = (1 << 29),
490 };
491
492 /*
493 * Stop CQ Processing Register (CQ_STOP) bit definitions.
494 */
495 enum {
496 CQ_STOP_QUEUE_MASK = (0x007f0000),
497 CQ_STOP_TYPE_MASK = (0x03000000),
498 CQ_STOP_TYPE_START = 0x00000100,
499 CQ_STOP_TYPE_STOP = 0x00000200,
500 CQ_STOP_TYPE_READ = 0x00000300,
501 CQ_STOP_EN = (1 << 15),
502 };
503
504 /*
505 * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.
506 */
507 enum {
508 MAC_ADDR_IDX_SHIFT = 4,
509 MAC_ADDR_TYPE_SHIFT = 16,
510 MAC_ADDR_TYPE_MASK = 0x000f0000,
511 MAC_ADDR_TYPE_CAM_MAC = 0x00000000,
512 MAC_ADDR_TYPE_MULTI_MAC = 0x00010000,
513 MAC_ADDR_TYPE_VLAN = 0x00020000,
514 MAC_ADDR_TYPE_MULTI_FLTR = 0x00030000,
515 MAC_ADDR_TYPE_FC_MAC = 0x00040000,
516 MAC_ADDR_TYPE_MGMT_MAC = 0x00050000,
517 MAC_ADDR_TYPE_MGMT_VLAN = 0x00060000,
518 MAC_ADDR_TYPE_MGMT_V4 = 0x00070000,
519 MAC_ADDR_TYPE_MGMT_V6 = 0x00080000,
520 MAC_ADDR_TYPE_MGMT_TU_DP = 0x00090000,
521 MAC_ADDR_ADR = (1 << 25),
522 MAC_ADDR_RS = (1 << 26),
523 MAC_ADDR_E = (1 << 27),
524 MAC_ADDR_MR = (1 << 30),
525 MAC_ADDR_MW = (1 << 31),
526 MAX_MULTICAST_ENTRIES = 32,
527 };
528
529 /*
530 * MAC Protocol Address Index Register (SPLT_HDR) bit definitions.
531 */
532 enum {
533 SPLT_HDR_EP = (1 << 31),
534 };
535
536 /*
537 * FCoE Receive Configuration Register (FC_RCV_CFG) bit definitions.
538 */
539 enum {
540 FC_RCV_CFG_ECT = (1 << 15),
541 FC_RCV_CFG_DFH = (1 << 20),
542 FC_RCV_CFG_DVF = (1 << 21),
543 FC_RCV_CFG_RCE = (1 << 27),
544 FC_RCV_CFG_RFE = (1 << 28),
545 FC_RCV_CFG_TEE = (1 << 29),
546 FC_RCV_CFG_TCE = (1 << 30),
547 FC_RCV_CFG_TFE = (1 << 31),
548 };
549
550 /*
551 * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.
552 */
553 enum {
554 NIC_RCV_CFG_PPE = (1 << 0),
555 NIC_RCV_CFG_VLAN_MASK = 0x00060000,
556 NIC_RCV_CFG_VLAN_ALL = 0x00000000,
557 NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002,
558 NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004,
559 NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006,
560 NIC_RCV_CFG_RV = (1 << 3),
561 NIC_RCV_CFG_DFQ_MASK = (0x7f000000),
562 NIC_RCV_CFG_DFQ_SHIFT = 8,
563 NIC_RCV_CFG_DFQ = 0, /* HARDCODE default queue to 0. */
564 };
565
566 /*
567 * Mgmt Receive Configuration Register (MGMT_RCV_CFG) bit definitions.
568 */
569 enum {
570 MGMT_RCV_CFG_ARP = (1 << 0),
571 MGMT_RCV_CFG_DHC = (1 << 1),
572 MGMT_RCV_CFG_DHS = (1 << 2),
573 MGMT_RCV_CFG_NP = (1 << 3),
574 MGMT_RCV_CFG_I6N = (1 << 4),
575 MGMT_RCV_CFG_I6R = (1 << 5),
576 MGMT_RCV_CFG_DH6 = (1 << 6),
577 MGMT_RCV_CFG_UD1 = (1 << 7),
578 MGMT_RCV_CFG_UD0 = (1 << 8),
579 MGMT_RCV_CFG_BCT = (1 << 9),
580 MGMT_RCV_CFG_MCT = (1 << 10),
581 MGMT_RCV_CFG_DM = (1 << 11),
582 MGMT_RCV_CFG_RM = (1 << 12),
583 MGMT_RCV_CFG_STL = (1 << 13),
584 MGMT_RCV_CFG_VLAN_MASK = 0xc0000000,
585 MGMT_RCV_CFG_VLAN_ALL = 0x00000000,
586 MGMT_RCV_CFG_VLAN_MATCH_ONLY = 0x00004000,
587 MGMT_RCV_CFG_VLAN_MATCH_AND_NON = 0x00008000,
588 MGMT_RCV_CFG_VLAN_NONE_AND_NON = 0x0000c000,
589 };
590
591 /*
592 * Routing Index Register (RT_IDX) bit definitions.
593 */
594 enum {
595 RT_IDX_IDX_SHIFT = 8,
596 RT_IDX_TYPE_MASK = 0x000f0000,
597 RT_IDX_TYPE_RT = 0x00000000,
598 RT_IDX_TYPE_RT_INV = 0x00010000,
599 RT_IDX_TYPE_NICQ = 0x00020000,
600 RT_IDX_TYPE_NICQ_INV = 0x00030000,
601 RT_IDX_DST_MASK = 0x00700000,
602 RT_IDX_DST_RSS = 0x00000000,
603 RT_IDX_DST_CAM_Q = 0x00100000,
604 RT_IDX_DST_COS_Q = 0x00200000,
605 RT_IDX_DST_DFLT_Q = 0x00300000,
606 RT_IDX_DST_DEST_Q = 0x00400000,
607 RT_IDX_RS = (1 << 26),
608 RT_IDX_E = (1 << 27),
609 RT_IDX_MR = (1 << 30),
610 RT_IDX_MW = (1 << 31),
611
612 /* Nic Queue format - type 2 bits */
613 RT_IDX_BCAST = (1 << 0),
614 RT_IDX_MCAST = (1 << 1),
615 RT_IDX_MCAST_MATCH = (1 << 2),
616 RT_IDX_MCAST_REG_MATCH = (1 << 3),
617 RT_IDX_MCAST_HASH_MATCH = (1 << 4),
618 RT_IDX_FC_MACH = (1 << 5),
619 RT_IDX_ETH_FCOE = (1 << 6),
620 RT_IDX_CAM_HIT = (1 << 7),
621 RT_IDX_CAM_BIT0 = (1 << 8),
622 RT_IDX_CAM_BIT1 = (1 << 9),
623 RT_IDX_VLAN_TAG = (1 << 10),
624 RT_IDX_VLAN_MATCH = (1 << 11),
625 RT_IDX_VLAN_FILTER = (1 << 12),
626 RT_IDX_ETH_SKIP1 = (1 << 13),
627 RT_IDX_ETH_SKIP2 = (1 << 14),
628 RT_IDX_BCAST_MCAST_MATCH = (1 << 15),
629 RT_IDX_802_3 = (1 << 16),
630 RT_IDX_LLDP = (1 << 17),
631 RT_IDX_UNUSED018 = (1 << 18),
632 RT_IDX_UNUSED019 = (1 << 19),
633 RT_IDX_UNUSED20 = (1 << 20),
634 RT_IDX_UNUSED21 = (1 << 21),
635 RT_IDX_ERR = (1 << 22),
636 RT_IDX_VALID = (1 << 23),
637 RT_IDX_TU_CSUM_ERR = (1 << 24),
638 RT_IDX_IP_CSUM_ERR = (1 << 25),
639 RT_IDX_MAC_ERR = (1 << 26),
640 RT_IDX_RSS_TCP6 = (1 << 27),
641 RT_IDX_RSS_TCP4 = (1 << 28),
642 RT_IDX_RSS_IPV6 = (1 << 29),
643 RT_IDX_RSS_IPV4 = (1 << 30),
644 RT_IDX_RSS_MATCH = (1 << 31),
645
646 /* Hierarchy for the NIC Queue Mask */
647 RT_IDX_ALL_ERR_SLOT = 0,
648 RT_IDX_MAC_ERR_SLOT = 0,
649 RT_IDX_IP_CSUM_ERR_SLOT = 1,
650 RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2,
651 RT_IDX_BCAST_SLOT = 3,
652 RT_IDX_MCAST_MATCH_SLOT = 4,
653 RT_IDX_ALLMULTI_SLOT = 5,
654 RT_IDX_UNUSED6_SLOT = 6,
655 RT_IDX_UNUSED7_SLOT = 7,
656 RT_IDX_RSS_MATCH_SLOT = 8,
657 RT_IDX_RSS_IPV4_SLOT = 8,
658 RT_IDX_RSS_IPV6_SLOT = 9,
659 RT_IDX_RSS_TCP4_SLOT = 10,
660 RT_IDX_RSS_TCP6_SLOT = 11,
661 RT_IDX_CAM_HIT_SLOT = 12,
662 RT_IDX_UNUSED013 = 13,
663 RT_IDX_UNUSED014 = 14,
664 RT_IDX_PROMISCUOUS_SLOT = 15,
665 RT_IDX_MAX_SLOTS = 16,
666 };
667
668 /*
669 * Control Register Set Map
670 */
671 enum {
672 PROC_ADDR = 0, /* Use semaphore */
673 PROC_DATA = 0x04, /* Use semaphore */
674 SYS = 0x08,
675 RST_FO = 0x0c,
676 FSC = 0x10,
677 CSR = 0x14,
678 LED = 0x18,
679 ICB_RID = 0x1c, /* Use semaphore */
680 ICB_L = 0x20, /* Use semaphore */
681 ICB_H = 0x24, /* Use semaphore */
682 CFG = 0x28,
683 BIOS_ADDR = 0x2c,
684 STS = 0x30,
685 INTR_EN = 0x34,
686 INTR_MASK = 0x38,
687 ISR1 = 0x3c,
688 ISR2 = 0x40,
689 ISR3 = 0x44,
690 ISR4 = 0x48,
691 REV_ID = 0x4c,
692 FRC_ECC_ERR = 0x50,
693 ERR_STS = 0x54,
694 RAM_DBG_ADDR = 0x58,
695 RAM_DBG_DATA = 0x5c,
696 ECC_ERR_CNT = 0x60,
697 SEM = 0x64,
698 GPIO_1 = 0x68, /* Use semaphore */
699 GPIO_2 = 0x6c, /* Use semaphore */
700 GPIO_3 = 0x70, /* Use semaphore */
701 RSVD2 = 0x74,
702 XGMAC_ADDR = 0x78, /* Use semaphore */
703 XGMAC_DATA = 0x7c, /* Use semaphore */
704 NIC_ETS = 0x80,
705 CNA_ETS = 0x84,
706 FLASH_ADDR = 0x88, /* Use semaphore */
707 FLASH_DATA = 0x8c, /* Use semaphore */
708 CQ_STOP = 0x90,
709 PAGE_TBL_RID = 0x94,
710 WQ_PAGE_TBL_LO = 0x98,
711 WQ_PAGE_TBL_HI = 0x9c,
712 CQ_PAGE_TBL_LO = 0xa0,
713 CQ_PAGE_TBL_HI = 0xa4,
714 MAC_ADDR_IDX = 0xa8, /* Use semaphore */
715 MAC_ADDR_DATA = 0xac, /* Use semaphore */
716 COS_DFLT_CQ1 = 0xb0,
717 COS_DFLT_CQ2 = 0xb4,
718 ETYPE_SKIP1 = 0xb8,
719 ETYPE_SKIP2 = 0xbc,
720 SPLT_HDR = 0xc0,
721 FC_PAUSE_THRES = 0xc4,
722 NIC_PAUSE_THRES = 0xc8,
723 FC_ETHERTYPE = 0xcc,
724 FC_RCV_CFG = 0xd0,
725 NIC_RCV_CFG = 0xd4,
726 FC_COS_TAGS = 0xd8,
727 NIC_COS_TAGS = 0xdc,
728 MGMT_RCV_CFG = 0xe0,
729 RT_IDX = 0xe4,
730 RT_DATA = 0xe8,
731 RSVD7 = 0xec,
732 XG_SERDES_ADDR = 0xf0,
733 XG_SERDES_DATA = 0xf4,
734 PRB_MX_ADDR = 0xf8, /* Use semaphore */
735 PRB_MX_DATA = 0xfc, /* Use semaphore */
736 };
737
738 /*
739 * CAM output format.
740 */
741 enum {
742 CAM_OUT_ROUTE_FC = 0,
743 CAM_OUT_ROUTE_NIC = 1,
744 CAM_OUT_FUNC_SHIFT = 2,
745 CAM_OUT_RV = (1 << 4),
746 CAM_OUT_SH = (1 << 15),
747 CAM_OUT_CQ_ID_SHIFT = 5,
748 };
749
750 /*
751 * Mailbox definitions
752 */
753 enum {
754 /* Asynchronous Event Notifications */
755 AEN_SYS_ERR = 0x00008002,
756 AEN_LINK_UP = 0x00008011,
757 AEN_LINK_DOWN = 0x00008012,
758 AEN_IDC_CMPLT = 0x00008100,
759 AEN_IDC_REQ = 0x00008101,
760 AEN_IDC_EXT = 0x00008102,
761 AEN_DCBX_CHG = 0x00008110,
762 AEN_AEN_LOST = 0x00008120,
763 AEN_AEN_SFP_IN = 0x00008130,
764 AEN_AEN_SFP_OUT = 0x00008131,
765 AEN_FW_INIT_DONE = 0x00008400,
766 AEN_FW_INIT_FAIL = 0x00008401,
767
768 /* Mailbox Command Opcodes. */
769 MB_CMD_NOP = 0x00000000,
770 MB_CMD_EX_FW = 0x00000002,
771 MB_CMD_MB_TEST = 0x00000006,
772 MB_CMD_CSUM_TEST = 0x00000007, /* Verify Checksum */
773 MB_CMD_ABOUT_FW = 0x00000008,
774 MB_CMD_COPY_RISC_RAM = 0x0000000a,
775 MB_CMD_LOAD_RISC_RAM = 0x0000000b,
776 MB_CMD_DUMP_RISC_RAM = 0x0000000c,
777 MB_CMD_WRITE_RAM = 0x0000000d,
778 MB_CMD_INIT_RISC_RAM = 0x0000000e,
779 MB_CMD_READ_RAM = 0x0000000f,
780 MB_CMD_STOP_FW = 0x00000014,
781 MB_CMD_MAKE_SYS_ERR = 0x0000002a,
782 MB_CMD_WRITE_SFP = 0x00000030,
783 MB_CMD_READ_SFP = 0x00000031,
784 MB_CMD_INIT_FW = 0x00000060,
785 MB_CMD_GET_IFCB = 0x00000061,
786 MB_CMD_GET_FW_STATE = 0x00000069,
787 MB_CMD_IDC_REQ = 0x00000100, /* Inter-Driver Communication */
788 MB_CMD_IDC_ACK = 0x00000101, /* Inter-Driver Communication */
789 MB_CMD_SET_WOL_MODE = 0x00000110, /* Wake On Lan */
790 MB_WOL_DISABLE = 0,
791 MB_WOL_MAGIC_PKT = (1 << 1),
792 MB_WOL_FLTR = (1 << 2),
793 MB_WOL_UCAST = (1 << 3),
794 MB_WOL_MCAST = (1 << 4),
795 MB_WOL_BCAST = (1 << 5),
796 MB_WOL_LINK_UP = (1 << 6),
797 MB_WOL_LINK_DOWN = (1 << 7),
798 MB_CMD_SET_WOL_FLTR = 0x00000111, /* Wake On Lan Filter */
799 MB_CMD_CLEAR_WOL_FLTR = 0x00000112, /* Wake On Lan Filter */
800 MB_CMD_SET_WOL_MAGIC = 0x00000113, /* Wake On Lan Magic Packet */
801 MB_CMD_CLEAR_WOL_MAGIC = 0x00000114,/* Wake On Lan Magic Packet */
802 MB_CMD_SET_WOL_IMMED = 0x00000115,
803 MB_CMD_PORT_RESET = 0x00000120,
804 MB_CMD_SET_PORT_CFG = 0x00000122,
805 MB_CMD_GET_PORT_CFG = 0x00000123,
806 MB_CMD_GET_LINK_STS = 0x00000124,
807 MB_CMD_SET_MGMNT_TFK_CTL = 0x00000160, /* Set Mgmnt Traffic Control */
808 MB_SET_MPI_TFK_STOP = (1 << 0),
809 MB_SET_MPI_TFK_RESUME = (1 << 1),
810 MB_CMD_GET_MGMNT_TFK_CTL = 0x00000161, /* Get Mgmnt Traffic Control */
811 MB_GET_MPI_TFK_STOPPED = (1 << 0),
812 MB_GET_MPI_TFK_FIFO_EMPTY = (1 << 1),
813
814 /* Mailbox Command Status. */
815 MB_CMD_STS_GOOD = 0x00004000, /* Success. */
816 MB_CMD_STS_INTRMDT = 0x00001000, /* Intermediate Complete. */
817 MB_CMD_STS_INVLD_CMD = 0x00004001, /* Invalid. */
818 MB_CMD_STS_XFC_ERR = 0x00004002, /* Interface Error. */
819 MB_CMD_STS_CSUM_ERR = 0x00004003, /* Csum Error. */
820 MB_CMD_STS_ERR = 0x00004005, /* System Error. */
821 MB_CMD_STS_PARAM_ERR = 0x00004006, /* Parameter Error. */
822 };
823
824 struct mbox_params {
825 u32 mbox_in[MAILBOX_COUNT];
826 u32 mbox_out[MAILBOX_COUNT];
827 int in_count;
828 int out_count;
829 };
830
831 struct flash_params_8012 {
832 u8 dev_id_str[4];
833 __le16 size;
834 __le16 csum;
835 __le16 ver;
836 __le16 sub_dev_id;
837 u8 mac_addr[6];
838 __le16 res;
839 };
840
841 /* 8000 device's flash is a different structure
842 * at a different offset in flash.
843 */
844 #define FUNC0_FLASH_OFFSET 0x140200
845 #define FUNC1_FLASH_OFFSET 0x140600
846
847 /* Flash related data structures. */
848 struct flash_params_8000 {
849 u8 dev_id_str[4]; /* "8000" */
850 __le16 ver;
851 __le16 size;
852 __le16 csum;
853 __le16 reserved0;
854 __le16 total_size;
855 __le16 entry_count;
856 u8 data_type0;
857 u8 data_size0;
858 u8 mac_addr[6];
859 u8 data_type1;
860 u8 data_size1;
861 u8 mac_addr1[6];
862 u8 data_type2;
863 u8 data_size2;
864 __le16 vlan_id;
865 u8 data_type3;
866 u8 data_size3;
867 __le16 last;
868 u8 reserved1[464];
869 __le16 subsys_ven_id;
870 __le16 subsys_dev_id;
871 u8 reserved2[4];
872 };
873
874 union flash_params {
875 struct flash_params_8012 flash_params_8012;
876 struct flash_params_8000 flash_params_8000;
877 };
878
879 /*
880 * doorbell space for the rx ring context
881 */
882 struct rx_doorbell_context {
883 u32 cnsmr_idx; /* 0x00 */
884 u32 valid; /* 0x04 */
885 u32 reserved[4]; /* 0x08-0x14 */
886 u32 lbq_prod_idx; /* 0x18 */
887 u32 sbq_prod_idx; /* 0x1c */
888 };
889
890 /*
891 * doorbell space for the tx ring context
892 */
893 struct tx_doorbell_context {
894 u32 prod_idx; /* 0x00 */
895 u32 valid; /* 0x04 */
896 u32 reserved[4]; /* 0x08-0x14 */
897 u32 lbq_prod_idx; /* 0x18 */
898 u32 sbq_prod_idx; /* 0x1c */
899 };
900
901 /* DATA STRUCTURES SHARED WITH HARDWARE. */
902 struct tx_buf_desc {
903 __le64 addr;
904 __le32 len;
905 #define TX_DESC_LEN_MASK 0x000fffff
906 #define TX_DESC_C 0x40000000
907 #define TX_DESC_E 0x80000000
908 } __attribute((packed));
909
910 /*
911 * IOCB Definitions...
912 */
913
914 #define OPCODE_OB_MAC_IOCB 0x01
915 #define OPCODE_OB_MAC_TSO_IOCB 0x02
916 #define OPCODE_IB_MAC_IOCB 0x20
917 #define OPCODE_IB_MPI_IOCB 0x21
918 #define OPCODE_IB_AE_IOCB 0x3f
919
920 struct ob_mac_iocb_req {
921 u8 opcode;
922 u8 flags1;
923 #define OB_MAC_IOCB_REQ_OI 0x01
924 #define OB_MAC_IOCB_REQ_I 0x02
925 #define OB_MAC_IOCB_REQ_D 0x08
926 #define OB_MAC_IOCB_REQ_F 0x10
927 u8 flags2;
928 u8 flags3;
929 #define OB_MAC_IOCB_DFP 0x02
930 #define OB_MAC_IOCB_V 0x04
931 __le32 reserved1[2];
932 __le16 frame_len;
933 #define OB_MAC_IOCB_LEN_MASK 0x3ffff
934 __le16 reserved2;
935 u32 tid;
936 u32 txq_idx;
937 __le32 reserved3;
938 __le16 vlan_tci;
939 __le16 reserved4;
940 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
941 } __attribute((packed));
942
943 struct ob_mac_iocb_rsp {
944 u8 opcode; /* */
945 u8 flags1; /* */
946 #define OB_MAC_IOCB_RSP_OI 0x01 /* */
947 #define OB_MAC_IOCB_RSP_I 0x02 /* */
948 #define OB_MAC_IOCB_RSP_E 0x08 /* */
949 #define OB_MAC_IOCB_RSP_S 0x10 /* too Short */
950 #define OB_MAC_IOCB_RSP_L 0x20 /* too Large */
951 #define OB_MAC_IOCB_RSP_P 0x40 /* Padded */
952 u8 flags2; /* */
953 u8 flags3; /* */
954 #define OB_MAC_IOCB_RSP_B 0x80 /* */
955 u32 tid;
956 u32 txq_idx;
957 __le32 reserved[13];
958 } __attribute((packed));
959
960 struct ob_mac_tso_iocb_req {
961 u8 opcode;
962 u8 flags1;
963 #define OB_MAC_TSO_IOCB_OI 0x01
964 #define OB_MAC_TSO_IOCB_I 0x02
965 #define OB_MAC_TSO_IOCB_D 0x08
966 #define OB_MAC_TSO_IOCB_IP4 0x40
967 #define OB_MAC_TSO_IOCB_IP6 0x80
968 u8 flags2;
969 #define OB_MAC_TSO_IOCB_LSO 0x20
970 #define OB_MAC_TSO_IOCB_UC 0x40
971 #define OB_MAC_TSO_IOCB_TC 0x80
972 u8 flags3;
973 #define OB_MAC_TSO_IOCB_IC 0x01
974 #define OB_MAC_TSO_IOCB_DFP 0x02
975 #define OB_MAC_TSO_IOCB_V 0x04
976 __le32 reserved1[2];
977 __le32 frame_len;
978 u32 tid;
979 u32 txq_idx;
980 __le16 total_hdrs_len;
981 __le16 net_trans_offset;
982 #define OB_MAC_TRANSPORT_HDR_SHIFT 6
983 __le16 vlan_tci;
984 __le16 mss;
985 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
986 } __attribute((packed));
987
988 struct ob_mac_tso_iocb_rsp {
989 u8 opcode;
990 u8 flags1;
991 #define OB_MAC_TSO_IOCB_RSP_OI 0x01
992 #define OB_MAC_TSO_IOCB_RSP_I 0x02
993 #define OB_MAC_TSO_IOCB_RSP_E 0x08
994 #define OB_MAC_TSO_IOCB_RSP_S 0x10
995 #define OB_MAC_TSO_IOCB_RSP_L 0x20
996 #define OB_MAC_TSO_IOCB_RSP_P 0x40
997 u8 flags2; /* */
998 u8 flags3; /* */
999 #define OB_MAC_TSO_IOCB_RSP_B 0x8000
1000 u32 tid;
1001 u32 txq_idx;
1002 __le32 reserved2[13];
1003 } __attribute((packed));
1004
1005 struct ib_mac_iocb_rsp {
1006 u8 opcode; /* 0x20 */
1007 u8 flags1;
1008 #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */
1009 #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */
1010 #define IB_MAC_CSUM_ERR_MASK 0x1c /* A mask to use for csum errs */
1011 #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */
1012 #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */
1013 #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */
1014 #define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */
1015 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */
1016 #define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */
1017 #define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */
1018 #define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */
1019 #define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */
1020 u8 flags2;
1021 #define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */
1022 #define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */
1023 #define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */
1024 #define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04
1025 #define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08
1026 #define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10
1027 #define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14
1028 #define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18
1029 #define IB_MAC_IOCB_RSP_ERR_CRC 0x1c
1030 #define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */
1031 #define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */
1032 #define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */
1033 u8 flags3;
1034 #define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */
1035 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */
1036 #define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */
1037 #define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */
1038 #define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */
1039 #define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */
1040 #define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */
1041 #define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */
1042 #define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */
1043 #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */
1044 #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */
1045 __le32 data_len; /* */
1046 __le64 data_addr; /* */
1047 __le32 rss; /* */
1048 __le16 vlan_id; /* 12 bits */
1049 #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */
1050 #define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */
1051 #define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff
1052
1053 __le16 reserved1;
1054 __le32 reserved2[6];
1055 u8 reserved3[3];
1056 u8 flags4;
1057 #define IB_MAC_IOCB_RSP_HV 0x20
1058 #define IB_MAC_IOCB_RSP_HS 0x40
1059 #define IB_MAC_IOCB_RSP_HL 0x80
1060 __le32 hdr_len; /* */
1061 __le64 hdr_addr; /* */
1062 } __attribute((packed));
1063
1064 struct ib_ae_iocb_rsp {
1065 u8 opcode;
1066 u8 flags1;
1067 #define IB_AE_IOCB_RSP_OI 0x01
1068 #define IB_AE_IOCB_RSP_I 0x02
1069 u8 event;
1070 #define LINK_UP_EVENT 0x00
1071 #define LINK_DOWN_EVENT 0x01
1072 #define CAM_LOOKUP_ERR_EVENT 0x06
1073 #define SOFT_ECC_ERROR_EVENT 0x07
1074 #define MGMT_ERR_EVENT 0x08
1075 #define TEN_GIG_MAC_EVENT 0x09
1076 #define GPI0_H2L_EVENT 0x10
1077 #define GPI0_L2H_EVENT 0x20
1078 #define GPI1_H2L_EVENT 0x11
1079 #define GPI1_L2H_EVENT 0x21
1080 #define PCI_ERR_ANON_BUF_RD 0x40
1081 u8 q_id;
1082 __le32 reserved[15];
1083 } __attribute((packed));
1084
1085 /*
1086 * These three structures are for generic
1087 * handling of ib and ob iocbs.
1088 */
1089 struct ql_net_rsp_iocb {
1090 u8 opcode;
1091 u8 flags0;
1092 __le16 length;
1093 __le32 tid;
1094 __le32 reserved[14];
1095 } __attribute((packed));
1096
1097 struct net_req_iocb {
1098 u8 opcode;
1099 u8 flags0;
1100 __le16 flags1;
1101 __le32 tid;
1102 __le32 reserved1[30];
1103 } __attribute((packed));
1104
1105 /*
1106 * tx ring initialization control block for chip.
1107 * It is defined as:
1108 * "Work Queue Initialization Control Block"
1109 */
1110 struct wqicb {
1111 __le16 len;
1112 #define Q_LEN_V (1 << 4)
1113 #define Q_LEN_CPP_CONT 0x0000
1114 #define Q_LEN_CPP_16 0x0001
1115 #define Q_LEN_CPP_32 0x0002
1116 #define Q_LEN_CPP_64 0x0003
1117 #define Q_LEN_CPP_512 0x0006
1118 __le16 flags;
1119 #define Q_PRI_SHIFT 1
1120 #define Q_FLAGS_LC 0x1000
1121 #define Q_FLAGS_LB 0x2000
1122 #define Q_FLAGS_LI 0x4000
1123 #define Q_FLAGS_LO 0x8000
1124 __le16 cq_id_rss;
1125 #define Q_CQ_ID_RSS_RV 0x8000
1126 __le16 rid;
1127 __le64 addr;
1128 __le64 cnsmr_idx_addr;
1129 } __attribute((packed));
1130
1131 /*
1132 * rx ring initialization control block for chip.
1133 * It is defined as:
1134 * "Completion Queue Initialization Control Block"
1135 */
1136 struct cqicb {
1137 u8 msix_vect;
1138 u8 reserved1;
1139 u8 reserved2;
1140 u8 flags;
1141 #define FLAGS_LV 0x08
1142 #define FLAGS_LS 0x10
1143 #define FLAGS_LL 0x20
1144 #define FLAGS_LI 0x40
1145 #define FLAGS_LC 0x80
1146 __le16 len;
1147 #define LEN_V (1 << 4)
1148 #define LEN_CPP_CONT 0x0000
1149 #define LEN_CPP_32 0x0001
1150 #define LEN_CPP_64 0x0002
1151 #define LEN_CPP_128 0x0003
1152 __le16 rid;
1153 __le64 addr;
1154 __le64 prod_idx_addr;
1155 __le16 pkt_delay;
1156 __le16 irq_delay;
1157 __le64 lbq_addr;
1158 __le16 lbq_buf_size;
1159 __le16 lbq_len; /* entry count */
1160 __le64 sbq_addr;
1161 __le16 sbq_buf_size;
1162 __le16 sbq_len; /* entry count */
1163 } __attribute((packed));
1164
1165 struct ricb {
1166 u8 base_cq;
1167 #define RSS_L4K 0x80
1168 u8 flags;
1169 #define RSS_L6K 0x01
1170 #define RSS_LI 0x02
1171 #define RSS_LB 0x04
1172 #define RSS_LM 0x08
1173 #define RSS_RI4 0x10
1174 #define RSS_RT4 0x20
1175 #define RSS_RI6 0x40
1176 #define RSS_RT6 0x80
1177 __le16 mask;
1178 u8 hash_cq_id[1024];
1179 __le32 ipv6_hash_key[10];
1180 __le32 ipv4_hash_key[4];
1181 } __attribute((packed));
1182
1183 /* SOFTWARE/DRIVER DATA STRUCTURES. */
1184
1185 struct oal {
1186 struct tx_buf_desc oal[TX_DESC_PER_OAL];
1187 };
1188
1189 struct map_list {
1190 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1191 DECLARE_PCI_UNMAP_LEN(maplen);
1192 };
1193
1194 struct tx_ring_desc {
1195 struct sk_buff *skb;
1196 struct ob_mac_iocb_req *queue_entry;
1197 u32 index;
1198 struct oal oal;
1199 struct map_list map[MAX_SKB_FRAGS + 1];
1200 int map_cnt;
1201 struct tx_ring_desc *next;
1202 };
1203
1204 struct bq_desc {
1205 union {
1206 struct page *lbq_page;
1207 struct sk_buff *skb;
1208 } p;
1209 __le64 *addr;
1210 u32 index;
1211 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1212 DECLARE_PCI_UNMAP_LEN(maplen);
1213 };
1214
1215 #define QL_TXQ_IDX(qdev, skb) (smp_processor_id()%(qdev->tx_ring_count))
1216
1217 struct tx_ring {
1218 /*
1219 * queue info.
1220 */
1221 struct wqicb wqicb; /* structure used to inform chip of new queue */
1222 void *wq_base; /* pci_alloc:virtual addr for tx */
1223 dma_addr_t wq_base_dma; /* pci_alloc:dma addr for tx */
1224 __le32 *cnsmr_idx_sh_reg; /* shadow copy of consumer idx */
1225 dma_addr_t cnsmr_idx_sh_reg_dma; /* dma-shadow copy of consumer */
1226 u32 wq_size; /* size in bytes of queue area */
1227 u32 wq_len; /* number of entries in queue */
1228 void __iomem *prod_idx_db_reg; /* doorbell area index reg at offset 0x00 */
1229 void __iomem *valid_db_reg; /* doorbell area valid reg at offset 0x04 */
1230 u16 prod_idx; /* current value for prod idx */
1231 u16 cq_id; /* completion (rx) queue for tx completions */
1232 u8 wq_id; /* queue id for this entry */
1233 u8 reserved1[3];
1234 struct tx_ring_desc *q; /* descriptor list for the queue */
1235 spinlock_t lock;
1236 atomic_t tx_count; /* counts down for every outstanding IO */
1237 atomic_t queue_stopped; /* Turns queue off when full. */
1238 struct delayed_work tx_work;
1239 struct ql_adapter *qdev;
1240 };
1241
1242 /*
1243 * Type of inbound queue.
1244 */
1245 enum {
1246 DEFAULT_Q = 2, /* Handles slow queue and chip/MPI events. */
1247 TX_Q = 3, /* Handles outbound completions. */
1248 RX_Q = 4, /* Handles inbound completions. */
1249 };
1250
1251 struct rx_ring {
1252 struct cqicb cqicb; /* The chip's completion queue init control block. */
1253
1254 /* Completion queue elements. */
1255 void *cq_base;
1256 dma_addr_t cq_base_dma;
1257 u32 cq_size;
1258 u32 cq_len;
1259 u16 cq_id;
1260 __le32 *prod_idx_sh_reg; /* Shadowed producer register. */
1261 dma_addr_t prod_idx_sh_reg_dma;
1262 void __iomem *cnsmr_idx_db_reg; /* PCI doorbell mem area + 0 */
1263 u32 cnsmr_idx; /* current sw idx */
1264 struct ql_net_rsp_iocb *curr_entry; /* next entry on queue */
1265 void __iomem *valid_db_reg; /* PCI doorbell mem area + 0x04 */
1266
1267 /* Large buffer queue elements. */
1268 u32 lbq_len; /* entry count */
1269 u32 lbq_size; /* size in bytes of queue */
1270 u32 lbq_buf_size;
1271 void *lbq_base;
1272 dma_addr_t lbq_base_dma;
1273 void *lbq_base_indirect;
1274 dma_addr_t lbq_base_indirect_dma;
1275 struct bq_desc *lbq; /* array of control blocks */
1276 void __iomem *lbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x18 */
1277 u32 lbq_prod_idx; /* current sw prod idx */
1278 u32 lbq_curr_idx; /* next entry we expect */
1279 u32 lbq_clean_idx; /* beginning of new descs */
1280 u32 lbq_free_cnt; /* free buffer desc cnt */
1281
1282 /* Small buffer queue elements. */
1283 u32 sbq_len; /* entry count */
1284 u32 sbq_size; /* size in bytes of queue */
1285 u32 sbq_buf_size;
1286 void *sbq_base;
1287 dma_addr_t sbq_base_dma;
1288 void *sbq_base_indirect;
1289 dma_addr_t sbq_base_indirect_dma;
1290 struct bq_desc *sbq; /* array of control blocks */
1291 void __iomem *sbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x1c */
1292 u32 sbq_prod_idx; /* current sw prod idx */
1293 u32 sbq_curr_idx; /* next entry we expect */
1294 u32 sbq_clean_idx; /* beginning of new descs */
1295 u32 sbq_free_cnt; /* free buffer desc cnt */
1296
1297 /* Misc. handler elements. */
1298 u32 type; /* Type of queue, tx, rx. */
1299 u32 irq; /* Which vector this ring is assigned. */
1300 u32 cpu; /* Which CPU this should run on. */
1301 char name[IFNAMSIZ + 5];
1302 struct napi_struct napi;
1303 u8 reserved;
1304 struct ql_adapter *qdev;
1305 };
1306
1307 /*
1308 * RSS Initialization Control Block
1309 */
1310 struct hash_id {
1311 u8 value[4];
1312 };
1313
1314 struct nic_stats {
1315 /*
1316 * These stats come from offset 200h to 278h
1317 * in the XGMAC register.
1318 */
1319 u64 tx_pkts;
1320 u64 tx_bytes;
1321 u64 tx_mcast_pkts;
1322 u64 tx_bcast_pkts;
1323 u64 tx_ucast_pkts;
1324 u64 tx_ctl_pkts;
1325 u64 tx_pause_pkts;
1326 u64 tx_64_pkt;
1327 u64 tx_65_to_127_pkt;
1328 u64 tx_128_to_255_pkt;
1329 u64 tx_256_511_pkt;
1330 u64 tx_512_to_1023_pkt;
1331 u64 tx_1024_to_1518_pkt;
1332 u64 tx_1519_to_max_pkt;
1333 u64 tx_undersize_pkt;
1334 u64 tx_oversize_pkt;
1335
1336 /*
1337 * These stats come from offset 300h to 3C8h
1338 * in the XGMAC register.
1339 */
1340 u64 rx_bytes;
1341 u64 rx_bytes_ok;
1342 u64 rx_pkts;
1343 u64 rx_pkts_ok;
1344 u64 rx_bcast_pkts;
1345 u64 rx_mcast_pkts;
1346 u64 rx_ucast_pkts;
1347 u64 rx_undersize_pkts;
1348 u64 rx_oversize_pkts;
1349 u64 rx_jabber_pkts;
1350 u64 rx_undersize_fcerr_pkts;
1351 u64 rx_drop_events;
1352 u64 rx_fcerr_pkts;
1353 u64 rx_align_err;
1354 u64 rx_symbol_err;
1355 u64 rx_mac_err;
1356 u64 rx_ctl_pkts;
1357 u64 rx_pause_pkts;
1358 u64 rx_64_pkts;
1359 u64 rx_65_to_127_pkts;
1360 u64 rx_128_255_pkts;
1361 u64 rx_256_511_pkts;
1362 u64 rx_512_to_1023_pkts;
1363 u64 rx_1024_to_1518_pkts;
1364 u64 rx_1519_to_max_pkts;
1365 u64 rx_len_err_pkts;
1366 };
1367
1368 /*
1369 * intr_context structure is used during initialization
1370 * to hook the interrupts. It is also used in a single
1371 * irq environment as a context to the ISR.
1372 */
1373 struct intr_context {
1374 struct ql_adapter *qdev;
1375 u32 intr;
1376 u32 irq_mask; /* Mask of which rings the vector services. */
1377 u32 hooked;
1378 u32 intr_en_mask; /* value/mask used to enable this intr */
1379 u32 intr_dis_mask; /* value/mask used to disable this intr */
1380 u32 intr_read_mask; /* value/mask used to read this intr */
1381 char name[IFNAMSIZ * 2];
1382 atomic_t irq_cnt; /* irq_cnt is used in single vector
1383 * environment. It's incremented for each
1384 * irq handler that is scheduled. When each
1385 * handler finishes it decrements irq_cnt and
1386 * enables interrupts if it's zero. */
1387 irq_handler_t handler;
1388 };
1389
1390 /* adapter flags definitions. */
1391 enum {
1392 QL_ADAPTER_UP = 0, /* Adapter has been brought up. */
1393 QL_LEGACY_ENABLED = 1,
1394 QL_MSI_ENABLED = 2,
1395 QL_MSIX_ENABLED = 3,
1396 QL_DMA64 = 4,
1397 QL_PROMISCUOUS = 5,
1398 QL_ALLMULTI = 6,
1399 QL_PORT_CFG = 7,
1400 QL_CAM_RT_SET = 8,
1401 };
1402
1403 /* link_status bit definitions */
1404 enum {
1405 STS_LOOPBACK_MASK = 0x00000700,
1406 STS_LOOPBACK_PCS = 0x00000100,
1407 STS_LOOPBACK_HSS = 0x00000200,
1408 STS_LOOPBACK_EXT = 0x00000300,
1409 STS_PAUSE_MASK = 0x000000c0,
1410 STS_PAUSE_STD = 0x00000040,
1411 STS_PAUSE_PRI = 0x00000080,
1412 STS_SPEED_MASK = 0x00000038,
1413 STS_SPEED_100Mb = 0x00000000,
1414 STS_SPEED_1Gb = 0x00000008,
1415 STS_SPEED_10Gb = 0x00000010,
1416 STS_LINK_TYPE_MASK = 0x00000007,
1417 STS_LINK_TYPE_XFI = 0x00000001,
1418 STS_LINK_TYPE_XAUI = 0x00000002,
1419 STS_LINK_TYPE_XFI_BP = 0x00000003,
1420 STS_LINK_TYPE_XAUI_BP = 0x00000004,
1421 STS_LINK_TYPE_10GBASET = 0x00000005,
1422 };
1423
1424 /* link_config bit definitions */
1425 enum {
1426 CFG_JUMBO_FRAME_SIZE = 0x00010000,
1427 CFG_PAUSE_MASK = 0x00000060,
1428 CFG_PAUSE_STD = 0x00000020,
1429 CFG_PAUSE_PRI = 0x00000040,
1430 CFG_DCBX = 0x00000010,
1431 CFG_LOOPBACK_MASK = 0x00000007,
1432 CFG_LOOPBACK_PCS = 0x00000002,
1433 CFG_LOOPBACK_HSS = 0x00000004,
1434 CFG_LOOPBACK_EXT = 0x00000006,
1435 CFG_DEFAULT_MAX_FRAME_SIZE = 0x00002580,
1436 };
1437
1438 struct nic_operations {
1439
1440 int (*get_flash) (struct ql_adapter *);
1441 int (*port_initialize) (struct ql_adapter *);
1442 };
1443
1444 /*
1445 * The main Adapter structure definition.
1446 * This structure has all fields relevant to the hardware.
1447 */
1448 struct ql_adapter {
1449 struct ricb ricb;
1450 unsigned long flags;
1451 u32 wol;
1452
1453 struct nic_stats nic_stats;
1454
1455 struct vlan_group *vlgrp;
1456
1457 /* PCI Configuration information for this device */
1458 struct pci_dev *pdev;
1459 struct net_device *ndev; /* Parent NET device */
1460
1461 /* Hardware information */
1462 u32 chip_rev_id;
1463 u32 fw_rev_id;
1464 u32 func; /* PCI function for this adapter */
1465 u32 alt_func; /* PCI function for alternate adapter */
1466 u32 port; /* Port number this adapter */
1467
1468 spinlock_t adapter_lock;
1469 spinlock_t hw_lock;
1470 spinlock_t stats_lock;
1471
1472 /* PCI Bus Relative Register Addresses */
1473 void __iomem *reg_base;
1474 void __iomem *doorbell_area;
1475 u32 doorbell_area_size;
1476
1477 u32 msg_enable;
1478
1479 /* Page for Shadow Registers */
1480 void *rx_ring_shadow_reg_area;
1481 dma_addr_t rx_ring_shadow_reg_dma;
1482 void *tx_ring_shadow_reg_area;
1483 dma_addr_t tx_ring_shadow_reg_dma;
1484
1485 u32 mailbox_in;
1486 u32 mailbox_out;
1487 struct mbox_params idc_mbc;
1488
1489 int tx_ring_size;
1490 int rx_ring_size;
1491 u32 intr_count;
1492 struct msix_entry *msi_x_entry;
1493 struct intr_context intr_context[MAX_RX_RINGS];
1494
1495 int tx_ring_count; /* One per online CPU. */
1496 u32 rss_ring_count; /* One per irq vector. */
1497 /*
1498 * rx_ring_count =
1499 * (CPU count * outbound completion rx_ring) +
1500 * (irq_vector_cnt * inbound (RSS) completion rx_ring)
1501 */
1502 int rx_ring_count;
1503 int ring_mem_size;
1504 void *ring_mem;
1505
1506 struct rx_ring rx_ring[MAX_RX_RINGS];
1507 struct tx_ring tx_ring[MAX_TX_RINGS];
1508
1509 int rx_csum;
1510 u32 default_rx_queue;
1511
1512 u16 rx_coalesce_usecs; /* cqicb->int_delay */
1513 u16 rx_max_coalesced_frames; /* cqicb->pkt_int_delay */
1514 u16 tx_coalesce_usecs; /* cqicb->int_delay */
1515 u16 tx_max_coalesced_frames; /* cqicb->pkt_int_delay */
1516
1517 u32 xg_sem_mask;
1518 u32 port_link_up;
1519 u32 port_init;
1520 u32 link_status;
1521 u32 link_config;
1522 u32 max_frame_size;
1523
1524 union flash_params flash;
1525
1526 struct net_device_stats stats;
1527 struct workqueue_struct *workqueue;
1528 struct delayed_work asic_reset_work;
1529 struct delayed_work mpi_reset_work;
1530 struct delayed_work mpi_work;
1531 struct delayed_work mpi_port_cfg_work;
1532 struct delayed_work mpi_idc_work;
1533 struct completion ide_completion;
1534 struct nic_operations *nic_ops;
1535 u16 device_id;
1536 };
1537
1538 /*
1539 * Typical Register accessor for memory mapped device.
1540 */
1541 static inline u32 ql_read32(const struct ql_adapter *qdev, int reg)
1542 {
1543 return readl(qdev->reg_base + reg);
1544 }
1545
1546 /*
1547 * Typical Register accessor for memory mapped device.
1548 */
1549 static inline void ql_write32(const struct ql_adapter *qdev, int reg, u32 val)
1550 {
1551 writel(val, qdev->reg_base + reg);
1552 }
1553
1554 /*
1555 * Doorbell Registers:
1556 * Doorbell registers are virtual registers in the PCI memory space.
1557 * The space is allocated by the chip during PCI initialization. The
1558 * device driver finds the doorbell address in BAR 3 in PCI config space.
1559 * The registers are used to control outbound and inbound queues. For
1560 * example, the producer index for an outbound queue. Each queue uses
1561 * 1 4k chunk of memory. The lower half of the space is for outbound
1562 * queues. The upper half is for inbound queues.
1563 */
1564 static inline void ql_write_db_reg(u32 val, void __iomem *addr)
1565 {
1566 writel(val, addr);
1567 mmiowb();
1568 }
1569
1570 /*
1571 * Shadow Registers:
1572 * Outbound queues have a consumer index that is maintained by the chip.
1573 * Inbound queues have a producer index that is maintained by the chip.
1574 * For lower overhead, these registers are "shadowed" to host memory
1575 * which allows the device driver to track the queue progress without
1576 * PCI reads. When an entry is placed on an inbound queue, the chip will
1577 * update the relevant index register and then copy the value to the
1578 * shadow register in host memory.
1579 */
1580 static inline u32 ql_read_sh_reg(__le32 *addr)
1581 {
1582 u32 reg;
1583 reg = le32_to_cpu(*addr);
1584 rmb();
1585 return reg;
1586 }
1587
1588 extern char qlge_driver_name[];
1589 extern const char qlge_driver_version[];
1590 extern const struct ethtool_ops qlge_ethtool_ops;
1591
1592 extern int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask);
1593 extern void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask);
1594 extern int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
1595 extern int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
1596 u32 *value);
1597 extern int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value);
1598 extern int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
1599 u16 q_id);
1600 void ql_queue_fw_error(struct ql_adapter *qdev);
1601 void ql_mpi_work(struct work_struct *work);
1602 void ql_mpi_reset_work(struct work_struct *work);
1603 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 ebit);
1604 void ql_queue_asic_error(struct ql_adapter *qdev);
1605 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr);
1606 void ql_set_ethtool_ops(struct net_device *ndev);
1607 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data);
1608 void ql_mpi_idc_work(struct work_struct *work);
1609 void ql_mpi_port_cfg_work(struct work_struct *work);
1610 int ql_mb_get_fw_state(struct ql_adapter *qdev);
1611 int ql_cam_route_initialize(struct ql_adapter *qdev);
1612 int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
1613 int ql_mb_about_fw(struct ql_adapter *qdev);
1614 void ql_link_on(struct ql_adapter *qdev);
1615 void ql_link_off(struct ql_adapter *qdev);
1616 int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 control);
1617 int ql_wait_fifo_empty(struct ql_adapter *qdev);
1618
1619 #if 1
1620 #define QL_ALL_DUMP
1621 #define QL_REG_DUMP
1622 #define QL_DEV_DUMP
1623 #define QL_CB_DUMP
1624 /* #define QL_IB_DUMP */
1625 /* #define QL_OB_DUMP */
1626 #endif
1627
1628 #ifdef QL_REG_DUMP
1629 extern void ql_dump_xgmac_control_regs(struct ql_adapter *qdev);
1630 extern void ql_dump_routing_entries(struct ql_adapter *qdev);
1631 extern void ql_dump_regs(struct ql_adapter *qdev);
1632 #define QL_DUMP_REGS(qdev) ql_dump_regs(qdev)
1633 #define QL_DUMP_ROUTE(qdev) ql_dump_routing_entries(qdev)
1634 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev) ql_dump_xgmac_control_regs(qdev)
1635 #else
1636 #define QL_DUMP_REGS(qdev)
1637 #define QL_DUMP_ROUTE(qdev)
1638 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev)
1639 #endif
1640
1641 #ifdef QL_STAT_DUMP
1642 extern void ql_dump_stat(struct ql_adapter *qdev);
1643 #define QL_DUMP_STAT(qdev) ql_dump_stat(qdev)
1644 #else
1645 #define QL_DUMP_STAT(qdev)
1646 #endif
1647
1648 #ifdef QL_DEV_DUMP
1649 extern void ql_dump_qdev(struct ql_adapter *qdev);
1650 #define QL_DUMP_QDEV(qdev) ql_dump_qdev(qdev)
1651 #else
1652 #define QL_DUMP_QDEV(qdev)
1653 #endif
1654
1655 #ifdef QL_CB_DUMP
1656 extern void ql_dump_wqicb(struct wqicb *wqicb);
1657 extern void ql_dump_tx_ring(struct tx_ring *tx_ring);
1658 extern void ql_dump_ricb(struct ricb *ricb);
1659 extern void ql_dump_cqicb(struct cqicb *cqicb);
1660 extern void ql_dump_rx_ring(struct rx_ring *rx_ring);
1661 extern void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id);
1662 #define QL_DUMP_RICB(ricb) ql_dump_ricb(ricb)
1663 #define QL_DUMP_WQICB(wqicb) ql_dump_wqicb(wqicb)
1664 #define QL_DUMP_TX_RING(tx_ring) ql_dump_tx_ring(tx_ring)
1665 #define QL_DUMP_CQICB(cqicb) ql_dump_cqicb(cqicb)
1666 #define QL_DUMP_RX_RING(rx_ring) ql_dump_rx_ring(rx_ring)
1667 #define QL_DUMP_HW_CB(qdev, size, bit, q_id) \
1668 ql_dump_hw_cb(qdev, size, bit, q_id)
1669 #else
1670 #define QL_DUMP_RICB(ricb)
1671 #define QL_DUMP_WQICB(wqicb)
1672 #define QL_DUMP_TX_RING(tx_ring)
1673 #define QL_DUMP_CQICB(cqicb)
1674 #define QL_DUMP_RX_RING(rx_ring)
1675 #define QL_DUMP_HW_CB(qdev, size, bit, q_id)
1676 #endif
1677
1678 #ifdef QL_OB_DUMP
1679 extern void ql_dump_tx_desc(struct tx_buf_desc *tbd);
1680 extern void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb);
1681 extern void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp);
1682 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) ql_dump_ob_mac_iocb(ob_mac_iocb)
1683 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) ql_dump_ob_mac_rsp(ob_mac_rsp)
1684 #else
1685 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb)
1686 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp)
1687 #endif
1688
1689 #ifdef QL_IB_DUMP
1690 extern void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp);
1691 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) ql_dump_ib_mac_rsp(ib_mac_rsp)
1692 #else
1693 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp)
1694 #endif
1695
1696 #ifdef QL_ALL_DUMP
1697 extern void ql_dump_all(struct ql_adapter *qdev);
1698 #define QL_DUMP_ALL(qdev) ql_dump_all(qdev)
1699 #else
1700 #define QL_DUMP_ALL(qdev)
1701 #endif
1702
1703 #endif /* _QLGE_H_ */
Linux with added FPC-III support