?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / net / skge.c
blob8f5414348e8629569a6fa12ff08f710d425abe6a
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/in.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/if_vlan.h>
35 #include <linux/ip.h>
36 #include <linux/delay.h>
37 #include <linux/crc32.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/debugfs.h>
40 #include <linux/sched.h>
41 #include <linux/seq_file.h>
42 #include <linux/mii.h>
43 #include <asm/irq.h>
44
45 #include "skge.h"
46
47 #define DRV_NAME "skge"
48 #define DRV_VERSION "1.13"
49 #define PFX DRV_NAME " "
50
51 #define DEFAULT_TX_RING_SIZE 128
52 #define DEFAULT_RX_RING_SIZE 512
53 #define MAX_TX_RING_SIZE 1024
54 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
55 #define MAX_RX_RING_SIZE 4096
56 #define RX_COPY_THRESHOLD 128
57 #define RX_BUF_SIZE 1536
58 #define PHY_RETRIES 1000
59 #define ETH_JUMBO_MTU 9000
60 #define TX_WATCHDOG (5 * HZ)
61 #define NAPI_WEIGHT 64
62 #define BLINK_MS 250
63 #define LINK_HZ HZ
64
65 #define SKGE_EEPROM_MAGIC 0x9933aabb
66
67
68 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
69 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
70 MODULE_LICENSE("GPL");
71 MODULE_VERSION(DRV_VERSION);
72
73 static const u32 default_msg
74 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
75 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
76
77 static int debug = -1; /* defaults above */
78 module_param(debug, int, 0);
79 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
80
81 static const struct pci_device_id skge_id_table[] = {
82 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
83 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
84 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
85 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
86 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
87 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
88 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
89 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
90 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
91 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
92 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
93 { 0 }
94 };
95 MODULE_DEVICE_TABLE(pci, skge_id_table);
96
97 static int skge_up(struct net_device *dev);
98 static int skge_down(struct net_device *dev);
99 static void skge_phy_reset(struct skge_port *skge);
100 static void skge_tx_clean(struct net_device *dev);
101 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
102 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
103 static void genesis_get_stats(struct skge_port *skge, u64 *data);
104 static void yukon_get_stats(struct skge_port *skge, u64 *data);
105 static void yukon_init(struct skge_hw *hw, int port);
106 static void genesis_mac_init(struct skge_hw *hw, int port);
107 static void genesis_link_up(struct skge_port *skge);
108 static void skge_set_multicast(struct net_device *dev);
109
110 /* Avoid conditionals by using array */
111 static const int txqaddr[] = { Q_XA1, Q_XA2 };
112 static const int rxqaddr[] = { Q_R1, Q_R2 };
113 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
114 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
115 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
116 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
117
118 static int skge_get_regs_len(struct net_device *dev)
119 {
120 return 0x4000;
121 }
122
123 /*
124 * Returns copy of whole control register region
125 * Note: skip RAM address register because accessing it will
126 * cause bus hangs!
127 */
128 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
129 void *p)
130 {
131 const struct skge_port *skge = netdev_priv(dev);
132 const void __iomem *io = skge->hw->regs;
133
134 regs->version = 1;
135 memset(p, 0, regs->len);
136 memcpy_fromio(p, io, B3_RAM_ADDR);
137
138 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
139 regs->len - B3_RI_WTO_R1);
140 }
141
142 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
143 static u32 wol_supported(const struct skge_hw *hw)
144 {
145 if (hw->chip_id == CHIP_ID_GENESIS)
146 return 0;
147
148 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
149 return 0;
150
151 return WAKE_MAGIC | WAKE_PHY;
152 }
153
154 static void skge_wol_init(struct skge_port *skge)
155 {
156 struct skge_hw *hw = skge->hw;
157 int port = skge->port;
158 u16 ctrl;
159
160 skge_write16(hw, B0_CTST, CS_RST_CLR);
161 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
162
163 /* Turn on Vaux */
164 skge_write8(hw, B0_POWER_CTRL,
165 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
166
167 /* WA code for COMA mode -- clear PHY reset */
168 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
169 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
170 u32 reg = skge_read32(hw, B2_GP_IO);
171 reg |= GP_DIR_9;
172 reg &= ~GP_IO_9;
173 skge_write32(hw, B2_GP_IO, reg);
174 }
175
176 skge_write32(hw, SK_REG(port, GPHY_CTRL),
177 GPC_DIS_SLEEP |
178 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
179 GPC_ANEG_1 | GPC_RST_SET);
180
181 skge_write32(hw, SK_REG(port, GPHY_CTRL),
182 GPC_DIS_SLEEP |
183 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
184 GPC_ANEG_1 | GPC_RST_CLR);
185
186 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
187
188 /* Force to 10/100 skge_reset will re-enable on resume */
189 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
190 PHY_AN_100FULL | PHY_AN_100HALF |
191 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
192 /* no 1000 HD/FD */
193 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
194 gm_phy_write(hw, port, PHY_MARV_CTRL,
195 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
196 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
197
198
199 /* Set GMAC to no flow control and auto update for speed/duplex */
200 gma_write16(hw, port, GM_GP_CTRL,
201 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
202 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
203
204 /* Set WOL address */
205 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
206 skge->netdev->dev_addr, ETH_ALEN);
207
208 /* Turn on appropriate WOL control bits */
209 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
210 ctrl = 0;
211 if (skge->wol & WAKE_PHY)
212 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
213 else
214 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
215
216 if (skge->wol & WAKE_MAGIC)
217 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
218 else
219 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
220
221 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
222 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
223
224 /* block receiver */
225 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
226 }
227
228 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
229 {
230 struct skge_port *skge = netdev_priv(dev);
231
232 wol->supported = wol_supported(skge->hw);
233 wol->wolopts = skge->wol;
234 }
235
236 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
237 {
238 struct skge_port *skge = netdev_priv(dev);
239 struct skge_hw *hw = skge->hw;
240
241 if ((wol->wolopts & ~wol_supported(hw))
242 || !device_can_wakeup(&hw->pdev->dev))
243 return -EOPNOTSUPP;
244
245 skge->wol = wol->wolopts;
246
247 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
248
249 return 0;
250 }
251
252 /* Determine supported/advertised modes based on hardware.
253 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
254 */
255 static u32 skge_supported_modes(const struct skge_hw *hw)
256 {
257 u32 supported;
258
259 if (hw->copper) {
260 supported = SUPPORTED_10baseT_Half
261 | SUPPORTED_10baseT_Full
262 | SUPPORTED_100baseT_Half
263 | SUPPORTED_100baseT_Full
264 | SUPPORTED_1000baseT_Half
265 | SUPPORTED_1000baseT_Full
266 | SUPPORTED_Autoneg| SUPPORTED_TP;
267
268 if (hw->chip_id == CHIP_ID_GENESIS)
269 supported &= ~(SUPPORTED_10baseT_Half
270 | SUPPORTED_10baseT_Full
271 | SUPPORTED_100baseT_Half
272 | SUPPORTED_100baseT_Full);
273
274 else if (hw->chip_id == CHIP_ID_YUKON)
275 supported &= ~SUPPORTED_1000baseT_Half;
276 } else
277 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
278 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
279
280 return supported;
281 }
282
283 static int skge_get_settings(struct net_device *dev,
284 struct ethtool_cmd *ecmd)
285 {
286 struct skge_port *skge = netdev_priv(dev);
287 struct skge_hw *hw = skge->hw;
288
289 ecmd->transceiver = XCVR_INTERNAL;
290 ecmd->supported = skge_supported_modes(hw);
291
292 if (hw->copper) {
293 ecmd->port = PORT_TP;
294 ecmd->phy_address = hw->phy_addr;
295 } else
296 ecmd->port = PORT_FIBRE;
297
298 ecmd->advertising = skge->advertising;
299 ecmd->autoneg = skge->autoneg;
300 ecmd->speed = skge->speed;
301 ecmd->duplex = skge->duplex;
302 return 0;
303 }
304
305 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
306 {
307 struct skge_port *skge = netdev_priv(dev);
308 const struct skge_hw *hw = skge->hw;
309 u32 supported = skge_supported_modes(hw);
310 int err = 0;
311
312 if (ecmd->autoneg == AUTONEG_ENABLE) {
313 ecmd->advertising = supported;
314 skge->duplex = -1;
315 skge->speed = -1;
316 } else {
317 u32 setting;
318
319 switch (ecmd->speed) {
320 case SPEED_1000:
321 if (ecmd->duplex == DUPLEX_FULL)
322 setting = SUPPORTED_1000baseT_Full;
323 else if (ecmd->duplex == DUPLEX_HALF)
324 setting = SUPPORTED_1000baseT_Half;
325 else
326 return -EINVAL;
327 break;
328 case SPEED_100:
329 if (ecmd->duplex == DUPLEX_FULL)
330 setting = SUPPORTED_100baseT_Full;
331 else if (ecmd->duplex == DUPLEX_HALF)
332 setting = SUPPORTED_100baseT_Half;
333 else
334 return -EINVAL;
335 break;
336
337 case SPEED_10:
338 if (ecmd->duplex == DUPLEX_FULL)
339 setting = SUPPORTED_10baseT_Full;
340 else if (ecmd->duplex == DUPLEX_HALF)
341 setting = SUPPORTED_10baseT_Half;
342 else
343 return -EINVAL;
344 break;
345 default:
346 return -EINVAL;
347 }
348
349 if ((setting & supported) == 0)
350 return -EINVAL;
351
352 skge->speed = ecmd->speed;
353 skge->duplex = ecmd->duplex;
354 }
355
356 skge->autoneg = ecmd->autoneg;
357 skge->advertising = ecmd->advertising;
358
359 if (netif_running(dev)) {
360 skge_down(dev);
361 err = skge_up(dev);
362 if (err) {
363 dev_close(dev);
364 return err;
365 }
366 }
367
368 return (0);
369 }
370
371 static void skge_get_drvinfo(struct net_device *dev,
372 struct ethtool_drvinfo *info)
373 {
374 struct skge_port *skge = netdev_priv(dev);
375
376 strcpy(info->driver, DRV_NAME);
377 strcpy(info->version, DRV_VERSION);
378 strcpy(info->fw_version, "N/A");
379 strcpy(info->bus_info, pci_name(skge->hw->pdev));
380 }
381
382 static const struct skge_stat {
383 char name[ETH_GSTRING_LEN];
384 u16 xmac_offset;
385 u16 gma_offset;
386 } skge_stats[] = {
387 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
388 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
389
390 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
391 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
392 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
393 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
394 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
395 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
396 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
397 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
398
399 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
400 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
401 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
402 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
403 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
404 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
405
406 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
407 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
408 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
409 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
410 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
411 };
412
413 static int skge_get_sset_count(struct net_device *dev, int sset)
414 {
415 switch (sset) {
416 case ETH_SS_STATS:
417 return ARRAY_SIZE(skge_stats);
418 default:
419 return -EOPNOTSUPP;
420 }
421 }
422
423 static void skge_get_ethtool_stats(struct net_device *dev,
424 struct ethtool_stats *stats, u64 *data)
425 {
426 struct skge_port *skge = netdev_priv(dev);
427
428 if (skge->hw->chip_id == CHIP_ID_GENESIS)
429 genesis_get_stats(skge, data);
430 else
431 yukon_get_stats(skge, data);
432 }
433
434 /* Use hardware MIB variables for critical path statistics and
435 * transmit feedback not reported at interrupt.
436 * Other errors are accounted for in interrupt handler.
437 */
438 static struct net_device_stats *skge_get_stats(struct net_device *dev)
439 {
440 struct skge_port *skge = netdev_priv(dev);
441 u64 data[ARRAY_SIZE(skge_stats)];
442
443 if (skge->hw->chip_id == CHIP_ID_GENESIS)
444 genesis_get_stats(skge, data);
445 else
446 yukon_get_stats(skge, data);
447
448 dev->stats.tx_bytes = data[0];
449 dev->stats.rx_bytes = data[1];
450 dev->stats.tx_packets = data[2] + data[4] + data[6];
451 dev->stats.rx_packets = data[3] + data[5] + data[7];
452 dev->stats.multicast = data[3] + data[5];
453 dev->stats.collisions = data[10];
454 dev->stats.tx_aborted_errors = data[12];
455
456 return &dev->stats;
457 }
458
459 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
460 {
461 int i;
462
463 switch (stringset) {
464 case ETH_SS_STATS:
465 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
466 memcpy(data + i * ETH_GSTRING_LEN,
467 skge_stats[i].name, ETH_GSTRING_LEN);
468 break;
469 }
470 }
471
472 static void skge_get_ring_param(struct net_device *dev,
473 struct ethtool_ringparam *p)
474 {
475 struct skge_port *skge = netdev_priv(dev);
476
477 p->rx_max_pending = MAX_RX_RING_SIZE;
478 p->tx_max_pending = MAX_TX_RING_SIZE;
479 p->rx_mini_max_pending = 0;
480 p->rx_jumbo_max_pending = 0;
481
482 p->rx_pending = skge->rx_ring.count;
483 p->tx_pending = skge->tx_ring.count;
484 p->rx_mini_pending = 0;
485 p->rx_jumbo_pending = 0;
486 }
487
488 static int skge_set_ring_param(struct net_device *dev,
489 struct ethtool_ringparam *p)
490 {
491 struct skge_port *skge = netdev_priv(dev);
492 int err = 0;
493
494 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
495 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
496 return -EINVAL;
497
498 skge->rx_ring.count = p->rx_pending;
499 skge->tx_ring.count = p->tx_pending;
500
501 if (netif_running(dev)) {
502 skge_down(dev);
503 err = skge_up(dev);
504 if (err)
505 dev_close(dev);
506 }
507
508 return err;
509 }
510
511 static u32 skge_get_msglevel(struct net_device *netdev)
512 {
513 struct skge_port *skge = netdev_priv(netdev);
514 return skge->msg_enable;
515 }
516
517 static void skge_set_msglevel(struct net_device *netdev, u32 value)
518 {
519 struct skge_port *skge = netdev_priv(netdev);
520 skge->msg_enable = value;
521 }
522
523 static int skge_nway_reset(struct net_device *dev)
524 {
525 struct skge_port *skge = netdev_priv(dev);
526
527 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
528 return -EINVAL;
529
530 skge_phy_reset(skge);
531 return 0;
532 }
533
534 static int skge_set_sg(struct net_device *dev, u32 data)
535 {
536 struct skge_port *skge = netdev_priv(dev);
537 struct skge_hw *hw = skge->hw;
538
539 if (hw->chip_id == CHIP_ID_GENESIS && data)
540 return -EOPNOTSUPP;
541 return ethtool_op_set_sg(dev, data);
542 }
543
544 static int skge_set_tx_csum(struct net_device *dev, u32 data)
545 {
546 struct skge_port *skge = netdev_priv(dev);
547 struct skge_hw *hw = skge->hw;
548
549 if (hw->chip_id == CHIP_ID_GENESIS && data)
550 return -EOPNOTSUPP;
551
552 return ethtool_op_set_tx_csum(dev, data);
553 }
554
555 static u32 skge_get_rx_csum(struct net_device *dev)
556 {
557 struct skge_port *skge = netdev_priv(dev);
558
559 return skge->rx_csum;
560 }
561
562 /* Only Yukon supports checksum offload. */
563 static int skge_set_rx_csum(struct net_device *dev, u32 data)
564 {
565 struct skge_port *skge = netdev_priv(dev);
566
567 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
568 return -EOPNOTSUPP;
569
570 skge->rx_csum = data;
571 return 0;
572 }
573
574 static void skge_get_pauseparam(struct net_device *dev,
575 struct ethtool_pauseparam *ecmd)
576 {
577 struct skge_port *skge = netdev_priv(dev);
578
579 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
580 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
581 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
582
583 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
584 }
585
586 static int skge_set_pauseparam(struct net_device *dev,
587 struct ethtool_pauseparam *ecmd)
588 {
589 struct skge_port *skge = netdev_priv(dev);
590 struct ethtool_pauseparam old;
591 int err = 0;
592
593 skge_get_pauseparam(dev, &old);
594
595 if (ecmd->autoneg != old.autoneg)
596 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
597 else {
598 if (ecmd->rx_pause && ecmd->tx_pause)
599 skge->flow_control = FLOW_MODE_SYMMETRIC;
600 else if (ecmd->rx_pause && !ecmd->tx_pause)
601 skge->flow_control = FLOW_MODE_SYM_OR_REM;
602 else if (!ecmd->rx_pause && ecmd->tx_pause)
603 skge->flow_control = FLOW_MODE_LOC_SEND;
604 else
605 skge->flow_control = FLOW_MODE_NONE;
606 }
607
608 if (netif_running(dev)) {
609 skge_down(dev);
610 err = skge_up(dev);
611 if (err) {
612 dev_close(dev);
613 return err;
614 }
615 }
616
617 return 0;
618 }
619
620 /* Chip internal frequency for clock calculations */
621 static inline u32 hwkhz(const struct skge_hw *hw)
622 {
623 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
624 }
625
626 /* Chip HZ to microseconds */
627 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
628 {
629 return (ticks * 1000) / hwkhz(hw);
630 }
631
632 /* Microseconds to chip HZ */
633 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
634 {
635 return hwkhz(hw) * usec / 1000;
636 }
637
638 static int skge_get_coalesce(struct net_device *dev,
639 struct ethtool_coalesce *ecmd)
640 {
641 struct skge_port *skge = netdev_priv(dev);
642 struct skge_hw *hw = skge->hw;
643 int port = skge->port;
644
645 ecmd->rx_coalesce_usecs = 0;
646 ecmd->tx_coalesce_usecs = 0;
647
648 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
649 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
650 u32 msk = skge_read32(hw, B2_IRQM_MSK);
651
652 if (msk & rxirqmask[port])
653 ecmd->rx_coalesce_usecs = delay;
654 if (msk & txirqmask[port])
655 ecmd->tx_coalesce_usecs = delay;
656 }
657
658 return 0;
659 }
660
661 /* Note: interrupt timer is per board, but can turn on/off per port */
662 static int skge_set_coalesce(struct net_device *dev,
663 struct ethtool_coalesce *ecmd)
664 {
665 struct skge_port *skge = netdev_priv(dev);
666 struct skge_hw *hw = skge->hw;
667 int port = skge->port;
668 u32 msk = skge_read32(hw, B2_IRQM_MSK);
669 u32 delay = 25;
670
671 if (ecmd->rx_coalesce_usecs == 0)
672 msk &= ~rxirqmask[port];
673 else if (ecmd->rx_coalesce_usecs < 25 ||
674 ecmd->rx_coalesce_usecs > 33333)
675 return -EINVAL;
676 else {
677 msk |= rxirqmask[port];
678 delay = ecmd->rx_coalesce_usecs;
679 }
680
681 if (ecmd->tx_coalesce_usecs == 0)
682 msk &= ~txirqmask[port];
683 else if (ecmd->tx_coalesce_usecs < 25 ||
684 ecmd->tx_coalesce_usecs > 33333)
685 return -EINVAL;
686 else {
687 msk |= txirqmask[port];
688 delay = min(delay, ecmd->rx_coalesce_usecs);
689 }
690
691 skge_write32(hw, B2_IRQM_MSK, msk);
692 if (msk == 0)
693 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
694 else {
695 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
696 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
697 }
698 return 0;
699 }
700
701 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
702 static void skge_led(struct skge_port *skge, enum led_mode mode)
703 {
704 struct skge_hw *hw = skge->hw;
705 int port = skge->port;
706
707 spin_lock_bh(&hw->phy_lock);
708 if (hw->chip_id == CHIP_ID_GENESIS) {
709 switch (mode) {
710 case LED_MODE_OFF:
711 if (hw->phy_type == SK_PHY_BCOM)
712 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
713 else {
714 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
715 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
716 }
717 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
718 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
719 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
720 break;
721
722 case LED_MODE_ON:
723 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
724 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
725
726 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
727 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
728
729 break;
730
731 case LED_MODE_TST:
732 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
733 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
734 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
735
736 if (hw->phy_type == SK_PHY_BCOM)
737 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
738 else {
739 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
740 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
741 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
742 }
743
744 }
745 } else {
746 switch (mode) {
747 case LED_MODE_OFF:
748 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
749 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
750 PHY_M_LED_MO_DUP(MO_LED_OFF) |
751 PHY_M_LED_MO_10(MO_LED_OFF) |
752 PHY_M_LED_MO_100(MO_LED_OFF) |
753 PHY_M_LED_MO_1000(MO_LED_OFF) |
754 PHY_M_LED_MO_RX(MO_LED_OFF));
755 break;
756 case LED_MODE_ON:
757 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
758 PHY_M_LED_PULS_DUR(PULS_170MS) |
759 PHY_M_LED_BLINK_RT(BLINK_84MS) |
760 PHY_M_LEDC_TX_CTRL |
761 PHY_M_LEDC_DP_CTRL);
762
763 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
764 PHY_M_LED_MO_RX(MO_LED_OFF) |
765 (skge->speed == SPEED_100 ?
766 PHY_M_LED_MO_100(MO_LED_ON) : 0));
767 break;
768 case LED_MODE_TST:
769 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
770 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
771 PHY_M_LED_MO_DUP(MO_LED_ON) |
772 PHY_M_LED_MO_10(MO_LED_ON) |
773 PHY_M_LED_MO_100(MO_LED_ON) |
774 PHY_M_LED_MO_1000(MO_LED_ON) |
775 PHY_M_LED_MO_RX(MO_LED_ON));
776 }
777 }
778 spin_unlock_bh(&hw->phy_lock);
779 }
780
781 /* blink LED's for finding board */
782 static int skge_phys_id(struct net_device *dev, u32 data)
783 {
784 struct skge_port *skge = netdev_priv(dev);
785 unsigned long ms;
786 enum led_mode mode = LED_MODE_TST;
787
788 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
789 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
790 else
791 ms = data * 1000;
792
793 while (ms > 0) {
794 skge_led(skge, mode);
795 mode ^= LED_MODE_TST;
796
797 if (msleep_interruptible(BLINK_MS))
798 break;
799 ms -= BLINK_MS;
800 }
801
802 /* back to regular LED state */
803 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
804
805 return 0;
806 }
807
808 static int skge_get_eeprom_len(struct net_device *dev)
809 {
810 struct skge_port *skge = netdev_priv(dev);
811 u32 reg2;
812
813 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
814 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
815 }
816
817 static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
818 {
819 u32 val;
820
821 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
822
823 do {
824 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
825 } while (!(offset & PCI_VPD_ADDR_F));
826
827 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
828 return val;
829 }
830
831 static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
832 {
833 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
834 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
835 offset | PCI_VPD_ADDR_F);
836
837 do {
838 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
839 } while (offset & PCI_VPD_ADDR_F);
840 }
841
842 static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
843 u8 *data)
844 {
845 struct skge_port *skge = netdev_priv(dev);
846 struct pci_dev *pdev = skge->hw->pdev;
847 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
848 int length = eeprom->len;
849 u16 offset = eeprom->offset;
850
851 if (!cap)
852 return -EINVAL;
853
854 eeprom->magic = SKGE_EEPROM_MAGIC;
855
856 while (length > 0) {
857 u32 val = skge_vpd_read(pdev, cap, offset);
858 int n = min_t(int, length, sizeof(val));
859
860 memcpy(data, &val, n);
861 length -= n;
862 data += n;
863 offset += n;
864 }
865 return 0;
866 }
867
868 static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
869 u8 *data)
870 {
871 struct skge_port *skge = netdev_priv(dev);
872 struct pci_dev *pdev = skge->hw->pdev;
873 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
874 int length = eeprom->len;
875 u16 offset = eeprom->offset;
876
877 if (!cap)
878 return -EINVAL;
879
880 if (eeprom->magic != SKGE_EEPROM_MAGIC)
881 return -EINVAL;
882
883 while (length > 0) {
884 u32 val;
885 int n = min_t(int, length, sizeof(val));
886
887 if (n < sizeof(val))
888 val = skge_vpd_read(pdev, cap, offset);
889 memcpy(&val, data, n);
890
891 skge_vpd_write(pdev, cap, offset, val);
892
893 length -= n;
894 data += n;
895 offset += n;
896 }
897 return 0;
898 }
899
900 static const struct ethtool_ops skge_ethtool_ops = {
901 .get_settings = skge_get_settings,
902 .set_settings = skge_set_settings,
903 .get_drvinfo = skge_get_drvinfo,
904 .get_regs_len = skge_get_regs_len,
905 .get_regs = skge_get_regs,
906 .get_wol = skge_get_wol,
907 .set_wol = skge_set_wol,
908 .get_msglevel = skge_get_msglevel,
909 .set_msglevel = skge_set_msglevel,
910 .nway_reset = skge_nway_reset,
911 .get_link = ethtool_op_get_link,
912 .get_eeprom_len = skge_get_eeprom_len,
913 .get_eeprom = skge_get_eeprom,
914 .set_eeprom = skge_set_eeprom,
915 .get_ringparam = skge_get_ring_param,
916 .set_ringparam = skge_set_ring_param,
917 .get_pauseparam = skge_get_pauseparam,
918 .set_pauseparam = skge_set_pauseparam,
919 .get_coalesce = skge_get_coalesce,
920 .set_coalesce = skge_set_coalesce,
921 .set_sg = skge_set_sg,
922 .set_tx_csum = skge_set_tx_csum,
923 .get_rx_csum = skge_get_rx_csum,
924 .set_rx_csum = skge_set_rx_csum,
925 .get_strings = skge_get_strings,
926 .phys_id = skge_phys_id,
927 .get_sset_count = skge_get_sset_count,
928 .get_ethtool_stats = skge_get_ethtool_stats,
929 };
930
931 /*
932 * Allocate ring elements and chain them together
933 * One-to-one association of board descriptors with ring elements
934 */
935 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
936 {
937 struct skge_tx_desc *d;
938 struct skge_element *e;
939 int i;
940
941 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
942 if (!ring->start)
943 return -ENOMEM;
944
945 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
946 e->desc = d;
947 if (i == ring->count - 1) {
948 e->next = ring->start;
949 d->next_offset = base;
950 } else {
951 e->next = e + 1;
952 d->next_offset = base + (i+1) * sizeof(*d);
953 }
954 }
955 ring->to_use = ring->to_clean = ring->start;
956
957 return 0;
958 }
959
960 /* Allocate and setup a new buffer for receiving */
961 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
962 struct sk_buff *skb, unsigned int bufsize)
963 {
964 struct skge_rx_desc *rd = e->desc;
965 u64 map;
966
967 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
968 PCI_DMA_FROMDEVICE);
969
970 rd->dma_lo = map;
971 rd->dma_hi = map >> 32;
972 e->skb = skb;
973 rd->csum1_start = ETH_HLEN;
974 rd->csum2_start = ETH_HLEN;
975 rd->csum1 = 0;
976 rd->csum2 = 0;
977
978 wmb();
979
980 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
981 pci_unmap_addr_set(e, mapaddr, map);
982 pci_unmap_len_set(e, maplen, bufsize);
983 }
984
985 /* Resume receiving using existing skb,
986 * Note: DMA address is not changed by chip.
987 * MTU not changed while receiver active.
988 */
989 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
990 {
991 struct skge_rx_desc *rd = e->desc;
992
993 rd->csum2 = 0;
994 rd->csum2_start = ETH_HLEN;
995
996 wmb();
997
998 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
999 }
1000
1001
1002 /* Free all buffers in receive ring, assumes receiver stopped */
1003 static void skge_rx_clean(struct skge_port *skge)
1004 {
1005 struct skge_hw *hw = skge->hw;
1006 struct skge_ring *ring = &skge->rx_ring;
1007 struct skge_element *e;
1008
1009 e = ring->start;
1010 do {
1011 struct skge_rx_desc *rd = e->desc;
1012 rd->control = 0;
1013 if (e->skb) {
1014 pci_unmap_single(hw->pdev,
1015 pci_unmap_addr(e, mapaddr),
1016 pci_unmap_len(e, maplen),
1017 PCI_DMA_FROMDEVICE);
1018 dev_kfree_skb(e->skb);
1019 e->skb = NULL;
1020 }
1021 } while ((e = e->next) != ring->start);
1022 }
1023
1024
1025 /* Allocate buffers for receive ring
1026 * For receive: to_clean is next received frame.
1027 */
1028 static int skge_rx_fill(struct net_device *dev)
1029 {
1030 struct skge_port *skge = netdev_priv(dev);
1031 struct skge_ring *ring = &skge->rx_ring;
1032 struct skge_element *e;
1033
1034 e = ring->start;
1035 do {
1036 struct sk_buff *skb;
1037
1038 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1039 GFP_KERNEL);
1040 if (!skb)
1041 return -ENOMEM;
1042
1043 skb_reserve(skb, NET_IP_ALIGN);
1044 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
1045 } while ( (e = e->next) != ring->start);
1046
1047 ring->to_clean = ring->start;
1048 return 0;
1049 }
1050
1051 static const char *skge_pause(enum pause_status status)
1052 {
1053 switch(status) {
1054 case FLOW_STAT_NONE:
1055 return "none";
1056 case FLOW_STAT_REM_SEND:
1057 return "rx only";
1058 case FLOW_STAT_LOC_SEND:
1059 return "tx_only";
1060 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1061 return "both";
1062 default:
1063 return "indeterminated";
1064 }
1065 }
1066
1067
1068 static void skge_link_up(struct skge_port *skge)
1069 {
1070 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1071 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1072
1073 netif_carrier_on(skge->netdev);
1074 netif_wake_queue(skge->netdev);
1075
1076 if (netif_msg_link(skge)) {
1077 printk(KERN_INFO PFX
1078 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1079 skge->netdev->name, skge->speed,
1080 skge->duplex == DUPLEX_FULL ? "full" : "half",
1081 skge_pause(skge->flow_status));
1082 }
1083 }
1084
1085 static void skge_link_down(struct skge_port *skge)
1086 {
1087 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
1088 netif_carrier_off(skge->netdev);
1089 netif_stop_queue(skge->netdev);
1090
1091 if (netif_msg_link(skge))
1092 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
1093 }
1094
1095
1096 static void xm_link_down(struct skge_hw *hw, int port)
1097 {
1098 struct net_device *dev = hw->dev[port];
1099 struct skge_port *skge = netdev_priv(dev);
1100
1101 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1102
1103 if (netif_carrier_ok(dev))
1104 skge_link_down(skge);
1105 }
1106
1107 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1108 {
1109 int i;
1110
1111 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1112 *val = xm_read16(hw, port, XM_PHY_DATA);
1113
1114 if (hw->phy_type == SK_PHY_XMAC)
1115 goto ready;
1116
1117 for (i = 0; i < PHY_RETRIES; i++) {
1118 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1119 goto ready;
1120 udelay(1);
1121 }
1122
1123 return -ETIMEDOUT;
1124 ready:
1125 *val = xm_read16(hw, port, XM_PHY_DATA);
1126
1127 return 0;
1128 }
1129
1130 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1131 {
1132 u16 v = 0;
1133 if (__xm_phy_read(hw, port, reg, &v))
1134 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1135 hw->dev[port]->name);
1136 return v;
1137 }
1138
1139 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1140 {
1141 int i;
1142
1143 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1144 for (i = 0; i < PHY_RETRIES; i++) {
1145 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1146 goto ready;
1147 udelay(1);
1148 }
1149 return -EIO;
1150
1151 ready:
1152 xm_write16(hw, port, XM_PHY_DATA, val);
1153 for (i = 0; i < PHY_RETRIES; i++) {
1154 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1155 return 0;
1156 udelay(1);
1157 }
1158 return -ETIMEDOUT;
1159 }
1160
1161 static void genesis_init(struct skge_hw *hw)
1162 {
1163 /* set blink source counter */
1164 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1165 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1166
1167 /* configure mac arbiter */
1168 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1169
1170 /* configure mac arbiter timeout values */
1171 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1172 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1173 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1174 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1175
1176 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1177 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1178 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1179 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1180
1181 /* configure packet arbiter timeout */
1182 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1183 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1184 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1185 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1186 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1187 }
1188
1189 static void genesis_reset(struct skge_hw *hw, int port)
1190 {
1191 const u8 zero[8] = { 0 };
1192 u32 reg;
1193
1194 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1195
1196 /* reset the statistics module */
1197 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1198 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1199 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1200 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1201 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1202
1203 /* disable Broadcom PHY IRQ */
1204 if (hw->phy_type == SK_PHY_BCOM)
1205 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1206
1207 xm_outhash(hw, port, XM_HSM, zero);
1208
1209 /* Flush TX and RX fifo */
1210 reg = xm_read32(hw, port, XM_MODE);
1211 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1212 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1213 }
1214
1215
1216 /* Convert mode to MII values */
1217 static const u16 phy_pause_map[] = {
1218 [FLOW_MODE_NONE] = 0,
1219 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1220 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1221 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1222 };
1223
1224 /* special defines for FIBER (88E1011S only) */
1225 static const u16 fiber_pause_map[] = {
1226 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1227 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1228 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1229 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1230 };
1231
1232
1233 /* Check status of Broadcom phy link */
1234 static void bcom_check_link(struct skge_hw *hw, int port)
1235 {
1236 struct net_device *dev = hw->dev[port];
1237 struct skge_port *skge = netdev_priv(dev);
1238 u16 status;
1239
1240 /* read twice because of latch */
1241 xm_phy_read(hw, port, PHY_BCOM_STAT);
1242 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1243
1244 if ((status & PHY_ST_LSYNC) == 0) {
1245 xm_link_down(hw, port);
1246 return;
1247 }
1248
1249 if (skge->autoneg == AUTONEG_ENABLE) {
1250 u16 lpa, aux;
1251
1252 if (!(status & PHY_ST_AN_OVER))
1253 return;
1254
1255 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1256 if (lpa & PHY_B_AN_RF) {
1257 printk(KERN_NOTICE PFX "%s: remote fault\n",
1258 dev->name);
1259 return;
1260 }
1261
1262 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1263
1264 /* Check Duplex mismatch */
1265 switch (aux & PHY_B_AS_AN_RES_MSK) {
1266 case PHY_B_RES_1000FD:
1267 skge->duplex = DUPLEX_FULL;
1268 break;
1269 case PHY_B_RES_1000HD:
1270 skge->duplex = DUPLEX_HALF;
1271 break;
1272 default:
1273 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1274 dev->name);
1275 return;
1276 }
1277
1278 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1279 switch (aux & PHY_B_AS_PAUSE_MSK) {
1280 case PHY_B_AS_PAUSE_MSK:
1281 skge->flow_status = FLOW_STAT_SYMMETRIC;
1282 break;
1283 case PHY_B_AS_PRR:
1284 skge->flow_status = FLOW_STAT_REM_SEND;
1285 break;
1286 case PHY_B_AS_PRT:
1287 skge->flow_status = FLOW_STAT_LOC_SEND;
1288 break;
1289 default:
1290 skge->flow_status = FLOW_STAT_NONE;
1291 }
1292 skge->speed = SPEED_1000;
1293 }
1294
1295 if (!netif_carrier_ok(dev))
1296 genesis_link_up(skge);
1297 }
1298
1299 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1300 * Phy on for 100 or 10Mbit operation
1301 */
1302 static void bcom_phy_init(struct skge_port *skge)
1303 {
1304 struct skge_hw *hw = skge->hw;
1305 int port = skge->port;
1306 int i;
1307 u16 id1, r, ext, ctl;
1308
1309 /* magic workaround patterns for Broadcom */
1310 static const struct {
1311 u16 reg;
1312 u16 val;
1313 } A1hack[] = {
1314 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1315 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1316 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1317 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1318 }, C0hack[] = {
1319 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1320 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1321 };
1322
1323 /* read Id from external PHY (all have the same address) */
1324 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1325
1326 /* Optimize MDIO transfer by suppressing preamble. */
1327 r = xm_read16(hw, port, XM_MMU_CMD);
1328 r |= XM_MMU_NO_PRE;
1329 xm_write16(hw, port, XM_MMU_CMD,r);
1330
1331 switch (id1) {
1332 case PHY_BCOM_ID1_C0:
1333 /*
1334 * Workaround BCOM Errata for the C0 type.
1335 * Write magic patterns to reserved registers.
1336 */
1337 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1338 xm_phy_write(hw, port,
1339 C0hack[i].reg, C0hack[i].val);
1340
1341 break;
1342 case PHY_BCOM_ID1_A1:
1343 /*
1344 * Workaround BCOM Errata for the A1 type.
1345 * Write magic patterns to reserved registers.
1346 */
1347 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1348 xm_phy_write(hw, port,
1349 A1hack[i].reg, A1hack[i].val);
1350 break;
1351 }
1352
1353 /*
1354 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1355 * Disable Power Management after reset.
1356 */
1357 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1358 r |= PHY_B_AC_DIS_PM;
1359 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1360
1361 /* Dummy read */
1362 xm_read16(hw, port, XM_ISRC);
1363
1364 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1365 ctl = PHY_CT_SP1000; /* always 1000mbit */
1366
1367 if (skge->autoneg == AUTONEG_ENABLE) {
1368 /*
1369 * Workaround BCOM Errata #1 for the C5 type.
1370 * 1000Base-T Link Acquisition Failure in Slave Mode
1371 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1372 */
1373 u16 adv = PHY_B_1000C_RD;
1374 if (skge->advertising & ADVERTISED_1000baseT_Half)
1375 adv |= PHY_B_1000C_AHD;
1376 if (skge->advertising & ADVERTISED_1000baseT_Full)
1377 adv |= PHY_B_1000C_AFD;
1378 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1379
1380 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1381 } else {
1382 if (skge->duplex == DUPLEX_FULL)
1383 ctl |= PHY_CT_DUP_MD;
1384 /* Force to slave */
1385 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1386 }
1387
1388 /* Set autonegotiation pause parameters */
1389 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1390 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1391
1392 /* Handle Jumbo frames */
1393 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1394 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1395 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1396
1397 ext |= PHY_B_PEC_HIGH_LA;
1398
1399 }
1400
1401 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1402 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1403
1404 /* Use link status change interrupt */
1405 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1406 }
1407
1408 static void xm_phy_init(struct skge_port *skge)
1409 {
1410 struct skge_hw *hw = skge->hw;
1411 int port = skge->port;
1412 u16 ctrl = 0;
1413
1414 if (skge->autoneg == AUTONEG_ENABLE) {
1415 if (skge->advertising & ADVERTISED_1000baseT_Half)
1416 ctrl |= PHY_X_AN_HD;
1417 if (skge->advertising & ADVERTISED_1000baseT_Full)
1418 ctrl |= PHY_X_AN_FD;
1419
1420 ctrl |= fiber_pause_map[skge->flow_control];
1421
1422 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1423
1424 /* Restart Auto-negotiation */
1425 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1426 } else {
1427 /* Set DuplexMode in Config register */
1428 if (skge->duplex == DUPLEX_FULL)
1429 ctrl |= PHY_CT_DUP_MD;
1430 /*
1431 * Do NOT enable Auto-negotiation here. This would hold
1432 * the link down because no IDLEs are transmitted
1433 */
1434 }
1435
1436 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1437
1438 /* Poll PHY for status changes */
1439 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1440 }
1441
1442 static int xm_check_link(struct net_device *dev)
1443 {
1444 struct skge_port *skge = netdev_priv(dev);
1445 struct skge_hw *hw = skge->hw;
1446 int port = skge->port;
1447 u16 status;
1448
1449 /* read twice because of latch */
1450 xm_phy_read(hw, port, PHY_XMAC_STAT);
1451 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1452
1453 if ((status & PHY_ST_LSYNC) == 0) {
1454 xm_link_down(hw, port);
1455 return 0;
1456 }
1457
1458 if (skge->autoneg == AUTONEG_ENABLE) {
1459 u16 lpa, res;
1460
1461 if (!(status & PHY_ST_AN_OVER))
1462 return 0;
1463
1464 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1465 if (lpa & PHY_B_AN_RF) {
1466 printk(KERN_NOTICE PFX "%s: remote fault\n",
1467 dev->name);
1468 return 0;
1469 }
1470
1471 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1472
1473 /* Check Duplex mismatch */
1474 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1475 case PHY_X_RS_FD:
1476 skge->duplex = DUPLEX_FULL;
1477 break;
1478 case PHY_X_RS_HD:
1479 skge->duplex = DUPLEX_HALF;
1480 break;
1481 default:
1482 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1483 dev->name);
1484 return 0;
1485 }
1486
1487 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1488 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1489 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1490 (lpa & PHY_X_P_SYM_MD))
1491 skge->flow_status = FLOW_STAT_SYMMETRIC;
1492 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1493 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1494 /* Enable PAUSE receive, disable PAUSE transmit */
1495 skge->flow_status = FLOW_STAT_REM_SEND;
1496 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1497 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1498 /* Disable PAUSE receive, enable PAUSE transmit */
1499 skge->flow_status = FLOW_STAT_LOC_SEND;
1500 else
1501 skge->flow_status = FLOW_STAT_NONE;
1502
1503 skge->speed = SPEED_1000;
1504 }
1505
1506 if (!netif_carrier_ok(dev))
1507 genesis_link_up(skge);
1508 return 1;
1509 }
1510
1511 /* Poll to check for link coming up.
1512 *
1513 * Since internal PHY is wired to a level triggered pin, can't
1514 * get an interrupt when carrier is detected, need to poll for
1515 * link coming up.
1516 */
1517 static void xm_link_timer(unsigned long arg)
1518 {
1519 struct skge_port *skge = (struct skge_port *) arg;
1520 struct net_device *dev = skge->netdev;
1521 struct skge_hw *hw = skge->hw;
1522 int port = skge->port;
1523 int i;
1524 unsigned long flags;
1525
1526 if (!netif_running(dev))
1527 return;
1528
1529 spin_lock_irqsave(&hw->phy_lock, flags);
1530
1531 /*
1532 * Verify that the link by checking GPIO register three times.
1533 * This pin has the signal from the link_sync pin connected to it.
1534 */
1535 for (i = 0; i < 3; i++) {
1536 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1537 goto link_down;
1538 }
1539
1540 /* Re-enable interrupt to detect link down */
1541 if (xm_check_link(dev)) {
1542 u16 msk = xm_read16(hw, port, XM_IMSK);
1543 msk &= ~XM_IS_INP_ASS;
1544 xm_write16(hw, port, XM_IMSK, msk);
1545 xm_read16(hw, port, XM_ISRC);
1546 } else {
1547 link_down:
1548 mod_timer(&skge->link_timer,
1549 round_jiffies(jiffies + LINK_HZ));
1550 }
1551 spin_unlock_irqrestore(&hw->phy_lock, flags);
1552 }
1553
1554 static void genesis_mac_init(struct skge_hw *hw, int port)
1555 {
1556 struct net_device *dev = hw->dev[port];
1557 struct skge_port *skge = netdev_priv(dev);
1558 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1559 int i;
1560 u32 r;
1561 const u8 zero[6] = { 0 };
1562
1563 for (i = 0; i < 10; i++) {
1564 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1565 MFF_SET_MAC_RST);
1566 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1567 goto reset_ok;
1568 udelay(1);
1569 }
1570
1571 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1572
1573 reset_ok:
1574 /* Unreset the XMAC. */
1575 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1576
1577 /*
1578 * Perform additional initialization for external PHYs,
1579 * namely for the 1000baseTX cards that use the XMAC's
1580 * GMII mode.
1581 */
1582 if (hw->phy_type != SK_PHY_XMAC) {
1583 /* Take external Phy out of reset */
1584 r = skge_read32(hw, B2_GP_IO);
1585 if (port == 0)
1586 r |= GP_DIR_0|GP_IO_0;
1587 else
1588 r |= GP_DIR_2|GP_IO_2;
1589
1590 skge_write32(hw, B2_GP_IO, r);
1591
1592 /* Enable GMII interface */
1593 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1594 }
1595
1596
1597 switch(hw->phy_type) {
1598 case SK_PHY_XMAC:
1599 xm_phy_init(skge);
1600 break;
1601 case SK_PHY_BCOM:
1602 bcom_phy_init(skge);
1603 bcom_check_link(hw, port);
1604 }
1605
1606 /* Set Station Address */
1607 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1608
1609 /* We don't use match addresses so clear */
1610 for (i = 1; i < 16; i++)
1611 xm_outaddr(hw, port, XM_EXM(i), zero);
1612
1613 /* Clear MIB counters */
1614 xm_write16(hw, port, XM_STAT_CMD,
1615 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1616 /* Clear two times according to Errata #3 */
1617 xm_write16(hw, port, XM_STAT_CMD,
1618 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1619
1620 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1621 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1622
1623 /* We don't need the FCS appended to the packet. */
1624 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1625 if (jumbo)
1626 r |= XM_RX_BIG_PK_OK;
1627
1628 if (skge->duplex == DUPLEX_HALF) {
1629 /*
1630 * If in manual half duplex mode the other side might be in
1631 * full duplex mode, so ignore if a carrier extension is not seen
1632 * on frames received
1633 */
1634 r |= XM_RX_DIS_CEXT;
1635 }
1636 xm_write16(hw, port, XM_RX_CMD, r);
1637
1638 /* We want short frames padded to 60 bytes. */
1639 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1640
1641 /* Increase threshold for jumbo frames on dual port */
1642 if (hw->ports > 1 && jumbo)
1643 xm_write16(hw, port, XM_TX_THR, 1020);
1644 else
1645 xm_write16(hw, port, XM_TX_THR, 512);
1646
1647 /*
1648 * Enable the reception of all error frames. This is is
1649 * a necessary evil due to the design of the XMAC. The
1650 * XMAC's receive FIFO is only 8K in size, however jumbo
1651 * frames can be up to 9000 bytes in length. When bad
1652 * frame filtering is enabled, the XMAC's RX FIFO operates
1653 * in 'store and forward' mode. For this to work, the
1654 * entire frame has to fit into the FIFO, but that means
1655 * that jumbo frames larger than 8192 bytes will be
1656 * truncated. Disabling all bad frame filtering causes
1657 * the RX FIFO to operate in streaming mode, in which
1658 * case the XMAC will start transferring frames out of the
1659 * RX FIFO as soon as the FIFO threshold is reached.
1660 */
1661 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1662
1663
1664 /*
1665 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1666 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1667 * and 'Octets Rx OK Hi Cnt Ov'.
1668 */
1669 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1670
1671 /*
1672 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1673 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1674 * and 'Octets Tx OK Hi Cnt Ov'.
1675 */
1676 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1677
1678 /* Configure MAC arbiter */
1679 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1680
1681 /* configure timeout values */
1682 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1683 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1684 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1685 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1686
1687 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1688 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1689 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1690 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1691
1692 /* Configure Rx MAC FIFO */
1693 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1694 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1695 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1696
1697 /* Configure Tx MAC FIFO */
1698 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1699 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1700 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1701
1702 if (jumbo) {
1703 /* Enable frame flushing if jumbo frames used */
1704 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1705 } else {
1706 /* enable timeout timers if normal frames */
1707 skge_write16(hw, B3_PA_CTRL,
1708 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1709 }
1710 }
1711
1712 static void genesis_stop(struct skge_port *skge)
1713 {
1714 struct skge_hw *hw = skge->hw;
1715 int port = skge->port;
1716 unsigned retries = 1000;
1717 u16 cmd;
1718
1719 /* Disable Tx and Rx */
1720 cmd = xm_read16(hw, port, XM_MMU_CMD);
1721 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1722 xm_write16(hw, port, XM_MMU_CMD, cmd);
1723
1724 genesis_reset(hw, port);
1725
1726 /* Clear Tx packet arbiter timeout IRQ */
1727 skge_write16(hw, B3_PA_CTRL,
1728 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1729
1730 /* Reset the MAC */
1731 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1732 do {
1733 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1734 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1735 break;
1736 } while (--retries > 0);
1737
1738 /* For external PHYs there must be special handling */
1739 if (hw->phy_type != SK_PHY_XMAC) {
1740 u32 reg = skge_read32(hw, B2_GP_IO);
1741 if (port == 0) {
1742 reg |= GP_DIR_0;
1743 reg &= ~GP_IO_0;
1744 } else {
1745 reg |= GP_DIR_2;
1746 reg &= ~GP_IO_2;
1747 }
1748 skge_write32(hw, B2_GP_IO, reg);
1749 skge_read32(hw, B2_GP_IO);
1750 }
1751
1752 xm_write16(hw, port, XM_MMU_CMD,
1753 xm_read16(hw, port, XM_MMU_CMD)
1754 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1755
1756 xm_read16(hw, port, XM_MMU_CMD);
1757 }
1758
1759
1760 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1761 {
1762 struct skge_hw *hw = skge->hw;
1763 int port = skge->port;
1764 int i;
1765 unsigned long timeout = jiffies + HZ;
1766
1767 xm_write16(hw, port,
1768 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1769
1770 /* wait for update to complete */
1771 while (xm_read16(hw, port, XM_STAT_CMD)
1772 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1773 if (time_after(jiffies, timeout))
1774 break;
1775 udelay(10);
1776 }
1777
1778 /* special case for 64 bit octet counter */
1779 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1780 | xm_read32(hw, port, XM_TXO_OK_LO);
1781 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1782 | xm_read32(hw, port, XM_RXO_OK_LO);
1783
1784 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1785 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1786 }
1787
1788 static void genesis_mac_intr(struct skge_hw *hw, int port)
1789 {
1790 struct net_device *dev = hw->dev[port];
1791 struct skge_port *skge = netdev_priv(dev);
1792 u16 status = xm_read16(hw, port, XM_ISRC);
1793
1794 if (netif_msg_intr(skge))
1795 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1796 dev->name, status);
1797
1798 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1799 xm_link_down(hw, port);
1800 mod_timer(&skge->link_timer, jiffies + 1);
1801 }
1802
1803 if (status & XM_IS_TXF_UR) {
1804 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1805 ++dev->stats.tx_fifo_errors;
1806 }
1807 }
1808
1809 static void genesis_link_up(struct skge_port *skge)
1810 {
1811 struct skge_hw *hw = skge->hw;
1812 int port = skge->port;
1813 u16 cmd, msk;
1814 u32 mode;
1815
1816 cmd = xm_read16(hw, port, XM_MMU_CMD);
1817
1818 /*
1819 * enabling pause frame reception is required for 1000BT
1820 * because the XMAC is not reset if the link is going down
1821 */
1822 if (skge->flow_status == FLOW_STAT_NONE ||
1823 skge->flow_status == FLOW_STAT_LOC_SEND)
1824 /* Disable Pause Frame Reception */
1825 cmd |= XM_MMU_IGN_PF;
1826 else
1827 /* Enable Pause Frame Reception */
1828 cmd &= ~XM_MMU_IGN_PF;
1829
1830 xm_write16(hw, port, XM_MMU_CMD, cmd);
1831
1832 mode = xm_read32(hw, port, XM_MODE);
1833 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1834 skge->flow_status == FLOW_STAT_LOC_SEND) {
1835 /*
1836 * Configure Pause Frame Generation
1837 * Use internal and external Pause Frame Generation.
1838 * Sending pause frames is edge triggered.
1839 * Send a Pause frame with the maximum pause time if
1840 * internal oder external FIFO full condition occurs.
1841 * Send a zero pause time frame to re-start transmission.
1842 */
1843 /* XM_PAUSE_DA = '010000C28001' (default) */
1844 /* XM_MAC_PTIME = 0xffff (maximum) */
1845 /* remember this value is defined in big endian (!) */
1846 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1847
1848 mode |= XM_PAUSE_MODE;
1849 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1850 } else {
1851 /*
1852 * disable pause frame generation is required for 1000BT
1853 * because the XMAC is not reset if the link is going down
1854 */
1855 /* Disable Pause Mode in Mode Register */
1856 mode &= ~XM_PAUSE_MODE;
1857
1858 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1859 }
1860
1861 xm_write32(hw, port, XM_MODE, mode);
1862
1863 /* Turn on detection of Tx underrun */
1864 msk = xm_read16(hw, port, XM_IMSK);
1865 msk &= ~XM_IS_TXF_UR;
1866 xm_write16(hw, port, XM_IMSK, msk);
1867
1868 xm_read16(hw, port, XM_ISRC);
1869
1870 /* get MMU Command Reg. */
1871 cmd = xm_read16(hw, port, XM_MMU_CMD);
1872 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1873 cmd |= XM_MMU_GMII_FD;
1874
1875 /*
1876 * Workaround BCOM Errata (#10523) for all BCom Phys
1877 * Enable Power Management after link up
1878 */
1879 if (hw->phy_type == SK_PHY_BCOM) {
1880 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1881 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1882 & ~PHY_B_AC_DIS_PM);
1883 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1884 }
1885
1886 /* enable Rx/Tx */
1887 xm_write16(hw, port, XM_MMU_CMD,
1888 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1889 skge_link_up(skge);
1890 }
1891
1892
1893 static inline void bcom_phy_intr(struct skge_port *skge)
1894 {
1895 struct skge_hw *hw = skge->hw;
1896 int port = skge->port;
1897 u16 isrc;
1898
1899 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1900 if (netif_msg_intr(skge))
1901 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1902 skge->netdev->name, isrc);
1903
1904 if (isrc & PHY_B_IS_PSE)
1905 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1906 hw->dev[port]->name);
1907
1908 /* Workaround BCom Errata:
1909 * enable and disable loopback mode if "NO HCD" occurs.
1910 */
1911 if (isrc & PHY_B_IS_NO_HDCL) {
1912 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1913 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1914 ctrl | PHY_CT_LOOP);
1915 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1916 ctrl & ~PHY_CT_LOOP);
1917 }
1918
1919 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1920 bcom_check_link(hw, port);
1921
1922 }
1923
1924 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1925 {
1926 int i;
1927
1928 gma_write16(hw, port, GM_SMI_DATA, val);
1929 gma_write16(hw, port, GM_SMI_CTRL,
1930 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1931 for (i = 0; i < PHY_RETRIES; i++) {
1932 udelay(1);
1933
1934 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1935 return 0;
1936 }
1937
1938 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1939 hw->dev[port]->name);
1940 return -EIO;
1941 }
1942
1943 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1944 {
1945 int i;
1946
1947 gma_write16(hw, port, GM_SMI_CTRL,
1948 GM_SMI_CT_PHY_AD(hw->phy_addr)
1949 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1950
1951 for (i = 0; i < PHY_RETRIES; i++) {
1952 udelay(1);
1953 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1954 goto ready;
1955 }
1956
1957 return -ETIMEDOUT;
1958 ready:
1959 *val = gma_read16(hw, port, GM_SMI_DATA);
1960 return 0;
1961 }
1962
1963 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1964 {
1965 u16 v = 0;
1966 if (__gm_phy_read(hw, port, reg, &v))
1967 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1968 hw->dev[port]->name);
1969 return v;
1970 }
1971
1972 /* Marvell Phy Initialization */
1973 static void yukon_init(struct skge_hw *hw, int port)
1974 {
1975 struct skge_port *skge = netdev_priv(hw->dev[port]);
1976 u16 ctrl, ct1000, adv;
1977
1978 if (skge->autoneg == AUTONEG_ENABLE) {
1979 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1980
1981 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1982 PHY_M_EC_MAC_S_MSK);
1983 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1984
1985 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1986
1987 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1988 }
1989
1990 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1991 if (skge->autoneg == AUTONEG_DISABLE)
1992 ctrl &= ~PHY_CT_ANE;
1993
1994 ctrl |= PHY_CT_RESET;
1995 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1996
1997 ctrl = 0;
1998 ct1000 = 0;
1999 adv = PHY_AN_CSMA;
2000
2001 if (skge->autoneg == AUTONEG_ENABLE) {
2002 if (hw->copper) {
2003 if (skge->advertising & ADVERTISED_1000baseT_Full)
2004 ct1000 |= PHY_M_1000C_AFD;
2005 if (skge->advertising & ADVERTISED_1000baseT_Half)
2006 ct1000 |= PHY_M_1000C_AHD;
2007 if (skge->advertising & ADVERTISED_100baseT_Full)
2008 adv |= PHY_M_AN_100_FD;
2009 if (skge->advertising & ADVERTISED_100baseT_Half)
2010 adv |= PHY_M_AN_100_HD;
2011 if (skge->advertising & ADVERTISED_10baseT_Full)
2012 adv |= PHY_M_AN_10_FD;
2013 if (skge->advertising & ADVERTISED_10baseT_Half)
2014 adv |= PHY_M_AN_10_HD;
2015
2016 /* Set Flow-control capabilities */
2017 adv |= phy_pause_map[skge->flow_control];
2018 } else {
2019 if (skge->advertising & ADVERTISED_1000baseT_Full)
2020 adv |= PHY_M_AN_1000X_AFD;
2021 if (skge->advertising & ADVERTISED_1000baseT_Half)
2022 adv |= PHY_M_AN_1000X_AHD;
2023
2024 adv |= fiber_pause_map[skge->flow_control];
2025 }
2026
2027 /* Restart Auto-negotiation */
2028 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2029 } else {
2030 /* forced speed/duplex settings */
2031 ct1000 = PHY_M_1000C_MSE;
2032
2033 if (skge->duplex == DUPLEX_FULL)
2034 ctrl |= PHY_CT_DUP_MD;
2035
2036 switch (skge->speed) {
2037 case SPEED_1000:
2038 ctrl |= PHY_CT_SP1000;
2039 break;
2040 case SPEED_100:
2041 ctrl |= PHY_CT_SP100;
2042 break;
2043 }
2044
2045 ctrl |= PHY_CT_RESET;
2046 }
2047
2048 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2049
2050 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2051 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2052
2053 /* Enable phy interrupt on autonegotiation complete (or link up) */
2054 if (skge->autoneg == AUTONEG_ENABLE)
2055 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2056 else
2057 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2058 }
2059
2060 static void yukon_reset(struct skge_hw *hw, int port)
2061 {
2062 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2063 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2064 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2065 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2066 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2067
2068 gma_write16(hw, port, GM_RX_CTRL,
2069 gma_read16(hw, port, GM_RX_CTRL)
2070 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2071 }
2072
2073 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2074 static int is_yukon_lite_a0(struct skge_hw *hw)
2075 {
2076 u32 reg;
2077 int ret;
2078
2079 if (hw->chip_id != CHIP_ID_YUKON)
2080 return 0;
2081
2082 reg = skge_read32(hw, B2_FAR);
2083 skge_write8(hw, B2_FAR + 3, 0xff);
2084 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2085 skge_write32(hw, B2_FAR, reg);
2086 return ret;
2087 }
2088
2089 static void yukon_mac_init(struct skge_hw *hw, int port)
2090 {
2091 struct skge_port *skge = netdev_priv(hw->dev[port]);
2092 int i;
2093 u32 reg;
2094 const u8 *addr = hw->dev[port]->dev_addr;
2095
2096 /* WA code for COMA mode -- set PHY reset */
2097 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2098 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2099 reg = skge_read32(hw, B2_GP_IO);
2100 reg |= GP_DIR_9 | GP_IO_9;
2101 skge_write32(hw, B2_GP_IO, reg);
2102 }
2103
2104 /* hard reset */
2105 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2106 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2107
2108 /* WA code for COMA mode -- clear PHY reset */
2109 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2110 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2111 reg = skge_read32(hw, B2_GP_IO);
2112 reg |= GP_DIR_9;
2113 reg &= ~GP_IO_9;
2114 skge_write32(hw, B2_GP_IO, reg);
2115 }
2116
2117 /* Set hardware config mode */
2118 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2119 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2120 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2121
2122 /* Clear GMC reset */
2123 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2124 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2125 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2126
2127 if (skge->autoneg == AUTONEG_DISABLE) {
2128 reg = GM_GPCR_AU_ALL_DIS;
2129 gma_write16(hw, port, GM_GP_CTRL,
2130 gma_read16(hw, port, GM_GP_CTRL) | reg);
2131
2132 switch (skge->speed) {
2133 case SPEED_1000:
2134 reg &= ~GM_GPCR_SPEED_100;
2135 reg |= GM_GPCR_SPEED_1000;
2136 break;
2137 case SPEED_100:
2138 reg &= ~GM_GPCR_SPEED_1000;
2139 reg |= GM_GPCR_SPEED_100;
2140 break;
2141 case SPEED_10:
2142 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2143 break;
2144 }
2145
2146 if (skge->duplex == DUPLEX_FULL)
2147 reg |= GM_GPCR_DUP_FULL;
2148 } else
2149 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2150
2151 switch (skge->flow_control) {
2152 case FLOW_MODE_NONE:
2153 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2154 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2155 break;
2156 case FLOW_MODE_LOC_SEND:
2157 /* disable Rx flow-control */
2158 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2159 break;
2160 case FLOW_MODE_SYMMETRIC:
2161 case FLOW_MODE_SYM_OR_REM:
2162 /* enable Tx & Rx flow-control */
2163 break;
2164 }
2165
2166 gma_write16(hw, port, GM_GP_CTRL, reg);
2167 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2168
2169 yukon_init(hw, port);
2170
2171 /* MIB clear */
2172 reg = gma_read16(hw, port, GM_PHY_ADDR);
2173 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2174
2175 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2176 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2177 gma_write16(hw, port, GM_PHY_ADDR, reg);
2178
2179 /* transmit control */
2180 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2181
2182 /* receive control reg: unicast + multicast + no FCS */
2183 gma_write16(hw, port, GM_RX_CTRL,
2184 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2185
2186 /* transmit flow control */
2187 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2188
2189 /* transmit parameter */
2190 gma_write16(hw, port, GM_TX_PARAM,
2191 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2192 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2193 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2194
2195 /* configure the Serial Mode Register */
2196 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2197 | GM_SMOD_VLAN_ENA
2198 | IPG_DATA_VAL(IPG_DATA_DEF);
2199
2200 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2201 reg |= GM_SMOD_JUMBO_ENA;
2202
2203 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2204
2205 /* physical address: used for pause frames */
2206 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2207 /* virtual address for data */
2208 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2209
2210 /* enable interrupt mask for counter overflows */
2211 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2212 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2213 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2214
2215 /* Initialize Mac Fifo */
2216
2217 /* Configure Rx MAC FIFO */
2218 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2219 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2220
2221 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2222 if (is_yukon_lite_a0(hw))
2223 reg &= ~GMF_RX_F_FL_ON;
2224
2225 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2226 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2227 /*
2228 * because Pause Packet Truncation in GMAC is not working
2229 * we have to increase the Flush Threshold to 64 bytes
2230 * in order to flush pause packets in Rx FIFO on Yukon-1
2231 */
2232 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2233
2234 /* Configure Tx MAC FIFO */
2235 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2236 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2237 }
2238
2239 /* Go into power down mode */
2240 static void yukon_suspend(struct skge_hw *hw, int port)
2241 {
2242 u16 ctrl;
2243
2244 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2245 ctrl |= PHY_M_PC_POL_R_DIS;
2246 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2247
2248 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2249 ctrl |= PHY_CT_RESET;
2250 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2251
2252 /* switch IEEE compatible power down mode on */
2253 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2254 ctrl |= PHY_CT_PDOWN;
2255 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2256 }
2257
2258 static void yukon_stop(struct skge_port *skge)
2259 {
2260 struct skge_hw *hw = skge->hw;
2261 int port = skge->port;
2262
2263 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2264 yukon_reset(hw, port);
2265
2266 gma_write16(hw, port, GM_GP_CTRL,
2267 gma_read16(hw, port, GM_GP_CTRL)
2268 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2269 gma_read16(hw, port, GM_GP_CTRL);
2270
2271 yukon_suspend(hw, port);
2272
2273 /* set GPHY Control reset */
2274 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2275 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2276 }
2277
2278 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2279 {
2280 struct skge_hw *hw = skge->hw;
2281 int port = skge->port;
2282 int i;
2283
2284 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2285 | gma_read32(hw, port, GM_TXO_OK_LO);
2286 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2287 | gma_read32(hw, port, GM_RXO_OK_LO);
2288
2289 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2290 data[i] = gma_read32(hw, port,
2291 skge_stats[i].gma_offset);
2292 }
2293
2294 static void yukon_mac_intr(struct skge_hw *hw, int port)
2295 {
2296 struct net_device *dev = hw->dev[port];
2297 struct skge_port *skge = netdev_priv(dev);
2298 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2299
2300 if (netif_msg_intr(skge))
2301 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2302 dev->name, status);
2303
2304 if (status & GM_IS_RX_FF_OR) {
2305 ++dev->stats.rx_fifo_errors;
2306 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2307 }
2308
2309 if (status & GM_IS_TX_FF_UR) {
2310 ++dev->stats.tx_fifo_errors;
2311 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2312 }
2313
2314 }
2315
2316 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2317 {
2318 switch (aux & PHY_M_PS_SPEED_MSK) {
2319 case PHY_M_PS_SPEED_1000:
2320 return SPEED_1000;
2321 case PHY_M_PS_SPEED_100:
2322 return SPEED_100;
2323 default:
2324 return SPEED_10;
2325 }
2326 }
2327
2328 static void yukon_link_up(struct skge_port *skge)
2329 {
2330 struct skge_hw *hw = skge->hw;
2331 int port = skge->port;
2332 u16 reg;
2333
2334 /* Enable Transmit FIFO Underrun */
2335 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2336
2337 reg = gma_read16(hw, port, GM_GP_CTRL);
2338 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2339 reg |= GM_GPCR_DUP_FULL;
2340
2341 /* enable Rx/Tx */
2342 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2343 gma_write16(hw, port, GM_GP_CTRL, reg);
2344
2345 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2346 skge_link_up(skge);
2347 }
2348
2349 static void yukon_link_down(struct skge_port *skge)
2350 {
2351 struct skge_hw *hw = skge->hw;
2352 int port = skge->port;
2353 u16 ctrl;
2354
2355 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2356 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2357 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2358
2359 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2360 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2361 ctrl |= PHY_M_AN_ASP;
2362 /* restore Asymmetric Pause bit */
2363 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2364 }
2365
2366 skge_link_down(skge);
2367
2368 yukon_init(hw, port);
2369 }
2370
2371 static void yukon_phy_intr(struct skge_port *skge)
2372 {
2373 struct skge_hw *hw = skge->hw;
2374 int port = skge->port;
2375 const char *reason = NULL;
2376 u16 istatus, phystat;
2377
2378 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2379 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2380
2381 if (netif_msg_intr(skge))
2382 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2383 skge->netdev->name, istatus, phystat);
2384
2385 if (istatus & PHY_M_IS_AN_COMPL) {
2386 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2387 & PHY_M_AN_RF) {
2388 reason = "remote fault";
2389 goto failed;
2390 }
2391
2392 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2393 reason = "master/slave fault";
2394 goto failed;
2395 }
2396
2397 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2398 reason = "speed/duplex";
2399 goto failed;
2400 }
2401
2402 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2403 ? DUPLEX_FULL : DUPLEX_HALF;
2404 skge->speed = yukon_speed(hw, phystat);
2405
2406 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2407 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2408 case PHY_M_PS_PAUSE_MSK:
2409 skge->flow_status = FLOW_STAT_SYMMETRIC;
2410 break;
2411 case PHY_M_PS_RX_P_EN:
2412 skge->flow_status = FLOW_STAT_REM_SEND;
2413 break;
2414 case PHY_M_PS_TX_P_EN:
2415 skge->flow_status = FLOW_STAT_LOC_SEND;
2416 break;
2417 default:
2418 skge->flow_status = FLOW_STAT_NONE;
2419 }
2420
2421 if (skge->flow_status == FLOW_STAT_NONE ||
2422 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2423 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2424 else
2425 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2426 yukon_link_up(skge);
2427 return;
2428 }
2429
2430 if (istatus & PHY_M_IS_LSP_CHANGE)
2431 skge->speed = yukon_speed(hw, phystat);
2432
2433 if (istatus & PHY_M_IS_DUP_CHANGE)
2434 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2435 if (istatus & PHY_M_IS_LST_CHANGE) {
2436 if (phystat & PHY_M_PS_LINK_UP)
2437 yukon_link_up(skge);
2438 else
2439 yukon_link_down(skge);
2440 }
2441 return;
2442 failed:
2443 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2444 skge->netdev->name, reason);
2445
2446 /* XXX restart autonegotiation? */
2447 }
2448
2449 static void skge_phy_reset(struct skge_port *skge)
2450 {
2451 struct skge_hw *hw = skge->hw;
2452 int port = skge->port;
2453 struct net_device *dev = hw->dev[port];
2454
2455 netif_stop_queue(skge->netdev);
2456 netif_carrier_off(skge->netdev);
2457
2458 spin_lock_bh(&hw->phy_lock);
2459 if (hw->chip_id == CHIP_ID_GENESIS) {
2460 genesis_reset(hw, port);
2461 genesis_mac_init(hw, port);
2462 } else {
2463 yukon_reset(hw, port);
2464 yukon_init(hw, port);
2465 }
2466 spin_unlock_bh(&hw->phy_lock);
2467
2468 skge_set_multicast(dev);
2469 }
2470
2471 /* Basic MII support */
2472 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2473 {
2474 struct mii_ioctl_data *data = if_mii(ifr);
2475 struct skge_port *skge = netdev_priv(dev);
2476 struct skge_hw *hw = skge->hw;
2477 int err = -EOPNOTSUPP;
2478
2479 if (!netif_running(dev))
2480 return -ENODEV; /* Phy still in reset */
2481
2482 switch(cmd) {
2483 case SIOCGMIIPHY:
2484 data->phy_id = hw->phy_addr;
2485
2486 /* fallthru */
2487 case SIOCGMIIREG: {
2488 u16 val = 0;
2489 spin_lock_bh(&hw->phy_lock);
2490 if (hw->chip_id == CHIP_ID_GENESIS)
2491 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2492 else
2493 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2494 spin_unlock_bh(&hw->phy_lock);
2495 data->val_out = val;
2496 break;
2497 }
2498
2499 case SIOCSMIIREG:
2500 spin_lock_bh(&hw->phy_lock);
2501 if (hw->chip_id == CHIP_ID_GENESIS)
2502 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2503 data->val_in);
2504 else
2505 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2506 data->val_in);
2507 spin_unlock_bh(&hw->phy_lock);
2508 break;
2509 }
2510 return err;
2511 }
2512
2513 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2514 {
2515 u32 end;
2516
2517 start /= 8;
2518 len /= 8;
2519 end = start + len - 1;
2520
2521 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2522 skge_write32(hw, RB_ADDR(q, RB_START), start);
2523 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2524 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2525 skge_write32(hw, RB_ADDR(q, RB_END), end);
2526
2527 if (q == Q_R1 || q == Q_R2) {
2528 /* Set thresholds on receive queue's */
2529 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2530 start + (2*len)/3);
2531 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2532 start + (len/3));
2533 } else {
2534 /* Enable store & forward on Tx queue's because
2535 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2536 */
2537 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2538 }
2539
2540 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2541 }
2542
2543 /* Setup Bus Memory Interface */
2544 static void skge_qset(struct skge_port *skge, u16 q,
2545 const struct skge_element *e)
2546 {
2547 struct skge_hw *hw = skge->hw;
2548 u32 watermark = 0x600;
2549 u64 base = skge->dma + (e->desc - skge->mem);
2550
2551 /* optimization to reduce window on 32bit/33mhz */
2552 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2553 watermark /= 2;
2554
2555 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2556 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2557 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2558 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2559 }
2560
2561 static int skge_up(struct net_device *dev)
2562 {
2563 struct skge_port *skge = netdev_priv(dev);
2564 struct skge_hw *hw = skge->hw;
2565 int port = skge->port;
2566 u32 chunk, ram_addr;
2567 size_t rx_size, tx_size;
2568 int err;
2569
2570 if (!is_valid_ether_addr(dev->dev_addr))
2571 return -EINVAL;
2572
2573 if (netif_msg_ifup(skge))
2574 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2575
2576 if (dev->mtu > RX_BUF_SIZE)
2577 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2578 else
2579 skge->rx_buf_size = RX_BUF_SIZE;
2580
2581
2582 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2583 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2584 skge->mem_size = tx_size + rx_size;
2585 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2586 if (!skge->mem)
2587 return -ENOMEM;
2588
2589 BUG_ON(skge->dma & 7);
2590
2591 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2592 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2593 err = -EINVAL;
2594 goto free_pci_mem;
2595 }
2596
2597 memset(skge->mem, 0, skge->mem_size);
2598
2599 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2600 if (err)
2601 goto free_pci_mem;
2602
2603 err = skge_rx_fill(dev);
2604 if (err)
2605 goto free_rx_ring;
2606
2607 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2608 skge->dma + rx_size);
2609 if (err)
2610 goto free_rx_ring;
2611
2612 /* Initialize MAC */
2613 spin_lock_bh(&hw->phy_lock);
2614 if (hw->chip_id == CHIP_ID_GENESIS)
2615 genesis_mac_init(hw, port);
2616 else
2617 yukon_mac_init(hw, port);
2618 spin_unlock_bh(&hw->phy_lock);
2619
2620 /* Configure RAMbuffers - equally between ports and tx/rx */
2621 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2622 ram_addr = hw->ram_offset + 2 * chunk * port;
2623
2624 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2625 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2626
2627 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2628 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2629 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2630
2631 /* Start receiver BMU */
2632 wmb();
2633 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2634 skge_led(skge, LED_MODE_ON);
2635
2636 spin_lock_irq(&hw->hw_lock);
2637 hw->intr_mask |= portmask[port];
2638 skge_write32(hw, B0_IMSK, hw->intr_mask);
2639 spin_unlock_irq(&hw->hw_lock);
2640
2641 napi_enable(&skge->napi);
2642 return 0;
2643
2644 free_rx_ring:
2645 skge_rx_clean(skge);
2646 kfree(skge->rx_ring.start);
2647 free_pci_mem:
2648 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2649 skge->mem = NULL;
2650
2651 return err;
2652 }
2653
2654 /* stop receiver */
2655 static void skge_rx_stop(struct skge_hw *hw, int port)
2656 {
2657 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2658 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2659 RB_RST_SET|RB_DIS_OP_MD);
2660 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2661 }
2662
2663 static int skge_down(struct net_device *dev)
2664 {
2665 struct skge_port *skge = netdev_priv(dev);
2666 struct skge_hw *hw = skge->hw;
2667 int port = skge->port;
2668
2669 if (skge->mem == NULL)
2670 return 0;
2671
2672 if (netif_msg_ifdown(skge))
2673 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2674
2675 netif_tx_disable(dev);
2676
2677 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2678 del_timer_sync(&skge->link_timer);
2679
2680 napi_disable(&skge->napi);
2681 netif_carrier_off(dev);
2682
2683 spin_lock_irq(&hw->hw_lock);
2684 hw->intr_mask &= ~portmask[port];
2685 skge_write32(hw, B0_IMSK, hw->intr_mask);
2686 spin_unlock_irq(&hw->hw_lock);
2687
2688 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2689 if (hw->chip_id == CHIP_ID_GENESIS)
2690 genesis_stop(skge);
2691 else
2692 yukon_stop(skge);
2693
2694 /* Stop transmitter */
2695 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2696 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2697 RB_RST_SET|RB_DIS_OP_MD);
2698
2699
2700 /* Disable Force Sync bit and Enable Alloc bit */
2701 skge_write8(hw, SK_REG(port, TXA_CTRL),
2702 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2703
2704 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2705 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2706 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2707
2708 /* Reset PCI FIFO */
2709 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2710 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2711
2712 /* Reset the RAM Buffer async Tx queue */
2713 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2714
2715 skge_rx_stop(hw, port);
2716
2717 if (hw->chip_id == CHIP_ID_GENESIS) {
2718 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2719 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2720 } else {
2721 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2722 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2723 }
2724
2725 skge_led(skge, LED_MODE_OFF);
2726
2727 netif_tx_lock_bh(dev);
2728 skge_tx_clean(dev);
2729 netif_tx_unlock_bh(dev);
2730
2731 skge_rx_clean(skge);
2732
2733 kfree(skge->rx_ring.start);
2734 kfree(skge->tx_ring.start);
2735 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2736 skge->mem = NULL;
2737 return 0;
2738 }
2739
2740 static inline int skge_avail(const struct skge_ring *ring)
2741 {
2742 smp_mb();
2743 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2744 + (ring->to_clean - ring->to_use) - 1;
2745 }
2746
2747 static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2748 struct net_device *dev)
2749 {
2750 struct skge_port *skge = netdev_priv(dev);
2751 struct skge_hw *hw = skge->hw;
2752 struct skge_element *e;
2753 struct skge_tx_desc *td;
2754 int i;
2755 u32 control, len;
2756 u64 map;
2757
2758 if (skb_padto(skb, ETH_ZLEN))
2759 return NETDEV_TX_OK;
2760
2761 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2762 return NETDEV_TX_BUSY;
2763
2764 e = skge->tx_ring.to_use;
2765 td = e->desc;
2766 BUG_ON(td->control & BMU_OWN);
2767 e->skb = skb;
2768 len = skb_headlen(skb);
2769 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2770 pci_unmap_addr_set(e, mapaddr, map);
2771 pci_unmap_len_set(e, maplen, len);
2772
2773 td->dma_lo = map;
2774 td->dma_hi = map >> 32;
2775
2776 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2777 const int offset = skb_transport_offset(skb);
2778
2779 /* This seems backwards, but it is what the sk98lin
2780 * does. Looks like hardware is wrong?
2781 */
2782 if (ipip_hdr(skb)->protocol == IPPROTO_UDP
2783 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2784 control = BMU_TCP_CHECK;
2785 else
2786 control = BMU_UDP_CHECK;
2787
2788 td->csum_offs = 0;
2789 td->csum_start = offset;
2790 td->csum_write = offset + skb->csum_offset;
2791 } else
2792 control = BMU_CHECK;
2793
2794 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2795 control |= BMU_EOF| BMU_IRQ_EOF;
2796 else {
2797 struct skge_tx_desc *tf = td;
2798
2799 control |= BMU_STFWD;
2800 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2801 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2802
2803 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2804 frag->size, PCI_DMA_TODEVICE);
2805
2806 e = e->next;
2807 e->skb = skb;
2808 tf = e->desc;
2809 BUG_ON(tf->control & BMU_OWN);
2810
2811 tf->dma_lo = map;
2812 tf->dma_hi = (u64) map >> 32;
2813 pci_unmap_addr_set(e, mapaddr, map);
2814 pci_unmap_len_set(e, maplen, frag->size);
2815
2816 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2817 }
2818 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2819 }
2820 /* Make sure all the descriptors written */
2821 wmb();
2822 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2823 wmb();
2824
2825 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2826
2827 if (unlikely(netif_msg_tx_queued(skge)))
2828 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2829 dev->name, e - skge->tx_ring.start, skb->len);
2830
2831 skge->tx_ring.to_use = e->next;
2832 smp_wmb();
2833
2834 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2835 pr_debug("%s: transmit queue full\n", dev->name);
2836 netif_stop_queue(dev);
2837 }
2838
2839 return NETDEV_TX_OK;
2840 }
2841
2842
2843 /* Free resources associated with this reing element */
2844 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2845 u32 control)
2846 {
2847 struct pci_dev *pdev = skge->hw->pdev;
2848
2849 /* skb header vs. fragment */
2850 if (control & BMU_STF)
2851 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2852 pci_unmap_len(e, maplen),
2853 PCI_DMA_TODEVICE);
2854 else
2855 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2856 pci_unmap_len(e, maplen),
2857 PCI_DMA_TODEVICE);
2858
2859 if (control & BMU_EOF) {
2860 if (unlikely(netif_msg_tx_done(skge)))
2861 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2862 skge->netdev->name, e - skge->tx_ring.start);
2863
2864 dev_kfree_skb(e->skb);
2865 }
2866 }
2867
2868 /* Free all buffers in transmit ring */
2869 static void skge_tx_clean(struct net_device *dev)
2870 {
2871 struct skge_port *skge = netdev_priv(dev);
2872 struct skge_element *e;
2873
2874 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2875 struct skge_tx_desc *td = e->desc;
2876 skge_tx_free(skge, e, td->control);
2877 td->control = 0;
2878 }
2879
2880 skge->tx_ring.to_clean = e;
2881 }
2882
2883 static void skge_tx_timeout(struct net_device *dev)
2884 {
2885 struct skge_port *skge = netdev_priv(dev);
2886
2887 if (netif_msg_timer(skge))
2888 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2889
2890 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2891 skge_tx_clean(dev);
2892 netif_wake_queue(dev);
2893 }
2894
2895 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2896 {
2897 int err;
2898
2899 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2900 return -EINVAL;
2901
2902 if (!netif_running(dev)) {
2903 dev->mtu = new_mtu;
2904 return 0;
2905 }
2906
2907 skge_down(dev);
2908
2909 dev->mtu = new_mtu;
2910
2911 err = skge_up(dev);
2912 if (err)
2913 dev_close(dev);
2914
2915 return err;
2916 }
2917
2918 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2919
2920 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2921 {
2922 u32 crc, bit;
2923
2924 crc = ether_crc_le(ETH_ALEN, addr);
2925 bit = ~crc & 0x3f;
2926 filter[bit/8] |= 1 << (bit%8);
2927 }
2928
2929 static void genesis_set_multicast(struct net_device *dev)
2930 {
2931 struct skge_port *skge = netdev_priv(dev);
2932 struct skge_hw *hw = skge->hw;
2933 int port = skge->port;
2934 int i, count = dev->mc_count;
2935 struct dev_mc_list *list = dev->mc_list;
2936 u32 mode;
2937 u8 filter[8];
2938
2939 mode = xm_read32(hw, port, XM_MODE);
2940 mode |= XM_MD_ENA_HASH;
2941 if (dev->flags & IFF_PROMISC)
2942 mode |= XM_MD_ENA_PROM;
2943 else
2944 mode &= ~XM_MD_ENA_PROM;
2945
2946 if (dev->flags & IFF_ALLMULTI)
2947 memset(filter, 0xff, sizeof(filter));
2948 else {
2949 memset(filter, 0, sizeof(filter));
2950
2951 if (skge->flow_status == FLOW_STAT_REM_SEND
2952 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2953 genesis_add_filter(filter, pause_mc_addr);
2954
2955 for (i = 0; list && i < count; i++, list = list->next)
2956 genesis_add_filter(filter, list->dmi_addr);
2957 }
2958
2959 xm_write32(hw, port, XM_MODE, mode);
2960 xm_outhash(hw, port, XM_HSM, filter);
2961 }
2962
2963 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2964 {
2965 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2966 filter[bit/8] |= 1 << (bit%8);
2967 }
2968
2969 static void yukon_set_multicast(struct net_device *dev)
2970 {
2971 struct skge_port *skge = netdev_priv(dev);
2972 struct skge_hw *hw = skge->hw;
2973 int port = skge->port;
2974 struct dev_mc_list *list = dev->mc_list;
2975 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
2976 || skge->flow_status == FLOW_STAT_SYMMETRIC);
2977 u16 reg;
2978 u8 filter[8];
2979
2980 memset(filter, 0, sizeof(filter));
2981
2982 reg = gma_read16(hw, port, GM_RX_CTRL);
2983 reg |= GM_RXCR_UCF_ENA;
2984
2985 if (dev->flags & IFF_PROMISC) /* promiscuous */
2986 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2987 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2988 memset(filter, 0xff, sizeof(filter));
2989 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
2990 reg &= ~GM_RXCR_MCF_ENA;
2991 else {
2992 int i;
2993 reg |= GM_RXCR_MCF_ENA;
2994
2995 if (rx_pause)
2996 yukon_add_filter(filter, pause_mc_addr);
2997
2998 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2999 yukon_add_filter(filter, list->dmi_addr);
3000 }
3001
3002
3003 gma_write16(hw, port, GM_MC_ADDR_H1,
3004 (u16)filter[0] | ((u16)filter[1] << 8));
3005 gma_write16(hw, port, GM_MC_ADDR_H2,
3006 (u16)filter[2] | ((u16)filter[3] << 8));
3007 gma_write16(hw, port, GM_MC_ADDR_H3,
3008 (u16)filter[4] | ((u16)filter[5] << 8));
3009 gma_write16(hw, port, GM_MC_ADDR_H4,
3010 (u16)filter[6] | ((u16)filter[7] << 8));
3011
3012 gma_write16(hw, port, GM_RX_CTRL, reg);
3013 }
3014
3015 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3016 {
3017 if (hw->chip_id == CHIP_ID_GENESIS)
3018 return status >> XMR_FS_LEN_SHIFT;
3019 else
3020 return status >> GMR_FS_LEN_SHIFT;
3021 }
3022
3023 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3024 {
3025 if (hw->chip_id == CHIP_ID_GENESIS)
3026 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3027 else
3028 return (status & GMR_FS_ANY_ERR) ||
3029 (status & GMR_FS_RX_OK) == 0;
3030 }
3031
3032 static void skge_set_multicast(struct net_device *dev)
3033 {
3034 struct skge_port *skge = netdev_priv(dev);
3035 struct skge_hw *hw = skge->hw;
3036
3037 if (hw->chip_id == CHIP_ID_GENESIS)
3038 genesis_set_multicast(dev);
3039 else
3040 yukon_set_multicast(dev);
3041
3042 }
3043
3044
3045 /* Get receive buffer from descriptor.
3046 * Handles copy of small buffers and reallocation failures
3047 */
3048 static struct sk_buff *skge_rx_get(struct net_device *dev,
3049 struct skge_element *e,
3050 u32 control, u32 status, u16 csum)
3051 {
3052 struct skge_port *skge = netdev_priv(dev);
3053 struct sk_buff *skb;
3054 u16 len = control & BMU_BBC;
3055
3056 if (unlikely(netif_msg_rx_status(skge)))
3057 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
3058 dev->name, e - skge->rx_ring.start,
3059 status, len);
3060
3061 if (len > skge->rx_buf_size)
3062 goto error;
3063
3064 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3065 goto error;
3066
3067 if (bad_phy_status(skge->hw, status))
3068 goto error;
3069
3070 if (phy_length(skge->hw, status) != len)
3071 goto error;
3072
3073 if (len < RX_COPY_THRESHOLD) {
3074 skb = netdev_alloc_skb(dev, len + 2);
3075 if (!skb)
3076 goto resubmit;
3077
3078 skb_reserve(skb, 2);
3079 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3080 pci_unmap_addr(e, mapaddr),
3081 len, PCI_DMA_FROMDEVICE);
3082 skb_copy_from_linear_data(e->skb, skb->data, len);
3083 pci_dma_sync_single_for_device(skge->hw->pdev,
3084 pci_unmap_addr(e, mapaddr),
3085 len, PCI_DMA_FROMDEVICE);
3086 skge_rx_reuse(e, skge->rx_buf_size);
3087 } else {
3088 struct sk_buff *nskb;
3089 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
3090 if (!nskb)
3091 goto resubmit;
3092
3093 skb_reserve(nskb, NET_IP_ALIGN);
3094 pci_unmap_single(skge->hw->pdev,
3095 pci_unmap_addr(e, mapaddr),
3096 pci_unmap_len(e, maplen),
3097 PCI_DMA_FROMDEVICE);
3098 skb = e->skb;
3099 prefetch(skb->data);
3100 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
3101 }
3102
3103 skb_put(skb, len);
3104 if (skge->rx_csum) {
3105 skb->csum = csum;
3106 skb->ip_summed = CHECKSUM_COMPLETE;
3107 }
3108
3109 skb->protocol = eth_type_trans(skb, dev);
3110
3111 return skb;
3112 error:
3113
3114 if (netif_msg_rx_err(skge))
3115 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
3116 dev->name, e - skge->rx_ring.start,
3117 control, status);
3118
3119 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3120 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3121 dev->stats.rx_length_errors++;
3122 if (status & XMR_FS_FRA_ERR)
3123 dev->stats.rx_frame_errors++;
3124 if (status & XMR_FS_FCS_ERR)
3125 dev->stats.rx_crc_errors++;
3126 } else {
3127 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3128 dev->stats.rx_length_errors++;
3129 if (status & GMR_FS_FRAGMENT)
3130 dev->stats.rx_frame_errors++;
3131 if (status & GMR_FS_CRC_ERR)
3132 dev->stats.rx_crc_errors++;
3133 }
3134
3135 resubmit:
3136 skge_rx_reuse(e, skge->rx_buf_size);
3137 return NULL;
3138 }
3139
3140 /* Free all buffers in Tx ring which are no longer owned by device */
3141 static void skge_tx_done(struct net_device *dev)
3142 {
3143 struct skge_port *skge = netdev_priv(dev);
3144 struct skge_ring *ring = &skge->tx_ring;
3145 struct skge_element *e;
3146
3147 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3148
3149 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3150 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3151
3152 if (control & BMU_OWN)
3153 break;
3154
3155 skge_tx_free(skge, e, control);
3156 }
3157 skge->tx_ring.to_clean = e;
3158
3159 /* Can run lockless until we need to synchronize to restart queue. */
3160 smp_mb();
3161
3162 if (unlikely(netif_queue_stopped(dev) &&
3163 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3164 netif_tx_lock(dev);
3165 if (unlikely(netif_queue_stopped(dev) &&
3166 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3167 netif_wake_queue(dev);
3168
3169 }
3170 netif_tx_unlock(dev);
3171 }
3172 }
3173
3174 static int skge_poll(struct napi_struct *napi, int to_do)
3175 {
3176 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3177 struct net_device *dev = skge->netdev;
3178 struct skge_hw *hw = skge->hw;
3179 struct skge_ring *ring = &skge->rx_ring;
3180 struct skge_element *e;
3181 int work_done = 0;
3182
3183 skge_tx_done(dev);
3184
3185 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3186
3187 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3188 struct skge_rx_desc *rd = e->desc;
3189 struct sk_buff *skb;
3190 u32 control;
3191
3192 rmb();
3193 control = rd->control;
3194 if (control & BMU_OWN)
3195 break;
3196
3197 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3198 if (likely(skb)) {
3199 netif_receive_skb(skb);
3200
3201 ++work_done;
3202 }
3203 }
3204 ring->to_clean = e;
3205
3206 /* restart receiver */
3207 wmb();
3208 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3209
3210 if (work_done < to_do) {
3211 unsigned long flags;
3212
3213 spin_lock_irqsave(&hw->hw_lock, flags);
3214 __napi_complete(napi);
3215 hw->intr_mask |= napimask[skge->port];
3216 skge_write32(hw, B0_IMSK, hw->intr_mask);
3217 skge_read32(hw, B0_IMSK);
3218 spin_unlock_irqrestore(&hw->hw_lock, flags);
3219 }
3220
3221 return work_done;
3222 }
3223
3224 /* Parity errors seem to happen when Genesis is connected to a switch
3225 * with no other ports present. Heartbeat error??
3226 */
3227 static void skge_mac_parity(struct skge_hw *hw, int port)
3228 {
3229 struct net_device *dev = hw->dev[port];
3230
3231 ++dev->stats.tx_heartbeat_errors;
3232
3233 if (hw->chip_id == CHIP_ID_GENESIS)
3234 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3235 MFF_CLR_PERR);
3236 else
3237 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3238 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3239 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3240 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3241 }
3242
3243 static void skge_mac_intr(struct skge_hw *hw, int port)
3244 {
3245 if (hw->chip_id == CHIP_ID_GENESIS)
3246 genesis_mac_intr(hw, port);
3247 else
3248 yukon_mac_intr(hw, port);
3249 }
3250
3251 /* Handle device specific framing and timeout interrupts */
3252 static void skge_error_irq(struct skge_hw *hw)
3253 {
3254 struct pci_dev *pdev = hw->pdev;
3255 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3256
3257 if (hw->chip_id == CHIP_ID_GENESIS) {
3258 /* clear xmac errors */
3259 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3260 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3261 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3262 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3263 } else {
3264 /* Timestamp (unused) overflow */
3265 if (hwstatus & IS_IRQ_TIST_OV)
3266 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3267 }
3268
3269 if (hwstatus & IS_RAM_RD_PAR) {
3270 dev_err(&pdev->dev, "Ram read data parity error\n");
3271 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3272 }
3273
3274 if (hwstatus & IS_RAM_WR_PAR) {
3275 dev_err(&pdev->dev, "Ram write data parity error\n");
3276 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3277 }
3278
3279 if (hwstatus & IS_M1_PAR_ERR)
3280 skge_mac_parity(hw, 0);
3281
3282 if (hwstatus & IS_M2_PAR_ERR)
3283 skge_mac_parity(hw, 1);
3284
3285 if (hwstatus & IS_R1_PAR_ERR) {
3286 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3287 hw->dev[0]->name);
3288 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3289 }
3290
3291 if (hwstatus & IS_R2_PAR_ERR) {
3292 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3293 hw->dev[1]->name);
3294 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3295 }
3296
3297 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3298 u16 pci_status, pci_cmd;
3299
3300 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3301 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3302
3303 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3304 pci_cmd, pci_status);
3305
3306 /* Write the error bits back to clear them. */
3307 pci_status &= PCI_STATUS_ERROR_BITS;
3308 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3309 pci_write_config_word(pdev, PCI_COMMAND,
3310 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3311 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3312 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3313
3314 /* if error still set then just ignore it */
3315 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3316 if (hwstatus & IS_IRQ_STAT) {
3317 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3318 hw->intr_mask &= ~IS_HW_ERR;
3319 }
3320 }
3321 }
3322
3323 /*
3324 * Interrupt from PHY are handled in tasklet (softirq)
3325 * because accessing phy registers requires spin wait which might
3326 * cause excess interrupt latency.
3327 */
3328 static void skge_extirq(unsigned long arg)
3329 {
3330 struct skge_hw *hw = (struct skge_hw *) arg;
3331 int port;
3332
3333 for (port = 0; port < hw->ports; port++) {
3334 struct net_device *dev = hw->dev[port];
3335
3336 if (netif_running(dev)) {
3337 struct skge_port *skge = netdev_priv(dev);
3338
3339 spin_lock(&hw->phy_lock);
3340 if (hw->chip_id != CHIP_ID_GENESIS)
3341 yukon_phy_intr(skge);
3342 else if (hw->phy_type == SK_PHY_BCOM)
3343 bcom_phy_intr(skge);
3344 spin_unlock(&hw->phy_lock);
3345 }
3346 }
3347
3348 spin_lock_irq(&hw->hw_lock);
3349 hw->intr_mask |= IS_EXT_REG;
3350 skge_write32(hw, B0_IMSK, hw->intr_mask);
3351 skge_read32(hw, B0_IMSK);
3352 spin_unlock_irq(&hw->hw_lock);
3353 }
3354
3355 static irqreturn_t skge_intr(int irq, void *dev_id)
3356 {
3357 struct skge_hw *hw = dev_id;
3358 u32 status;
3359 int handled = 0;
3360
3361 spin_lock(&hw->hw_lock);
3362 /* Reading this register masks IRQ */
3363 status = skge_read32(hw, B0_SP_ISRC);
3364 if (status == 0 || status == ~0)
3365 goto out;
3366
3367 handled = 1;
3368 status &= hw->intr_mask;
3369 if (status & IS_EXT_REG) {
3370 hw->intr_mask &= ~IS_EXT_REG;
3371 tasklet_schedule(&hw->phy_task);
3372 }
3373
3374 if (status & (IS_XA1_F|IS_R1_F)) {
3375 struct skge_port *skge = netdev_priv(hw->dev[0]);
3376 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3377 napi_schedule(&skge->napi);
3378 }
3379
3380 if (status & IS_PA_TO_TX1)
3381 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3382
3383 if (status & IS_PA_TO_RX1) {
3384 ++hw->dev[0]->stats.rx_over_errors;
3385 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3386 }
3387
3388
3389 if (status & IS_MAC1)
3390 skge_mac_intr(hw, 0);
3391
3392 if (hw->dev[1]) {
3393 struct skge_port *skge = netdev_priv(hw->dev[1]);
3394
3395 if (status & (IS_XA2_F|IS_R2_F)) {
3396 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3397 napi_schedule(&skge->napi);
3398 }
3399
3400 if (status & IS_PA_TO_RX2) {
3401 ++hw->dev[1]->stats.rx_over_errors;
3402 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3403 }
3404
3405 if (status & IS_PA_TO_TX2)
3406 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3407
3408 if (status & IS_MAC2)
3409 skge_mac_intr(hw, 1);
3410 }
3411
3412 if (status & IS_HW_ERR)
3413 skge_error_irq(hw);
3414
3415 skge_write32(hw, B0_IMSK, hw->intr_mask);
3416 skge_read32(hw, B0_IMSK);
3417 out:
3418 spin_unlock(&hw->hw_lock);
3419
3420 return IRQ_RETVAL(handled);
3421 }
3422
3423 #ifdef CONFIG_NET_POLL_CONTROLLER
3424 static void skge_netpoll(struct net_device *dev)
3425 {
3426 struct skge_port *skge = netdev_priv(dev);
3427
3428 disable_irq(dev->irq);
3429 skge_intr(dev->irq, skge->hw);
3430 enable_irq(dev->irq);
3431 }
3432 #endif
3433
3434 static int skge_set_mac_address(struct net_device *dev, void *p)
3435 {
3436 struct skge_port *skge = netdev_priv(dev);
3437 struct skge_hw *hw = skge->hw;
3438 unsigned port = skge->port;
3439 const struct sockaddr *addr = p;
3440 u16 ctrl;
3441
3442 if (!is_valid_ether_addr(addr->sa_data))
3443 return -EADDRNOTAVAIL;
3444
3445 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3446
3447 if (!netif_running(dev)) {
3448 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3449 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3450 } else {
3451 /* disable Rx */
3452 spin_lock_bh(&hw->phy_lock);
3453 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3454 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3455
3456 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3457 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3458
3459 if (hw->chip_id == CHIP_ID_GENESIS)
3460 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3461 else {
3462 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3463 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3464 }
3465
3466 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3467 spin_unlock_bh(&hw->phy_lock);
3468 }
3469
3470 return 0;
3471 }
3472
3473 static const struct {
3474 u8 id;
3475 const char *name;
3476 } skge_chips[] = {
3477 { CHIP_ID_GENESIS, "Genesis" },
3478 { CHIP_ID_YUKON, "Yukon" },
3479 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3480 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3481 };
3482
3483 static const char *skge_board_name(const struct skge_hw *hw)
3484 {
3485 int i;
3486 static char buf[16];
3487
3488 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3489 if (skge_chips[i].id == hw->chip_id)
3490 return skge_chips[i].name;
3491
3492 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3493 return buf;
3494 }
3495
3496
3497 /*
3498 * Setup the board data structure, but don't bring up
3499 * the port(s)
3500 */
3501 static int skge_reset(struct skge_hw *hw)
3502 {
3503 u32 reg;
3504 u16 ctst, pci_status;
3505 u8 t8, mac_cfg, pmd_type;
3506 int i;
3507
3508 ctst = skge_read16(hw, B0_CTST);
3509
3510 /* do a SW reset */
3511 skge_write8(hw, B0_CTST, CS_RST_SET);
3512 skge_write8(hw, B0_CTST, CS_RST_CLR);
3513
3514 /* clear PCI errors, if any */
3515 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3516 skge_write8(hw, B2_TST_CTRL2, 0);
3517
3518 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3519 pci_write_config_word(hw->pdev, PCI_STATUS,
3520 pci_status | PCI_STATUS_ERROR_BITS);
3521 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3522 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3523
3524 /* restore CLK_RUN bits (for Yukon-Lite) */
3525 skge_write16(hw, B0_CTST,
3526 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3527
3528 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3529 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3530 pmd_type = skge_read8(hw, B2_PMD_TYP);
3531 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3532
3533 switch (hw->chip_id) {
3534 case CHIP_ID_GENESIS:
3535 switch (hw->phy_type) {
3536 case SK_PHY_XMAC:
3537 hw->phy_addr = PHY_ADDR_XMAC;
3538 break;
3539 case SK_PHY_BCOM:
3540 hw->phy_addr = PHY_ADDR_BCOM;
3541 break;
3542 default:
3543 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3544 hw->phy_type);
3545 return -EOPNOTSUPP;
3546 }
3547 break;
3548
3549 case CHIP_ID_YUKON:
3550 case CHIP_ID_YUKON_LITE:
3551 case CHIP_ID_YUKON_LP:
3552 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3553 hw->copper = 1;
3554
3555 hw->phy_addr = PHY_ADDR_MARV;
3556 break;
3557
3558 default:
3559 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3560 hw->chip_id);
3561 return -EOPNOTSUPP;
3562 }
3563
3564 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3565 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3566 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3567
3568 /* read the adapters RAM size */
3569 t8 = skge_read8(hw, B2_E_0);
3570 if (hw->chip_id == CHIP_ID_GENESIS) {
3571 if (t8 == 3) {
3572 /* special case: 4 x 64k x 36, offset = 0x80000 */
3573 hw->ram_size = 0x100000;
3574 hw->ram_offset = 0x80000;
3575 } else
3576 hw->ram_size = t8 * 512;
3577 }
3578 else if (t8 == 0)
3579 hw->ram_size = 0x20000;
3580 else
3581 hw->ram_size = t8 * 4096;
3582
3583 hw->intr_mask = IS_HW_ERR;
3584
3585 /* Use PHY IRQ for all but fiber based Genesis board */
3586 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3587 hw->intr_mask |= IS_EXT_REG;
3588
3589 if (hw->chip_id == CHIP_ID_GENESIS)
3590 genesis_init(hw);
3591 else {
3592 /* switch power to VCC (WA for VAUX problem) */
3593 skge_write8(hw, B0_POWER_CTRL,
3594 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3595
3596 /* avoid boards with stuck Hardware error bits */
3597 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3598 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3599 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3600 hw->intr_mask &= ~IS_HW_ERR;
3601 }
3602
3603 /* Clear PHY COMA */
3604 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3605 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3606 reg &= ~PCI_PHY_COMA;
3607 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3608 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3609
3610
3611 for (i = 0; i < hw->ports; i++) {
3612 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3613 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3614 }
3615 }
3616
3617 /* turn off hardware timer (unused) */
3618 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3619 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3620 skge_write8(hw, B0_LED, LED_STAT_ON);
3621
3622 /* enable the Tx Arbiters */
3623 for (i = 0; i < hw->ports; i++)
3624 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3625
3626 /* Initialize ram interface */
3627 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3628
3629 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3630 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3631 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3632 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3633 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3634 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3635 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3636 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3637 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3638 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3639 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3640 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3641
3642 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3643
3644 /* Set interrupt moderation for Transmit only
3645 * Receive interrupts avoided by NAPI
3646 */
3647 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3648 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3649 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3650
3651 skge_write32(hw, B0_IMSK, hw->intr_mask);
3652
3653 for (i = 0; i < hw->ports; i++) {
3654 if (hw->chip_id == CHIP_ID_GENESIS)
3655 genesis_reset(hw, i);
3656 else
3657 yukon_reset(hw, i);
3658 }
3659
3660 return 0;
3661 }
3662
3663
3664 #ifdef CONFIG_SKGE_DEBUG
3665
3666 static struct dentry *skge_debug;
3667
3668 static int skge_debug_show(struct seq_file *seq, void *v)
3669 {
3670 struct net_device *dev = seq->private;
3671 const struct skge_port *skge = netdev_priv(dev);
3672 const struct skge_hw *hw = skge->hw;
3673 const struct skge_element *e;
3674
3675 if (!netif_running(dev))
3676 return -ENETDOWN;
3677
3678 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3679 skge_read32(hw, B0_IMSK));
3680
3681 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3682 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3683 const struct skge_tx_desc *t = e->desc;
3684 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3685 t->control, t->dma_hi, t->dma_lo, t->status,
3686 t->csum_offs, t->csum_write, t->csum_start);
3687 }
3688
3689 seq_printf(seq, "\nRx Ring: \n");
3690 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3691 const struct skge_rx_desc *r = e->desc;
3692
3693 if (r->control & BMU_OWN)
3694 break;
3695
3696 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3697 r->control, r->dma_hi, r->dma_lo, r->status,
3698 r->timestamp, r->csum1, r->csum1_start);
3699 }
3700
3701 return 0;
3702 }
3703
3704 static int skge_debug_open(struct inode *inode, struct file *file)
3705 {
3706 return single_open(file, skge_debug_show, inode->i_private);
3707 }
3708
3709 static const struct file_operations skge_debug_fops = {
3710 .owner = THIS_MODULE,
3711 .open = skge_debug_open,
3712 .read = seq_read,
3713 .llseek = seq_lseek,
3714 .release = single_release,
3715 };
3716
3717 /*
3718 * Use network device events to create/remove/rename
3719 * debugfs file entries
3720 */
3721 static int skge_device_event(struct notifier_block *unused,
3722 unsigned long event, void *ptr)
3723 {
3724 struct net_device *dev = ptr;
3725 struct skge_port *skge;
3726 struct dentry *d;
3727
3728 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
3729 goto done;
3730
3731 skge = netdev_priv(dev);
3732 switch(event) {
3733 case NETDEV_CHANGENAME:
3734 if (skge->debugfs) {
3735 d = debugfs_rename(skge_debug, skge->debugfs,
3736 skge_debug, dev->name);
3737 if (d)
3738 skge->debugfs = d;
3739 else {
3740 pr_info(PFX "%s: rename failed\n", dev->name);
3741 debugfs_remove(skge->debugfs);
3742 }
3743 }
3744 break;
3745
3746 case NETDEV_GOING_DOWN:
3747 if (skge->debugfs) {
3748 debugfs_remove(skge->debugfs);
3749 skge->debugfs = NULL;
3750 }
3751 break;
3752
3753 case NETDEV_UP:
3754 d = debugfs_create_file(dev->name, S_IRUGO,
3755 skge_debug, dev,
3756 &skge_debug_fops);
3757 if (!d || IS_ERR(d))
3758 pr_info(PFX "%s: debugfs create failed\n",
3759 dev->name);
3760 else
3761 skge->debugfs = d;
3762 break;
3763 }
3764
3765 done:
3766 return NOTIFY_DONE;
3767 }
3768
3769 static struct notifier_block skge_notifier = {
3770 .notifier_call = skge_device_event,
3771 };
3772
3773
3774 static __init void skge_debug_init(void)
3775 {
3776 struct dentry *ent;
3777
3778 ent = debugfs_create_dir("skge", NULL);
3779 if (!ent || IS_ERR(ent)) {
3780 pr_info(PFX "debugfs create directory failed\n");
3781 return;
3782 }
3783
3784 skge_debug = ent;
3785 register_netdevice_notifier(&skge_notifier);
3786 }
3787
3788 static __exit void skge_debug_cleanup(void)
3789 {
3790 if (skge_debug) {
3791 unregister_netdevice_notifier(&skge_notifier);
3792 debugfs_remove(skge_debug);
3793 skge_debug = NULL;
3794 }
3795 }
3796
3797 #else
3798 #define skge_debug_init()
3799 #define skge_debug_cleanup()
3800 #endif
3801
3802 static const struct net_device_ops skge_netdev_ops = {
3803 .ndo_open = skge_up,
3804 .ndo_stop = skge_down,
3805 .ndo_start_xmit = skge_xmit_frame,
3806 .ndo_do_ioctl = skge_ioctl,
3807 .ndo_get_stats = skge_get_stats,
3808 .ndo_tx_timeout = skge_tx_timeout,
3809 .ndo_change_mtu = skge_change_mtu,
3810 .ndo_validate_addr = eth_validate_addr,
3811 .ndo_set_multicast_list = skge_set_multicast,
3812 .ndo_set_mac_address = skge_set_mac_address,
3813 #ifdef CONFIG_NET_POLL_CONTROLLER
3814 .ndo_poll_controller = skge_netpoll,
3815 #endif
3816 };
3817
3818
3819 /* Initialize network device */
3820 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3821 int highmem)
3822 {
3823 struct skge_port *skge;
3824 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3825
3826 if (!dev) {
3827 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3828 return NULL;
3829 }
3830
3831 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3832 dev->netdev_ops = &skge_netdev_ops;
3833 dev->ethtool_ops = &skge_ethtool_ops;
3834 dev->watchdog_timeo = TX_WATCHDOG;
3835 dev->irq = hw->pdev->irq;
3836
3837 if (highmem)
3838 dev->features |= NETIF_F_HIGHDMA;
3839
3840 skge = netdev_priv(dev);
3841 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
3842 skge->netdev = dev;
3843 skge->hw = hw;
3844 skge->msg_enable = netif_msg_init(debug, default_msg);
3845
3846 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3847 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3848
3849 /* Auto speed and flow control */
3850 skge->autoneg = AUTONEG_ENABLE;
3851 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3852 skge->duplex = -1;
3853 skge->speed = -1;
3854 skge->advertising = skge_supported_modes(hw);
3855
3856 if (device_can_wakeup(&hw->pdev->dev)) {
3857 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3858 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3859 }
3860
3861 hw->dev[port] = dev;
3862
3863 skge->port = port;
3864
3865 /* Only used for Genesis XMAC */
3866 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3867
3868 if (hw->chip_id != CHIP_ID_GENESIS) {
3869 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3870 skge->rx_csum = 1;
3871 }
3872
3873 /* read the mac address */
3874 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3875 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3876
3877 /* device is off until link detection */
3878 netif_carrier_off(dev);
3879 netif_stop_queue(dev);
3880
3881 return dev;
3882 }
3883
3884 static void __devinit skge_show_addr(struct net_device *dev)
3885 {
3886 const struct skge_port *skge = netdev_priv(dev);
3887
3888 if (netif_msg_probe(skge))
3889 printk(KERN_INFO PFX "%s: addr %pM\n",
3890 dev->name, dev->dev_addr);
3891 }
3892
3893 static int __devinit skge_probe(struct pci_dev *pdev,
3894 const struct pci_device_id *ent)
3895 {
3896 struct net_device *dev, *dev1;
3897 struct skge_hw *hw;
3898 int err, using_dac = 0;
3899
3900 err = pci_enable_device(pdev);
3901 if (err) {
3902 dev_err(&pdev->dev, "cannot enable PCI device\n");
3903 goto err_out;
3904 }
3905
3906 err = pci_request_regions(pdev, DRV_NAME);
3907 if (err) {
3908 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3909 goto err_out_disable_pdev;
3910 }
3911
3912 pci_set_master(pdev);
3913
3914 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3915 using_dac = 1;
3916 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3917 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3918 using_dac = 0;
3919 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3920 }
3921
3922 if (err) {
3923 dev_err(&pdev->dev, "no usable DMA configuration\n");
3924 goto err_out_free_regions;
3925 }
3926
3927 #ifdef __BIG_ENDIAN
3928 /* byte swap descriptors in hardware */
3929 {
3930 u32 reg;
3931
3932 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3933 reg |= PCI_REV_DESC;
3934 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3935 }
3936 #endif
3937
3938 err = -ENOMEM;
3939 /* space for skge@pci:0000:04:00.0 */
3940 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:" )
3941 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
3942 if (!hw) {
3943 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3944 goto err_out_free_regions;
3945 }
3946 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3947
3948 hw->pdev = pdev;
3949 spin_lock_init(&hw->hw_lock);
3950 spin_lock_init(&hw->phy_lock);
3951 tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
3952
3953 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3954 if (!hw->regs) {
3955 dev_err(&pdev->dev, "cannot map device registers\n");
3956 goto err_out_free_hw;
3957 }
3958
3959 err = skge_reset(hw);
3960 if (err)
3961 goto err_out_iounmap;
3962
3963 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3964 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3965 skge_board_name(hw), hw->chip_rev);
3966
3967 dev = skge_devinit(hw, 0, using_dac);
3968 if (!dev)
3969 goto err_out_led_off;
3970
3971 /* Some motherboards are broken and has zero in ROM. */
3972 if (!is_valid_ether_addr(dev->dev_addr))
3973 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3974
3975 err = register_netdev(dev);
3976 if (err) {
3977 dev_err(&pdev->dev, "cannot register net device\n");
3978 goto err_out_free_netdev;
3979 }
3980
3981 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, hw->irq_name, hw);
3982 if (err) {
3983 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
3984 dev->name, pdev->irq);
3985 goto err_out_unregister;
3986 }
3987 skge_show_addr(dev);
3988
3989 if (hw->ports > 1) {
3990 dev1 = skge_devinit(hw, 1, using_dac);
3991 if (dev1 && register_netdev(dev1) == 0)
3992 skge_show_addr(dev1);
3993 else {
3994 /* Failure to register second port need not be fatal */
3995 dev_warn(&pdev->dev, "register of second port failed\n");
3996 hw->dev[1] = NULL;
3997 hw->ports = 1;
3998 if (dev1)
3999 free_netdev(dev1);
4000 }
4001 }
4002 pci_set_drvdata(pdev, hw);
4003
4004 return 0;
4005
4006 err_out_unregister:
4007 unregister_netdev(dev);
4008 err_out_free_netdev:
4009 free_netdev(dev);
4010 err_out_led_off:
4011 skge_write16(hw, B0_LED, LED_STAT_OFF);
4012 err_out_iounmap:
4013 iounmap(hw->regs);
4014 err_out_free_hw:
4015 kfree(hw);
4016 err_out_free_regions:
4017 pci_release_regions(pdev);
4018 err_out_disable_pdev:
4019 pci_disable_device(pdev);
4020 pci_set_drvdata(pdev, NULL);
4021 err_out:
4022 return err;
4023 }
4024
4025 static void __devexit skge_remove(struct pci_dev *pdev)
4026 {
4027 struct skge_hw *hw = pci_get_drvdata(pdev);
4028 struct net_device *dev0, *dev1;
4029
4030 if (!hw)
4031 return;
4032
4033 flush_scheduled_work();
4034
4035 if ((dev1 = hw->dev[1]))
4036 unregister_netdev(dev1);
4037 dev0 = hw->dev[0];
4038 unregister_netdev(dev0);
4039
4040 tasklet_disable(&hw->phy_task);
4041
4042 spin_lock_irq(&hw->hw_lock);
4043 hw->intr_mask = 0;
4044 skge_write32(hw, B0_IMSK, 0);
4045 skge_read32(hw, B0_IMSK);
4046 spin_unlock_irq(&hw->hw_lock);
4047
4048 skge_write16(hw, B0_LED, LED_STAT_OFF);
4049 skge_write8(hw, B0_CTST, CS_RST_SET);
4050
4051 free_irq(pdev->irq, hw);
4052 pci_release_regions(pdev);
4053 pci_disable_device(pdev);
4054 if (dev1)
4055 free_netdev(dev1);
4056 free_netdev(dev0);
4057
4058 iounmap(hw->regs);
4059 kfree(hw);
4060 pci_set_drvdata(pdev, NULL);
4061 }
4062
4063 #ifdef CONFIG_PM
4064 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
4065 {
4066 struct skge_hw *hw = pci_get_drvdata(pdev);
4067 int i, err, wol = 0;
4068
4069 if (!hw)
4070 return 0;
4071
4072 err = pci_save_state(pdev);
4073 if (err)
4074 return err;
4075
4076 for (i = 0; i < hw->ports; i++) {
4077 struct net_device *dev = hw->dev[i];
4078 struct skge_port *skge = netdev_priv(dev);
4079
4080 if (netif_running(dev))
4081 skge_down(dev);
4082 if (skge->wol)
4083 skge_wol_init(skge);
4084
4085 wol |= skge->wol;
4086 }
4087
4088 skge_write32(hw, B0_IMSK, 0);
4089
4090 pci_prepare_to_sleep(pdev);
4091
4092 return 0;
4093 }
4094
4095 static int skge_resume(struct pci_dev *pdev)
4096 {
4097 struct skge_hw *hw = pci_get_drvdata(pdev);
4098 int i, err;
4099
4100 if (!hw)
4101 return 0;
4102
4103 err = pci_back_from_sleep(pdev);
4104 if (err)
4105 goto out;
4106
4107 err = pci_restore_state(pdev);
4108 if (err)
4109 goto out;
4110
4111 err = skge_reset(hw);
4112 if (err)
4113 goto out;
4114
4115 for (i = 0; i < hw->ports; i++) {
4116 struct net_device *dev = hw->dev[i];
4117
4118 if (netif_running(dev)) {
4119 err = skge_up(dev);
4120
4121 if (err) {
4122 printk(KERN_ERR PFX "%s: could not up: %d\n",
4123 dev->name, err);
4124 dev_close(dev);
4125 goto out;
4126 }
4127 }
4128 }
4129 out:
4130 return err;
4131 }
4132 #endif
4133
4134 static void skge_shutdown(struct pci_dev *pdev)
4135 {
4136 struct skge_hw *hw = pci_get_drvdata(pdev);
4137 int i, wol = 0;
4138
4139 if (!hw)
4140 return;
4141
4142 for (i = 0; i < hw->ports; i++) {
4143 struct net_device *dev = hw->dev[i];
4144 struct skge_port *skge = netdev_priv(dev);
4145
4146 if (skge->wol)
4147 skge_wol_init(skge);
4148 wol |= skge->wol;
4149 }
4150
4151 if (pci_enable_wake(pdev, PCI_D3cold, wol))
4152 pci_enable_wake(pdev, PCI_D3hot, wol);
4153
4154 pci_disable_device(pdev);
4155 pci_set_power_state(pdev, PCI_D3hot);
4156
4157 }
4158
4159 static struct pci_driver skge_driver = {
4160 .name = DRV_NAME,
4161 .id_table = skge_id_table,
4162 .probe = skge_probe,
4163 .remove = __devexit_p(skge_remove),
4164 #ifdef CONFIG_PM
4165 .suspend = skge_suspend,
4166 .resume = skge_resume,
4167 #endif
4168 .shutdown = skge_shutdown,
4169 };
4170
4171 static int __init skge_init_module(void)
4172 {
4173 skge_debug_init();
4174 return pci_register_driver(&skge_driver);
4175 }
4176
4177 static void __exit skge_cleanup_module(void)
4178 {
4179 pci_unregister_driver(&skge_driver);
4180 skge_debug_cleanup();
4181 }
4182
4183 module_init(skge_init_module);
4184 module_exit(skge_cleanup_module);
Linux with added FPC-III support