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x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath5k / ath5k.h
blob6cd5efcec41719de9535558fdbb244ffbc1838fa
1 /*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #ifndef _ATH5K_H
19 #define _ATH5K_H
20
21 /* TODO: Clean up channel debuging -doesn't work anyway- and start
22 * working on reg. control code using all available eeprom information
23 * -rev. engineering needed- */
24 #define CHAN_DEBUG 0
25
26 #include <linux/io.h>
27 #include <linux/types.h>
28 #include <net/mac80211.h>
29
30 /* RX/TX descriptor hw structs
31 * TODO: Driver part should only see sw structs */
32 #include "desc.h"
33
34 /* EEPROM structs/offsets
35 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
36 * and clean up common bits, then introduce set/get functions in eeprom.c */
37 #include "eeprom.h"
38
39 /* PCI IDs */
40 #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
41 #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
42 #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
43 #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
44 #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
45 #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
46 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
47 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
48 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
49 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
50 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
51 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
52 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
53 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
54 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
55 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
56 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
57 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
58 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
59 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
60 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
61 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
62 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
63 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
64 #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
65 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
66 #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
67 #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
68
69 /****************************\
70 GENERIC DRIVER DEFINITIONS
71 \****************************/
72
73 #define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
74
75 #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
76 printk(_level "ath5k %s: " _fmt, \
77 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
78 ##__VA_ARGS__)
79
80 #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
81 if (net_ratelimit()) \
82 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
83 } while (0)
84
85 #define ATH5K_INFO(_sc, _fmt, ...) \
86 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
87
88 #define ATH5K_WARN(_sc, _fmt, ...) \
89 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
90
91 #define ATH5K_ERR(_sc, _fmt, ...) \
92 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
93
94 /*
95 * AR5K REGISTER ACCESS
96 */
97
98 /* Some macros to read/write fields */
99
100 /* First shift, then mask */
101 #define AR5K_REG_SM(_val, _flags) \
102 (((_val) << _flags##_S) & (_flags))
103
104 /* First mask, then shift */
105 #define AR5K_REG_MS(_val, _flags) \
106 (((_val) & (_flags)) >> _flags##_S)
107
108 /* Some registers can hold multiple values of interest. For this
109 * reason when we want to write to these registers we must first
110 * retrieve the values which we do not want to clear (lets call this
111 * old_data) and then set the register with this and our new_value:
112 * ( old_data | new_value) */
113 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
114 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
115 (((_val) << _flags##_S) & (_flags)), _reg)
116
117 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
118 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
119 (_mask)) | (_flags), _reg)
120
121 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
122 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
123
124 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
125 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
126
127 /* Access to PHY registers */
128 #define AR5K_PHY_READ(ah, _reg) \
129 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
130
131 #define AR5K_PHY_WRITE(ah, _reg, _val) \
132 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
133
134 /* Access QCU registers per queue */
135 #define AR5K_REG_READ_Q(ah, _reg, _queue) \
136 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
137
138 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
139 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
140
141 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
142 _reg |= 1 << _queue; \
143 } while (0)
144
145 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
146 _reg &= ~(1 << _queue); \
147 } while (0)
148
149 /* Used while writing initvals */
150 #define AR5K_REG_WAIT(_i) do { \
151 if (_i % 64) \
152 udelay(1); \
153 } while (0)
154
155 /* Register dumps are done per operation mode */
156 #define AR5K_INI_RFGAIN_5GHZ 0
157 #define AR5K_INI_RFGAIN_2GHZ 1
158
159 /* TODO: Clean this up */
160 #define AR5K_INI_VAL_11A 0
161 #define AR5K_INI_VAL_11A_TURBO 1
162 #define AR5K_INI_VAL_11B 2
163 #define AR5K_INI_VAL_11G 3
164 #define AR5K_INI_VAL_11G_TURBO 4
165 #define AR5K_INI_VAL_XR 0
166 #define AR5K_INI_VAL_MAX 5
167
168 /* Used for BSSID etc manipulation */
169 #define AR5K_LOW_ID(_a)( \
170 (_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
171 )
172
173 #define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8)
174
175 /*
176 * Some tuneable values (these should be changeable by the user)
177 * TODO: Make use of them and add more options OR use debug/configfs
178 */
179 #define AR5K_TUNE_DMA_BEACON_RESP 2
180 #define AR5K_TUNE_SW_BEACON_RESP 10
181 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
182 #define AR5K_TUNE_RADAR_ALERT false
183 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1
184 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
185 #define AR5K_TUNE_REGISTER_TIMEOUT 20000
186 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
187 * be the max value. */
188 #define AR5K_TUNE_RSSI_THRES 129
189 /* This must be set when setting the RSSI threshold otherwise it can
190 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
191 * the BMISS_THRES will be seen as 0, seems harware doesn't keep
192 * track of it. Max value depends on harware. For AR5210 this is just 7.
193 * For AR5211+ this seems to be up to 255. */
194 #define AR5K_TUNE_BMISS_THRES 7
195 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000
196 #define AR5K_TUNE_BEACON_INTERVAL 100
197 #define AR5K_TUNE_AIFS 2
198 #define AR5K_TUNE_AIFS_11B 2
199 #define AR5K_TUNE_AIFS_XR 0
200 #define AR5K_TUNE_CWMIN 15
201 #define AR5K_TUNE_CWMIN_11B 31
202 #define AR5K_TUNE_CWMIN_XR 3
203 #define AR5K_TUNE_CWMAX 1023
204 #define AR5K_TUNE_CWMAX_11B 1023
205 #define AR5K_TUNE_CWMAX_XR 7
206 #define AR5K_TUNE_NOISE_FLOOR -72
207 #define AR5K_TUNE_MAX_TXPOWER 63
208 #define AR5K_TUNE_DEFAULT_TXPOWER 25
209 #define AR5K_TUNE_TPC_TXPOWER false
210 #define AR5K_TUNE_HWTXTRIES 4
211
212 #define AR5K_INIT_CARR_SENSE_EN 1
213
214 /*Swap RX/TX Descriptor for big endian archs*/
215 #if defined(__BIG_ENDIAN)
216 #define AR5K_INIT_CFG ( \
217 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
218 )
219 #else
220 #define AR5K_INIT_CFG 0x00000000
221 #endif
222
223 /* Initial values */
224 #define AR5K_INIT_CYCRSSI_THR1 2
225 #define AR5K_INIT_TX_LATENCY 502
226 #define AR5K_INIT_USEC 39
227 #define AR5K_INIT_USEC_TURBO 79
228 #define AR5K_INIT_USEC_32 31
229 #define AR5K_INIT_SLOT_TIME 396
230 #define AR5K_INIT_SLOT_TIME_TURBO 480
231 #define AR5K_INIT_ACK_CTS_TIMEOUT 1024
232 #define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
233 #define AR5K_INIT_PROG_IFS 920
234 #define AR5K_INIT_PROG_IFS_TURBO 960
235 #define AR5K_INIT_EIFS 3440
236 #define AR5K_INIT_EIFS_TURBO 6880
237 #define AR5K_INIT_SIFS 560
238 #define AR5K_INIT_SIFS_TURBO 480
239 #define AR5K_INIT_SH_RETRY 10
240 #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
241 #define AR5K_INIT_SSH_RETRY 32
242 #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
243 #define AR5K_INIT_TX_RETRY 10
244
245 #define AR5K_INIT_TRANSMIT_LATENCY ( \
246 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
247 (AR5K_INIT_USEC) \
248 )
249 #define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
250 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
251 (AR5K_INIT_USEC_TURBO) \
252 )
253 #define AR5K_INIT_PROTO_TIME_CNTRL ( \
254 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
255 (AR5K_INIT_PROG_IFS) \
256 )
257 #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
258 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
259 (AR5K_INIT_PROG_IFS_TURBO) \
260 )
261
262 /* token to use for aifs, cwmin, cwmax in MadWiFi */
263 #define AR5K_TXQ_USEDEFAULT ((u32) -1)
264
265 /* GENERIC CHIPSET DEFINITIONS */
266
267 /* MAC Chips */
268 enum ath5k_version {
269 AR5K_AR5210 = 0,
270 AR5K_AR5211 = 1,
271 AR5K_AR5212 = 2,
272 };
273
274 /* PHY Chips */
275 enum ath5k_radio {
276 AR5K_RF5110 = 0,
277 AR5K_RF5111 = 1,
278 AR5K_RF5112 = 2,
279 AR5K_RF2413 = 3,
280 AR5K_RF5413 = 4,
281 AR5K_RF2316 = 5,
282 AR5K_RF2317 = 6,
283 AR5K_RF2425 = 7,
284 };
285
286 /*
287 * Common silicon revision/version values
288 */
289
290 enum ath5k_srev_type {
291 AR5K_VERSION_MAC,
292 AR5K_VERSION_RAD,
293 };
294
295 struct ath5k_srev_name {
296 const char *sr_name;
297 enum ath5k_srev_type sr_type;
298 u_int sr_val;
299 };
300
301 #define AR5K_SREV_UNKNOWN 0xffff
302
303 #define AR5K_SREV_AR5210 0x00 /* Crete */
304 #define AR5K_SREV_AR5311 0x10 /* Maui 1 */
305 #define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
306 #define AR5K_SREV_AR5311B 0x30 /* Spirit */
307 #define AR5K_SREV_AR5211 0x40 /* Oahu */
308 #define AR5K_SREV_AR5212 0x50 /* Venice */
309 #define AR5K_SREV_AR5212_V4 0x54 /* ??? */
310 #define AR5K_SREV_AR5213 0x55 /* ??? */
311 #define AR5K_SREV_AR5213A 0x59 /* Hainan */
312 #define AR5K_SREV_AR2413 0x78 /* Griffin lite */
313 #define AR5K_SREV_AR2414 0x70 /* Griffin */
314 #define AR5K_SREV_AR5424 0x90 /* Condor */
315 #define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
316 #define AR5K_SREV_AR5414 0xa0 /* Eagle */
317 #define AR5K_SREV_AR2415 0xb0 /* Talon */
318 #define AR5K_SREV_AR5416 0xc0 /* PCI-E */
319 #define AR5K_SREV_AR5418 0xca /* PCI-E */
320 #define AR5K_SREV_AR2425 0xe0 /* Swan */
321 #define AR5K_SREV_AR2417 0xf0 /* Nala */
322
323 #define AR5K_SREV_RAD_5110 0x00
324 #define AR5K_SREV_RAD_5111 0x10
325 #define AR5K_SREV_RAD_5111A 0x15
326 #define AR5K_SREV_RAD_2111 0x20
327 #define AR5K_SREV_RAD_5112 0x30
328 #define AR5K_SREV_RAD_5112A 0x35
329 #define AR5K_SREV_RAD_5112B 0x36
330 #define AR5K_SREV_RAD_2112 0x40
331 #define AR5K_SREV_RAD_2112A 0x45
332 #define AR5K_SREV_RAD_2112B 0x46
333 #define AR5K_SREV_RAD_2413 0x50
334 #define AR5K_SREV_RAD_5413 0x60
335 #define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
336 #define AR5K_SREV_RAD_2317 0x80
337 #define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
338 #define AR5K_SREV_RAD_2425 0xa2
339 #define AR5K_SREV_RAD_5133 0xc0
340
341 #define AR5K_SREV_PHY_5211 0x30
342 #define AR5K_SREV_PHY_5212 0x41
343 #define AR5K_SREV_PHY_5212A 0x42
344 #define AR5K_SREV_PHY_5212B 0x43
345 #define AR5K_SREV_PHY_2413 0x45
346 #define AR5K_SREV_PHY_5413 0x61
347 #define AR5K_SREV_PHY_2425 0x70
348
349 /* IEEE defs */
350 #define IEEE80211_MAX_LEN 2500
351
352 /* TODO add support to mac80211 for vendor-specific rates and modes */
353
354 /*
355 * Some of this information is based on Documentation from:
356 *
357 * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
358 *
359 * Modulation for Atheros' eXtended Range - range enhancing extension that is
360 * supposed to double the distance an Atheros client device can keep a
361 * connection with an Atheros access point. This is achieved by increasing
362 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
363 * the 802.11 specifications demand. In addition, new (proprietary) data rates
364 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
365 *
366 * Please note that can you either use XR or TURBO but you cannot use both,
367 * they are exclusive.
368 *
369 */
370 #define MODULATION_XR 0x00000200
371 /*
372 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
373 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
374 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
375 * channels. To use this feature your Access Point must also suport it.
376 * There is also a distinction between "static" and "dynamic" turbo modes:
377 *
378 * - Static: is the dumb version: devices set to this mode stick to it until
379 * the mode is turned off.
380 * - Dynamic: is the intelligent version, the network decides itself if it
381 * is ok to use turbo. As soon as traffic is detected on adjacent channels
382 * (which would get used in turbo mode), or when a non-turbo station joins
383 * the network, turbo mode won't be used until the situation changes again.
384 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
385 * monitors the used radio band in order to decide whether turbo mode may
386 * be used or not.
387 *
388 * This article claims Super G sticks to bonding of channels 5 and 6 for
389 * USA:
390 *
391 * http://www.pcworld.com/article/id,113428-page,1/article.html
392 *
393 * The channel bonding seems to be driver specific though. In addition to
394 * deciding what channels will be used, these "Turbo" modes are accomplished
395 * by also enabling the following features:
396 *
397 * - Bursting: allows multiple frames to be sent at once, rather than pausing
398 * after each frame. Bursting is a standards-compliant feature that can be
399 * used with any Access Point.
400 * - Fast frames: increases the amount of information that can be sent per
401 * frame, also resulting in a reduction of transmission overhead. It is a
402 * proprietary feature that needs to be supported by the Access Point.
403 * - Compression: data frames are compressed in real time using a Lempel Ziv
404 * algorithm. This is done transparently. Once this feature is enabled,
405 * compression and decompression takes place inside the chipset, without
406 * putting additional load on the host CPU.
407 *
408 */
409 #define MODULATION_TURBO 0x00000080
410
411 enum ath5k_driver_mode {
412 AR5K_MODE_11A = 0,
413 AR5K_MODE_11A_TURBO = 1,
414 AR5K_MODE_11B = 2,
415 AR5K_MODE_11G = 3,
416 AR5K_MODE_11G_TURBO = 4,
417 AR5K_MODE_XR = 0,
418 AR5K_MODE_MAX = 5
419 };
420
421 enum ath5k_ant_mode {
422 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */
423 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */
424 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */
425 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */
426 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */
427 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */
428 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */
429 AR5K_ANTMODE_MAX,
430 };
431
432
433 /****************\
434 TX DEFINITIONS
435 \****************/
436
437 /*
438 * TX Status descriptor
439 */
440 struct ath5k_tx_status {
441 u16 ts_seqnum;
442 u16 ts_tstamp;
443 u8 ts_status;
444 u8 ts_rate[4];
445 u8 ts_retry[4];
446 u8 ts_final_idx;
447 s8 ts_rssi;
448 u8 ts_shortretry;
449 u8 ts_longretry;
450 u8 ts_virtcol;
451 u8 ts_antenna;
452 };
453
454 #define AR5K_TXSTAT_ALTRATE 0x80
455 #define AR5K_TXERR_XRETRY 0x01
456 #define AR5K_TXERR_FILT 0x02
457 #define AR5K_TXERR_FIFO 0x04
458
459 /**
460 * enum ath5k_tx_queue - Queue types used to classify tx queues.
461 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
462 * @AR5K_TX_QUEUE_DATA: A normal data queue
463 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
464 * @AR5K_TX_QUEUE_BEACON: The beacon queue
465 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
466 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
467 */
468 enum ath5k_tx_queue {
469 AR5K_TX_QUEUE_INACTIVE = 0,
470 AR5K_TX_QUEUE_DATA,
471 AR5K_TX_QUEUE_XR_DATA,
472 AR5K_TX_QUEUE_BEACON,
473 AR5K_TX_QUEUE_CAB,
474 AR5K_TX_QUEUE_UAPSD,
475 };
476
477 #define AR5K_NUM_TX_QUEUES 10
478 #define AR5K_NUM_TX_QUEUES_NOQCU 2
479
480 /*
481 * Queue syb-types to classify normal data queues.
482 * These are the 4 Access Categories as defined in
483 * WME spec. 0 is the lowest priority and 4 is the
484 * highest. Normal data that hasn't been classified
485 * goes to the Best Effort AC.
486 */
487 enum ath5k_tx_queue_subtype {
488 AR5K_WME_AC_BK = 0, /*Background traffic*/
489 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/
490 AR5K_WME_AC_VI, /*Video traffic*/
491 AR5K_WME_AC_VO, /*Voice traffic*/
492 };
493
494 /*
495 * Queue ID numbers as returned by the hw functions, each number
496 * represents a hw queue. If hw does not support hw queues
497 * (eg 5210) all data goes in one queue. These match
498 * d80211 definitions (net80211/MadWiFi don't use them).
499 */
500 enum ath5k_tx_queue_id {
501 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
502 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
503 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
504 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/
505 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
506 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
507 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
508 AR5K_TX_QUEUE_ID_UAPSD = 8,
509 AR5K_TX_QUEUE_ID_XR_DATA = 9,
510 };
511
512 /*
513 * Flags to set hw queue's parameters...
514 */
515 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
516 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
517 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
518 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
519 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
520 #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */
521 #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */
522 #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
523 #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
524 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
525 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
526 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
527 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
528 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
529
530 /*
531 * A struct to hold tx queue's parameters
532 */
533 struct ath5k_txq_info {
534 enum ath5k_tx_queue tqi_type;
535 enum ath5k_tx_queue_subtype tqi_subtype;
536 u16 tqi_flags; /* Tx queue flags (see above) */
537 u32 tqi_aifs; /* Arbitrated Interframe Space */
538 s32 tqi_cw_min; /* Minimum Contention Window */
539 s32 tqi_cw_max; /* Maximum Contention Window */
540 u32 tqi_cbr_period; /* Constant bit rate period */
541 u32 tqi_cbr_overflow_limit;
542 u32 tqi_burst_time;
543 u32 tqi_ready_time; /* Not used */
544 };
545
546 /*
547 * Transmit packet types.
548 * used on tx control descriptor
549 * TODO: Use them inside base.c corectly
550 */
551 enum ath5k_pkt_type {
552 AR5K_PKT_TYPE_NORMAL = 0,
553 AR5K_PKT_TYPE_ATIM = 1,
554 AR5K_PKT_TYPE_PSPOLL = 2,
555 AR5K_PKT_TYPE_BEACON = 3,
556 AR5K_PKT_TYPE_PROBE_RESP = 4,
557 AR5K_PKT_TYPE_PIFS = 5,
558 };
559
560 /*
561 * TX power and TPC settings
562 */
563 #define AR5K_TXPOWER_OFDM(_r, _v) ( \
564 ((0 & 1) << ((_v) + 6)) | \
565 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
566 )
567
568 #define AR5K_TXPOWER_CCK(_r, _v) ( \
569 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
570 )
571
572 /*
573 * DMA size definitions (2^n+2)
574 */
575 enum ath5k_dmasize {
576 AR5K_DMASIZE_4B = 0,
577 AR5K_DMASIZE_8B,
578 AR5K_DMASIZE_16B,
579 AR5K_DMASIZE_32B,
580 AR5K_DMASIZE_64B,
581 AR5K_DMASIZE_128B,
582 AR5K_DMASIZE_256B,
583 AR5K_DMASIZE_512B
584 };
585
586
587 /****************\
588 RX DEFINITIONS
589 \****************/
590
591 /*
592 * RX Status descriptor
593 */
594 struct ath5k_rx_status {
595 u16 rs_datalen;
596 u16 rs_tstamp;
597 u8 rs_status;
598 u8 rs_phyerr;
599 s8 rs_rssi;
600 u8 rs_keyix;
601 u8 rs_rate;
602 u8 rs_antenna;
603 u8 rs_more;
604 };
605
606 #define AR5K_RXERR_CRC 0x01
607 #define AR5K_RXERR_PHY 0x02
608 #define AR5K_RXERR_FIFO 0x04
609 #define AR5K_RXERR_DECRYPT 0x08
610 #define AR5K_RXERR_MIC 0x10
611 #define AR5K_RXKEYIX_INVALID ((u8) - 1)
612 #define AR5K_TXKEYIX_INVALID ((u32) - 1)
613
614
615 /**************************\
616 BEACON TIMERS DEFINITIONS
617 \**************************/
618
619 #define AR5K_BEACON_PERIOD 0x0000ffff
620 #define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
621 #define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
622
623 #if 0
624 /**
625 * struct ath5k_beacon_state - Per-station beacon timer state.
626 * @bs_interval: in TU's, can also include the above flags
627 * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
628 * Point Coordination Function capable AP
629 */
630 struct ath5k_beacon_state {
631 u32 bs_next_beacon;
632 u32 bs_next_dtim;
633 u32 bs_interval;
634 u8 bs_dtim_period;
635 u8 bs_cfp_period;
636 u16 bs_cfp_max_duration;
637 u16 bs_cfp_du_remain;
638 u16 bs_tim_offset;
639 u16 bs_sleep_duration;
640 u16 bs_bmiss_threshold;
641 u32 bs_cfp_next;
642 };
643 #endif
644
645
646 /*
647 * TSF to TU conversion:
648 *
649 * TSF is a 64bit value in usec (microseconds).
650 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
651 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
652 */
653 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
654
655
656 /*******************************\
657 GAIN OPTIMIZATION DEFINITIONS
658 \*******************************/
659
660 enum ath5k_rfgain {
661 AR5K_RFGAIN_INACTIVE = 0,
662 AR5K_RFGAIN_ACTIVE,
663 AR5K_RFGAIN_READ_REQUESTED,
664 AR5K_RFGAIN_NEED_CHANGE,
665 };
666
667 struct ath5k_gain {
668 u8 g_step_idx;
669 u8 g_current;
670 u8 g_target;
671 u8 g_low;
672 u8 g_high;
673 u8 g_f_corr;
674 u8 g_state;
675 };
676
677 /********************\
678 COMMON DEFINITIONS
679 \********************/
680
681 #define AR5K_SLOT_TIME_9 396
682 #define AR5K_SLOT_TIME_20 880
683 #define AR5K_SLOT_TIME_MAX 0xffff
684
685 /* channel_flags */
686 #define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
687 #define CHANNEL_TURBO 0x0010 /* Turbo Channel */
688 #define CHANNEL_CCK 0x0020 /* CCK channel */
689 #define CHANNEL_OFDM 0x0040 /* OFDM channel */
690 #define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
691 #define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
692 #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
693 #define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
694 #define CHANNEL_XR 0x0800 /* XR channel */
695
696 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
697 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
698 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
699 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
700 #define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
701 #define CHANNEL_108A CHANNEL_T
702 #define CHANNEL_108G CHANNEL_TG
703 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
704
705 #define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
706 CHANNEL_TURBO)
707
708 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO)
709 #define CHANNEL_MODES CHANNEL_ALL
710
711 /*
712 * Used internaly for reset_tx_queue).
713 * Also see struct struct ieee80211_channel.
714 */
715 #define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0)
716 #define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0)
717
718 /*
719 * The following structure is used to map 2GHz channels to
720 * 5GHz Atheros channels.
721 * TODO: Clean up
722 */
723 struct ath5k_athchan_2ghz {
724 u32 a2_flags;
725 u16 a2_athchan;
726 };
727
728
729 /******************\
730 RATE DEFINITIONS
731 \******************/
732
733 /**
734 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
735 *
736 * The rate code is used to get the RX rate or set the TX rate on the
737 * hardware descriptors. It is also used for internal modulation control
738 * and settings.
739 *
740 * This is the hardware rate map we are aware of:
741 *
742 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
743 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
744 *
745 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
746 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
747 *
748 * rate_code 17 18 19 20 21 22 23 24
749 * rate_kbps ? ? ? ? ? ? ? 11000
750 *
751 * rate_code 25 26 27 28 29 30 31 32
752 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
753 *
754 * "S" indicates CCK rates with short preamble.
755 *
756 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
757 * lowest 4 bits, so they are the same as below with a 0xF mask.
758 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
759 * We handle this in ath5k_setup_bands().
760 */
761 #define AR5K_MAX_RATES 32
762
763 /* B */
764 #define ATH5K_RATE_CODE_1M 0x1B
765 #define ATH5K_RATE_CODE_2M 0x1A
766 #define ATH5K_RATE_CODE_5_5M 0x19
767 #define ATH5K_RATE_CODE_11M 0x18
768 /* A and G */
769 #define ATH5K_RATE_CODE_6M 0x0B
770 #define ATH5K_RATE_CODE_9M 0x0F
771 #define ATH5K_RATE_CODE_12M 0x0A
772 #define ATH5K_RATE_CODE_18M 0x0E
773 #define ATH5K_RATE_CODE_24M 0x09
774 #define ATH5K_RATE_CODE_36M 0x0D
775 #define ATH5K_RATE_CODE_48M 0x08
776 #define ATH5K_RATE_CODE_54M 0x0C
777 /* XR */
778 #define ATH5K_RATE_CODE_XR_500K 0x07
779 #define ATH5K_RATE_CODE_XR_1M 0x02
780 #define ATH5K_RATE_CODE_XR_2M 0x06
781 #define ATH5K_RATE_CODE_XR_3M 0x01
782
783 /* adding this flag to rate_code enables short preamble */
784 #define AR5K_SET_SHORT_PREAMBLE 0x04
785
786 /*
787 * Crypto definitions
788 */
789
790 #define AR5K_KEYCACHE_SIZE 8
791
792 /***********************\
793 HW RELATED DEFINITIONS
794 \***********************/
795
796 /*
797 * Misc definitions
798 */
799 #define AR5K_RSSI_EP_MULTIPLIER (1<<7)
800
801 #define AR5K_ASSERT_ENTRY(_e, _s) do { \
802 if (_e >= _s) \
803 return (false); \
804 } while (0)
805
806 /*
807 * Hardware interrupt abstraction
808 */
809
810 /**
811 * enum ath5k_int - Hardware interrupt masks helpers
812 *
813 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
814 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
815 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
816 * @AR5K_INT_RXNOFRM: No frame received (?)
817 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
818 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
819 * LinkPtr is NULL. For more details, refer to:
820 * http://www.freepatentsonline.com/20030225739.html
821 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
822 * Note that Rx overrun is not always fatal, on some chips we can continue
823 * operation without reseting the card, that's why int_fatal is not
824 * common for all chips.
825 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
826 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
827 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
828 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
829 * We currently do increments on interrupt by
830 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
831 * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
832 * checked. We should do this with ath5k_hw_update_mib_counters() but
833 * it seems we should also then do some noise immunity work.
834 * @AR5K_INT_RXPHY: RX PHY Error
835 * @AR5K_INT_RXKCM: RX Key cache miss
836 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
837 * beacon that must be handled in software. The alternative is if you
838 * have VEOL support, in that case you let the hardware deal with things.
839 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
840 * beacons from the AP have associated with, we should probably try to
841 * reassociate. When in IBSS mode this might mean we have not received
842 * any beacons from any local stations. Note that every station in an
843 * IBSS schedules to send beacons at the Target Beacon Transmission Time
844 * (TBTT) with a random backoff.
845 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
846 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
847 * until properly handled
848 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
849 * errors. These types of errors we can enable seem to be of type
850 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
851 * @AR5K_INT_GLOBAL: Used to clear and set the IER
852 * @AR5K_INT_NOCARD: signals the card has been removed
853 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
854 * bit value
855 *
856 * These are mapped to take advantage of some common bits
857 * between the MACs, to be able to set intr properties
858 * easier. Some of them are not used yet inside hw.c. Most map
859 * to the respective hw interrupt value as they are common amogst different
860 * MACs.
861 */
862 enum ath5k_int {
863 AR5K_INT_RXOK = 0x00000001,
864 AR5K_INT_RXDESC = 0x00000002,
865 AR5K_INT_RXERR = 0x00000004,
866 AR5K_INT_RXNOFRM = 0x00000008,
867 AR5K_INT_RXEOL = 0x00000010,
868 AR5K_INT_RXORN = 0x00000020,
869 AR5K_INT_TXOK = 0x00000040,
870 AR5K_INT_TXDESC = 0x00000080,
871 AR5K_INT_TXERR = 0x00000100,
872 AR5K_INT_TXNOFRM = 0x00000200,
873 AR5K_INT_TXEOL = 0x00000400,
874 AR5K_INT_TXURN = 0x00000800,
875 AR5K_INT_MIB = 0x00001000,
876 AR5K_INT_SWI = 0x00002000,
877 AR5K_INT_RXPHY = 0x00004000,
878 AR5K_INT_RXKCM = 0x00008000,
879 AR5K_INT_SWBA = 0x00010000,
880 AR5K_INT_BRSSI = 0x00020000,
881 AR5K_INT_BMISS = 0x00040000,
882 AR5K_INT_FATAL = 0x00080000, /* Non common */
883 AR5K_INT_BNR = 0x00100000, /* Non common */
884 AR5K_INT_TIM = 0x00200000, /* Non common */
885 AR5K_INT_DTIM = 0x00400000, /* Non common */
886 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
887 AR5K_INT_GPIO = 0x01000000,
888 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
889 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
890 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */
891 AR5K_INT_QCBRORN = 0x10000000, /* Non common */
892 AR5K_INT_QCBRURN = 0x20000000, /* Non common */
893 AR5K_INT_QTRIG = 0x40000000, /* Non common */
894 AR5K_INT_GLOBAL = 0x80000000,
895
896 AR5K_INT_COMMON = AR5K_INT_RXOK
897 | AR5K_INT_RXDESC
898 | AR5K_INT_RXERR
899 | AR5K_INT_RXNOFRM
900 | AR5K_INT_RXEOL
901 | AR5K_INT_RXORN
902 | AR5K_INT_TXOK
903 | AR5K_INT_TXDESC
904 | AR5K_INT_TXERR
905 | AR5K_INT_TXNOFRM
906 | AR5K_INT_TXEOL
907 | AR5K_INT_TXURN
908 | AR5K_INT_MIB
909 | AR5K_INT_SWI
910 | AR5K_INT_RXPHY
911 | AR5K_INT_RXKCM
912 | AR5K_INT_SWBA
913 | AR5K_INT_BRSSI
914 | AR5K_INT_BMISS
915 | AR5K_INT_GPIO
916 | AR5K_INT_GLOBAL,
917
918 AR5K_INT_NOCARD = 0xffffffff
919 };
920
921 /* Software interrupts used for calibration */
922 enum ath5k_software_interrupt {
923 AR5K_SWI_FULL_CALIBRATION = 0x01,
924 AR5K_SWI_SHORT_CALIBRATION = 0x02,
925 };
926
927 /*
928 * Power management
929 */
930 enum ath5k_power_mode {
931 AR5K_PM_UNDEFINED = 0,
932 AR5K_PM_AUTO,
933 AR5K_PM_AWAKE,
934 AR5K_PM_FULL_SLEEP,
935 AR5K_PM_NETWORK_SLEEP,
936 };
937
938 /*
939 * These match net80211 definitions (not used in
940 * mac80211).
941 * TODO: Clean this up
942 */
943 #define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
944 #define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
945 #define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
946 #define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
947 #define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
948
949 /* GPIO-controlled software LED */
950 #define AR5K_SOFTLED_PIN 0
951 #define AR5K_SOFTLED_ON 0
952 #define AR5K_SOFTLED_OFF 1
953
954 /*
955 * Chipset capabilities -see ath5k_hw_get_capability-
956 * get_capability function is not yet fully implemented
957 * in ath5k so most of these don't work yet...
958 * TODO: Implement these & merge with _TUNE_ stuff above
959 */
960 enum ath5k_capability_type {
961 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
962 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */
963 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
964 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
965 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
966 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */
967 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
968 AR5K_CAP_COMPRESSION = 8, /* Supports compression */
969 AR5K_CAP_BURST = 9, /* Supports packet bursting */
970 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
971 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */
972 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */
973 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
974 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */
975 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
976 AR5K_CAP_XR = 16, /* Supports XR mode */
977 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */
978 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */
979 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */
980 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
981 };
982
983
984 /* XXX: we *may* move cap_range stuff to struct wiphy */
985 struct ath5k_capabilities {
986 /*
987 * Supported PHY modes
988 * (ie. CHANNEL_A, CHANNEL_B, ...)
989 */
990 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
991
992 /*
993 * Frequency range (without regulation restrictions)
994 */
995 struct {
996 u16 range_2ghz_min;
997 u16 range_2ghz_max;
998 u16 range_5ghz_min;
999 u16 range_5ghz_max;
1000 } cap_range;
1001
1002 /*
1003 * Values stored in the EEPROM (some of them...)
1004 */
1005 struct ath5k_eeprom_info cap_eeprom;
1006
1007 /*
1008 * Queue information
1009 */
1010 struct {
1011 u8 q_tx_num;
1012 } cap_queues;
1013 };
1014
1015
1016 /***************************************\
1017 HARDWARE ABSTRACTION LAYER STRUCTURE
1018 \***************************************/
1019
1020 /*
1021 * Misc defines
1022 */
1023
1024 #define AR5K_MAX_GPIO 10
1025 #define AR5K_MAX_RF_BANKS 8
1026
1027 /* TODO: Clean up and merge with ath5k_softc */
1028 struct ath5k_hw {
1029 u32 ah_magic;
1030
1031 struct ath5k_softc *ah_sc;
1032 void __iomem *ah_iobase;
1033
1034 enum ath5k_int ah_imr;
1035
1036 enum nl80211_iftype ah_op_mode;
1037 struct ieee80211_channel *ah_current_channel;
1038 bool ah_turbo;
1039 bool ah_calibration;
1040 bool ah_single_chip;
1041 bool ah_aes_support;
1042 bool ah_combined_mic;
1043
1044 enum ath5k_version ah_version;
1045 enum ath5k_radio ah_radio;
1046 u32 ah_phy;
1047 u32 ah_mac_srev;
1048 u16 ah_mac_version;
1049 u16 ah_mac_revision;
1050 u16 ah_phy_revision;
1051 u16 ah_radio_5ghz_revision;
1052 u16 ah_radio_2ghz_revision;
1053
1054 #define ah_modes ah_capabilities.cap_mode
1055 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1056
1057 u32 ah_atim_window;
1058 u32 ah_aifs;
1059 u32 ah_cw_min;
1060 u32 ah_cw_max;
1061 u32 ah_limit_tx_retries;
1062
1063 /* Antenna Control */
1064 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1065 u8 ah_ant_mode;
1066 u8 ah_tx_ant;
1067 u8 ah_def_ant;
1068 bool ah_software_retry;
1069
1070 u8 ah_sta_id[ETH_ALEN];
1071
1072 /* Current BSSID we are trying to assoc to / create.
1073 * This is passed by mac80211 on config_interface() and cached here for
1074 * use in resets */
1075 u8 ah_bssid[ETH_ALEN];
1076 u8 ah_bssid_mask[ETH_ALEN];
1077
1078 int ah_gpio_npins;
1079
1080 struct ath5k_capabilities ah_capabilities;
1081
1082 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1083 u32 ah_txq_status;
1084 u32 ah_txq_imr_txok;
1085 u32 ah_txq_imr_txerr;
1086 u32 ah_txq_imr_txurn;
1087 u32 ah_txq_imr_txdesc;
1088 u32 ah_txq_imr_txeol;
1089 u32 ah_txq_imr_cbrorn;
1090 u32 ah_txq_imr_cbrurn;
1091 u32 ah_txq_imr_qtrig;
1092 u32 ah_txq_imr_nofrm;
1093 u32 ah_txq_isr;
1094 u32 *ah_rf_banks;
1095 size_t ah_rf_banks_size;
1096 size_t ah_rf_regs_count;
1097 struct ath5k_gain ah_gain;
1098 u8 ah_offset[AR5K_MAX_RF_BANKS];
1099
1100
1101 struct {
1102 /* Temporary tables used for interpolation */
1103 u8 tmpL[AR5K_EEPROM_N_PD_GAINS]
1104 [AR5K_EEPROM_POWER_TABLE_SIZE];
1105 u8 tmpR[AR5K_EEPROM_N_PD_GAINS]
1106 [AR5K_EEPROM_POWER_TABLE_SIZE];
1107 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
1108 u16 txp_rates_power_table[AR5K_MAX_RATES];
1109 u8 txp_min_idx;
1110 bool txp_tpc;
1111 /* Values in 0.25dB units */
1112 s16 txp_min_pwr;
1113 s16 txp_max_pwr;
1114 /* Values in 0.5dB units */
1115 s16 txp_offset;
1116 s16 txp_ofdm;
1117 s16 txp_cck_ofdm_gainf_delta;
1118 /* Value in dB units */
1119 s16 txp_cck_ofdm_pwr_delta;
1120 } ah_txpower;
1121
1122 struct {
1123 bool r_enabled;
1124 int r_last_alert;
1125 struct ieee80211_channel r_last_channel;
1126 } ah_radar;
1127
1128 /* noise floor from last periodic calibration */
1129 s32 ah_noise_floor;
1130
1131 /* Calibration timestamp */
1132 unsigned long ah_cal_tstamp;
1133
1134 /* Calibration interval (secs) */
1135 u8 ah_cal_intval;
1136
1137 /* Software interrupt mask */
1138 u8 ah_swi_mask;
1139
1140 /*
1141 * Function pointers
1142 */
1143 int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
1144 u32 size, unsigned int flags);
1145 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1146 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
1147 unsigned int, unsigned int, unsigned int, unsigned int,
1148 unsigned int, unsigned int, unsigned int);
1149 int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1150 unsigned int, unsigned int, unsigned int, unsigned int,
1151 unsigned int, unsigned int);
1152 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1153 struct ath5k_tx_status *);
1154 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1155 struct ath5k_rx_status *);
1156 };
1157
1158 /*
1159 * Prototypes
1160 */
1161
1162 /* Attach/Detach Functions */
1163 extern struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc);
1164 extern void ath5k_hw_detach(struct ath5k_hw *ah);
1165
1166 /* LED functions */
1167 extern int ath5k_init_leds(struct ath5k_softc *sc);
1168 extern void ath5k_led_enable(struct ath5k_softc *sc);
1169 extern void ath5k_led_off(struct ath5k_softc *sc);
1170 extern void ath5k_unregister_leds(struct ath5k_softc *sc);
1171
1172 /* Reset Functions */
1173 extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
1174 extern int ath5k_hw_on_hold(struct ath5k_hw *ah);
1175 extern int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, struct ieee80211_channel *channel, bool change_channel);
1176 /* Power management functions */
1177 extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration);
1178
1179 /* DMA Related Functions */
1180 extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
1181 extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
1182 extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1183 extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1184 extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1185 extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1186 extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1187 extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1188 u32 phys_addr);
1189 extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1190 /* Interrupt handling */
1191 extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1192 extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1193 extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum
1194 ath5k_int new_mask);
1195 extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_low_level_stats *stats);
1196
1197 /* EEPROM access functions */
1198 extern int ath5k_eeprom_init(struct ath5k_hw *ah);
1199 extern void ath5k_eeprom_detach(struct ath5k_hw *ah);
1200 extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
1201 extern bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah);
1202
1203 /* Protocol Control Unit Functions */
1204 extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
1205 /* BSSID Functions */
1206 extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
1207 extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1208 extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id);
1209 extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1210 /* Receive start/stop functions */
1211 extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1212 extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1213 /* RX Filter functions */
1214 extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1215 extern int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
1216 extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
1217 extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1218 extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1219 /* Beacon control functions */
1220 extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah);
1221 extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1222 extern void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1223 extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1224 extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1225 #if 0
1226 extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct ath5k_beacon_state *state);
1227 extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
1228 extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
1229 #endif
1230 /* ACK bit rate */
1231 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
1232 /* ACK/CTS Timeouts */
1233 extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
1234 extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
1235 extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
1236 extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
1237 /* Key table (WEP) functions */
1238 extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
1239 extern int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry);
1240 extern int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac);
1241 extern int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac);
1242
1243 /* Queue Control Unit, DFS Control Unit Functions */
1244 extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info);
1245 extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1246 const struct ath5k_txq_info *queue_info);
1247 extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1248 enum ath5k_tx_queue queue_type,
1249 struct ath5k_txq_info *queue_info);
1250 extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1251 extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1252 extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1253 extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah);
1254 extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
1255
1256 /* Hardware Descriptor Functions */
1257 extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1258
1259 /* GPIO Functions */
1260 extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1261 extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1262 extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1263 extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1264 extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1265 extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
1266
1267 /* rfkill Functions */
1268 extern void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1269 extern void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
1270
1271 /* Misc functions */
1272 int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
1273 extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
1274 extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1275 extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
1276
1277 /* Initial register settings functions */
1278 extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
1279
1280 /* Initialize RF */
1281 extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
1282 struct ieee80211_channel *channel,
1283 unsigned int mode);
1284 extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
1285 extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1286 extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
1287 /* PHY/RF channel functions */
1288 extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1289 extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1290 /* PHY calibration */
1291 extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1292 extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
1293 extern void ath5k_hw_calibration_poll(struct ath5k_hw *ah);
1294 /* Spur mitigation */
1295 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1296 struct ieee80211_channel *channel);
1297 void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1298 struct ieee80211_channel *channel);
1299 /* Misc PHY functions */
1300 extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1301 extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1302 /* Antenna control */
1303 extern void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
1304 extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant);
1305 extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
1306 /* TX power setup */
1307 extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, u8 ee_mode, u8 txpower);
1308 extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
1309
1310 /*
1311 * Functions used internaly
1312 */
1313
1314 /*
1315 * Translate usec to hw clock units
1316 * TODO: Half/quarter rate
1317 */
1318 static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
1319 {
1320 return turbo ? (usec * 80) : (usec * 40);
1321 }
1322
1323 /*
1324 * Translate hw clock units to usec
1325 * TODO: Half/quarter rate
1326 */
1327 static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
1328 {
1329 return turbo ? (clock / 80) : (clock / 40);
1330 }
1331
1332 /*
1333 * Read from a register
1334 */
1335 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1336 {
1337 return ioread32(ah->ah_iobase + reg);
1338 }
1339
1340 /*
1341 * Write to a register
1342 */
1343 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1344 {
1345 iowrite32(val, ah->ah_iobase + reg);
1346 }
1347
1348 #if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
1349 /*
1350 * Check if a register write has been completed
1351 */
1352 static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
1353 u32 val, bool is_set)
1354 {
1355 int i;
1356 u32 data;
1357
1358 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
1359 data = ath5k_hw_reg_read(ah, reg);
1360 if (is_set && (data & flag))
1361 break;
1362 else if ((data & flag) == val)
1363 break;
1364 udelay(15);
1365 }
1366
1367 return (i <= 0) ? -EAGAIN : 0;
1368 }
1369 #endif
1370
1371 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1372 {
1373 u32 retval = 0, bit, i;
1374
1375 for (i = 0; i < bits; i++) {
1376 bit = (val >> i) & 1;
1377 retval = (retval << 1) | bit;
1378 }
1379
1380 return retval;
1381 }
1382
1383 static inline int ath5k_pad_size(int hdrlen)
1384 {
1385 return (hdrlen < 24) ? 0 : hdrlen & 3;
1386 }
1387
1388 #endif
Linux with added FPC-III support