drivers/net/wireless/ath/ath9k/eeprom.h

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef EEPROM_H
  18 #define EEPROM_H
  19
  20 #include <net/cfg80211.h>
  21
  22 #define AH_USE_EEPROM   0x1
  23
  24 #ifdef __BIG_ENDIAN
  25 #define AR5416_EEPROM_MAGIC 0x5aa5
  26 #else
  27 #define AR5416_EEPROM_MAGIC 0xa55a
  28 #endif
  29
  30 #define CTRY_DEBUG   0x1ff
  31 #define CTRY_DEFAULT 0
  32
  33 #define AR_EEPROM_EEPCAP_COMPRESS_DIS   0x0001
  34 #define AR_EEPROM_EEPCAP_AES_DIS        0x0002
  35 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS  0x0004
  36 #define AR_EEPROM_EEPCAP_BURST_DIS      0x0008
  37 #define AR_EEPROM_EEPCAP_MAXQCU         0x01F0
  38 #define AR_EEPROM_EEPCAP_MAXQCU_S       4
  39 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN  0x0200
  40 #define AR_EEPROM_EEPCAP_KC_ENTRIES     0xF000
  41 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S   12
  42
  43 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND   0x0040
  44 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN    0x0080
  45 #define AR_EEPROM_EEREGCAP_EN_KK_U2         0x0100
  46 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND    0x0200
  47 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD     0x0400
  48 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A    0x0800
  49
  50 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0  0x4000
  51 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
  52
  53 #define AR5416_EEPROM_MAGIC_OFFSET  0x0
  54 #define AR5416_EEPROM_S             2
  55 #define AR5416_EEPROM_OFFSET        0x2000
  56 #define AR5416_EEPROM_MAX           0xae0
  57
  58 #define AR5416_EEPROM_START_ADDR \
  59         (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
  60
  61 #define SD_NO_CTL               0xE0
  62 #define NO_CTL                  0xff
  63 #define CTL_MODE_M              7
  64 #define CTL_11A                 0
  65 #define CTL_11B                 1
  66 #define CTL_11G                 2
  67 #define CTL_2GHT20              5
  68 #define CTL_5GHT20              6
  69 #define CTL_2GHT40              7
  70 #define CTL_5GHT40              8
  71
  72 #define EXT_ADDITIVE (0x8000)
  73 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  74 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  75 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  76
  77 #define SUB_NUM_CTL_MODES_AT_5G_40 2
  78 #define SUB_NUM_CTL_MODES_AT_2G_40 3
  79
  80 #define INCREASE_MAXPOW_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
  81 #define INCREASE_MAXPOW_BY_THREE_CHAIN   10 /* 10*log10(3)*2 */
  82
  83 /*
  84  * For AR9285 and later chipsets, the following bits are not being programmed
  85  * in EEPROM and so need to be enabled always.
  86  *
  87  * Bit 0: en_fcc_mid
  88  * Bit 1: en_jap_mid
  89  * Bit 2: en_fcc_dfs_ht40
  90  * Bit 3: en_jap_ht40
  91  * Bit 4: en_jap_dfs_ht40
  92  */
  93 #define AR9285_RDEXT_DEFAULT    0x1F
  94
  95 #define AR_EEPROM_MAC(i)        (0x1d+(i))
  96 #define ATH9K_POW_SM(_r, _s)    (((_r) & 0x3f) << (_s))
  97 #define FREQ2FBIN(x, y)         ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
  98 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
  99
 100 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
 101 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
 102                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
 103 #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_10_OR_LATER(ah) && \
 104                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
 105
 106 #define AR_EEPROM_RFSILENT_GPIO_SEL     0x001c
 107 #define AR_EEPROM_RFSILENT_GPIO_SEL_S   2
 108 #define AR_EEPROM_RFSILENT_POLARITY     0x0002
 109 #define AR_EEPROM_RFSILENT_POLARITY_S   1
 110
 111 #define EEP_RFSILENT_ENABLED        0x0001
 112 #define EEP_RFSILENT_ENABLED_S      0
 113 #define EEP_RFSILENT_POLARITY       0x0002
 114 #define EEP_RFSILENT_POLARITY_S     1
 115 #define EEP_RFSILENT_GPIO_SEL       0x001c
 116 #define EEP_RFSILENT_GPIO_SEL_S     2
 117
 118 #define AR5416_OPFLAGS_11A           0x01
 119 #define AR5416_OPFLAGS_11G           0x02
 120 #define AR5416_OPFLAGS_N_5G_HT40     0x04
 121 #define AR5416_OPFLAGS_N_2G_HT40     0x08
 122 #define AR5416_OPFLAGS_N_5G_HT20     0x10
 123 #define AR5416_OPFLAGS_N_2G_HT20     0x20
 124
 125 #define AR5416_EEP_NO_BACK_VER       0x1
 126 #define AR5416_EEP_VER               0xE
 127 #define AR5416_EEP_VER_MINOR_MASK    0x0FFF
 128 #define AR5416_EEP_MINOR_VER_2       0x2
 129 #define AR5416_EEP_MINOR_VER_3       0x3
 130 #define AR5416_EEP_MINOR_VER_7       0x7
 131 #define AR5416_EEP_MINOR_VER_9       0x9
 132 #define AR5416_EEP_MINOR_VER_16      0x10
 133 #define AR5416_EEP_MINOR_VER_17      0x11
 134 #define AR5416_EEP_MINOR_VER_19      0x13
 135 #define AR5416_EEP_MINOR_VER_20      0x14
 136 #define AR5416_EEP_MINOR_VER_22      0x16
 137
 138 #define AR5416_NUM_5G_CAL_PIERS         8
 139 #define AR5416_NUM_2G_CAL_PIERS         4
 140 #define AR5416_NUM_5G_20_TARGET_POWERS  8
 141 #define AR5416_NUM_5G_40_TARGET_POWERS  8
 142 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
 143 #define AR5416_NUM_2G_20_TARGET_POWERS  4
 144 #define AR5416_NUM_2G_40_TARGET_POWERS  4
 145 #define AR5416_NUM_CTLS                 24
 146 #define AR5416_NUM_BAND_EDGES           8
 147 #define AR5416_NUM_PD_GAINS             4
 148 #define AR5416_PD_GAINS_IN_MASK         4
 149 #define AR5416_PD_GAIN_ICEPTS           5
 150 #define AR5416_EEPROM_MODAL_SPURS       5
 151 #define AR5416_MAX_RATE_POWER           63
 152 #define AR5416_NUM_PDADC_VALUES         128
 153 #define AR5416_BCHAN_UNUSED             0xFF
 154 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
 155 #define AR5416_MAX_CHAINS               3
 156 #define AR5416_PWR_TABLE_OFFSET         -5
 157
 158 /* Rx gain type values */
 159 #define AR5416_EEP_RXGAIN_23DB_BACKOFF     0
 160 #define AR5416_EEP_RXGAIN_13DB_BACKOFF     1
 161 #define AR5416_EEP_RXGAIN_ORIG             2
 162
 163 /* Tx gain type values */
 164 #define AR5416_EEP_TXGAIN_ORIGINAL         0
 165 #define AR5416_EEP_TXGAIN_HIGH_POWER       1
 166
 167 #define AR5416_EEP4K_START_LOC                64
 168 #define AR5416_EEP4K_NUM_2G_CAL_PIERS         3
 169 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
 170 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS  3
 171 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS  3
 172 #define AR5416_EEP4K_NUM_CTLS                 12
 173 #define AR5416_EEP4K_NUM_BAND_EDGES           4
 174 #define AR5416_EEP4K_NUM_PD_GAINS             2
 175 #define AR5416_EEP4K_PD_GAINS_IN_MASK         4
 176 #define AR5416_EEP4K_PD_GAIN_ICEPTS           5
 177 #define AR5416_EEP4K_MAX_CHAINS               1
 178
 179 #define AR9280_TX_GAIN_TABLE_SIZE 22
 180
 181 #define AR9287_EEP_VER               0xE
 182 #define AR9287_EEP_VER_MINOR_MASK    0xFFF
 183 #define AR9287_EEP_MINOR_VER_1       0x1
 184 #define AR9287_EEP_MINOR_VER_2       0x2
 185 #define AR9287_EEP_MINOR_VER_3       0x3
 186 #define AR9287_EEP_MINOR_VER         AR9287_EEP_MINOR_VER_3
 187 #define AR9287_EEP_MINOR_VER_b       AR9287_EEP_MINOR_VER
 188 #define AR9287_EEP_NO_BACK_VER       AR9287_EEP_MINOR_VER_1
 189
 190 #define AR9287_EEP_START_LOC            128
 191 #define AR9287_NUM_2G_CAL_PIERS         3
 192 #define AR9287_NUM_2G_CCK_TARGET_POWERS 3
 193 #define AR9287_NUM_2G_20_TARGET_POWERS  3
 194 #define AR9287_NUM_2G_40_TARGET_POWERS  3
 195 #define AR9287_NUM_CTLS                 12
 196 #define AR9287_NUM_BAND_EDGES           4
 197 #define AR9287_NUM_PD_GAINS             4
 198 #define AR9287_PD_GAINS_IN_MASK         4
 199 #define AR9287_PD_GAIN_ICEPTS           1
 200 #define AR9287_EEPROM_MODAL_SPURS       5
 201 #define AR9287_MAX_RATE_POWER           63
 202 #define AR9287_NUM_PDADC_VALUES         128
 203 #define AR9287_NUM_RATES                16
 204 #define AR9287_BCHAN_UNUSED             0xFF
 205 #define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64
 206 #define AR9287_OPFLAGS_11A              0x01
 207 #define AR9287_OPFLAGS_11G              0x02
 208 #define AR9287_OPFLAGS_2G_HT40          0x08
 209 #define AR9287_OPFLAGS_2G_HT20          0x20
 210 #define AR9287_OPFLAGS_5G_HT40          0x04
 211 #define AR9287_OPFLAGS_5G_HT20          0x10
 212 #define AR9287_EEPMISC_BIG_ENDIAN       0x01
 213 #define AR9287_EEPMISC_WOW              0x02
 214 #define AR9287_MAX_CHAINS               2
 215 #define AR9287_ANT_16S                  32
 216 #define AR9287_custdatasize             20
 217
 218 #define AR9287_NUM_ANT_CHAIN_FIELDS     6
 219 #define AR9287_NUM_ANT_COMMON_FIELDS    4
 220 #define AR9287_SIZE_ANT_CHAIN_FIELD     2
 221 #define AR9287_SIZE_ANT_COMMON_FIELD    4
 222 #define AR9287_ANT_CHAIN_MASK           0x3
 223 #define AR9287_ANT_COMMON_MASK          0xf
 224 #define AR9287_CHAIN_0_IDX              0
 225 #define AR9287_CHAIN_1_IDX              1
 226 #define AR9287_DATA_SZ                  32
 227
 228 #define AR9287_PWR_TABLE_OFFSET_DB  -5
 229
 230 #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
 231
 232 enum eeprom_param {
 233         EEP_NFTHRESH_5,
 234         EEP_NFTHRESH_2,
 235         EEP_MAC_MSW,
 236         EEP_MAC_MID,
 237         EEP_MAC_LSW,
 238         EEP_REG_0,
 239         EEP_REG_1,
 240         EEP_OP_CAP,
 241         EEP_OP_MODE,
 242         EEP_RF_SILENT,
 243         EEP_OB_5,
 244         EEP_DB_5,
 245         EEP_OB_2,
 246         EEP_DB_2,
 247         EEP_MINOR_REV,
 248         EEP_TX_MASK,
 249         EEP_RX_MASK,
 250         EEP_RXGAIN_TYPE,
 251         EEP_TXGAIN_TYPE,
 252         EEP_OL_PWRCTRL,
 253         EEP_RC_CHAIN_MASK,
 254         EEP_DAC_HPWR_5G,
 255         EEP_FRAC_N_5G,
 256         EEP_DEV_TYPE,
 257         EEP_TEMPSENSE_SLOPE,
 258         EEP_TEMPSENSE_SLOPE_PAL_ON,
 259         EEP_PWR_TABLE_OFFSET
 260 };
 261
 262 enum ar5416_rates {
 263         rate6mb, rate9mb, rate12mb, rate18mb,
 264         rate24mb, rate36mb, rate48mb, rate54mb,
 265         rate1l, rate2l, rate2s, rate5_5l,
 266         rate5_5s, rate11l, rate11s, rateXr,
 267         rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
 268         rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
 269         rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
 270         rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
 271         rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
 272         Ar5416RateSize
 273 };
 274
 275 enum ath9k_hal_freq_band {
 276         ATH9K_HAL_FREQ_BAND_5GHZ = 0,
 277         ATH9K_HAL_FREQ_BAND_2GHZ = 1
 278 };
 279
 280 struct base_eep_header {
 281         u16 length;
 282         u16 checksum;
 283         u16 version;
 284         u8 opCapFlags;
 285         u8 eepMisc;
 286         u16 regDmn[2];
 287         u8 macAddr[6];
 288         u8 rxMask;
 289         u8 txMask;
 290         u16 rfSilent;
 291         u16 blueToothOptions;
 292         u16 deviceCap;
 293         u32 binBuildNumber;
 294         u8 deviceType;
 295         u8 pwdclkind;
 296         u8 futureBase_1[2];
 297         u8 rxGainType;
 298         u8 dacHiPwrMode_5G;
 299         u8 openLoopPwrCntl;
 300         u8 dacLpMode;
 301         u8 txGainType;
 302         u8 rcChainMask;
 303         u8 desiredScaleCCK;
 304         u8 power_table_offset;
 305         u8 frac_n_5g;
 306         u8 futureBase_3[21];
 307 } __packed;
 308
 309 struct base_eep_header_4k {
 310         u16 length;
 311         u16 checksum;
 312         u16 version;
 313         u8 opCapFlags;
 314         u8 eepMisc;
 315         u16 regDmn[2];
 316         u8 macAddr[6];
 317         u8 rxMask;
 318         u8 txMask;
 319         u16 rfSilent;
 320         u16 blueToothOptions;
 321         u16 deviceCap;
 322         u32 binBuildNumber;
 323         u8 deviceType;
 324         u8 txGainType;
 325 } __packed;
 326
 327
 328 struct spur_chan {
 329         u16 spurChan;
 330         u8 spurRangeLow;
 331         u8 spurRangeHigh;
 332 } __packed;
 333
 334 struct modal_eep_header {
 335         u32 antCtrlChain[AR5416_MAX_CHAINS];
 336         u32 antCtrlCommon;
 337         u8 antennaGainCh[AR5416_MAX_CHAINS];
 338         u8 switchSettling;
 339         u8 txRxAttenCh[AR5416_MAX_CHAINS];
 340         u8 rxTxMarginCh[AR5416_MAX_CHAINS];
 341         u8 adcDesiredSize;
 342         u8 pgaDesiredSize;
 343         u8 xlnaGainCh[AR5416_MAX_CHAINS];
 344         u8 txEndToXpaOff;
 345         u8 txEndToRxOn;
 346         u8 txFrameToXpaOn;
 347         u8 thresh62;
 348         u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
 349         u8 xpdGain;
 350         u8 xpd;
 351         u8 iqCalICh[AR5416_MAX_CHAINS];
 352         u8 iqCalQCh[AR5416_MAX_CHAINS];
 353         u8 pdGainOverlap;
 354         u8 ob;
 355         u8 db;
 356         u8 xpaBiasLvl;
 357         u8 pwrDecreaseFor2Chain;
 358         u8 pwrDecreaseFor3Chain;
 359         u8 txFrameToDataStart;
 360         u8 txFrameToPaOn;
 361         u8 ht40PowerIncForPdadc;
 362         u8 bswAtten[AR5416_MAX_CHAINS];
 363         u8 bswMargin[AR5416_MAX_CHAINS];
 364         u8 swSettleHt40;
 365         u8 xatten2Db[AR5416_MAX_CHAINS];
 366         u8 xatten2Margin[AR5416_MAX_CHAINS];
 367         u8 ob_ch1;
 368         u8 db_ch1;
 369         u8 useAnt1:1,
 370             force_xpaon:1,
 371             local_bias:1,
 372             femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
 373         u8 miscBits;
 374         u16 xpaBiasLvlFreq[3];
 375         u8 futureModal[6];
 376
 377         struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
 378 } __packed;
 379
 380 struct calDataPerFreqOpLoop {
 381         u8 pwrPdg[2][5];
 382         u8 vpdPdg[2][5];
 383         u8 pcdac[2][5];
 384         u8 empty[2][5];
 385 } __packed;
 386
 387 struct modal_eep_4k_header {
 388         u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
 389         u32 antCtrlCommon;
 390         u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
 391         u8 switchSettling;
 392         u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
 393         u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
 394         u8 adcDesiredSize;
 395         u8 pgaDesiredSize;
 396         u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
 397         u8 txEndToXpaOff;
 398         u8 txEndToRxOn;
 399         u8 txFrameToXpaOn;
 400         u8 thresh62;
 401         u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
 402         u8 xpdGain;
 403         u8 xpd;
 404         u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
 405         u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
 406         u8 pdGainOverlap;
 407 #ifdef __BIG_ENDIAN_BITFIELD
 408         u8 ob_1:4, ob_0:4;
 409         u8 db1_1:4, db1_0:4;
 410 #else
 411         u8 ob_0:4, ob_1:4;
 412         u8 db1_0:4, db1_1:4;
 413 #endif
 414         u8 xpaBiasLvl;
 415         u8 txFrameToDataStart;
 416         u8 txFrameToPaOn;
 417         u8 ht40PowerIncForPdadc;
 418         u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
 419         u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
 420         u8 swSettleHt40;
 421         u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
 422         u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
 423 #ifdef __BIG_ENDIAN_BITFIELD
 424         u8 db2_1:4, db2_0:4;
 425 #else
 426         u8 db2_0:4, db2_1:4;
 427 #endif
 428         u8 version;
 429 #ifdef __BIG_ENDIAN_BITFIELD
 430         u8 ob_3:4, ob_2:4;
 431         u8 antdiv_ctl1:4, ob_4:4;
 432         u8 db1_3:4, db1_2:4;
 433         u8 antdiv_ctl2:4, db1_4:4;
 434         u8 db2_2:4, db2_3:4;
 435         u8 reserved:4, db2_4:4;
 436 #else
 437         u8 ob_2:4, ob_3:4;
 438         u8 ob_4:4, antdiv_ctl1:4;
 439         u8 db1_2:4, db1_3:4;
 440         u8 db1_4:4, antdiv_ctl2:4;
 441         u8 db2_2:4, db2_3:4;
 442         u8 db2_4:4, reserved:4;
 443 #endif
 444         u8 futureModal[4];
 445         struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
 446 } __packed;
 447
 448 struct base_eep_ar9287_header {
 449         u16 length;
 450         u16 checksum;
 451         u16 version;
 452         u8 opCapFlags;
 453         u8 eepMisc;
 454         u16 regDmn[2];
 455         u8 macAddr[6];
 456         u8 rxMask;
 457         u8 txMask;
 458         u16 rfSilent;
 459         u16 blueToothOptions;
 460         u16 deviceCap;
 461         u32 binBuildNumber;
 462         u8 deviceType;
 463         u8 openLoopPwrCntl;
 464         int8_t pwrTableOffset;
 465         int8_t tempSensSlope;
 466         int8_t tempSensSlopePalOn;
 467         u8 futureBase[29];
 468 } __packed;
 469
 470 struct modal_eep_ar9287_header {
 471         u32 antCtrlChain[AR9287_MAX_CHAINS];
 472         u32 antCtrlCommon;
 473         int8_t antennaGainCh[AR9287_MAX_CHAINS];
 474         u8 switchSettling;
 475         u8 txRxAttenCh[AR9287_MAX_CHAINS];
 476         u8 rxTxMarginCh[AR9287_MAX_CHAINS];
 477         int8_t adcDesiredSize;
 478         u8 txEndToXpaOff;
 479         u8 txEndToRxOn;
 480         u8 txFrameToXpaOn;
 481         u8 thresh62;
 482         int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
 483         u8 xpdGain;
 484         u8 xpd;
 485         int8_t iqCalICh[AR9287_MAX_CHAINS];
 486         int8_t iqCalQCh[AR9287_MAX_CHAINS];
 487         u8 pdGainOverlap;
 488         u8 xpaBiasLvl;
 489         u8 txFrameToDataStart;
 490         u8 txFrameToPaOn;
 491         u8 ht40PowerIncForPdadc;
 492         u8 bswAtten[AR9287_MAX_CHAINS];
 493         u8 bswMargin[AR9287_MAX_CHAINS];
 494         u8 swSettleHt40;
 495         u8 version;
 496         u8 db1;
 497         u8 db2;
 498         u8 ob_cck;
 499         u8 ob_psk;
 500         u8 ob_qam;
 501         u8 ob_pal_off;
 502         u8 futureModal[30];
 503         struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS];
 504 } __packed;
 505
 506 struct cal_data_per_freq {
 507         u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 508         u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 509 } __packed;
 510
 511 struct cal_data_per_freq_4k {
 512         u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
 513         u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
 514 } __packed;
 515
 516 struct cal_target_power_leg {
 517         u8 bChannel;
 518         u8 tPow2x[4];
 519 } __packed;
 520
 521 struct cal_target_power_ht {
 522         u8 bChannel;
 523         u8 tPow2x[8];
 524 } __packed;
 525
 526
 527 #ifdef __BIG_ENDIAN_BITFIELD
 528 struct cal_ctl_edges {
 529         u8 bChannel;
 530         u8 flag:2, tPower:6;
 531 } __packed;
 532 #else
 533 struct cal_ctl_edges {
 534         u8 bChannel;
 535         u8 tPower:6, flag:2;
 536 } __packed;
 537 #endif
 538
 539 struct cal_data_op_loop_ar9287 {
 540         u8 pwrPdg[2][5];
 541         u8 vpdPdg[2][5];
 542         u8 pcdac[2][5];
 543         u8 empty[2][5];
 544 } __packed;
 545
 546 struct cal_data_per_freq_ar9287 {
 547         u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
 548         u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
 549 } __packed;
 550
 551 union cal_data_per_freq_ar9287_u {
 552         struct cal_data_op_loop_ar9287 calDataOpen;
 553         struct cal_data_per_freq_ar9287 calDataClose;
 554 } __packed;
 555
 556 struct cal_ctl_data_ar9287 {
 557         struct cal_ctl_edges
 558         ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];
 559 } __packed;
 560
 561 struct cal_ctl_data {
 562         struct cal_ctl_edges
 563         ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
 564 } __packed;
 565
 566 struct cal_ctl_data_4k {
 567         struct cal_ctl_edges
 568         ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
 569 } __packed;
 570
 571 struct ar5416_eeprom_def {
 572         struct base_eep_header baseEepHeader;
 573         u8 custData[64];
 574         struct modal_eep_header modalHeader[2];
 575         u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
 576         u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
 577         struct cal_data_per_freq
 578          calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
 579         struct cal_data_per_freq
 580          calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
 581         struct cal_target_power_leg
 582          calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
 583         struct cal_target_power_ht
 584          calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
 585         struct cal_target_power_ht
 586          calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
 587         struct cal_target_power_leg
 588          calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
 589         struct cal_target_power_leg
 590          calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
 591         struct cal_target_power_ht
 592          calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
 593         struct cal_target_power_ht
 594          calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
 595         u8 ctlIndex[AR5416_NUM_CTLS];
 596         struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
 597         u8 padding;
 598 } __packed;
 599
 600 struct ar5416_eeprom_4k {
 601         struct base_eep_header_4k baseEepHeader;
 602         u8 custData[20];
 603         struct modal_eep_4k_header modalHeader;
 604         u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
 605         struct cal_data_per_freq_4k
 606         calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
 607         struct cal_target_power_leg
 608         calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
 609         struct cal_target_power_leg
 610         calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
 611         struct cal_target_power_ht
 612         calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
 613         struct cal_target_power_ht
 614         calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
 615         u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
 616         struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
 617         u8 padding;
 618 } __packed;
 619
 620 struct ar9287_eeprom {
 621         struct base_eep_ar9287_header baseEepHeader;
 622         u8 custData[AR9287_DATA_SZ];
 623         struct modal_eep_ar9287_header modalHeader;
 624         u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
 625         union cal_data_per_freq_ar9287_u
 626         calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
 627         struct cal_target_power_leg
 628         calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
 629         struct cal_target_power_leg
 630         calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
 631         struct cal_target_power_ht
 632         calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
 633         struct cal_target_power_ht
 634         calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
 635         u8 ctlIndex[AR9287_NUM_CTLS];
 636         struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];
 637         u8 padding;
 638 } __packed;
 639
 640 enum reg_ext_bitmap {
 641         REG_EXT_JAPAN_MIDBAND = 1,
 642         REG_EXT_FCC_DFS_HT40 = 2,
 643         REG_EXT_JAPAN_NONDFS_HT40 = 3,
 644         REG_EXT_JAPAN_DFS_HT40 = 4
 645 };
 646
 647 struct ath9k_country_entry {
 648         u16 countryCode;
 649         u16 regDmnEnum;
 650         u16 regDmn5G;
 651         u16 regDmn2G;
 652         u8 isMultidomain;
 653         u8 iso[3];
 654 };
 655
 656 enum ath9k_eep_map {
 657         EEP_MAP_DEFAULT = 0x0,
 658         EEP_MAP_4KBITS,
 659         EEP_MAP_AR9287,
 660         EEP_MAP_MAX
 661 };
 662
 663 struct eeprom_ops {
 664         int (*check_eeprom)(struct ath_hw *hw);
 665         u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
 666         bool (*fill_eeprom)(struct ath_hw *hw);
 667         int (*get_eeprom_ver)(struct ath_hw *hw);
 668         int (*get_eeprom_rev)(struct ath_hw *hw);
 669         u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band);
 670         u16 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
 671                                       struct ath9k_channel *chan);
 672         void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
 673         void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
 674         void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
 675                            u16 cfgCtl, u8 twiceAntennaReduction,
 676                            u8 twiceMaxRegulatoryPower, u8 powerLimit);
 677         u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
 678 };
 679
 680 void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
 681                                u32 shift, u32 val);
 682 int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
 683                              int16_t targetLeft,
 684                              int16_t targetRight);
 685 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
 686                                     u16 *indexL, u16 *indexR);
 687 bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data);
 688 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
 689                              u8 *pVpdList, u16 numIntercepts,
 690                              u8 *pRetVpdList);
 691 void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
 692                                        struct ath9k_channel *chan,
 693                                        struct cal_target_power_leg *powInfo,
 694                                        u16 numChannels,
 695                                        struct cal_target_power_leg *pNewPower,
 696                                        u16 numRates, bool isExtTarget);
 697 void ath9k_hw_get_target_powers(struct ath_hw *ah,
 698                                 struct ath9k_channel *chan,
 699                                 struct cal_target_power_ht *powInfo,
 700                                 u16 numChannels,
 701                                 struct cal_target_power_ht *pNewPower,
 702                                 u16 numRates, bool isHt40Target);
 703 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
 704                                 bool is2GHz, int num_band_edges);
 705 int ath9k_hw_eeprom_init(struct ath_hw *ah);
 706
 707 #define ar5416_get_ntxchains(_txchainmask)                      \
 708         (((_txchainmask >> 2) & 1) +                            \
 709          ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
 710
 711 extern const struct eeprom_ops eep_def_ops;
 712 extern const struct eeprom_ops eep_4k_ops;
 713 extern const struct eeprom_ops eep_AR9287_ops;
 714
 715 #endif /* EEPROM_H */