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x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / eeprom_def.c
blob4071fc91da0a94509b4ba3361da0f26278f89bc2
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "ath9k.h"
18
19 static void ath9k_get_txgain_index(struct ath_hw *ah,
20 struct ath9k_channel *chan,
21 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
22 u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx)
23 {
24 u8 pcdac, i = 0;
25 u16 idxL = 0, idxR = 0, numPiers;
26 bool match;
27 struct chan_centers centers;
28
29 ath9k_hw_get_channel_centers(ah, chan, &centers);
30
31 for (numPiers = 0; numPiers < availPiers; numPiers++)
32 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
33 break;
34
35 match = ath9k_hw_get_lower_upper_index(
36 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
37 calChans, numPiers, &idxL, &idxR);
38 if (match) {
39 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
40 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
41 } else {
42 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
43 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
44 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
45 }
46
47 while (pcdac > ah->originalGain[i] &&
48 i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
49 i++;
50
51 *pcdacIdx = i;
52 return;
53 }
54
55 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
56 u32 initTxGain,
57 int txPower,
58 u8 *pPDADCValues)
59 {
60 u32 i;
61 u32 offset;
62
63 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
64 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
65 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
66 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
67
68 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
69 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
70
71 offset = txPower;
72 for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
73 if (i < offset)
74 pPDADCValues[i] = 0x0;
75 else
76 pPDADCValues[i] = 0xFF;
77 }
78
79 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
80 {
81 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
82 }
83
84 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
85 {
86 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
87 }
88
89 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
90 {
91 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
92 u16 *eep_data = (u16 *)&ah->eeprom.def;
93 int addr, ar5416_eep_start_loc = 0x100;
94
95 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
96 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
97 eep_data)) {
98 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
99 "Unable to read eeprom region\n");
100 return false;
101 }
102 eep_data++;
103 }
104 return true;
105 #undef SIZE_EEPROM_DEF
106 }
107
108 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
109 {
110 struct ar5416_eeprom_def *eep =
111 (struct ar5416_eeprom_def *) &ah->eeprom.def;
112 u16 *eepdata, temp, magic, magic2;
113 u32 sum = 0, el;
114 bool need_swap = false;
115 int i, addr, size;
116
117 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
118 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Reading Magic # failed\n");
119 return false;
120 }
121
122 if (!ath9k_hw_use_flash(ah)) {
123 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
124 "Read Magic = 0x%04X\n", magic);
125
126 if (magic != AR5416_EEPROM_MAGIC) {
127 magic2 = swab16(magic);
128
129 if (magic2 == AR5416_EEPROM_MAGIC) {
130 size = sizeof(struct ar5416_eeprom_def);
131 need_swap = true;
132 eepdata = (u16 *) (&ah->eeprom);
133
134 for (addr = 0; addr < size / sizeof(u16); addr++) {
135 temp = swab16(*eepdata);
136 *eepdata = temp;
137 eepdata++;
138 }
139 } else {
140 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
141 "Invalid EEPROM Magic. "
142 "Endianness mismatch.\n");
143 return -EINVAL;
144 }
145 }
146 }
147
148 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
149 need_swap ? "True" : "False");
150
151 if (need_swap)
152 el = swab16(ah->eeprom.def.baseEepHeader.length);
153 else
154 el = ah->eeprom.def.baseEepHeader.length;
155
156 if (el > sizeof(struct ar5416_eeprom_def))
157 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
158 else
159 el = el / sizeof(u16);
160
161 eepdata = (u16 *)(&ah->eeprom);
162
163 for (i = 0; i < el; i++)
164 sum ^= *eepdata++;
165
166 if (need_swap) {
167 u32 integer, j;
168 u16 word;
169
170 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
171 "EEPROM Endianness is not native.. Changing.\n");
172
173 word = swab16(eep->baseEepHeader.length);
174 eep->baseEepHeader.length = word;
175
176 word = swab16(eep->baseEepHeader.checksum);
177 eep->baseEepHeader.checksum = word;
178
179 word = swab16(eep->baseEepHeader.version);
180 eep->baseEepHeader.version = word;
181
182 word = swab16(eep->baseEepHeader.regDmn[0]);
183 eep->baseEepHeader.regDmn[0] = word;
184
185 word = swab16(eep->baseEepHeader.regDmn[1]);
186 eep->baseEepHeader.regDmn[1] = word;
187
188 word = swab16(eep->baseEepHeader.rfSilent);
189 eep->baseEepHeader.rfSilent = word;
190
191 word = swab16(eep->baseEepHeader.blueToothOptions);
192 eep->baseEepHeader.blueToothOptions = word;
193
194 word = swab16(eep->baseEepHeader.deviceCap);
195 eep->baseEepHeader.deviceCap = word;
196
197 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
198 struct modal_eep_header *pModal =
199 &eep->modalHeader[j];
200 integer = swab32(pModal->antCtrlCommon);
201 pModal->antCtrlCommon = integer;
202
203 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
204 integer = swab32(pModal->antCtrlChain[i]);
205 pModal->antCtrlChain[i] = integer;
206 }
207
208 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
209 word = swab16(pModal->spurChans[i].spurChan);
210 pModal->spurChans[i].spurChan = word;
211 }
212 }
213 }
214
215 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
216 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
217 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
218 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
219 sum, ah->eep_ops->get_eeprom_ver(ah));
220 return -EINVAL;
221 }
222
223 return 0;
224 }
225
226 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
227 enum eeprom_param param)
228 {
229 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
230 struct modal_eep_header *pModal = eep->modalHeader;
231 struct base_eep_header *pBase = &eep->baseEepHeader;
232
233 switch (param) {
234 case EEP_NFTHRESH_5:
235 return pModal[0].noiseFloorThreshCh[0];
236 case EEP_NFTHRESH_2:
237 return pModal[1].noiseFloorThreshCh[0];
238 case AR_EEPROM_MAC(0):
239 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
240 case AR_EEPROM_MAC(1):
241 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
242 case AR_EEPROM_MAC(2):
243 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
244 case EEP_REG_0:
245 return pBase->regDmn[0];
246 case EEP_REG_1:
247 return pBase->regDmn[1];
248 case EEP_OP_CAP:
249 return pBase->deviceCap;
250 case EEP_OP_MODE:
251 return pBase->opCapFlags;
252 case EEP_RF_SILENT:
253 return pBase->rfSilent;
254 case EEP_OB_5:
255 return pModal[0].ob;
256 case EEP_DB_5:
257 return pModal[0].db;
258 case EEP_OB_2:
259 return pModal[1].ob;
260 case EEP_DB_2:
261 return pModal[1].db;
262 case EEP_MINOR_REV:
263 return AR5416_VER_MASK;
264 case EEP_TX_MASK:
265 return pBase->txMask;
266 case EEP_RX_MASK:
267 return pBase->rxMask;
268 case EEP_RXGAIN_TYPE:
269 return pBase->rxGainType;
270 case EEP_TXGAIN_TYPE:
271 return pBase->txGainType;
272 case EEP_OL_PWRCTRL:
273 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
274 return pBase->openLoopPwrCntl ? true : false;
275 else
276 return false;
277 case EEP_RC_CHAIN_MASK:
278 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
279 return pBase->rcChainMask;
280 else
281 return 0;
282 case EEP_DAC_HPWR_5G:
283 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
284 return pBase->dacHiPwrMode_5G;
285 else
286 return 0;
287 case EEP_FRAC_N_5G:
288 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
289 return pBase->frac_n_5g;
290 else
291 return 0;
292 default:
293 return 0;
294 }
295 }
296
297 static void ath9k_hw_def_set_gain(struct ath_hw *ah,
298 struct modal_eep_header *pModal,
299 struct ar5416_eeprom_def *eep,
300 u8 txRxAttenLocal, int regChainOffset, int i)
301 {
302 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
303 txRxAttenLocal = pModal->txRxAttenCh[i];
304
305 if (AR_SREV_9280_10_OR_LATER(ah)) {
306 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
307 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
308 pModal->bswMargin[i]);
309 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
310 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
311 pModal->bswAtten[i]);
312 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
313 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
314 pModal->xatten2Margin[i]);
315 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
316 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
317 pModal->xatten2Db[i]);
318 } else {
319 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
320 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
321 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
322 | SM(pModal-> bswMargin[i],
323 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
324 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
325 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
326 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
327 | SM(pModal->bswAtten[i],
328 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
329 }
330 }
331
332 if (AR_SREV_9280_10_OR_LATER(ah)) {
333 REG_RMW_FIELD(ah,
334 AR_PHY_RXGAIN + regChainOffset,
335 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
336 REG_RMW_FIELD(ah,
337 AR_PHY_RXGAIN + regChainOffset,
338 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
339 } else {
340 REG_WRITE(ah,
341 AR_PHY_RXGAIN + regChainOffset,
342 (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
343 ~AR_PHY_RXGAIN_TXRX_ATTEN)
344 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
345 REG_WRITE(ah,
346 AR_PHY_GAIN_2GHZ + regChainOffset,
347 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
348 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
349 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
350 }
351 }
352
353 static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
354 struct ath9k_channel *chan)
355 {
356 struct modal_eep_header *pModal;
357 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
358 int i, regChainOffset;
359 u8 txRxAttenLocal;
360
361 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
362 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
363
364 REG_WRITE(ah, AR_PHY_SWITCH_COM,
365 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
366
367 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
368 if (AR_SREV_9280(ah)) {
369 if (i >= 2)
370 break;
371 }
372
373 if (AR_SREV_5416_20_OR_LATER(ah) &&
374 (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
375 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
376 else
377 regChainOffset = i * 0x1000;
378
379 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
380 pModal->antCtrlChain[i]);
381
382 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
383 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
384 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
385 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
386 SM(pModal->iqCalICh[i],
387 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
388 SM(pModal->iqCalQCh[i],
389 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
390
391 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
392 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
393 regChainOffset, i);
394 }
395
396 if (AR_SREV_9280_10_OR_LATER(ah)) {
397 if (IS_CHAN_2GHZ(chan)) {
398 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
399 AR_AN_RF2G1_CH0_OB,
400 AR_AN_RF2G1_CH0_OB_S,
401 pModal->ob);
402 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
403 AR_AN_RF2G1_CH0_DB,
404 AR_AN_RF2G1_CH0_DB_S,
405 pModal->db);
406 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
407 AR_AN_RF2G1_CH1_OB,
408 AR_AN_RF2G1_CH1_OB_S,
409 pModal->ob_ch1);
410 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
411 AR_AN_RF2G1_CH1_DB,
412 AR_AN_RF2G1_CH1_DB_S,
413 pModal->db_ch1);
414 } else {
415 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
416 AR_AN_RF5G1_CH0_OB5,
417 AR_AN_RF5G1_CH0_OB5_S,
418 pModal->ob);
419 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
420 AR_AN_RF5G1_CH0_DB5,
421 AR_AN_RF5G1_CH0_DB5_S,
422 pModal->db);
423 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
424 AR_AN_RF5G1_CH1_OB5,
425 AR_AN_RF5G1_CH1_OB5_S,
426 pModal->ob_ch1);
427 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
428 AR_AN_RF5G1_CH1_DB5,
429 AR_AN_RF5G1_CH1_DB5_S,
430 pModal->db_ch1);
431 }
432 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
433 AR_AN_TOP2_XPABIAS_LVL,
434 AR_AN_TOP2_XPABIAS_LVL_S,
435 pModal->xpaBiasLvl);
436 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
437 AR_AN_TOP2_LOCALBIAS,
438 AR_AN_TOP2_LOCALBIAS_S,
439 pModal->local_bias);
440 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
441 pModal->force_xpaon);
442 }
443
444 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
445 pModal->switchSettling);
446 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
447 pModal->adcDesiredSize);
448
449 if (!AR_SREV_9280_10_OR_LATER(ah))
450 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
451 AR_PHY_DESIRED_SZ_PGA,
452 pModal->pgaDesiredSize);
453
454 REG_WRITE(ah, AR_PHY_RF_CTL4,
455 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
456 | SM(pModal->txEndToXpaOff,
457 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
458 | SM(pModal->txFrameToXpaOn,
459 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
460 | SM(pModal->txFrameToXpaOn,
461 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
462
463 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
464 pModal->txEndToRxOn);
465
466 if (AR_SREV_9280_10_OR_LATER(ah)) {
467 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
468 pModal->thresh62);
469 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
470 AR_PHY_EXT_CCA0_THRESH62,
471 pModal->thresh62);
472 } else {
473 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
474 pModal->thresh62);
475 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
476 AR_PHY_EXT_CCA_THRESH62,
477 pModal->thresh62);
478 }
479
480 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
481 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
482 AR_PHY_TX_END_DATA_START,
483 pModal->txFrameToDataStart);
484 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
485 pModal->txFrameToPaOn);
486 }
487
488 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
489 if (IS_CHAN_HT40(chan))
490 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
491 AR_PHY_SETTLING_SWITCH,
492 pModal->swSettleHt40);
493 }
494
495 if (AR_SREV_9280_20_OR_LATER(ah) &&
496 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
497 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
498 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
499 pModal->miscBits);
500
501
502 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
503 if (IS_CHAN_2GHZ(chan))
504 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
505 eep->baseEepHeader.dacLpMode);
506 else if (eep->baseEepHeader.dacHiPwrMode_5G)
507 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
508 else
509 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
510 eep->baseEepHeader.dacLpMode);
511
512 udelay(100);
513
514 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
515 pModal->miscBits >> 2);
516
517 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
518 AR_PHY_TX_DESIRED_SCALE_CCK,
519 eep->baseEepHeader.desiredScaleCCK);
520 }
521 }
522
523 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
524 struct ath9k_channel *chan)
525 {
526 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
527 struct modal_eep_header *pModal;
528 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
529 u8 biaslevel;
530
531 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
532 return;
533
534 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
535 return;
536
537 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
538
539 if (pModal->xpaBiasLvl != 0xff) {
540 biaslevel = pModal->xpaBiasLvl;
541 } else {
542 u16 resetFreqBin, freqBin, freqCount = 0;
543 struct chan_centers centers;
544
545 ath9k_hw_get_channel_centers(ah, chan, &centers);
546
547 resetFreqBin = FREQ2FBIN(centers.synth_center,
548 IS_CHAN_2GHZ(chan));
549 freqBin = XPA_LVL_FREQ(0) & 0xff;
550 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
551
552 freqCount++;
553
554 while (freqCount < 3) {
555 if (XPA_LVL_FREQ(freqCount) == 0x0)
556 break;
557
558 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
559 if (resetFreqBin >= freqBin)
560 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
561 else
562 break;
563 freqCount++;
564 }
565 }
566
567 if (IS_CHAN_2GHZ(chan)) {
568 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
569 7, 1) & (~0x18)) | biaslevel << 3;
570 } else {
571 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
572 6, 1) & (~0xc0)) | biaslevel << 6;
573 }
574 #undef XPA_LVL_FREQ
575 }
576
577 static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
578 struct ath9k_channel *chan,
579 struct cal_data_per_freq *pRawDataSet,
580 u8 *bChans, u16 availPiers,
581 u16 tPdGainOverlap, int16_t *pMinCalPower,
582 u16 *pPdGainBoundaries, u8 *pPDADCValues,
583 u16 numXpdGains)
584 {
585 int i, j, k;
586 int16_t ss;
587 u16 idxL = 0, idxR = 0, numPiers;
588 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
589 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
590 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
591 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
592 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
593 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
594
595 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
596 u8 minPwrT4[AR5416_NUM_PD_GAINS];
597 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
598 int16_t vpdStep;
599 int16_t tmpVal;
600 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
601 bool match;
602 int16_t minDelta = 0;
603 struct chan_centers centers;
604
605 ath9k_hw_get_channel_centers(ah, chan, &centers);
606
607 for (numPiers = 0; numPiers < availPiers; numPiers++) {
608 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
609 break;
610 }
611
612 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
613 IS_CHAN_2GHZ(chan)),
614 bChans, numPiers, &idxL, &idxR);
615
616 if (match) {
617 for (i = 0; i < numXpdGains; i++) {
618 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
619 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
620 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
621 pRawDataSet[idxL].pwrPdg[i],
622 pRawDataSet[idxL].vpdPdg[i],
623 AR5416_PD_GAIN_ICEPTS,
624 vpdTableI[i]);
625 }
626 } else {
627 for (i = 0; i < numXpdGains; i++) {
628 pVpdL = pRawDataSet[idxL].vpdPdg[i];
629 pPwrL = pRawDataSet[idxL].pwrPdg[i];
630 pVpdR = pRawDataSet[idxR].vpdPdg[i];
631 pPwrR = pRawDataSet[idxR].pwrPdg[i];
632
633 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
634
635 maxPwrT4[i] =
636 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
637 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
638
639
640 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
641 pPwrL, pVpdL,
642 AR5416_PD_GAIN_ICEPTS,
643 vpdTableL[i]);
644 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
645 pPwrR, pVpdR,
646 AR5416_PD_GAIN_ICEPTS,
647 vpdTableR[i]);
648
649 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
650 vpdTableI[i][j] =
651 (u8)(ath9k_hw_interpolate((u16)
652 FREQ2FBIN(centers.
653 synth_center,
654 IS_CHAN_2GHZ
655 (chan)),
656 bChans[idxL], bChans[idxR],
657 vpdTableL[i][j], vpdTableR[i][j]));
658 }
659 }
660 }
661
662 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
663
664 k = 0;
665
666 for (i = 0; i < numXpdGains; i++) {
667 if (i == (numXpdGains - 1))
668 pPdGainBoundaries[i] =
669 (u16)(maxPwrT4[i] / 2);
670 else
671 pPdGainBoundaries[i] =
672 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
673
674 pPdGainBoundaries[i] =
675 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
676
677 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
678 minDelta = pPdGainBoundaries[0] - 23;
679 pPdGainBoundaries[0] = 23;
680 } else {
681 minDelta = 0;
682 }
683
684 if (i == 0) {
685 if (AR_SREV_9280_10_OR_LATER(ah))
686 ss = (int16_t)(0 - (minPwrT4[i] / 2));
687 else
688 ss = 0;
689 } else {
690 ss = (int16_t)((pPdGainBoundaries[i - 1] -
691 (minPwrT4[i] / 2)) -
692 tPdGainOverlap + 1 + minDelta);
693 }
694 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
695 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
696
697 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
698 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
699 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
700 ss++;
701 }
702
703 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
704 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
705 (minPwrT4[i] / 2));
706 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
707 tgtIndex : sizeCurrVpdTable;
708
709 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
710 pPDADCValues[k++] = vpdTableI[i][ss++];
711 }
712
713 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
714 vpdTableI[i][sizeCurrVpdTable - 2]);
715 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
716
717 if (tgtIndex > maxIndex) {
718 while ((ss <= tgtIndex) &&
719 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
720 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
721 (ss - maxIndex + 1) * vpdStep));
722 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
723 255 : tmpVal);
724 ss++;
725 }
726 }
727 }
728
729 while (i < AR5416_PD_GAINS_IN_MASK) {
730 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
731 i++;
732 }
733
734 while (k < AR5416_NUM_PDADC_VALUES) {
735 pPDADCValues[k] = pPDADCValues[k - 1];
736 k++;
737 }
738
739 return;
740 }
741
742 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
743 struct ath9k_channel *chan,
744 int16_t *pTxPowerIndexOffset)
745 {
746 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
747 #define SM_PDGAIN_B(x, y) \
748 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
749
750 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
751 struct cal_data_per_freq *pRawDataset;
752 u8 *pCalBChans = NULL;
753 u16 pdGainOverlap_t2;
754 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
755 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
756 u16 numPiers, i, j;
757 int16_t tMinCalPower;
758 u16 numXpdGain, xpdMask;
759 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
760 u32 reg32, regOffset, regChainOffset;
761 int16_t modalIdx;
762
763 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
764 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
765
766 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
767 AR5416_EEP_MINOR_VER_2) {
768 pdGainOverlap_t2 =
769 pEepData->modalHeader[modalIdx].pdGainOverlap;
770 } else {
771 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
772 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
773 }
774
775 if (IS_CHAN_2GHZ(chan)) {
776 pCalBChans = pEepData->calFreqPier2G;
777 numPiers = AR5416_NUM_2G_CAL_PIERS;
778 } else {
779 pCalBChans = pEepData->calFreqPier5G;
780 numPiers = AR5416_NUM_5G_CAL_PIERS;
781 }
782
783 if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
784 pRawDataset = pEepData->calPierData2G[0];
785 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
786 pRawDataset)->vpdPdg[0][0];
787 }
788
789 numXpdGain = 0;
790
791 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
792 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
793 if (numXpdGain >= AR5416_NUM_PD_GAINS)
794 break;
795 xpdGainValues[numXpdGain] =
796 (u16)(AR5416_PD_GAINS_IN_MASK - i);
797 numXpdGain++;
798 }
799 }
800
801 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
802 (numXpdGain - 1) & 0x3);
803 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
804 xpdGainValues[0]);
805 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
806 xpdGainValues[1]);
807 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
808 xpdGainValues[2]);
809
810 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
811 if (AR_SREV_5416_20_OR_LATER(ah) &&
812 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
813 (i != 0)) {
814 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
815 } else
816 regChainOffset = i * 0x1000;
817
818 if (pEepData->baseEepHeader.txMask & (1 << i)) {
819 if (IS_CHAN_2GHZ(chan))
820 pRawDataset = pEepData->calPierData2G[i];
821 else
822 pRawDataset = pEepData->calPierData5G[i];
823
824
825 if (OLC_FOR_AR9280_20_LATER) {
826 u8 pcdacIdx;
827 u8 txPower;
828
829 ath9k_get_txgain_index(ah, chan,
830 (struct calDataPerFreqOpLoop *)pRawDataset,
831 pCalBChans, numPiers, &txPower, &pcdacIdx);
832 ath9k_olc_get_pdadcs(ah, pcdacIdx,
833 txPower/2, pdadcValues);
834 } else {
835 ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
836 chan, pRawDataset,
837 pCalBChans, numPiers,
838 pdGainOverlap_t2,
839 &tMinCalPower,
840 gainBoundaries,
841 pdadcValues,
842 numXpdGain);
843 }
844
845 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
846 if (OLC_FOR_AR9280_20_LATER) {
847 REG_WRITE(ah,
848 AR_PHY_TPCRG5 + regChainOffset,
849 SM(0x6,
850 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
851 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
852 SM_PD_GAIN(3) | SM_PD_GAIN(4));
853 } else {
854 REG_WRITE(ah,
855 AR_PHY_TPCRG5 + regChainOffset,
856 SM(pdGainOverlap_t2,
857 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
858 SM_PDGAIN_B(0, 1) |
859 SM_PDGAIN_B(1, 2) |
860 SM_PDGAIN_B(2, 3) |
861 SM_PDGAIN_B(3, 4));
862 }
863 }
864
865 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
866 for (j = 0; j < 32; j++) {
867 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
868 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
869 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
870 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
871 REG_WRITE(ah, regOffset, reg32);
872
873 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
874 "PDADC (%d,%4x): %4.4x %8.8x\n",
875 i, regChainOffset, regOffset,
876 reg32);
877 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
878 "PDADC: Chain %d | PDADC %3d "
879 "Value %3d | PDADC %3d Value %3d | "
880 "PDADC %3d Value %3d | PDADC %3d "
881 "Value %3d |\n",
882 i, 4 * j, pdadcValues[4 * j],
883 4 * j + 1, pdadcValues[4 * j + 1],
884 4 * j + 2, pdadcValues[4 * j + 2],
885 4 * j + 3,
886 pdadcValues[4 * j + 3]);
887
888 regOffset += 4;
889 }
890 }
891 }
892
893 *pTxPowerIndexOffset = 0;
894 #undef SM_PD_GAIN
895 #undef SM_PDGAIN_B
896 }
897
898 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
899 struct ath9k_channel *chan,
900 int16_t *ratesArray,
901 u16 cfgCtl,
902 u16 AntennaReduction,
903 u16 twiceMaxRegulatoryPower,
904 u16 powerLimit)
905 {
906 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
907 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
908
909 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
910 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
911 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
912 static const u16 tpScaleReductionTable[5] =
913 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
914
915 int i;
916 int16_t twiceLargestAntenna;
917 struct cal_ctl_data *rep;
918 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
919 0, { 0, 0, 0, 0}
920 };
921 struct cal_target_power_leg targetPowerOfdmExt = {
922 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
923 0, { 0, 0, 0, 0 }
924 };
925 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
926 0, {0, 0, 0, 0}
927 };
928 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
929 u16 ctlModesFor11a[] =
930 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
931 u16 ctlModesFor11g[] =
932 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
933 CTL_2GHT40
934 };
935 u16 numCtlModes, *pCtlMode, ctlMode, freq;
936 struct chan_centers centers;
937 int tx_chainmask;
938 u16 twiceMinEdgePower;
939
940 tx_chainmask = ah->txchainmask;
941
942 ath9k_hw_get_channel_centers(ah, chan, &centers);
943
944 twiceLargestAntenna = max(
945 pEepData->modalHeader
946 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
947 pEepData->modalHeader
948 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
949
950 twiceLargestAntenna = max((u8)twiceLargestAntenna,
951 pEepData->modalHeader
952 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
953
954 twiceLargestAntenna = (int16_t)min(AntennaReduction -
955 twiceLargestAntenna, 0);
956
957 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
958
959 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
960 maxRegAllowedPower -=
961 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
962 }
963
964 scaledPower = min(powerLimit, maxRegAllowedPower);
965
966 switch (ar5416_get_ntxchains(tx_chainmask)) {
967 case 1:
968 break;
969 case 2:
970 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
971 break;
972 case 3:
973 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
974 break;
975 }
976
977 scaledPower = max((u16)0, scaledPower);
978
979 if (IS_CHAN_2GHZ(chan)) {
980 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
981 SUB_NUM_CTL_MODES_AT_2G_40;
982 pCtlMode = ctlModesFor11g;
983
984 ath9k_hw_get_legacy_target_powers(ah, chan,
985 pEepData->calTargetPowerCck,
986 AR5416_NUM_2G_CCK_TARGET_POWERS,
987 &targetPowerCck, 4, false);
988 ath9k_hw_get_legacy_target_powers(ah, chan,
989 pEepData->calTargetPower2G,
990 AR5416_NUM_2G_20_TARGET_POWERS,
991 &targetPowerOfdm, 4, false);
992 ath9k_hw_get_target_powers(ah, chan,
993 pEepData->calTargetPower2GHT20,
994 AR5416_NUM_2G_20_TARGET_POWERS,
995 &targetPowerHt20, 8, false);
996
997 if (IS_CHAN_HT40(chan)) {
998 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
999 ath9k_hw_get_target_powers(ah, chan,
1000 pEepData->calTargetPower2GHT40,
1001 AR5416_NUM_2G_40_TARGET_POWERS,
1002 &targetPowerHt40, 8, true);
1003 ath9k_hw_get_legacy_target_powers(ah, chan,
1004 pEepData->calTargetPowerCck,
1005 AR5416_NUM_2G_CCK_TARGET_POWERS,
1006 &targetPowerCckExt, 4, true);
1007 ath9k_hw_get_legacy_target_powers(ah, chan,
1008 pEepData->calTargetPower2G,
1009 AR5416_NUM_2G_20_TARGET_POWERS,
1010 &targetPowerOfdmExt, 4, true);
1011 }
1012 } else {
1013 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
1014 SUB_NUM_CTL_MODES_AT_5G_40;
1015 pCtlMode = ctlModesFor11a;
1016
1017 ath9k_hw_get_legacy_target_powers(ah, chan,
1018 pEepData->calTargetPower5G,
1019 AR5416_NUM_5G_20_TARGET_POWERS,
1020 &targetPowerOfdm, 4, false);
1021 ath9k_hw_get_target_powers(ah, chan,
1022 pEepData->calTargetPower5GHT20,
1023 AR5416_NUM_5G_20_TARGET_POWERS,
1024 &targetPowerHt20, 8, false);
1025
1026 if (IS_CHAN_HT40(chan)) {
1027 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
1028 ath9k_hw_get_target_powers(ah, chan,
1029 pEepData->calTargetPower5GHT40,
1030 AR5416_NUM_5G_40_TARGET_POWERS,
1031 &targetPowerHt40, 8, true);
1032 ath9k_hw_get_legacy_target_powers(ah, chan,
1033 pEepData->calTargetPower5G,
1034 AR5416_NUM_5G_20_TARGET_POWERS,
1035 &targetPowerOfdmExt, 4, true);
1036 }
1037 }
1038
1039 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1040 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1041 (pCtlMode[ctlMode] == CTL_2GHT40);
1042 if (isHt40CtlMode)
1043 freq = centers.synth_center;
1044 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1045 freq = centers.ext_center;
1046 else
1047 freq = centers.ctl_center;
1048
1049 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1050 ah->eep_ops->get_eeprom_rev(ah) <= 2)
1051 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1052
1053 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1054 if ((((cfgCtl & ~CTL_MODE_M) |
1055 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1056 pEepData->ctlIndex[i]) ||
1057 (((cfgCtl & ~CTL_MODE_M) |
1058 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1059 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1060 rep = &(pEepData->ctlData[i]);
1061
1062 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1063 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1064 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1065
1066 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1067 twiceMaxEdgePower = min(twiceMaxEdgePower,
1068 twiceMinEdgePower);
1069 } else {
1070 twiceMaxEdgePower = twiceMinEdgePower;
1071 break;
1072 }
1073 }
1074 }
1075
1076 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1077
1078 switch (pCtlMode[ctlMode]) {
1079 case CTL_11B:
1080 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1081 targetPowerCck.tPow2x[i] =
1082 min((u16)targetPowerCck.tPow2x[i],
1083 minCtlPower);
1084 }
1085 break;
1086 case CTL_11A:
1087 case CTL_11G:
1088 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1089 targetPowerOfdm.tPow2x[i] =
1090 min((u16)targetPowerOfdm.tPow2x[i],
1091 minCtlPower);
1092 }
1093 break;
1094 case CTL_5GHT20:
1095 case CTL_2GHT20:
1096 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1097 targetPowerHt20.tPow2x[i] =
1098 min((u16)targetPowerHt20.tPow2x[i],
1099 minCtlPower);
1100 }
1101 break;
1102 case CTL_11B_EXT:
1103 targetPowerCckExt.tPow2x[0] = min((u16)
1104 targetPowerCckExt.tPow2x[0],
1105 minCtlPower);
1106 break;
1107 case CTL_11A_EXT:
1108 case CTL_11G_EXT:
1109 targetPowerOfdmExt.tPow2x[0] = min((u16)
1110 targetPowerOfdmExt.tPow2x[0],
1111 minCtlPower);
1112 break;
1113 case CTL_5GHT40:
1114 case CTL_2GHT40:
1115 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1116 targetPowerHt40.tPow2x[i] =
1117 min((u16)targetPowerHt40.tPow2x[i],
1118 minCtlPower);
1119 }
1120 break;
1121 default:
1122 break;
1123 }
1124 }
1125
1126 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1127 ratesArray[rate18mb] = ratesArray[rate24mb] =
1128 targetPowerOfdm.tPow2x[0];
1129 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1130 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1131 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1132 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1133
1134 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1135 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1136
1137 if (IS_CHAN_2GHZ(chan)) {
1138 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1139 ratesArray[rate2s] = ratesArray[rate2l] =
1140 targetPowerCck.tPow2x[1];
1141 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1142 targetPowerCck.tPow2x[2];
1143 ratesArray[rate11s] = ratesArray[rate11l] =
1144 targetPowerCck.tPow2x[3];
1145 }
1146 if (IS_CHAN_HT40(chan)) {
1147 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1148 ratesArray[rateHt40_0 + i] =
1149 targetPowerHt40.tPow2x[i];
1150 }
1151 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1152 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1153 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1154 if (IS_CHAN_2GHZ(chan)) {
1155 ratesArray[rateExtCck] =
1156 targetPowerCckExt.tPow2x[0];
1157 }
1158 }
1159 }
1160
1161 static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1162 struct ath9k_channel *chan,
1163 u16 cfgCtl,
1164 u8 twiceAntennaReduction,
1165 u8 twiceMaxRegulatoryPower,
1166 u8 powerLimit)
1167 {
1168 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
1169 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1170 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1171 struct modal_eep_header *pModal =
1172 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1173 int16_t ratesArray[Ar5416RateSize];
1174 int16_t txPowerIndexOffset = 0;
1175 u8 ht40PowerIncForPdadc = 2;
1176 int i, cck_ofdm_delta = 0;
1177
1178 memset(ratesArray, 0, sizeof(ratesArray));
1179
1180 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1181 AR5416_EEP_MINOR_VER_2) {
1182 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1183 }
1184
1185 ath9k_hw_set_def_power_per_rate_table(ah, chan,
1186 &ratesArray[0], cfgCtl,
1187 twiceAntennaReduction,
1188 twiceMaxRegulatoryPower,
1189 powerLimit);
1190
1191 ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
1192
1193 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1194 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1195 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1196 ratesArray[i] = AR5416_MAX_RATE_POWER;
1197 }
1198
1199 if (AR_SREV_9280_10_OR_LATER(ah)) {
1200 for (i = 0; i < Ar5416RateSize; i++)
1201 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
1202 }
1203
1204 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1205 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1206 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1207 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1208 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1209 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1210 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1211 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1212 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1213 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1214
1215 if (IS_CHAN_2GHZ(chan)) {
1216 if (OLC_FOR_AR9280_20_LATER) {
1217 cck_ofdm_delta = 2;
1218 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1219 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1220 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1221 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1222 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1223 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1224 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1225 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1226 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1227 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1228 } else {
1229 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1230 ATH9K_POW_SM(ratesArray[rate2s], 24)
1231 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1232 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1233 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1234 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1235 ATH9K_POW_SM(ratesArray[rate11s], 24)
1236 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1237 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1238 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1239 }
1240 }
1241
1242 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1243 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1244 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1245 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1246 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1247 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1248 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1249 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1250 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1251 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1252
1253 if (IS_CHAN_HT40(chan)) {
1254 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1255 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1256 ht40PowerIncForPdadc, 24)
1257 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1258 ht40PowerIncForPdadc, 16)
1259 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1260 ht40PowerIncForPdadc, 8)
1261 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1262 ht40PowerIncForPdadc, 0));
1263 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1264 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1265 ht40PowerIncForPdadc, 24)
1266 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1267 ht40PowerIncForPdadc, 16)
1268 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1269 ht40PowerIncForPdadc, 8)
1270 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1271 ht40PowerIncForPdadc, 0));
1272 if (OLC_FOR_AR9280_20_LATER) {
1273 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1274 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1275 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1276 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1277 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1278 } else {
1279 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1280 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1281 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1282 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1283 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1284 }
1285 }
1286
1287 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1288 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1289 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1290
1291 i = rate6mb;
1292
1293 if (IS_CHAN_HT40(chan))
1294 i = rateHt40_0;
1295 else if (IS_CHAN_HT20(chan))
1296 i = rateHt20_0;
1297
1298 if (AR_SREV_9280_10_OR_LATER(ah))
1299 regulatory->max_power_level =
1300 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
1301 else
1302 regulatory->max_power_level = ratesArray[i];
1303
1304 switch(ar5416_get_ntxchains(ah->txchainmask)) {
1305 case 1:
1306 break;
1307 case 2:
1308 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
1309 break;
1310 case 3:
1311 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1312 break;
1313 default:
1314 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1315 "Invalid chainmask configuration\n");
1316 break;
1317 }
1318 }
1319
1320 static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
1321 enum ieee80211_band freq_band)
1322 {
1323 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1324 struct modal_eep_header *pModal =
1325 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
1326 struct base_eep_header *pBase = &eep->baseEepHeader;
1327 u8 num_ant_config;
1328
1329 num_ant_config = 1;
1330
1331 if (pBase->version >= 0x0E0D)
1332 if (pModal->useAnt1)
1333 num_ant_config += 1;
1334
1335 return num_ant_config;
1336 }
1337
1338 static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
1339 struct ath9k_channel *chan)
1340 {
1341 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1342 struct modal_eep_header *pModal =
1343 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1344
1345 return pModal->antCtrlCommon & 0xFFFF;
1346 }
1347
1348 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1349 {
1350 #define EEP_DEF_SPURCHAN \
1351 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1352
1353 u16 spur_val = AR_NO_SPUR;
1354
1355 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1356 "Getting spur idx %d is2Ghz. %d val %x\n",
1357 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1358
1359 switch (ah->config.spurmode) {
1360 case SPUR_DISABLE:
1361 break;
1362 case SPUR_ENABLE_IOCTL:
1363 spur_val = ah->config.spurchans[i][is2GHz];
1364 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1365 "Getting spur val from new loc. %d\n", spur_val);
1366 break;
1367 case SPUR_ENABLE_EEPROM:
1368 spur_val = EEP_DEF_SPURCHAN;
1369 break;
1370 }
1371
1372 return spur_val;
1373
1374 #undef EEP_DEF_SPURCHAN
1375 }
1376
1377 const struct eeprom_ops eep_def_ops = {
1378 .check_eeprom = ath9k_hw_def_check_eeprom,
1379 .get_eeprom = ath9k_hw_def_get_eeprom,
1380 .fill_eeprom = ath9k_hw_def_fill_eeprom,
1381 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
1382 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
1383 .get_num_ant_config = ath9k_hw_def_get_num_ant_config,
1384 .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
1385 .set_board_values = ath9k_hw_def_set_board_values,
1386 .set_addac = ath9k_hw_def_set_addac,
1387 .set_txpower = ath9k_hw_def_set_txpower,
1388 .get_spur_channel = ath9k_hw_def_get_spur_channel
1389 };
Linux with added FPC-III support