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x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / net / wireless / b43 / pio.c
blob9b9044400218e4e59a085272001037993ccda90a
1 /*
2
3 Broadcom B43 wireless driver
4
5 PIO data transfer
6
7 Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24 */
25
26 #include "b43.h"
27 #include "pio.h"
28 #include "dma.h"
29 #include "main.h"
30 #include "xmit.h"
31
32 #include <linux/delay.h>
33 #include <linux/sched.h>
34
35
36 static u16 generate_cookie(struct b43_pio_txqueue *q,
37 struct b43_pio_txpacket *pack)
38 {
39 u16 cookie;
40
41 /* Use the upper 4 bits of the cookie as
42 * PIO controller ID and store the packet index number
43 * in the lower 12 bits.
44 * Note that the cookie must never be 0, as this
45 * is a special value used in RX path.
46 * It can also not be 0xFFFF because that is special
47 * for multicast frames.
48 */
49 cookie = (((u16)q->index + 1) << 12);
50 cookie |= pack->index;
51
52 return cookie;
53 }
54
55 static
56 struct b43_pio_txqueue *parse_cookie(struct b43_wldev *dev,
57 u16 cookie,
58 struct b43_pio_txpacket **pack)
59 {
60 struct b43_pio *pio = &dev->pio;
61 struct b43_pio_txqueue *q = NULL;
62 unsigned int pack_index;
63
64 switch (cookie & 0xF000) {
65 case 0x1000:
66 q = pio->tx_queue_AC_BK;
67 break;
68 case 0x2000:
69 q = pio->tx_queue_AC_BE;
70 break;
71 case 0x3000:
72 q = pio->tx_queue_AC_VI;
73 break;
74 case 0x4000:
75 q = pio->tx_queue_AC_VO;
76 break;
77 case 0x5000:
78 q = pio->tx_queue_mcast;
79 break;
80 }
81 if (B43_WARN_ON(!q))
82 return NULL;
83 pack_index = (cookie & 0x0FFF);
84 if (B43_WARN_ON(pack_index >= ARRAY_SIZE(q->packets)))
85 return NULL;
86 *pack = &q->packets[pack_index];
87
88 return q;
89 }
90
91 static u16 index_to_pioqueue_base(struct b43_wldev *dev,
92 unsigned int index)
93 {
94 static const u16 bases[] = {
95 B43_MMIO_PIO_BASE0,
96 B43_MMIO_PIO_BASE1,
97 B43_MMIO_PIO_BASE2,
98 B43_MMIO_PIO_BASE3,
99 B43_MMIO_PIO_BASE4,
100 B43_MMIO_PIO_BASE5,
101 B43_MMIO_PIO_BASE6,
102 B43_MMIO_PIO_BASE7,
103 };
104 static const u16 bases_rev11[] = {
105 B43_MMIO_PIO11_BASE0,
106 B43_MMIO_PIO11_BASE1,
107 B43_MMIO_PIO11_BASE2,
108 B43_MMIO_PIO11_BASE3,
109 B43_MMIO_PIO11_BASE4,
110 B43_MMIO_PIO11_BASE5,
111 };
112
113 if (dev->dev->id.revision >= 11) {
114 B43_WARN_ON(index >= ARRAY_SIZE(bases_rev11));
115 return bases_rev11[index];
116 }
117 B43_WARN_ON(index >= ARRAY_SIZE(bases));
118 return bases[index];
119 }
120
121 static u16 pio_txqueue_offset(struct b43_wldev *dev)
122 {
123 if (dev->dev->id.revision >= 11)
124 return 0x18;
125 return 0;
126 }
127
128 static u16 pio_rxqueue_offset(struct b43_wldev *dev)
129 {
130 if (dev->dev->id.revision >= 11)
131 return 0x38;
132 return 8;
133 }
134
135 static struct b43_pio_txqueue *b43_setup_pioqueue_tx(struct b43_wldev *dev,
136 unsigned int index)
137 {
138 struct b43_pio_txqueue *q;
139 struct b43_pio_txpacket *p;
140 unsigned int i;
141
142 q = kzalloc(sizeof(*q), GFP_KERNEL);
143 if (!q)
144 return NULL;
145 q->dev = dev;
146 q->rev = dev->dev->id.revision;
147 q->mmio_base = index_to_pioqueue_base(dev, index) +
148 pio_txqueue_offset(dev);
149 q->index = index;
150
151 q->free_packet_slots = B43_PIO_MAX_NR_TXPACKETS;
152 if (q->rev >= 8) {
153 q->buffer_size = 1920; //FIXME this constant is wrong.
154 } else {
155 q->buffer_size = b43_piotx_read16(q, B43_PIO_TXQBUFSIZE);
156 q->buffer_size -= 80;
157 }
158
159 INIT_LIST_HEAD(&q->packets_list);
160 for (i = 0; i < ARRAY_SIZE(q->packets); i++) {
161 p = &(q->packets[i]);
162 INIT_LIST_HEAD(&p->list);
163 p->index = i;
164 p->queue = q;
165 list_add(&p->list, &q->packets_list);
166 }
167
168 return q;
169 }
170
171 static struct b43_pio_rxqueue *b43_setup_pioqueue_rx(struct b43_wldev *dev,
172 unsigned int index)
173 {
174 struct b43_pio_rxqueue *q;
175
176 q = kzalloc(sizeof(*q), GFP_KERNEL);
177 if (!q)
178 return NULL;
179 q->dev = dev;
180 q->rev = dev->dev->id.revision;
181 q->mmio_base = index_to_pioqueue_base(dev, index) +
182 pio_rxqueue_offset(dev);
183
184 /* Enable Direct FIFO RX (PIO) on the engine. */
185 b43_dma_direct_fifo_rx(dev, index, 1);
186
187 return q;
188 }
189
190 static void b43_pio_cancel_tx_packets(struct b43_pio_txqueue *q)
191 {
192 struct b43_pio_txpacket *pack;
193 unsigned int i;
194
195 for (i = 0; i < ARRAY_SIZE(q->packets); i++) {
196 pack = &(q->packets[i]);
197 if (pack->skb) {
198 dev_kfree_skb_any(pack->skb);
199 pack->skb = NULL;
200 }
201 }
202 }
203
204 static void b43_destroy_pioqueue_tx(struct b43_pio_txqueue *q,
205 const char *name)
206 {
207 if (!q)
208 return;
209 b43_pio_cancel_tx_packets(q);
210 kfree(q);
211 }
212
213 static void b43_destroy_pioqueue_rx(struct b43_pio_rxqueue *q,
214 const char *name)
215 {
216 if (!q)
217 return;
218 kfree(q);
219 }
220
221 #define destroy_queue_tx(pio, queue) do { \
222 b43_destroy_pioqueue_tx((pio)->queue, __stringify(queue)); \
223 (pio)->queue = NULL; \
224 } while (0)
225
226 #define destroy_queue_rx(pio, queue) do { \
227 b43_destroy_pioqueue_rx((pio)->queue, __stringify(queue)); \
228 (pio)->queue = NULL; \
229 } while (0)
230
231 void b43_pio_free(struct b43_wldev *dev)
232 {
233 struct b43_pio *pio;
234
235 if (!b43_using_pio_transfers(dev))
236 return;
237 pio = &dev->pio;
238
239 destroy_queue_rx(pio, rx_queue);
240 destroy_queue_tx(pio, tx_queue_mcast);
241 destroy_queue_tx(pio, tx_queue_AC_VO);
242 destroy_queue_tx(pio, tx_queue_AC_VI);
243 destroy_queue_tx(pio, tx_queue_AC_BE);
244 destroy_queue_tx(pio, tx_queue_AC_BK);
245 }
246
247 int b43_pio_init(struct b43_wldev *dev)
248 {
249 struct b43_pio *pio = &dev->pio;
250 int err = -ENOMEM;
251
252 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
253 & ~B43_MACCTL_BE);
254 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RXPADOFF, 0);
255
256 pio->tx_queue_AC_BK = b43_setup_pioqueue_tx(dev, 0);
257 if (!pio->tx_queue_AC_BK)
258 goto out;
259
260 pio->tx_queue_AC_BE = b43_setup_pioqueue_tx(dev, 1);
261 if (!pio->tx_queue_AC_BE)
262 goto err_destroy_bk;
263
264 pio->tx_queue_AC_VI = b43_setup_pioqueue_tx(dev, 2);
265 if (!pio->tx_queue_AC_VI)
266 goto err_destroy_be;
267
268 pio->tx_queue_AC_VO = b43_setup_pioqueue_tx(dev, 3);
269 if (!pio->tx_queue_AC_VO)
270 goto err_destroy_vi;
271
272 pio->tx_queue_mcast = b43_setup_pioqueue_tx(dev, 4);
273 if (!pio->tx_queue_mcast)
274 goto err_destroy_vo;
275
276 pio->rx_queue = b43_setup_pioqueue_rx(dev, 0);
277 if (!pio->rx_queue)
278 goto err_destroy_mcast;
279
280 b43dbg(dev->wl, "PIO initialized\n");
281 err = 0;
282 out:
283 return err;
284
285 err_destroy_mcast:
286 destroy_queue_tx(pio, tx_queue_mcast);
287 err_destroy_vo:
288 destroy_queue_tx(pio, tx_queue_AC_VO);
289 err_destroy_vi:
290 destroy_queue_tx(pio, tx_queue_AC_VI);
291 err_destroy_be:
292 destroy_queue_tx(pio, tx_queue_AC_BE);
293 err_destroy_bk:
294 destroy_queue_tx(pio, tx_queue_AC_BK);
295 return err;
296 }
297
298 /* Static mapping of mac80211's queues (priorities) to b43 PIO queues. */
299 static struct b43_pio_txqueue *select_queue_by_priority(struct b43_wldev *dev,
300 u8 queue_prio)
301 {
302 struct b43_pio_txqueue *q;
303
304 if (dev->qos_enabled) {
305 /* 0 = highest priority */
306 switch (queue_prio) {
307 default:
308 B43_WARN_ON(1);
309 /* fallthrough */
310 case 0:
311 q = dev->pio.tx_queue_AC_VO;
312 break;
313 case 1:
314 q = dev->pio.tx_queue_AC_VI;
315 break;
316 case 2:
317 q = dev->pio.tx_queue_AC_BE;
318 break;
319 case 3:
320 q = dev->pio.tx_queue_AC_BK;
321 break;
322 }
323 } else
324 q = dev->pio.tx_queue_AC_BE;
325
326 return q;
327 }
328
329 static u16 tx_write_2byte_queue(struct b43_pio_txqueue *q,
330 u16 ctl,
331 const void *_data,
332 unsigned int data_len)
333 {
334 struct b43_wldev *dev = q->dev;
335 struct b43_wl *wl = dev->wl;
336 const u8 *data = _data;
337
338 ctl |= B43_PIO_TXCTL_WRITELO | B43_PIO_TXCTL_WRITEHI;
339 b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
340
341 ssb_block_write(dev->dev, data, (data_len & ~1),
342 q->mmio_base + B43_PIO_TXDATA,
343 sizeof(u16));
344 if (data_len & 1) {
345 /* Write the last byte. */
346 ctl &= ~B43_PIO_TXCTL_WRITEHI;
347 b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
348 wl->tx_tail[0] = data[data_len - 1];
349 wl->tx_tail[1] = 0;
350 ssb_block_write(dev->dev, wl->tx_tail, 2,
351 q->mmio_base + B43_PIO_TXDATA,
352 sizeof(u16));
353 }
354
355 return ctl;
356 }
357
358 static void pio_tx_frame_2byte_queue(struct b43_pio_txpacket *pack,
359 const u8 *hdr, unsigned int hdrlen)
360 {
361 struct b43_pio_txqueue *q = pack->queue;
362 const char *frame = pack->skb->data;
363 unsigned int frame_len = pack->skb->len;
364 u16 ctl;
365
366 ctl = b43_piotx_read16(q, B43_PIO_TXCTL);
367 ctl |= B43_PIO_TXCTL_FREADY;
368 ctl &= ~B43_PIO_TXCTL_EOF;
369
370 /* Transfer the header data. */
371 ctl = tx_write_2byte_queue(q, ctl, hdr, hdrlen);
372 /* Transfer the frame data. */
373 ctl = tx_write_2byte_queue(q, ctl, frame, frame_len);
374
375 ctl |= B43_PIO_TXCTL_EOF;
376 b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
377 }
378
379 static u32 tx_write_4byte_queue(struct b43_pio_txqueue *q,
380 u32 ctl,
381 const void *_data,
382 unsigned int data_len)
383 {
384 struct b43_wldev *dev = q->dev;
385 struct b43_wl *wl = dev->wl;
386 const u8 *data = _data;
387
388 ctl |= B43_PIO8_TXCTL_0_7 | B43_PIO8_TXCTL_8_15 |
389 B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_24_31;
390 b43_piotx_write32(q, B43_PIO8_TXCTL, ctl);
391
392 ssb_block_write(dev->dev, data, (data_len & ~3),
393 q->mmio_base + B43_PIO8_TXDATA,
394 sizeof(u32));
395 if (data_len & 3) {
396 wl->tx_tail[3] = 0;
397 /* Write the last few bytes. */
398 ctl &= ~(B43_PIO8_TXCTL_8_15 | B43_PIO8_TXCTL_16_23 |
399 B43_PIO8_TXCTL_24_31);
400 switch (data_len & 3) {
401 case 3:
402 ctl |= B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_8_15;
403 wl->tx_tail[0] = data[data_len - 3];
404 wl->tx_tail[1] = data[data_len - 2];
405 wl->tx_tail[2] = data[data_len - 1];
406 break;
407 case 2:
408 ctl |= B43_PIO8_TXCTL_8_15;
409 wl->tx_tail[0] = data[data_len - 2];
410 wl->tx_tail[1] = data[data_len - 1];
411 wl->tx_tail[2] = 0;
412 break;
413 case 1:
414 wl->tx_tail[0] = data[data_len - 1];
415 wl->tx_tail[1] = 0;
416 wl->tx_tail[2] = 0;
417 break;
418 }
419 b43_piotx_write32(q, B43_PIO8_TXCTL, ctl);
420 ssb_block_write(dev->dev, wl->tx_tail, 4,
421 q->mmio_base + B43_PIO8_TXDATA,
422 sizeof(u32));
423 }
424
425 return ctl;
426 }
427
428 static void pio_tx_frame_4byte_queue(struct b43_pio_txpacket *pack,
429 const u8 *hdr, unsigned int hdrlen)
430 {
431 struct b43_pio_txqueue *q = pack->queue;
432 const char *frame = pack->skb->data;
433 unsigned int frame_len = pack->skb->len;
434 u32 ctl;
435
436 ctl = b43_piotx_read32(q, B43_PIO8_TXCTL);
437 ctl |= B43_PIO8_TXCTL_FREADY;
438 ctl &= ~B43_PIO8_TXCTL_EOF;
439
440 /* Transfer the header data. */
441 ctl = tx_write_4byte_queue(q, ctl, hdr, hdrlen);
442 /* Transfer the frame data. */
443 ctl = tx_write_4byte_queue(q, ctl, frame, frame_len);
444
445 ctl |= B43_PIO8_TXCTL_EOF;
446 b43_piotx_write32(q, B43_PIO_TXCTL, ctl);
447 }
448
449 static int pio_tx_frame(struct b43_pio_txqueue *q,
450 struct sk_buff *skb)
451 {
452 struct b43_wldev *dev = q->dev;
453 struct b43_wl *wl = dev->wl;
454 struct b43_pio_txpacket *pack;
455 u16 cookie;
456 int err;
457 unsigned int hdrlen;
458 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
459
460 B43_WARN_ON(list_empty(&q->packets_list));
461 pack = list_entry(q->packets_list.next,
462 struct b43_pio_txpacket, list);
463
464 cookie = generate_cookie(q, pack);
465 hdrlen = b43_txhdr_size(dev);
466 err = b43_generate_txhdr(dev, (u8 *)&wl->txhdr, skb,
467 info, cookie);
468 if (err)
469 return err;
470
471 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
472 /* Tell the firmware about the cookie of the last
473 * mcast frame, so it can clear the more-data bit in it. */
474 b43_shm_write16(dev, B43_SHM_SHARED,
475 B43_SHM_SH_MCASTCOOKIE, cookie);
476 }
477
478 pack->skb = skb;
479 if (q->rev >= 8)
480 pio_tx_frame_4byte_queue(pack, (const u8 *)&wl->txhdr, hdrlen);
481 else
482 pio_tx_frame_2byte_queue(pack, (const u8 *)&wl->txhdr, hdrlen);
483
484 /* Remove it from the list of available packet slots.
485 * It will be put back when we receive the status report. */
486 list_del(&pack->list);
487
488 /* Update the queue statistics. */
489 q->buffer_used += roundup(skb->len + hdrlen, 4);
490 q->free_packet_slots -= 1;
491
492 return 0;
493 }
494
495 int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb)
496 {
497 struct b43_pio_txqueue *q;
498 struct ieee80211_hdr *hdr;
499 unsigned int hdrlen, total_len;
500 int err = 0;
501 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
502
503 hdr = (struct ieee80211_hdr *)skb->data;
504
505 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
506 /* The multicast queue will be sent after the DTIM. */
507 q = dev->pio.tx_queue_mcast;
508 /* Set the frame More-Data bit. Ucode will clear it
509 * for us on the last frame. */
510 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
511 } else {
512 /* Decide by priority where to put this frame. */
513 q = select_queue_by_priority(dev, skb_get_queue_mapping(skb));
514 }
515
516 hdrlen = b43_txhdr_size(dev);
517 total_len = roundup(skb->len + hdrlen, 4);
518
519 if (unlikely(total_len > q->buffer_size)) {
520 err = -ENOBUFS;
521 b43dbg(dev->wl, "PIO: TX packet longer than queue.\n");
522 goto out;
523 }
524 if (unlikely(q->free_packet_slots == 0)) {
525 err = -ENOBUFS;
526 b43warn(dev->wl, "PIO: TX packet overflow.\n");
527 goto out;
528 }
529 B43_WARN_ON(q->buffer_used > q->buffer_size);
530
531 if (total_len > (q->buffer_size - q->buffer_used)) {
532 /* Not enough memory on the queue. */
533 err = -EBUSY;
534 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
535 q->stopped = 1;
536 goto out;
537 }
538
539 /* Assign the queue number to the ring (if not already done before)
540 * so TX status handling can use it. The mac80211-queue to b43-queue
541 * mapping is static, so we don't need to store it per frame. */
542 q->queue_prio = skb_get_queue_mapping(skb);
543
544 err = pio_tx_frame(q, skb);
545 if (unlikely(err == -ENOKEY)) {
546 /* Drop this packet, as we don't have the encryption key
547 * anymore and must not transmit it unencrypted. */
548 dev_kfree_skb_any(skb);
549 err = 0;
550 goto out;
551 }
552 if (unlikely(err)) {
553 b43err(dev->wl, "PIO transmission failure\n");
554 goto out;
555 }
556 q->nr_tx_packets++;
557
558 B43_WARN_ON(q->buffer_used > q->buffer_size);
559 if (((q->buffer_size - q->buffer_used) < roundup(2 + 2 + 6, 4)) ||
560 (q->free_packet_slots == 0)) {
561 /* The queue is full. */
562 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
563 q->stopped = 1;
564 }
565
566 out:
567 return err;
568 }
569
570 void b43_pio_handle_txstatus(struct b43_wldev *dev,
571 const struct b43_txstatus *status)
572 {
573 struct b43_pio_txqueue *q;
574 struct b43_pio_txpacket *pack = NULL;
575 unsigned int total_len;
576 struct ieee80211_tx_info *info;
577
578 q = parse_cookie(dev, status->cookie, &pack);
579 if (unlikely(!q))
580 return;
581 B43_WARN_ON(!pack);
582
583 info = IEEE80211_SKB_CB(pack->skb);
584
585 b43_fill_txstatus_report(dev, info, status);
586
587 total_len = pack->skb->len + b43_txhdr_size(dev);
588 total_len = roundup(total_len, 4);
589 q->buffer_used -= total_len;
590 q->free_packet_slots += 1;
591
592 ieee80211_tx_status(dev->wl->hw, pack->skb);
593 pack->skb = NULL;
594 list_add(&pack->list, &q->packets_list);
595
596 if (q->stopped) {
597 ieee80211_wake_queue(dev->wl->hw, q->queue_prio);
598 q->stopped = 0;
599 }
600 }
601
602 void b43_pio_get_tx_stats(struct b43_wldev *dev,
603 struct ieee80211_tx_queue_stats *stats)
604 {
605 const int nr_queues = dev->wl->hw->queues;
606 struct b43_pio_txqueue *q;
607 int i;
608
609 for (i = 0; i < nr_queues; i++) {
610 q = select_queue_by_priority(dev, i);
611
612 stats[i].len = B43_PIO_MAX_NR_TXPACKETS - q->free_packet_slots;
613 stats[i].limit = B43_PIO_MAX_NR_TXPACKETS;
614 stats[i].count = q->nr_tx_packets;
615 }
616 }
617
618 /* Returns whether we should fetch another frame. */
619 static bool pio_rx_frame(struct b43_pio_rxqueue *q)
620 {
621 struct b43_wldev *dev = q->dev;
622 struct b43_wl *wl = dev->wl;
623 u16 len;
624 u32 macstat;
625 unsigned int i, padding;
626 struct sk_buff *skb;
627 const char *err_msg = NULL;
628
629 memset(&wl->rxhdr, 0, sizeof(wl->rxhdr));
630
631 /* Check if we have data and wait for it to get ready. */
632 if (q->rev >= 8) {
633 u32 ctl;
634
635 ctl = b43_piorx_read32(q, B43_PIO8_RXCTL);
636 if (!(ctl & B43_PIO8_RXCTL_FRAMERDY))
637 return 0;
638 b43_piorx_write32(q, B43_PIO8_RXCTL,
639 B43_PIO8_RXCTL_FRAMERDY);
640 for (i = 0; i < 10; i++) {
641 ctl = b43_piorx_read32(q, B43_PIO8_RXCTL);
642 if (ctl & B43_PIO8_RXCTL_DATARDY)
643 goto data_ready;
644 udelay(10);
645 }
646 } else {
647 u16 ctl;
648
649 ctl = b43_piorx_read16(q, B43_PIO_RXCTL);
650 if (!(ctl & B43_PIO_RXCTL_FRAMERDY))
651 return 0;
652 b43_piorx_write16(q, B43_PIO_RXCTL,
653 B43_PIO_RXCTL_FRAMERDY);
654 for (i = 0; i < 10; i++) {
655 ctl = b43_piorx_read16(q, B43_PIO_RXCTL);
656 if (ctl & B43_PIO_RXCTL_DATARDY)
657 goto data_ready;
658 udelay(10);
659 }
660 }
661 b43dbg(q->dev->wl, "PIO RX timed out\n");
662 return 1;
663 data_ready:
664
665 /* Get the preamble (RX header) */
666 if (q->rev >= 8) {
667 ssb_block_read(dev->dev, &wl->rxhdr, sizeof(wl->rxhdr),
668 q->mmio_base + B43_PIO8_RXDATA,
669 sizeof(u32));
670 } else {
671 ssb_block_read(dev->dev, &wl->rxhdr, sizeof(wl->rxhdr),
672 q->mmio_base + B43_PIO_RXDATA,
673 sizeof(u16));
674 }
675 /* Sanity checks. */
676 len = le16_to_cpu(wl->rxhdr.frame_len);
677 if (unlikely(len > 0x700)) {
678 err_msg = "len > 0x700";
679 goto rx_error;
680 }
681 if (unlikely(len == 0)) {
682 err_msg = "len == 0";
683 goto rx_error;
684 }
685
686 macstat = le32_to_cpu(wl->rxhdr.mac_status);
687 if (macstat & B43_RX_MAC_FCSERR) {
688 if (!(q->dev->wl->filter_flags & FIF_FCSFAIL)) {
689 /* Drop frames with failed FCS. */
690 err_msg = "Frame FCS error";
691 goto rx_error;
692 }
693 }
694
695 /* We always pad 2 bytes, as that's what upstream code expects
696 * due to the RX-header being 30 bytes. In case the frame is
697 * unaligned, we pad another 2 bytes. */
698 padding = (macstat & B43_RX_MAC_PADDING) ? 2 : 0;
699 skb = dev_alloc_skb(len + padding + 2);
700 if (unlikely(!skb)) {
701 err_msg = "Out of memory";
702 goto rx_error;
703 }
704 skb_reserve(skb, 2);
705 skb_put(skb, len + padding);
706 if (q->rev >= 8) {
707 ssb_block_read(dev->dev, skb->data + padding, (len & ~3),
708 q->mmio_base + B43_PIO8_RXDATA,
709 sizeof(u32));
710 if (len & 3) {
711 /* Read the last few bytes. */
712 ssb_block_read(dev->dev, wl->rx_tail, 4,
713 q->mmio_base + B43_PIO8_RXDATA,
714 sizeof(u32));
715 switch (len & 3) {
716 case 3:
717 skb->data[len + padding - 3] = wl->rx_tail[0];
718 skb->data[len + padding - 2] = wl->rx_tail[1];
719 skb->data[len + padding - 1] = wl->rx_tail[2];
720 break;
721 case 2:
722 skb->data[len + padding - 2] = wl->rx_tail[0];
723 skb->data[len + padding - 1] = wl->rx_tail[1];
724 break;
725 case 1:
726 skb->data[len + padding - 1] = wl->rx_tail[0];
727 break;
728 }
729 }
730 } else {
731 ssb_block_read(dev->dev, skb->data + padding, (len & ~1),
732 q->mmio_base + B43_PIO_RXDATA,
733 sizeof(u16));
734 if (len & 1) {
735 /* Read the last byte. */
736 ssb_block_read(dev->dev, wl->rx_tail, 2,
737 q->mmio_base + B43_PIO_RXDATA,
738 sizeof(u16));
739 skb->data[len + padding - 1] = wl->rx_tail[0];
740 }
741 }
742
743 b43_rx(q->dev, skb, &wl->rxhdr);
744
745 return 1;
746
747 rx_error:
748 if (err_msg)
749 b43dbg(q->dev->wl, "PIO RX error: %s\n", err_msg);
750 b43_piorx_write16(q, B43_PIO_RXCTL, B43_PIO_RXCTL_DATARDY);
751 return 1;
752 }
753
754 void b43_pio_rx(struct b43_pio_rxqueue *q)
755 {
756 unsigned int count = 0;
757 bool stop;
758
759 while (1) {
760 stop = (pio_rx_frame(q) == 0);
761 if (stop)
762 break;
763 cond_resched();
764 if (WARN_ON_ONCE(++count > 10000))
765 break;
766 }
767 }
768
769 static void b43_pio_tx_suspend_queue(struct b43_pio_txqueue *q)
770 {
771 if (q->rev >= 8) {
772 b43_piotx_write32(q, B43_PIO8_TXCTL,
773 b43_piotx_read32(q, B43_PIO8_TXCTL)
774 | B43_PIO8_TXCTL_SUSPREQ);
775 } else {
776 b43_piotx_write16(q, B43_PIO_TXCTL,
777 b43_piotx_read16(q, B43_PIO_TXCTL)
778 | B43_PIO_TXCTL_SUSPREQ);
779 }
780 }
781
782 static void b43_pio_tx_resume_queue(struct b43_pio_txqueue *q)
783 {
784 if (q->rev >= 8) {
785 b43_piotx_write32(q, B43_PIO8_TXCTL,
786 b43_piotx_read32(q, B43_PIO8_TXCTL)
787 & ~B43_PIO8_TXCTL_SUSPREQ);
788 } else {
789 b43_piotx_write16(q, B43_PIO_TXCTL,
790 b43_piotx_read16(q, B43_PIO_TXCTL)
791 & ~B43_PIO_TXCTL_SUSPREQ);
792 }
793 }
794
795 void b43_pio_tx_suspend(struct b43_wldev *dev)
796 {
797 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
798 b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_BK);
799 b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_BE);
800 b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_VI);
801 b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_VO);
802 b43_pio_tx_suspend_queue(dev->pio.tx_queue_mcast);
803 }
804
805 void b43_pio_tx_resume(struct b43_wldev *dev)
806 {
807 b43_pio_tx_resume_queue(dev->pio.tx_queue_mcast);
808 b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_VO);
809 b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_VI);
810 b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_BE);
811 b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_BK);
812 b43_power_saving_ctl_bits(dev, 0);
813 }
Linux with added FPC-III support