drivers/scsi/be2iscsi/be_main.h

   1 /**
   2  * Copyright (C) 2005 - 2009 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Written by: Jayamohan Kallickal (jayamohank@serverengines.com)
  11  *
  12  * Contact Information:
  13  * linux-drivers@serverengines.com
  14  *
  15  * ServerEngines
  16  * 209 N. Fair Oaks Ave
  17  * Sunnyvale, CA 94085
  18  *
  19  */
  20
  21 #ifndef _BEISCSI_MAIN_
  22 #define _BEISCSI_MAIN_
  23
  24
  25 #include <linux/kernel.h>
  26 #include <linux/pci.h>
  27 #include <linux/in.h>
  28 #include <linux/blk-iopoll.h>
  29 #include <scsi/scsi.h>
  30 #include <scsi/scsi_cmnd.h>
  31 #include <scsi/scsi_device.h>
  32 #include <scsi/scsi_host.h>
  33 #include <scsi/iscsi_proto.h>
  34 #include <scsi/libiscsi.h>
  35 #include <scsi/scsi_transport_iscsi.h>
  36
  37 #include "be.h"
  38
  39
  40
  41 #define DRV_NAME                "be2iscsi"
  42 #define BUILD_STR               "2.0.527.0"
  43
  44 #define BE_NAME                 "ServerEngines BladeEngine2" \
  45                                 "Linux iSCSI Driver version" BUILD_STR
  46 #define DRV_DESC                BE_NAME " " "Driver"
  47
  48 #define BE_VENDOR_ID            0x19A2
  49 #define BE_DEVICE_ID1           0x212
  50 #define OC_DEVICE_ID1           0x702
  51 #define OC_DEVICE_ID2           0x703
  52
  53 #define BE2_MAX_SESSIONS        64
  54 #define BE2_CMDS_PER_CXN        128
  55 #define BE2_LOGOUTS             BE2_MAX_SESSIONS
  56 #define BE2_TMFS                16
  57 #define BE2_NOPOUT_REQ          16
  58 #define BE2_ASYNCPDUS           BE2_MAX_SESSIONS
  59 #define BE2_MAX_ICDS            2048
  60 #define BE2_SGE                 32
  61 #define BE2_DEFPDU_HDR_SZ       64
  62 #define BE2_DEFPDU_DATA_SZ      8192
  63 #define BE2_IO_DEPTH \
  64         (BE2_MAX_ICDS / 2 - (BE2_LOGOUTS + BE2_TMFS + BE2_NOPOUT_REQ))
  65
  66 #define BEISCSI_SGLIST_ELEMENTS BE2_SGE
  67
  68 #define BEISCSI_MAX_CMNDS       1024    /* Max IO's per Ctrlr sht->can_queue */
  69 #define BEISCSI_CMD_PER_LUN     128     /* scsi_host->cmd_per_lun */
  70 #define BEISCSI_MAX_SECTORS     2048    /* scsi_host->max_sectors */
  71
  72 #define BEISCSI_MAX_CMD_LEN     16      /* scsi_host->max_cmd_len */
  73 #define BEISCSI_NUM_MAX_LUN     256     /* scsi_host->max_lun */
  74 #define BEISCSI_NUM_DEVICES_SUPPORTED   0x01
  75 #define BEISCSI_MAX_FRAGS_INIT  192
  76 #define BE_NUM_MSIX_ENTRIES     1
  77 #define MPU_EP_SEMAPHORE        0xac
  78
  79 #define BE_SENSE_INFO_SIZE              258
  80 #define BE_ISCSI_PDU_HEADER_SIZE        64
  81 #define BE_MIN_MEM_SIZE                 16384
  82
  83 #define IIOC_SCSI_DATA                  0x05    /* Write Operation */
  84
  85 #define DBG_LVL                         0x00000001
  86 #define DBG_LVL_1                       0x00000001
  87 #define DBG_LVL_2                       0x00000002
  88 #define DBG_LVL_3                       0x00000004
  89 #define DBG_LVL_4                       0x00000008
  90 #define DBG_LVL_5                       0x00000010
  91 #define DBG_LVL_6                       0x00000020
  92 #define DBG_LVL_7                       0x00000040
  93 #define DBG_LVL_8                       0x00000080
  94
  95 #define SE_DEBUG(debug_mask, fmt, args...)              \
  96 do {                                                    \
  97         if (debug_mask & DBG_LVL) {                     \
  98                 printk(KERN_ERR "(%s():%d):", __func__, __LINE__);\
  99                 printk(fmt, ##args);                    \
 100         }                                               \
 101 } while (0);
 102
 103 /**
 104  * hardware needs the async PDU buffers to be posted in multiples of 8
 105  * So have atleast 8 of them by default
 106  */
 107
 108 #define HWI_GET_ASYNC_PDU_CTX(phwi)     (phwi->phwi_ctxt->pasync_ctx)
 109
 110 /********* Memory BAR register ************/
 111 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET      0xfc
 112 /**
 113  * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
 114  * Disable" may still globally block interrupts in addition to individual
 115  * interrupt masks; a mechanism for the device driver to block all interrupts
 116  * atomically without having to arbitrate for the PCI Interrupt Disable bit
 117  * with the OS.
 118  */
 119 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK      (1 << 29)       /* bit 29 */
 120
 121 /********* ISR0 Register offset **********/
 122 #define CEV_ISR0_OFFSET                         0xC18
 123 #define CEV_ISR_SIZE                            4
 124
 125 /**
 126  * Macros for reading/writing a protection domain or CSR registers
 127  * in BladeEngine.
 128  */
 129
 130 #define DB_TXULP0_OFFSET 0x40
 131 #define DB_RXULP0_OFFSET 0xA0
 132 /********* Event Q door bell *************/
 133 #define DB_EQ_OFFSET                    DB_CQ_OFFSET
 134 #define DB_EQ_RING_ID_MASK              0x1FF   /* bits 0 - 8 */
 135 /* Clear the interrupt for this eq */
 136 #define DB_EQ_CLR_SHIFT                 (9)     /* bit 9 */
 137 /* Must be 1 */
 138 #define DB_EQ_EVNT_SHIFT                (10)    /* bit 10 */
 139 /* Number of event entries processed */
 140 #define DB_EQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 141 /* Rearm bit */
 142 #define DB_EQ_REARM_SHIFT               (29)    /* bit 29 */
 143
 144 /********* Compl Q door bell *************/
 145 #define DB_CQ_OFFSET                    0x120
 146 #define DB_CQ_RING_ID_MASK              0x3FF   /* bits 0 - 9 */
 147 /* Number of event entries processed */
 148 #define DB_CQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 149 /* Rearm bit */
 150 #define DB_CQ_REARM_SHIFT               (29)    /* bit 29 */
 151
 152 #define GET_HWI_CONTROLLER_WS(pc)       (pc->phwi_ctrlr)
 153 #define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
 154                 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
 155 #define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
 156                 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
 157
 158 #define PAGES_REQUIRED(x) \
 159         ((x < PAGE_SIZE) ? 1 :  ((x + PAGE_SIZE - 1) / PAGE_SIZE))
 160
 161 enum be_mem_enum {
 162         HWI_MEM_ADDN_CONTEXT,
 163         HWI_MEM_CQ,
 164         HWI_MEM_EQ,
 165         HWI_MEM_WRB,
 166         HWI_MEM_WRBH,
 167         HWI_MEM_SGLH,   /* 5 */
 168         HWI_MEM_SGE,
 169         HWI_MEM_ASYNC_HEADER_BUF,
 170         HWI_MEM_ASYNC_DATA_BUF,
 171         HWI_MEM_ASYNC_HEADER_RING,
 172         HWI_MEM_ASYNC_DATA_RING,        /* 10 */
 173         HWI_MEM_ASYNC_HEADER_HANDLE,
 174         HWI_MEM_ASYNC_DATA_HANDLE,
 175         HWI_MEM_ASYNC_PDU_CONTEXT,
 176         ISCSI_MEM_GLOBAL_HEADER,
 177         SE_MEM_MAX      /* 15 */
 178 };
 179
 180 struct be_bus_address32 {
 181         unsigned int address_lo;
 182         unsigned int address_hi;
 183 };
 184
 185 struct be_bus_address64 {
 186         unsigned long long address;
 187 };
 188
 189 struct be_bus_address {
 190         union {
 191                 struct be_bus_address32 a32;
 192                 struct be_bus_address64 a64;
 193         } u;
 194 };
 195
 196 struct mem_array {
 197         struct be_bus_address bus_address;      /* Bus address of location */
 198         void *virtual_address;          /* virtual address to the location */
 199         unsigned int size;              /* Size required by memory block */
 200 };
 201
 202 struct be_mem_descriptor {
 203         unsigned int index;     /* Index of this memory parameter */
 204         unsigned int category;  /* type indicates cached/non-cached */
 205         unsigned int num_elements;      /* number of elements in this
 206                                          * descriptor
 207                                          */
 208         unsigned int alignment_mask;    /* Alignment mask for this block */
 209         unsigned int size_in_bytes;     /* Size required by memory block */
 210         struct mem_array *mem_array;
 211 };
 212
 213 struct sgl_handle {
 214         unsigned int sgl_index;
 215         struct iscsi_sge *pfrag;
 216 };
 217
 218 struct hba_parameters {
 219         unsigned int ios_per_ctrl;
 220         unsigned int cxns_per_ctrl;
 221         unsigned int asyncpdus_per_ctrl;
 222         unsigned int icds_per_ctrl;
 223         unsigned int num_sge_per_io;
 224         unsigned int defpdu_hdr_sz;
 225         unsigned int defpdu_data_sz;
 226         unsigned int num_cq_entries;
 227         unsigned int num_eq_entries;
 228         unsigned int wrbs_per_cxn;
 229         unsigned int crashmode;
 230         unsigned int hba_num;
 231
 232         unsigned int mgmt_ws_sz;
 233         unsigned int hwi_ws_sz;
 234
 235         unsigned int eto;
 236         unsigned int ldto;
 237
 238         unsigned int dbg_flags;
 239         unsigned int num_cxn;
 240
 241         unsigned int eq_timer;
 242         /**
 243          * These are calculated from other params. They're here
 244          * for debug purposes
 245          */
 246         unsigned int num_mcc_pages;
 247         unsigned int num_mcc_cq_pages;
 248         unsigned int num_cq_pages;
 249         unsigned int num_eq_pages;
 250
 251         unsigned int num_async_pdu_buf_pages;
 252         unsigned int num_async_pdu_buf_sgl_pages;
 253         unsigned int num_async_pdu_buf_cq_pages;
 254
 255         unsigned int num_async_pdu_hdr_pages;
 256         unsigned int num_async_pdu_hdr_sgl_pages;
 257         unsigned int num_async_pdu_hdr_cq_pages;
 258
 259         unsigned int num_sge;
 260 };
 261
 262 struct beiscsi_hba {
 263         struct hba_parameters params;
 264         struct hwi_controller *phwi_ctrlr;
 265         unsigned int mem_req[SE_MEM_MAX];
 266         /* PCI BAR mapped addresses */
 267         u8 __iomem *csr_va;     /* CSR */
 268         u8 __iomem *db_va;      /* Door  Bell  */
 269         u8 __iomem *pci_va;     /* PCI Config */
 270         struct be_bus_address csr_pa;   /* CSR */
 271         struct be_bus_address db_pa;    /* CSR */
 272         struct be_bus_address pci_pa;   /* CSR */
 273         /* PCI representation of our HBA */
 274         struct pci_dev *pcidev;
 275         unsigned int state;
 276         unsigned short asic_revision;
 277         struct blk_iopoll       iopoll;
 278         struct be_mem_descriptor *init_mem;
 279
 280         unsigned short io_sgl_alloc_index;
 281         unsigned short io_sgl_free_index;
 282         unsigned short io_sgl_hndl_avbl;
 283         struct sgl_handle **io_sgl_hndl_base;
 284
 285         unsigned short eh_sgl_alloc_index;
 286         unsigned short eh_sgl_free_index;
 287         unsigned short eh_sgl_hndl_avbl;
 288         struct sgl_handle **eh_sgl_hndl_base;
 289         spinlock_t io_sgl_lock;
 290         spinlock_t mgmt_sgl_lock;
 291         spinlock_t isr_lock;
 292         unsigned int age;
 293         unsigned short avlbl_cids;
 294         unsigned short cid_alloc;
 295         unsigned short cid_free;
 296         struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2];
 297         struct list_head hba_queue;
 298         unsigned short *cid_array;
 299         struct iscsi_endpoint **ep_array;
 300         struct Scsi_Host *shost;
 301         struct {
 302                 /**
 303                  * group together since they are used most frequently
 304                  * for cid to cri conversion
 305                  */
 306                 unsigned int iscsi_cid_start;
 307                 unsigned int phys_port;
 308
 309                 unsigned int isr_offset;
 310                 unsigned int iscsi_icd_start;
 311                 unsigned int iscsi_cid_count;
 312                 unsigned int iscsi_icd_count;
 313                 unsigned int pci_function;
 314
 315                 unsigned short cid_alloc;
 316                 unsigned short cid_free;
 317                 unsigned short avlbl_cids;
 318                 spinlock_t cid_lock;
 319         } fw_config;
 320
 321         u8 mac_address[ETH_ALEN];
 322         unsigned short todo_cq;
 323         unsigned short todo_mcc_cq;
 324         char wq_name[20];
 325         struct workqueue_struct *wq;    /* The actuak work queue */
 326         struct work_struct work_cqs;    /* The work being queued */
 327         struct be_ctrl_info ctrl;
 328 };
 329
 330 struct beiscsi_session {
 331         struct pci_pool *bhs_pool;
 332 };
 333
 334 /**
 335  * struct beiscsi_conn - iscsi connection structure
 336  */
 337 struct beiscsi_conn {
 338         struct iscsi_conn *conn;
 339         struct beiscsi_hba *phba;
 340         u32 exp_statsn;
 341         u32 beiscsi_conn_cid;
 342         struct beiscsi_endpoint *ep;
 343         unsigned short login_in_progress;
 344         struct sgl_handle *plogin_sgl_handle;
 345         struct beiscsi_session *beiscsi_sess;
 346 };
 347
 348 /* This structure is used by the chip */
 349 struct pdu_data_out {
 350         u32 dw[12];
 351 };
 352 /**
 353  * Pseudo amap definition in which each bit of the actual structure is defined
 354  * as a byte: used to calculate offset/shift/mask of each field
 355  */
 356 struct amap_pdu_data_out {
 357         u8 opcode[6];           /* opcode */
 358         u8 rsvd0[2];            /* should be 0 */
 359         u8 rsvd1[7];
 360         u8 final_bit;           /* F bit */
 361         u8 rsvd2[16];
 362         u8 ahs_length[8];       /* no AHS */
 363         u8 data_len_hi[8];
 364         u8 data_len_lo[16];     /* DataSegmentLength */
 365         u8 lun[64];
 366         u8 itt[32];             /* ITT; initiator task tag */
 367         u8 ttt[32];             /* TTT; valid for R2T or 0xffffffff */
 368         u8 rsvd3[32];
 369         u8 exp_stat_sn[32];
 370         u8 rsvd4[32];
 371         u8 data_sn[32];
 372         u8 buffer_offset[32];
 373         u8 rsvd5[32];
 374 };
 375
 376 struct be_cmd_bhs {
 377         struct iscsi_cmd iscsi_hdr;
 378         unsigned char pad1[16];
 379         struct pdu_data_out iscsi_data_pdu;
 380         unsigned char pad2[BE_SENSE_INFO_SIZE -
 381                         sizeof(struct pdu_data_out)];
 382 };
 383
 384 struct beiscsi_io_task {
 385         struct wrb_handle *pwrb_handle;
 386         struct sgl_handle *psgl_handle;
 387         struct beiscsi_conn *conn;
 388         struct scsi_cmnd *scsi_cmnd;
 389         unsigned int cmd_sn;
 390         unsigned int flags;
 391         unsigned short cid;
 392         unsigned short header_len;
 393
 394         struct be_cmd_bhs *cmd_bhs;
 395         struct be_bus_address bhs_pa;
 396         unsigned short bhs_len;
 397 };
 398
 399 struct be_nonio_bhs {
 400         struct iscsi_hdr iscsi_hdr;
 401         unsigned char pad1[16];
 402         struct pdu_data_out iscsi_data_pdu;
 403         unsigned char pad2[BE_SENSE_INFO_SIZE -
 404                         sizeof(struct pdu_data_out)];
 405 };
 406
 407 struct be_status_bhs {
 408         struct iscsi_cmd iscsi_hdr;
 409         unsigned char pad1[16];
 410         /**
 411          * The plus 2 below is to hold the sense info length that gets
 412          * DMA'ed by RxULP
 413          */
 414         unsigned char sense_info[BE_SENSE_INFO_SIZE];
 415 };
 416
 417 struct iscsi_sge {
 418         u32 dw[4];
 419 };
 420
 421 /**
 422  * Pseudo amap definition in which each bit of the actual structure is defined
 423  * as a byte: used to calculate offset/shift/mask of each field
 424  */
 425 struct amap_iscsi_sge {
 426         u8 addr_hi[32];
 427         u8 addr_lo[32];
 428         u8 sge_offset[22];      /* DWORD 2 */
 429         u8 rsvd0[9];            /* DWORD 2 */
 430         u8 last_sge;            /* DWORD 2 */
 431         u8 len[17];             /* DWORD 3 */
 432         u8 rsvd1[15];           /* DWORD 3 */
 433 };
 434
 435 struct beiscsi_offload_params {
 436         u32 dw[5];
 437 };
 438
 439 #define OFFLD_PARAMS_ERL        0x00000003
 440 #define OFFLD_PARAMS_DDE        0x00000004
 441 #define OFFLD_PARAMS_HDE        0x00000008
 442 #define OFFLD_PARAMS_IR2T       0x00000010
 443 #define OFFLD_PARAMS_IMD        0x00000020
 444
 445 /**
 446  * Pseudo amap definition in which each bit of the actual structure is defined
 447  * as a byte: used to calculate offset/shift/mask of each field
 448  */
 449 struct amap_beiscsi_offload_params {
 450         u8 max_burst_length[32];
 451         u8 max_send_data_segment_length[32];
 452         u8 first_burst_length[32];
 453         u8 erl[2];
 454         u8 dde[1];
 455         u8 hde[1];
 456         u8 ir2t[1];
 457         u8 imd[1];
 458         u8 pad[26];
 459         u8 exp_statsn[32];
 460 };
 461
 462 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
 463                 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
 464
 465 struct async_pdu_handle {
 466         struct list_head link;
 467         struct be_bus_address pa;
 468         void *pbuffer;
 469         unsigned int consumed;
 470         unsigned char index;
 471         unsigned char is_header;
 472         unsigned short cri;
 473         unsigned long buffer_len;
 474 };
 475
 476 struct hwi_async_entry {
 477         struct {
 478                 unsigned char hdr_received;
 479                 unsigned char hdr_len;
 480                 unsigned short bytes_received;
 481                 unsigned int bytes_needed;
 482                 struct list_head list;
 483         } wait_queue;
 484
 485         struct list_head header_busy_list;
 486         struct list_head data_busy_list;
 487 };
 488
 489 #define BE_MIN_ASYNC_ENTRIES 128
 490
 491 struct hwi_async_pdu_context {
 492         struct {
 493                 struct be_bus_address pa_base;
 494                 void *va_base;
 495                 void *ring_base;
 496                 struct async_pdu_handle *handle_base;
 497
 498                 unsigned int host_write_ptr;
 499                 unsigned int ep_read_ptr;
 500                 unsigned int writables;
 501
 502                 unsigned int free_entries;
 503                 unsigned int busy_entries;
 504                 unsigned int buffer_size;
 505                 unsigned int num_entries;
 506
 507                 struct list_head free_list;
 508         } async_header;
 509
 510         struct {
 511                 struct be_bus_address pa_base;
 512                 void *va_base;
 513                 void *ring_base;
 514                 struct async_pdu_handle *handle_base;
 515
 516                 unsigned int host_write_ptr;
 517                 unsigned int ep_read_ptr;
 518                 unsigned int writables;
 519
 520                 unsigned int free_entries;
 521                 unsigned int busy_entries;
 522                 unsigned int buffer_size;
 523                 struct list_head free_list;
 524                 unsigned int num_entries;
 525         } async_data;
 526
 527         /**
 528          * This is a varying size list! Do not add anything
 529          * after this entry!!
 530          */
 531         struct hwi_async_entry async_entry[BE_MIN_ASYNC_ENTRIES];
 532 };
 533
 534 #define PDUCQE_CODE_MASK        0x0000003F
 535 #define PDUCQE_DPL_MASK         0xFFFF0000
 536 #define PDUCQE_INDEX_MASK       0x0000FFFF
 537
 538 struct i_t_dpdu_cqe {
 539         u32 dw[4];
 540 } __packed;
 541
 542 /**
 543  * Pseudo amap definition in which each bit of the actual structure is defined
 544  * as a byte: used to calculate offset/shift/mask of each field
 545  */
 546 struct amap_i_t_dpdu_cqe {
 547         u8 db_addr_hi[32];
 548         u8 db_addr_lo[32];
 549         u8 code[6];
 550         u8 cid[10];
 551         u8 dpl[16];
 552         u8 index[16];
 553         u8 num_cons[10];
 554         u8 rsvd0[4];
 555         u8 final;
 556         u8 valid;
 557 } __packed;
 558
 559 #define CQE_VALID_MASK  0x80000000
 560 #define CQE_CODE_MASK   0x0000003F
 561 #define CQE_CID_MASK    0x0000FFC0
 562
 563 #define EQE_VALID_MASK          0x00000001
 564 #define EQE_MAJORCODE_MASK      0x0000000E
 565 #define EQE_RESID_MASK          0xFFFF0000
 566
 567 struct be_eq_entry {
 568         u32 dw[1];
 569 } __packed;
 570
 571 /**
 572  * Pseudo amap definition in which each bit of the actual structure is defined
 573  * as a byte: used to calculate offset/shift/mask of each field
 574  */
 575 struct amap_eq_entry {
 576         u8 valid;               /* DWORD 0 */
 577         u8 major_code[3];       /* DWORD 0 */
 578         u8 minor_code[12];      /* DWORD 0 */
 579         u8 resource_id[16];     /* DWORD 0 */
 580
 581 } __packed;
 582
 583 struct cq_db {
 584         u32 dw[1];
 585 } __packed;
 586
 587 /**
 588  * Pseudo amap definition in which each bit of the actual structure is defined
 589  * as a byte: used to calculate offset/shift/mask of each field
 590  */
 591 struct amap_cq_db {
 592         u8 qid[10];
 593         u8 event[1];
 594         u8 rsvd0[5];
 595         u8 num_popped[13];
 596         u8 rearm[1];
 597         u8 rsvd1[2];
 598 } __packed;
 599
 600 void beiscsi_process_eq(struct beiscsi_hba *phba);
 601
 602
 603 struct iscsi_wrb {
 604         u32 dw[16];
 605 } __packed;
 606
 607 #define WRB_TYPE_MASK 0xF0000000
 608
 609 /**
 610  * Pseudo amap definition in which each bit of the actual structure is defined
 611  * as a byte: used to calculate offset/shift/mask of each field
 612  */
 613 struct amap_iscsi_wrb {
 614         u8 lun[14];             /* DWORD 0 */
 615         u8 lt;                  /* DWORD 0 */
 616         u8 invld;               /* DWORD 0 */
 617         u8 wrb_idx[8];          /* DWORD 0 */
 618         u8 dsp;                 /* DWORD 0 */
 619         u8 dmsg;                /* DWORD 0 */
 620         u8 undr_run;            /* DWORD 0 */
 621         u8 over_run;            /* DWORD 0 */
 622         u8 type[4];             /* DWORD 0 */
 623         u8 ptr2nextwrb[8];      /* DWORD 1 */
 624         u8 r2t_exp_dtl[24];     /* DWORD 1 */
 625         u8 sgl_icd_idx[12];     /* DWORD 2 */
 626         u8 rsvd0[20];           /* DWORD 2 */
 627         u8 exp_data_sn[32];     /* DWORD 3 */
 628         u8 iscsi_bhs_addr_hi[32];       /* DWORD 4 */
 629         u8 iscsi_bhs_addr_lo[32];       /* DWORD 5 */
 630         u8 cmdsn_itt[32];       /* DWORD 6 */
 631         u8 dif_ref_tag[32];     /* DWORD 7 */
 632         u8 sge0_addr_hi[32];    /* DWORD 8 */
 633         u8 sge0_addr_lo[32];    /* DWORD 9  */
 634         u8 sge0_offset[22];     /* DWORD 10 */
 635         u8 pbs;                 /* DWORD 10 */
 636         u8 dif_mode[2];         /* DWORD 10 */
 637         u8 rsvd1[6];            /* DWORD 10 */
 638         u8 sge0_last;           /* DWORD 10 */
 639         u8 sge0_len[17];        /* DWORD 11 */
 640         u8 dif_meta_tag[14];    /* DWORD 11 */
 641         u8 sge0_in_ddr;         /* DWORD 11 */
 642         u8 sge1_addr_hi[32];    /* DWORD 12 */
 643         u8 sge1_addr_lo[32];    /* DWORD 13 */
 644         u8 sge1_r2t_offset[22]; /* DWORD 14 */
 645         u8 rsvd2[9];            /* DWORD 14 */
 646         u8 sge1_last;           /* DWORD 14 */
 647         u8 sge1_len[17];        /* DWORD 15 */
 648         u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
 649         u8 rsvd3[2];            /* DWORD 15 */
 650         u8 sge1_in_ddr;         /* DWORD 15 */
 651
 652 } __packed;
 653
 654 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
 655                                     int index);
 656 void
 657 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
 658
 659 struct pdu_nop_out {
 660         u32 dw[12];
 661 };
 662
 663 /**
 664  * Pseudo amap definition in which each bit of the actual structure is defined
 665  * as a byte: used to calculate offset/shift/mask of each field
 666  */
 667 struct amap_pdu_nop_out {
 668         u8 opcode[6];           /* opcode 0x00 */
 669         u8 i_bit;               /* I Bit */
 670         u8 x_bit;               /* reserved; should be 0 */
 671         u8 fp_bit_filler1[7];
 672         u8 f_bit;               /* always 1 */
 673         u8 reserved1[16];
 674         u8 ahs_length[8];       /* no AHS */
 675         u8 data_len_hi[8];
 676         u8 data_len_lo[16];     /* DataSegmentLength */
 677         u8 lun[64];
 678         u8 itt[32];             /* initiator id for ping or 0xffffffff */
 679         u8 ttt[32];             /* target id for ping or 0xffffffff */
 680         u8 cmd_sn[32];
 681         u8 exp_stat_sn[32];
 682         u8 reserved5[128];
 683 };
 684
 685 #define PDUBASE_OPCODE_MASK     0x0000003F
 686 #define PDUBASE_DATALENHI_MASK  0x0000FF00
 687 #define PDUBASE_DATALENLO_MASK  0xFFFF0000
 688
 689 struct pdu_base {
 690         u32 dw[16];
 691 } __packed;
 692
 693 /**
 694  * Pseudo amap definition in which each bit of the actual structure is defined
 695  * as a byte: used to calculate offset/shift/mask of each field
 696  */
 697 struct amap_pdu_base {
 698         u8 opcode[6];
 699         u8 i_bit;               /* immediate bit */
 700         u8 x_bit;               /* reserved, always 0 */
 701         u8 reserved1[24];       /* opcode-specific fields */
 702         u8 ahs_length[8];       /* length units is 4 byte words */
 703         u8 data_len_hi[8];
 704         u8 data_len_lo[16];     /* DatasegmentLength */
 705         u8 lun[64];             /* lun or opcode-specific fields */
 706         u8 itt[32];             /* initiator task tag */
 707         u8 reserved4[224];
 708 };
 709
 710 struct iscsi_target_context_update_wrb {
 711         u32 dw[16];
 712 } __packed;
 713
 714 /**
 715  * Pseudo amap definition in which each bit of the actual structure is defined
 716  * as a byte: used to calculate offset/shift/mask of each field
 717  */
 718 struct amap_iscsi_target_context_update_wrb {
 719         u8 lun[14];             /* DWORD 0 */
 720         u8 lt;                  /* DWORD 0 */
 721         u8 invld;               /* DWORD 0 */
 722         u8 wrb_idx[8];          /* DWORD 0 */
 723         u8 dsp;                 /* DWORD 0 */
 724         u8 dmsg;                /* DWORD 0 */
 725         u8 undr_run;            /* DWORD 0 */
 726         u8 over_run;            /* DWORD 0 */
 727         u8 type[4];             /* DWORD 0 */
 728         u8 ptr2nextwrb[8];      /* DWORD 1 */
 729         u8 max_burst_length[19];        /* DWORD 1 */
 730         u8 rsvd0[5];            /* DWORD 1 */
 731         u8 rsvd1[15];           /* DWORD 2 */
 732         u8 max_send_data_segment_length[17];    /* DWORD 2 */
 733         u8 first_burst_length[14];      /* DWORD 3 */
 734         u8 rsvd2[2];            /* DWORD 3 */
 735         u8 tx_wrbindex_drv_msg[8];      /* DWORD 3 */
 736         u8 rsvd3[5];            /* DWORD 3 */
 737         u8 session_state[3];    /* DWORD 3 */
 738         u8 rsvd4[16];           /* DWORD 4 */
 739         u8 tx_jumbo;            /* DWORD 4 */
 740         u8 hde;                 /* DWORD 4 */
 741         u8 dde;                 /* DWORD 4 */
 742         u8 erl[2];              /* DWORD 4 */
 743         u8 domain_id[5];                /* DWORD 4 */
 744         u8 mode;                /* DWORD 4 */
 745         u8 imd;                 /* DWORD 4 */
 746         u8 ir2t;                /* DWORD 4 */
 747         u8 notpredblq[2];       /* DWORD 4 */
 748         u8 compltonack;         /* DWORD 4 */
 749         u8 stat_sn[32];         /* DWORD 5 */
 750         u8 pad_buffer_addr_hi[32];      /* DWORD 6 */
 751         u8 pad_buffer_addr_lo[32];      /* DWORD 7 */
 752         u8 pad_addr_hi[32];     /* DWORD 8 */
 753         u8 pad_addr_lo[32];     /* DWORD 9 */
 754         u8 rsvd5[32];           /* DWORD 10 */
 755         u8 rsvd6[32];           /* DWORD 11 */
 756         u8 rsvd7[32];           /* DWORD 12 */
 757         u8 rsvd8[32];           /* DWORD 13 */
 758         u8 rsvd9[32];           /* DWORD 14 */
 759         u8 rsvd10[32];          /* DWORD 15 */
 760
 761 } __packed;
 762
 763 struct be_ring {
 764         u32 pages;              /* queue size in pages */
 765         u32 id;                 /* queue id assigned by beklib */
 766         u32 num;                /* number of elements in queue */
 767         u32 cidx;               /* consumer index */
 768         u32 pidx;               /* producer index -- not used by most rings */
 769         u32 item_size;          /* size in bytes of one object */
 770
 771         void *va;               /* The virtual address of the ring.  This
 772                                  * should be last to allow 32 & 64 bit debugger
 773                                  * extensions to work.
 774                                  */
 775 };
 776
 777 struct hwi_wrb_context {
 778         struct list_head wrb_handle_list;
 779         struct list_head wrb_handle_drvr_list;
 780         struct wrb_handle **pwrb_handle_base;
 781         struct wrb_handle **pwrb_handle_basestd;
 782         struct iscsi_wrb *plast_wrb;
 783         unsigned short alloc_index;
 784         unsigned short free_index;
 785         unsigned short wrb_handles_available;
 786         unsigned short cid;
 787 };
 788
 789 struct hwi_controller {
 790         struct list_head io_sgl_list;
 791         struct list_head eh_sgl_list;
 792         struct sgl_handle *psgl_handle_base;
 793         unsigned int wrb_mem_index;
 794
 795         struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2];
 796         struct mcc_wrb *pmcc_wrb_base;
 797         struct be_ring default_pdu_hdr;
 798         struct be_ring default_pdu_data;
 799         struct hwi_context_memory *phwi_ctxt;
 800         unsigned short cq_errors[CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN];
 801 };
 802
 803 enum hwh_type_enum {
 804         HWH_TYPE_IO = 1,
 805         HWH_TYPE_LOGOUT = 2,
 806         HWH_TYPE_TMF = 3,
 807         HWH_TYPE_NOP = 4,
 808         HWH_TYPE_IO_RD = 5,
 809         HWH_TYPE_LOGIN = 11,
 810         HWH_TYPE_INVALID = 0xFFFFFFFF
 811 };
 812
 813 struct wrb_handle {
 814         enum hwh_type_enum type;
 815         unsigned short wrb_index;
 816         unsigned short nxt_wrb_index;
 817
 818         struct iscsi_task *pio_handle;
 819         struct iscsi_wrb *pwrb;
 820 };
 821
 822 struct hwi_context_memory {
 823         struct be_eq_obj be_eq;
 824         struct be_queue_info be_cq;
 825         struct be_queue_info be_mcc_cq;
 826         struct be_queue_info be_mcc;
 827
 828         struct be_queue_info be_def_hdrq;
 829         struct be_queue_info be_def_dataq;
 830
 831         struct be_queue_info be_wrbq[BE2_MAX_SESSIONS];
 832         struct be_mcc_wrb_context *pbe_mcc_context;
 833
 834         struct hwi_async_pdu_context *pasync_ctx;
 835 };
 836
 837 #endif