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x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / sh / intc.c
blob559b5fe9dc0fd0ad7c6b96db9f5427fc76ccb0eb
1 /*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
4 * Copyright (C) 2007, 2008 Magnus Damm
5 *
6 * Based on intc2.c and ipr.c
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
11 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
12 * Copyright (C) 2005, 2006 Paul Mundt
13 *
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
16 * for more details.
17 */
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/module.h>
21 #include <linux/io.h>
22 #include <linux/interrupt.h>
23 #include <linux/sh_intc.h>
24 #include <linux/sysdev.h>
25 #include <linux/list.h>
26 #include <linux/topology.h>
27
28 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
29 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
30 ((addr_e) << 16) | ((addr_d << 24)))
31
32 #define _INTC_SHIFT(h) (h & 0x1f)
33 #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
34 #define _INTC_FN(h) ((h >> 9) & 0xf)
35 #define _INTC_MODE(h) ((h >> 13) & 0x7)
36 #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
37 #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
38
39 struct intc_handle_int {
40 unsigned int irq;
41 unsigned long handle;
42 };
43
44 struct intc_desc_int {
45 struct list_head list;
46 struct sys_device sysdev;
47 pm_message_t state;
48 unsigned long *reg;
49 #ifdef CONFIG_SMP
50 unsigned long *smp;
51 #endif
52 unsigned int nr_reg;
53 struct intc_handle_int *prio;
54 unsigned int nr_prio;
55 struct intc_handle_int *sense;
56 unsigned int nr_sense;
57 struct irq_chip chip;
58 };
59
60 static LIST_HEAD(intc_list);
61
62 #ifdef CONFIG_SMP
63 #define IS_SMP(x) x.smp
64 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
65 #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
66 #else
67 #define IS_SMP(x) 0
68 #define INTC_REG(d, x, c) (d->reg[(x)])
69 #define SMP_NR(d, x) 1
70 #endif
71
72 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
73 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
74 static unsigned long ack_handle[NR_IRQS];
75 #endif
76
77 static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
78 {
79 struct irq_chip *chip = get_irq_chip(irq);
80 return container_of(chip, struct intc_desc_int, chip);
81 }
82
83 static inline unsigned int set_field(unsigned int value,
84 unsigned int field_value,
85 unsigned int handle)
86 {
87 unsigned int width = _INTC_WIDTH(handle);
88 unsigned int shift = _INTC_SHIFT(handle);
89
90 value &= ~(((1 << width) - 1) << shift);
91 value |= field_value << shift;
92 return value;
93 }
94
95 static void write_8(unsigned long addr, unsigned long h, unsigned long data)
96 {
97 __raw_writeb(set_field(0, data, h), addr);
98 (void)__raw_readb(addr); /* Defeat write posting */
99 }
100
101 static void write_16(unsigned long addr, unsigned long h, unsigned long data)
102 {
103 __raw_writew(set_field(0, data, h), addr);
104 (void)__raw_readw(addr); /* Defeat write posting */
105 }
106
107 static void write_32(unsigned long addr, unsigned long h, unsigned long data)
108 {
109 __raw_writel(set_field(0, data, h), addr);
110 (void)__raw_readl(addr); /* Defeat write posting */
111 }
112
113 static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
114 {
115 unsigned long flags;
116 local_irq_save(flags);
117 __raw_writeb(set_field(__raw_readb(addr), data, h), addr);
118 (void)__raw_readb(addr); /* Defeat write posting */
119 local_irq_restore(flags);
120 }
121
122 static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
123 {
124 unsigned long flags;
125 local_irq_save(flags);
126 __raw_writew(set_field(__raw_readw(addr), data, h), addr);
127 (void)__raw_readw(addr); /* Defeat write posting */
128 local_irq_restore(flags);
129 }
130
131 static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
132 {
133 unsigned long flags;
134 local_irq_save(flags);
135 __raw_writel(set_field(__raw_readl(addr), data, h), addr);
136 (void)__raw_readl(addr); /* Defeat write posting */
137 local_irq_restore(flags);
138 }
139
140 enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
141
142 static void (*intc_reg_fns[])(unsigned long addr,
143 unsigned long h,
144 unsigned long data) = {
145 [REG_FN_WRITE_BASE + 0] = write_8,
146 [REG_FN_WRITE_BASE + 1] = write_16,
147 [REG_FN_WRITE_BASE + 3] = write_32,
148 [REG_FN_MODIFY_BASE + 0] = modify_8,
149 [REG_FN_MODIFY_BASE + 1] = modify_16,
150 [REG_FN_MODIFY_BASE + 3] = modify_32,
151 };
152
153 enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
154 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
155 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
156 MODE_PRIO_REG, /* Priority value written to enable interrupt */
157 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
158 };
159
160 static void intc_mode_field(unsigned long addr,
161 unsigned long handle,
162 void (*fn)(unsigned long,
163 unsigned long,
164 unsigned long),
165 unsigned int irq)
166 {
167 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
168 }
169
170 static void intc_mode_zero(unsigned long addr,
171 unsigned long handle,
172 void (*fn)(unsigned long,
173 unsigned long,
174 unsigned long),
175 unsigned int irq)
176 {
177 fn(addr, handle, 0);
178 }
179
180 static void intc_mode_prio(unsigned long addr,
181 unsigned long handle,
182 void (*fn)(unsigned long,
183 unsigned long,
184 unsigned long),
185 unsigned int irq)
186 {
187 fn(addr, handle, intc_prio_level[irq]);
188 }
189
190 static void (*intc_enable_fns[])(unsigned long addr,
191 unsigned long handle,
192 void (*fn)(unsigned long,
193 unsigned long,
194 unsigned long),
195 unsigned int irq) = {
196 [MODE_ENABLE_REG] = intc_mode_field,
197 [MODE_MASK_REG] = intc_mode_zero,
198 [MODE_DUAL_REG] = intc_mode_field,
199 [MODE_PRIO_REG] = intc_mode_prio,
200 [MODE_PCLR_REG] = intc_mode_prio,
201 };
202
203 static void (*intc_disable_fns[])(unsigned long addr,
204 unsigned long handle,
205 void (*fn)(unsigned long,
206 unsigned long,
207 unsigned long),
208 unsigned int irq) = {
209 [MODE_ENABLE_REG] = intc_mode_zero,
210 [MODE_MASK_REG] = intc_mode_field,
211 [MODE_DUAL_REG] = intc_mode_field,
212 [MODE_PRIO_REG] = intc_mode_zero,
213 [MODE_PCLR_REG] = intc_mode_field,
214 };
215
216 static inline void _intc_enable(unsigned int irq, unsigned long handle)
217 {
218 struct intc_desc_int *d = get_intc_desc(irq);
219 unsigned long addr;
220 unsigned int cpu;
221
222 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
223 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
224 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
225 [_INTC_FN(handle)], irq);
226 }
227 }
228
229 static void intc_enable(unsigned int irq)
230 {
231 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
232 }
233
234 static void intc_disable(unsigned int irq)
235 {
236 struct intc_desc_int *d = get_intc_desc(irq);
237 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
238 unsigned long addr;
239 unsigned int cpu;
240
241 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
242 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
243 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
244 [_INTC_FN(handle)], irq);
245 }
246 }
247
248 static int intc_set_wake(unsigned int irq, unsigned int on)
249 {
250 return 0; /* allow wakeup, but setup hardware in intc_suspend() */
251 }
252
253 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
254 static void intc_mask_ack(unsigned int irq)
255 {
256 struct intc_desc_int *d = get_intc_desc(irq);
257 unsigned long handle = ack_handle[irq];
258 unsigned long addr;
259
260 intc_disable(irq);
261
262 /* read register and write zero only to the assocaited bit */
263
264 if (handle) {
265 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
266 switch (_INTC_FN(handle)) {
267 case REG_FN_MODIFY_BASE + 0: /* 8bit */
268 __raw_readb(addr);
269 __raw_writeb(0xff ^ set_field(0, 1, handle), addr);
270 break;
271 case REG_FN_MODIFY_BASE + 1: /* 16bit */
272 __raw_readw(addr);
273 __raw_writew(0xffff ^ set_field(0, 1, handle), addr);
274 break;
275 case REG_FN_MODIFY_BASE + 3: /* 32bit */
276 __raw_readl(addr);
277 __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr);
278 break;
279 default:
280 BUG();
281 break;
282 }
283 }
284 }
285 #endif
286
287 static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
288 unsigned int nr_hp,
289 unsigned int irq)
290 {
291 int i;
292
293 /* this doesn't scale well, but...
294 *
295 * this function should only be used for cerain uncommon
296 * operations such as intc_set_priority() and intc_set_sense()
297 * and in those rare cases performance doesn't matter that much.
298 * keeping the memory footprint low is more important.
299 *
300 * one rather simple way to speed this up and still keep the
301 * memory footprint down is to make sure the array is sorted
302 * and then perform a bisect to lookup the irq.
303 */
304
305 for (i = 0; i < nr_hp; i++) {
306 if ((hp + i)->irq != irq)
307 continue;
308
309 return hp + i;
310 }
311
312 return NULL;
313 }
314
315 int intc_set_priority(unsigned int irq, unsigned int prio)
316 {
317 struct intc_desc_int *d = get_intc_desc(irq);
318 struct intc_handle_int *ihp;
319
320 if (!intc_prio_level[irq] || prio <= 1)
321 return -EINVAL;
322
323 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
324 if (ihp) {
325 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
326 return -EINVAL;
327
328 intc_prio_level[irq] = prio;
329
330 /*
331 * only set secondary masking method directly
332 * primary masking method is using intc_prio_level[irq]
333 * priority level will be set during next enable()
334 */
335
336 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
337 _intc_enable(irq, ihp->handle);
338 }
339 return 0;
340 }
341
342 #define VALID(x) (x | 0x80)
343
344 static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
345 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
346 [IRQ_TYPE_EDGE_RISING] = VALID(1),
347 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
348 /* SH7706, SH7707 and SH7709 do not support high level triggered */
349 #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
350 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
351 !defined(CONFIG_CPU_SUBTYPE_SH7709)
352 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
353 #endif
354 };
355
356 static int intc_set_sense(unsigned int irq, unsigned int type)
357 {
358 struct intc_desc_int *d = get_intc_desc(irq);
359 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
360 struct intc_handle_int *ihp;
361 unsigned long addr;
362
363 if (!value)
364 return -EINVAL;
365
366 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
367 if (ihp) {
368 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
369 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
370 }
371 return 0;
372 }
373
374 static unsigned int __init intc_get_reg(struct intc_desc_int *d,
375 unsigned long address)
376 {
377 unsigned int k;
378
379 for (k = 0; k < d->nr_reg; k++) {
380 if (d->reg[k] == address)
381 return k;
382 }
383
384 BUG();
385 return 0;
386 }
387
388 static intc_enum __init intc_grp_id(struct intc_desc *desc,
389 intc_enum enum_id)
390 {
391 struct intc_group *g = desc->groups;
392 unsigned int i, j;
393
394 for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
395 g = desc->groups + i;
396
397 for (j = 0; g->enum_ids[j]; j++) {
398 if (g->enum_ids[j] != enum_id)
399 continue;
400
401 return g->enum_id;
402 }
403 }
404
405 return 0;
406 }
407
408 static unsigned int __init intc_mask_data(struct intc_desc *desc,
409 struct intc_desc_int *d,
410 intc_enum enum_id, int do_grps)
411 {
412 struct intc_mask_reg *mr = desc->mask_regs;
413 unsigned int i, j, fn, mode;
414 unsigned long reg_e, reg_d;
415
416 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
417 mr = desc->mask_regs + i;
418
419 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
420 if (mr->enum_ids[j] != enum_id)
421 continue;
422
423 if (mr->set_reg && mr->clr_reg) {
424 fn = REG_FN_WRITE_BASE;
425 mode = MODE_DUAL_REG;
426 reg_e = mr->clr_reg;
427 reg_d = mr->set_reg;
428 } else {
429 fn = REG_FN_MODIFY_BASE;
430 if (mr->set_reg) {
431 mode = MODE_ENABLE_REG;
432 reg_e = mr->set_reg;
433 reg_d = mr->set_reg;
434 } else {
435 mode = MODE_MASK_REG;
436 reg_e = mr->clr_reg;
437 reg_d = mr->clr_reg;
438 }
439 }
440
441 fn += (mr->reg_width >> 3) - 1;
442 return _INTC_MK(fn, mode,
443 intc_get_reg(d, reg_e),
444 intc_get_reg(d, reg_d),
445 1,
446 (mr->reg_width - 1) - j);
447 }
448 }
449
450 if (do_grps)
451 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
452
453 return 0;
454 }
455
456 static unsigned int __init intc_prio_data(struct intc_desc *desc,
457 struct intc_desc_int *d,
458 intc_enum enum_id, int do_grps)
459 {
460 struct intc_prio_reg *pr = desc->prio_regs;
461 unsigned int i, j, fn, mode, bit;
462 unsigned long reg_e, reg_d;
463
464 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
465 pr = desc->prio_regs + i;
466
467 for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
468 if (pr->enum_ids[j] != enum_id)
469 continue;
470
471 if (pr->set_reg && pr->clr_reg) {
472 fn = REG_FN_WRITE_BASE;
473 mode = MODE_PCLR_REG;
474 reg_e = pr->set_reg;
475 reg_d = pr->clr_reg;
476 } else {
477 fn = REG_FN_MODIFY_BASE;
478 mode = MODE_PRIO_REG;
479 if (!pr->set_reg)
480 BUG();
481 reg_e = pr->set_reg;
482 reg_d = pr->set_reg;
483 }
484
485 fn += (pr->reg_width >> 3) - 1;
486
487 BUG_ON((j + 1) * pr->field_width > pr->reg_width);
488
489 bit = pr->reg_width - ((j + 1) * pr->field_width);
490
491 return _INTC_MK(fn, mode,
492 intc_get_reg(d, reg_e),
493 intc_get_reg(d, reg_d),
494 pr->field_width, bit);
495 }
496 }
497
498 if (do_grps)
499 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
500
501 return 0;
502 }
503
504 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
505 static unsigned int __init intc_ack_data(struct intc_desc *desc,
506 struct intc_desc_int *d,
507 intc_enum enum_id)
508 {
509 struct intc_mask_reg *mr = desc->ack_regs;
510 unsigned int i, j, fn, mode;
511 unsigned long reg_e, reg_d;
512
513 for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
514 mr = desc->ack_regs + i;
515
516 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
517 if (mr->enum_ids[j] != enum_id)
518 continue;
519
520 fn = REG_FN_MODIFY_BASE;
521 mode = MODE_ENABLE_REG;
522 reg_e = mr->set_reg;
523 reg_d = mr->set_reg;
524
525 fn += (mr->reg_width >> 3) - 1;
526 return _INTC_MK(fn, mode,
527 intc_get_reg(d, reg_e),
528 intc_get_reg(d, reg_d),
529 1,
530 (mr->reg_width - 1) - j);
531 }
532 }
533
534 return 0;
535 }
536 #endif
537
538 static unsigned int __init intc_sense_data(struct intc_desc *desc,
539 struct intc_desc_int *d,
540 intc_enum enum_id)
541 {
542 struct intc_sense_reg *sr = desc->sense_regs;
543 unsigned int i, j, fn, bit;
544
545 for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
546 sr = desc->sense_regs + i;
547
548 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
549 if (sr->enum_ids[j] != enum_id)
550 continue;
551
552 fn = REG_FN_MODIFY_BASE;
553 fn += (sr->reg_width >> 3) - 1;
554
555 BUG_ON((j + 1) * sr->field_width > sr->reg_width);
556
557 bit = sr->reg_width - ((j + 1) * sr->field_width);
558
559 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
560 0, sr->field_width, bit);
561 }
562 }
563
564 return 0;
565 }
566
567 static void __init intc_register_irq(struct intc_desc *desc,
568 struct intc_desc_int *d,
569 intc_enum enum_id,
570 unsigned int irq)
571 {
572 struct intc_handle_int *hp;
573 unsigned int data[2], primary;
574
575 /* Prefer single interrupt source bitmap over other combinations:
576 * 1. bitmap, single interrupt source
577 * 2. priority, single interrupt source
578 * 3. bitmap, multiple interrupt sources (groups)
579 * 4. priority, multiple interrupt sources (groups)
580 */
581
582 data[0] = intc_mask_data(desc, d, enum_id, 0);
583 data[1] = intc_prio_data(desc, d, enum_id, 0);
584
585 primary = 0;
586 if (!data[0] && data[1])
587 primary = 1;
588
589 if (!data[0] && !data[1])
590 pr_warning("intc: missing unique irq mask for "
591 "irq %d (vect 0x%04x)\n", irq, irq2evt(irq));
592
593 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
594 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
595
596 if (!data[primary])
597 primary ^= 1;
598
599 BUG_ON(!data[primary]); /* must have primary masking method */
600
601 disable_irq_nosync(irq);
602 set_irq_chip_and_handler_name(irq, &d->chip,
603 handle_level_irq, "level");
604 set_irq_chip_data(irq, (void *)data[primary]);
605
606 /* set priority level
607 * - this needs to be at least 2 for 5-bit priorities on 7780
608 */
609 intc_prio_level[irq] = 2;
610
611 /* enable secondary masking method if present */
612 if (data[!primary])
613 _intc_enable(irq, data[!primary]);
614
615 /* add irq to d->prio list if priority is available */
616 if (data[1]) {
617 hp = d->prio + d->nr_prio;
618 hp->irq = irq;
619 hp->handle = data[1];
620
621 if (primary) {
622 /*
623 * only secondary priority should access registers, so
624 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
625 */
626
627 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
628 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
629 }
630 d->nr_prio++;
631 }
632
633 /* add irq to d->sense list if sense is available */
634 data[0] = intc_sense_data(desc, d, enum_id);
635 if (data[0]) {
636 (d->sense + d->nr_sense)->irq = irq;
637 (d->sense + d->nr_sense)->handle = data[0];
638 d->nr_sense++;
639 }
640
641 /* irq should be disabled by default */
642 d->chip.mask(irq);
643
644 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
645 if (desc->ack_regs)
646 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
647 #endif
648 }
649
650 static unsigned int __init save_reg(struct intc_desc_int *d,
651 unsigned int cnt,
652 unsigned long value,
653 unsigned int smp)
654 {
655 if (value) {
656 d->reg[cnt] = value;
657 #ifdef CONFIG_SMP
658 d->smp[cnt] = smp;
659 #endif
660 return 1;
661 }
662
663 return 0;
664 }
665
666 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
667 {
668 generic_handle_irq((unsigned int)get_irq_data(irq));
669 }
670
671 void __init register_intc_controller(struct intc_desc *desc)
672 {
673 unsigned int i, k, smp;
674 struct intc_desc_int *d;
675
676 d = kzalloc(sizeof(*d), GFP_NOWAIT);
677
678 INIT_LIST_HEAD(&d->list);
679 list_add(&d->list, &intc_list);
680
681 d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
682 d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
683 d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
684
685 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
686 d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
687 #endif
688 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
689 #ifdef CONFIG_SMP
690 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
691 #endif
692 k = 0;
693
694 if (desc->mask_regs) {
695 for (i = 0; i < desc->nr_mask_regs; i++) {
696 smp = IS_SMP(desc->mask_regs[i]);
697 k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
698 k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
699 }
700 }
701
702 if (desc->prio_regs) {
703 d->prio = kzalloc(desc->nr_vectors * sizeof(*d->prio), GFP_NOWAIT);
704
705 for (i = 0; i < desc->nr_prio_regs; i++) {
706 smp = IS_SMP(desc->prio_regs[i]);
707 k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
708 k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
709 }
710 }
711
712 if (desc->sense_regs) {
713 d->sense = kzalloc(desc->nr_vectors * sizeof(*d->sense), GFP_NOWAIT);
714
715 for (i = 0; i < desc->nr_sense_regs; i++) {
716 k += save_reg(d, k, desc->sense_regs[i].reg, 0);
717 }
718 }
719
720 d->chip.name = desc->name;
721 d->chip.mask = intc_disable;
722 d->chip.unmask = intc_enable;
723 d->chip.mask_ack = intc_disable;
724 d->chip.enable = intc_enable;
725 d->chip.disable = intc_disable;
726 d->chip.shutdown = intc_disable;
727 d->chip.set_type = intc_set_sense;
728 d->chip.set_wake = intc_set_wake;
729
730 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
731 if (desc->ack_regs) {
732 for (i = 0; i < desc->nr_ack_regs; i++)
733 k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
734
735 d->chip.mask_ack = intc_mask_ack;
736 }
737 #endif
738
739 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
740
741 /* register the vectors one by one */
742 for (i = 0; i < desc->nr_vectors; i++) {
743 struct intc_vect *vect = desc->vectors + i;
744 unsigned int irq = evt2irq(vect->vect);
745 struct irq_desc *irq_desc;
746
747 if (!vect->enum_id)
748 continue;
749
750 irq_desc = irq_to_desc_alloc_node(irq, numa_node_id());
751 if (unlikely(!irq_desc)) {
752 pr_info("can't get irq_desc for %d\n", irq);
753 continue;
754 }
755
756 intc_register_irq(desc, d, vect->enum_id, irq);
757
758 for (k = i + 1; k < desc->nr_vectors; k++) {
759 struct intc_vect *vect2 = desc->vectors + k;
760 unsigned int irq2 = evt2irq(vect2->vect);
761
762 if (vect->enum_id != vect2->enum_id)
763 continue;
764
765 /*
766 * In the case of multi-evt handling and sparse
767 * IRQ support, each vector still needs to have
768 * its own backing irq_desc.
769 */
770 irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id());
771 if (unlikely(!irq_desc)) {
772 pr_info("can't get irq_desc for %d\n", irq2);
773 continue;
774 }
775
776 vect2->enum_id = 0;
777
778 /* redirect this interrupts to the first one */
779 set_irq_chip_and_handler_name(irq2, &d->chip,
780 intc_redirect_irq, "redirect");
781 set_irq_data(irq2, (void *)irq);
782 }
783 }
784 }
785
786 static int intc_suspend(struct sys_device *dev, pm_message_t state)
787 {
788 struct intc_desc_int *d;
789 struct irq_desc *desc;
790 int irq;
791
792 /* get intc controller associated with this sysdev */
793 d = container_of(dev, struct intc_desc_int, sysdev);
794
795 switch (state.event) {
796 case PM_EVENT_ON:
797 if (d->state.event != PM_EVENT_FREEZE)
798 break;
799 for_each_irq_desc(irq, desc) {
800 if (desc->chip != &d->chip)
801 continue;
802 if (desc->status & IRQ_DISABLED)
803 intc_disable(irq);
804 else
805 intc_enable(irq);
806 }
807 break;
808 case PM_EVENT_FREEZE:
809 /* nothing has to be done */
810 break;
811 case PM_EVENT_SUSPEND:
812 /* enable wakeup irqs belonging to this intc controller */
813 for_each_irq_desc(irq, desc) {
814 if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip))
815 intc_enable(irq);
816 }
817 break;
818 }
819 d->state = state;
820
821 return 0;
822 }
823
824 static int intc_resume(struct sys_device *dev)
825 {
826 return intc_suspend(dev, PMSG_ON);
827 }
828
829 static struct sysdev_class intc_sysdev_class = {
830 .name = "intc",
831 .suspend = intc_suspend,
832 .resume = intc_resume,
833 };
834
835 /* register this intc as sysdev to allow suspend/resume */
836 static int __init register_intc_sysdevs(void)
837 {
838 struct intc_desc_int *d;
839 int error;
840 int id = 0;
841
842 error = sysdev_class_register(&intc_sysdev_class);
843 if (!error) {
844 list_for_each_entry(d, &intc_list, list) {
845 d->sysdev.id = id;
846 d->sysdev.cls = &intc_sysdev_class;
847 error = sysdev_register(&d->sysdev);
848 if (error)
849 break;
850 id++;
851 }
852 }
853
854 if (error)
855 pr_warning("intc: sysdev registration error\n");
856
857 return error;
858 }
859
860 device_initcall(register_intc_sysdevs);
Linux with added FPC-III support