?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / spi / pxa2xx_spi.c
blobc8c2b693ffacbb757b281f7190f02f118e4da3fc
1 /*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/spi/spi.h>
28 #include <linux/workqueue.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
31 #include <linux/gpio.h>
32
33 #include <asm/io.h>
34 #include <asm/irq.h>
35 #include <asm/delay.h>
36
37 #include <mach/dma.h>
38 #include <mach/regs-ssp.h>
39 #include <mach/ssp.h>
40 #include <mach/pxa2xx_spi.h>
41
42 MODULE_AUTHOR("Stephen Street");
43 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
44 MODULE_LICENSE("GPL");
45 MODULE_ALIAS("platform:pxa2xx-spi");
46
47 #define MAX_BUSES 3
48
49 #define RX_THRESH_DFLT 8
50 #define TX_THRESH_DFLT 8
51 #define TIMOUT_DFLT 1000
52
53 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
54 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
55 #define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0)
56 #define MAX_DMA_LEN 8191
57 #define DMA_ALIGNMENT 8
58
59 /*
60 * for testing SSCR1 changes that require SSP restart, basically
61 * everything except the service and interrupt enables, the pxa270 developer
62 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
63 * list, but the PXA255 dev man says all bits without really meaning the
64 * service and interrupt enables
65 */
66 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
67 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
68 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
69 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
70 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
71 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
72
73 #define DEFINE_SSP_REG(reg, off) \
74 static inline u32 read_##reg(void const __iomem *p) \
75 { return __raw_readl(p + (off)); } \
76 \
77 static inline void write_##reg(u32 v, void __iomem *p) \
78 { __raw_writel(v, p + (off)); }
79
80 DEFINE_SSP_REG(SSCR0, 0x00)
81 DEFINE_SSP_REG(SSCR1, 0x04)
82 DEFINE_SSP_REG(SSSR, 0x08)
83 DEFINE_SSP_REG(SSITR, 0x0c)
84 DEFINE_SSP_REG(SSDR, 0x10)
85 DEFINE_SSP_REG(SSTO, 0x28)
86 DEFINE_SSP_REG(SSPSP, 0x2c)
87
88 #define START_STATE ((void*)0)
89 #define RUNNING_STATE ((void*)1)
90 #define DONE_STATE ((void*)2)
91 #define ERROR_STATE ((void*)-1)
92
93 #define QUEUE_RUNNING 0
94 #define QUEUE_STOPPED 1
95
96 struct driver_data {
97 /* Driver model hookup */
98 struct platform_device *pdev;
99
100 /* SSP Info */
101 struct ssp_device *ssp;
102
103 /* SPI framework hookup */
104 enum pxa_ssp_type ssp_type;
105 struct spi_master *master;
106
107 /* PXA hookup */
108 struct pxa2xx_spi_master *master_info;
109
110 /* DMA setup stuff */
111 int rx_channel;
112 int tx_channel;
113 u32 *null_dma_buf;
114
115 /* SSP register addresses */
116 void __iomem *ioaddr;
117 u32 ssdr_physical;
118
119 /* SSP masks*/
120 u32 dma_cr1;
121 u32 int_cr1;
122 u32 clear_sr;
123 u32 mask_sr;
124
125 /* Driver message queue */
126 struct workqueue_struct *workqueue;
127 struct work_struct pump_messages;
128 spinlock_t lock;
129 struct list_head queue;
130 int busy;
131 int run;
132
133 /* Message Transfer pump */
134 struct tasklet_struct pump_transfers;
135
136 /* Current message transfer state info */
137 struct spi_message* cur_msg;
138 struct spi_transfer* cur_transfer;
139 struct chip_data *cur_chip;
140 size_t len;
141 void *tx;
142 void *tx_end;
143 void *rx;
144 void *rx_end;
145 int dma_mapped;
146 dma_addr_t rx_dma;
147 dma_addr_t tx_dma;
148 size_t rx_map_len;
149 size_t tx_map_len;
150 u8 n_bytes;
151 u32 dma_width;
152 int (*write)(struct driver_data *drv_data);
153 int (*read)(struct driver_data *drv_data);
154 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
155 void (*cs_control)(u32 command);
156 };
157
158 struct chip_data {
159 u32 cr0;
160 u32 cr1;
161 u32 psp;
162 u32 timeout;
163 u8 n_bytes;
164 u32 dma_width;
165 u32 dma_burst_size;
166 u32 threshold;
167 u32 dma_threshold;
168 u8 enable_dma;
169 u8 bits_per_word;
170 u32 speed_hz;
171 int gpio_cs;
172 int gpio_cs_inverted;
173 int (*write)(struct driver_data *drv_data);
174 int (*read)(struct driver_data *drv_data);
175 void (*cs_control)(u32 command);
176 };
177
178 static void pump_messages(struct work_struct *work);
179
180 static void cs_assert(struct driver_data *drv_data)
181 {
182 struct chip_data *chip = drv_data->cur_chip;
183
184 if (chip->cs_control) {
185 chip->cs_control(PXA2XX_CS_ASSERT);
186 return;
187 }
188
189 if (gpio_is_valid(chip->gpio_cs))
190 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
191 }
192
193 static void cs_deassert(struct driver_data *drv_data)
194 {
195 struct chip_data *chip = drv_data->cur_chip;
196
197 if (chip->cs_control) {
198 chip->cs_control(PXA2XX_CS_DEASSERT);
199 return;
200 }
201
202 if (gpio_is_valid(chip->gpio_cs))
203 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
204 }
205
206 static int flush(struct driver_data *drv_data)
207 {
208 unsigned long limit = loops_per_jiffy << 1;
209
210 void __iomem *reg = drv_data->ioaddr;
211
212 do {
213 while (read_SSSR(reg) & SSSR_RNE) {
214 read_SSDR(reg);
215 }
216 } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
217 write_SSSR(SSSR_ROR, reg);
218
219 return limit;
220 }
221
222 static int null_writer(struct driver_data *drv_data)
223 {
224 void __iomem *reg = drv_data->ioaddr;
225 u8 n_bytes = drv_data->n_bytes;
226
227 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
228 || (drv_data->tx == drv_data->tx_end))
229 return 0;
230
231 write_SSDR(0, reg);
232 drv_data->tx += n_bytes;
233
234 return 1;
235 }
236
237 static int null_reader(struct driver_data *drv_data)
238 {
239 void __iomem *reg = drv_data->ioaddr;
240 u8 n_bytes = drv_data->n_bytes;
241
242 while ((read_SSSR(reg) & SSSR_RNE)
243 && (drv_data->rx < drv_data->rx_end)) {
244 read_SSDR(reg);
245 drv_data->rx += n_bytes;
246 }
247
248 return drv_data->rx == drv_data->rx_end;
249 }
250
251 static int u8_writer(struct driver_data *drv_data)
252 {
253 void __iomem *reg = drv_data->ioaddr;
254
255 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
256 || (drv_data->tx == drv_data->tx_end))
257 return 0;
258
259 write_SSDR(*(u8 *)(drv_data->tx), reg);
260 ++drv_data->tx;
261
262 return 1;
263 }
264
265 static int u8_reader(struct driver_data *drv_data)
266 {
267 void __iomem *reg = drv_data->ioaddr;
268
269 while ((read_SSSR(reg) & SSSR_RNE)
270 && (drv_data->rx < drv_data->rx_end)) {
271 *(u8 *)(drv_data->rx) = read_SSDR(reg);
272 ++drv_data->rx;
273 }
274
275 return drv_data->rx == drv_data->rx_end;
276 }
277
278 static int u16_writer(struct driver_data *drv_data)
279 {
280 void __iomem *reg = drv_data->ioaddr;
281
282 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
283 || (drv_data->tx == drv_data->tx_end))
284 return 0;
285
286 write_SSDR(*(u16 *)(drv_data->tx), reg);
287 drv_data->tx += 2;
288
289 return 1;
290 }
291
292 static int u16_reader(struct driver_data *drv_data)
293 {
294 void __iomem *reg = drv_data->ioaddr;
295
296 while ((read_SSSR(reg) & SSSR_RNE)
297 && (drv_data->rx < drv_data->rx_end)) {
298 *(u16 *)(drv_data->rx) = read_SSDR(reg);
299 drv_data->rx += 2;
300 }
301
302 return drv_data->rx == drv_data->rx_end;
303 }
304
305 static int u32_writer(struct driver_data *drv_data)
306 {
307 void __iomem *reg = drv_data->ioaddr;
308
309 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
310 || (drv_data->tx == drv_data->tx_end))
311 return 0;
312
313 write_SSDR(*(u32 *)(drv_data->tx), reg);
314 drv_data->tx += 4;
315
316 return 1;
317 }
318
319 static int u32_reader(struct driver_data *drv_data)
320 {
321 void __iomem *reg = drv_data->ioaddr;
322
323 while ((read_SSSR(reg) & SSSR_RNE)
324 && (drv_data->rx < drv_data->rx_end)) {
325 *(u32 *)(drv_data->rx) = read_SSDR(reg);
326 drv_data->rx += 4;
327 }
328
329 return drv_data->rx == drv_data->rx_end;
330 }
331
332 static void *next_transfer(struct driver_data *drv_data)
333 {
334 struct spi_message *msg = drv_data->cur_msg;
335 struct spi_transfer *trans = drv_data->cur_transfer;
336
337 /* Move to next transfer */
338 if (trans->transfer_list.next != &msg->transfers) {
339 drv_data->cur_transfer =
340 list_entry(trans->transfer_list.next,
341 struct spi_transfer,
342 transfer_list);
343 return RUNNING_STATE;
344 } else
345 return DONE_STATE;
346 }
347
348 static int map_dma_buffers(struct driver_data *drv_data)
349 {
350 struct spi_message *msg = drv_data->cur_msg;
351 struct device *dev = &msg->spi->dev;
352
353 if (!drv_data->cur_chip->enable_dma)
354 return 0;
355
356 if (msg->is_dma_mapped)
357 return drv_data->rx_dma && drv_data->tx_dma;
358
359 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
360 return 0;
361
362 /* Modify setup if rx buffer is null */
363 if (drv_data->rx == NULL) {
364 *drv_data->null_dma_buf = 0;
365 drv_data->rx = drv_data->null_dma_buf;
366 drv_data->rx_map_len = 4;
367 } else
368 drv_data->rx_map_len = drv_data->len;
369
370
371 /* Modify setup if tx buffer is null */
372 if (drv_data->tx == NULL) {
373 *drv_data->null_dma_buf = 0;
374 drv_data->tx = drv_data->null_dma_buf;
375 drv_data->tx_map_len = 4;
376 } else
377 drv_data->tx_map_len = drv_data->len;
378
379 /* Stream map the tx buffer. Always do DMA_TO_DEVICE first
380 * so we flush the cache *before* invalidating it, in case
381 * the tx and rx buffers overlap.
382 */
383 drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
384 drv_data->tx_map_len, DMA_TO_DEVICE);
385 if (dma_mapping_error(dev, drv_data->tx_dma))
386 return 0;
387
388 /* Stream map the rx buffer */
389 drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
390 drv_data->rx_map_len, DMA_FROM_DEVICE);
391 if (dma_mapping_error(dev, drv_data->rx_dma)) {
392 dma_unmap_single(dev, drv_data->tx_dma,
393 drv_data->tx_map_len, DMA_TO_DEVICE);
394 return 0;
395 }
396
397 return 1;
398 }
399
400 static void unmap_dma_buffers(struct driver_data *drv_data)
401 {
402 struct device *dev;
403
404 if (!drv_data->dma_mapped)
405 return;
406
407 if (!drv_data->cur_msg->is_dma_mapped) {
408 dev = &drv_data->cur_msg->spi->dev;
409 dma_unmap_single(dev, drv_data->rx_dma,
410 drv_data->rx_map_len, DMA_FROM_DEVICE);
411 dma_unmap_single(dev, drv_data->tx_dma,
412 drv_data->tx_map_len, DMA_TO_DEVICE);
413 }
414
415 drv_data->dma_mapped = 0;
416 }
417
418 /* caller already set message->status; dma and pio irqs are blocked */
419 static void giveback(struct driver_data *drv_data)
420 {
421 struct spi_transfer* last_transfer;
422 unsigned long flags;
423 struct spi_message *msg;
424
425 spin_lock_irqsave(&drv_data->lock, flags);
426 msg = drv_data->cur_msg;
427 drv_data->cur_msg = NULL;
428 drv_data->cur_transfer = NULL;
429 queue_work(drv_data->workqueue, &drv_data->pump_messages);
430 spin_unlock_irqrestore(&drv_data->lock, flags);
431
432 last_transfer = list_entry(msg->transfers.prev,
433 struct spi_transfer,
434 transfer_list);
435
436 /* Delay if requested before any change in chip select */
437 if (last_transfer->delay_usecs)
438 udelay(last_transfer->delay_usecs);
439
440 /* Drop chip select UNLESS cs_change is true or we are returning
441 * a message with an error, or next message is for another chip
442 */
443 if (!last_transfer->cs_change)
444 cs_deassert(drv_data);
445 else {
446 struct spi_message *next_msg;
447
448 /* Holding of cs was hinted, but we need to make sure
449 * the next message is for the same chip. Don't waste
450 * time with the following tests unless this was hinted.
451 *
452 * We cannot postpone this until pump_messages, because
453 * after calling msg->complete (below) the driver that
454 * sent the current message could be unloaded, which
455 * could invalidate the cs_control() callback...
456 */
457
458 /* get a pointer to the next message, if any */
459 spin_lock_irqsave(&drv_data->lock, flags);
460 if (list_empty(&drv_data->queue))
461 next_msg = NULL;
462 else
463 next_msg = list_entry(drv_data->queue.next,
464 struct spi_message, queue);
465 spin_unlock_irqrestore(&drv_data->lock, flags);
466
467 /* see if the next and current messages point
468 * to the same chip
469 */
470 if (next_msg && next_msg->spi != msg->spi)
471 next_msg = NULL;
472 if (!next_msg || msg->state == ERROR_STATE)
473 cs_deassert(drv_data);
474 }
475
476 msg->state = NULL;
477 if (msg->complete)
478 msg->complete(msg->context);
479
480 drv_data->cur_chip = NULL;
481 }
482
483 static int wait_ssp_rx_stall(void const __iomem *ioaddr)
484 {
485 unsigned long limit = loops_per_jiffy << 1;
486
487 while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit)
488 cpu_relax();
489
490 return limit;
491 }
492
493 static int wait_dma_channel_stop(int channel)
494 {
495 unsigned long limit = loops_per_jiffy << 1;
496
497 while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit)
498 cpu_relax();
499
500 return limit;
501 }
502
503 static void dma_error_stop(struct driver_data *drv_data, const char *msg)
504 {
505 void __iomem *reg = drv_data->ioaddr;
506
507 /* Stop and reset */
508 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
509 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
510 write_SSSR(drv_data->clear_sr, reg);
511 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
512 if (drv_data->ssp_type != PXA25x_SSP)
513 write_SSTO(0, reg);
514 flush(drv_data);
515 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
516
517 unmap_dma_buffers(drv_data);
518
519 dev_err(&drv_data->pdev->dev, "%s\n", msg);
520
521 drv_data->cur_msg->state = ERROR_STATE;
522 tasklet_schedule(&drv_data->pump_transfers);
523 }
524
525 static void dma_transfer_complete(struct driver_data *drv_data)
526 {
527 void __iomem *reg = drv_data->ioaddr;
528 struct spi_message *msg = drv_data->cur_msg;
529
530 /* Clear and disable interrupts on SSP and DMA channels*/
531 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
532 write_SSSR(drv_data->clear_sr, reg);
533 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
534 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
535
536 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
537 dev_err(&drv_data->pdev->dev,
538 "dma_handler: dma rx channel stop failed\n");
539
540 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
541 dev_err(&drv_data->pdev->dev,
542 "dma_transfer: ssp rx stall failed\n");
543
544 unmap_dma_buffers(drv_data);
545
546 /* update the buffer pointer for the amount completed in dma */
547 drv_data->rx += drv_data->len -
548 (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
549
550 /* read trailing data from fifo, it does not matter how many
551 * bytes are in the fifo just read until buffer is full
552 * or fifo is empty, which ever occurs first */
553 drv_data->read(drv_data);
554
555 /* return count of what was actually read */
556 msg->actual_length += drv_data->len -
557 (drv_data->rx_end - drv_data->rx);
558
559 /* Transfer delays and chip select release are
560 * handled in pump_transfers or giveback
561 */
562
563 /* Move to next transfer */
564 msg->state = next_transfer(drv_data);
565
566 /* Schedule transfer tasklet */
567 tasklet_schedule(&drv_data->pump_transfers);
568 }
569
570 static void dma_handler(int channel, void *data)
571 {
572 struct driver_data *drv_data = data;
573 u32 irq_status = DCSR(channel) & DMA_INT_MASK;
574
575 if (irq_status & DCSR_BUSERR) {
576
577 if (channel == drv_data->tx_channel)
578 dma_error_stop(drv_data,
579 "dma_handler: "
580 "bad bus address on tx channel");
581 else
582 dma_error_stop(drv_data,
583 "dma_handler: "
584 "bad bus address on rx channel");
585 return;
586 }
587
588 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
589 if ((channel == drv_data->tx_channel)
590 && (irq_status & DCSR_ENDINTR)
591 && (drv_data->ssp_type == PXA25x_SSP)) {
592
593 /* Wait for rx to stall */
594 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
595 dev_err(&drv_data->pdev->dev,
596 "dma_handler: ssp rx stall failed\n");
597
598 /* finish this transfer, start the next */
599 dma_transfer_complete(drv_data);
600 }
601 }
602
603 static irqreturn_t dma_transfer(struct driver_data *drv_data)
604 {
605 u32 irq_status;
606 void __iomem *reg = drv_data->ioaddr;
607
608 irq_status = read_SSSR(reg) & drv_data->mask_sr;
609 if (irq_status & SSSR_ROR) {
610 dma_error_stop(drv_data, "dma_transfer: fifo overrun");
611 return IRQ_HANDLED;
612 }
613
614 /* Check for false positive timeout */
615 if ((irq_status & SSSR_TINT)
616 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
617 write_SSSR(SSSR_TINT, reg);
618 return IRQ_HANDLED;
619 }
620
621 if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
622
623 /* Clear and disable timeout interrupt, do the rest in
624 * dma_transfer_complete */
625 if (drv_data->ssp_type != PXA25x_SSP)
626 write_SSTO(0, reg);
627
628 /* finish this transfer, start the next */
629 dma_transfer_complete(drv_data);
630
631 return IRQ_HANDLED;
632 }
633
634 /* Opps problem detected */
635 return IRQ_NONE;
636 }
637
638 static void int_error_stop(struct driver_data *drv_data, const char* msg)
639 {
640 void __iomem *reg = drv_data->ioaddr;
641
642 /* Stop and reset SSP */
643 write_SSSR(drv_data->clear_sr, reg);
644 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
645 if (drv_data->ssp_type != PXA25x_SSP)
646 write_SSTO(0, reg);
647 flush(drv_data);
648 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
649
650 dev_err(&drv_data->pdev->dev, "%s\n", msg);
651
652 drv_data->cur_msg->state = ERROR_STATE;
653 tasklet_schedule(&drv_data->pump_transfers);
654 }
655
656 static void int_transfer_complete(struct driver_data *drv_data)
657 {
658 void __iomem *reg = drv_data->ioaddr;
659
660 /* Stop SSP */
661 write_SSSR(drv_data->clear_sr, reg);
662 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
663 if (drv_data->ssp_type != PXA25x_SSP)
664 write_SSTO(0, reg);
665
666 /* Update total byte transfered return count actual bytes read */
667 drv_data->cur_msg->actual_length += drv_data->len -
668 (drv_data->rx_end - drv_data->rx);
669
670 /* Transfer delays and chip select release are
671 * handled in pump_transfers or giveback
672 */
673
674 /* Move to next transfer */
675 drv_data->cur_msg->state = next_transfer(drv_data);
676
677 /* Schedule transfer tasklet */
678 tasklet_schedule(&drv_data->pump_transfers);
679 }
680
681 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
682 {
683 void __iomem *reg = drv_data->ioaddr;
684
685 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
686 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
687
688 u32 irq_status = read_SSSR(reg) & irq_mask;
689
690 if (irq_status & SSSR_ROR) {
691 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
692 return IRQ_HANDLED;
693 }
694
695 if (irq_status & SSSR_TINT) {
696 write_SSSR(SSSR_TINT, reg);
697 if (drv_data->read(drv_data)) {
698 int_transfer_complete(drv_data);
699 return IRQ_HANDLED;
700 }
701 }
702
703 /* Drain rx fifo, Fill tx fifo and prevent overruns */
704 do {
705 if (drv_data->read(drv_data)) {
706 int_transfer_complete(drv_data);
707 return IRQ_HANDLED;
708 }
709 } while (drv_data->write(drv_data));
710
711 if (drv_data->read(drv_data)) {
712 int_transfer_complete(drv_data);
713 return IRQ_HANDLED;
714 }
715
716 if (drv_data->tx == drv_data->tx_end) {
717 write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
718 /* PXA25x_SSP has no timeout, read trailing bytes */
719 if (drv_data->ssp_type == PXA25x_SSP) {
720 if (!wait_ssp_rx_stall(reg))
721 {
722 int_error_stop(drv_data, "interrupt_transfer: "
723 "rx stall failed");
724 return IRQ_HANDLED;
725 }
726 if (!drv_data->read(drv_data))
727 {
728 int_error_stop(drv_data,
729 "interrupt_transfer: "
730 "trailing byte read failed");
731 return IRQ_HANDLED;
732 }
733 int_transfer_complete(drv_data);
734 }
735 }
736
737 /* We did something */
738 return IRQ_HANDLED;
739 }
740
741 static irqreturn_t ssp_int(int irq, void *dev_id)
742 {
743 struct driver_data *drv_data = dev_id;
744 void __iomem *reg = drv_data->ioaddr;
745
746 if (!drv_data->cur_msg) {
747
748 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
749 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
750 if (drv_data->ssp_type != PXA25x_SSP)
751 write_SSTO(0, reg);
752 write_SSSR(drv_data->clear_sr, reg);
753
754 dev_err(&drv_data->pdev->dev, "bad message state "
755 "in interrupt handler\n");
756
757 /* Never fail */
758 return IRQ_HANDLED;
759 }
760
761 return drv_data->transfer_handler(drv_data);
762 }
763
764 static int set_dma_burst_and_threshold(struct chip_data *chip,
765 struct spi_device *spi,
766 u8 bits_per_word, u32 *burst_code,
767 u32 *threshold)
768 {
769 struct pxa2xx_spi_chip *chip_info =
770 (struct pxa2xx_spi_chip *)spi->controller_data;
771 int bytes_per_word;
772 int burst_bytes;
773 int thresh_words;
774 int req_burst_size;
775 int retval = 0;
776
777 /* Set the threshold (in registers) to equal the same amount of data
778 * as represented by burst size (in bytes). The computation below
779 * is (burst_size rounded up to nearest 8 byte, word or long word)
780 * divided by (bytes/register); the tx threshold is the inverse of
781 * the rx, so that there will always be enough data in the rx fifo
782 * to satisfy a burst, and there will always be enough space in the
783 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
784 * there is not enough space), there must always remain enough empty
785 * space in the rx fifo for any data loaded to the tx fifo.
786 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
787 * will be 8, or half the fifo;
788 * The threshold can only be set to 2, 4 or 8, but not 16, because
789 * to burst 16 to the tx fifo, the fifo would have to be empty;
790 * however, the minimum fifo trigger level is 1, and the tx will
791 * request service when the fifo is at this level, with only 15 spaces.
792 */
793
794 /* find bytes/word */
795 if (bits_per_word <= 8)
796 bytes_per_word = 1;
797 else if (bits_per_word <= 16)
798 bytes_per_word = 2;
799 else
800 bytes_per_word = 4;
801
802 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
803 if (chip_info)
804 req_burst_size = chip_info->dma_burst_size;
805 else {
806 switch (chip->dma_burst_size) {
807 default:
808 /* if the default burst size is not set,
809 * do it now */
810 chip->dma_burst_size = DCMD_BURST8;
811 case DCMD_BURST8:
812 req_burst_size = 8;
813 break;
814 case DCMD_BURST16:
815 req_burst_size = 16;
816 break;
817 case DCMD_BURST32:
818 req_burst_size = 32;
819 break;
820 }
821 }
822 if (req_burst_size <= 8) {
823 *burst_code = DCMD_BURST8;
824 burst_bytes = 8;
825 } else if (req_burst_size <= 16) {
826 if (bytes_per_word == 1) {
827 /* don't burst more than 1/2 the fifo */
828 *burst_code = DCMD_BURST8;
829 burst_bytes = 8;
830 retval = 1;
831 } else {
832 *burst_code = DCMD_BURST16;
833 burst_bytes = 16;
834 }
835 } else {
836 if (bytes_per_word == 1) {
837 /* don't burst more than 1/2 the fifo */
838 *burst_code = DCMD_BURST8;
839 burst_bytes = 8;
840 retval = 1;
841 } else if (bytes_per_word == 2) {
842 /* don't burst more than 1/2 the fifo */
843 *burst_code = DCMD_BURST16;
844 burst_bytes = 16;
845 retval = 1;
846 } else {
847 *burst_code = DCMD_BURST32;
848 burst_bytes = 32;
849 }
850 }
851
852 thresh_words = burst_bytes / bytes_per_word;
853
854 /* thresh_words will be between 2 and 8 */
855 *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
856 | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
857
858 return retval;
859 }
860
861 static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
862 {
863 unsigned long ssp_clk = clk_get_rate(ssp->clk);
864
865 if (ssp->type == PXA25x_SSP)
866 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
867 else
868 return ((ssp_clk / rate - 1) & 0xfff) << 8;
869 }
870
871 static void pump_transfers(unsigned long data)
872 {
873 struct driver_data *drv_data = (struct driver_data *)data;
874 struct spi_message *message = NULL;
875 struct spi_transfer *transfer = NULL;
876 struct spi_transfer *previous = NULL;
877 struct chip_data *chip = NULL;
878 struct ssp_device *ssp = drv_data->ssp;
879 void __iomem *reg = drv_data->ioaddr;
880 u32 clk_div = 0;
881 u8 bits = 0;
882 u32 speed = 0;
883 u32 cr0;
884 u32 cr1;
885 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
886 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
887
888 /* Get current state information */
889 message = drv_data->cur_msg;
890 transfer = drv_data->cur_transfer;
891 chip = drv_data->cur_chip;
892
893 /* Handle for abort */
894 if (message->state == ERROR_STATE) {
895 message->status = -EIO;
896 giveback(drv_data);
897 return;
898 }
899
900 /* Handle end of message */
901 if (message->state == DONE_STATE) {
902 message->status = 0;
903 giveback(drv_data);
904 return;
905 }
906
907 /* Delay if requested at end of transfer before CS change */
908 if (message->state == RUNNING_STATE) {
909 previous = list_entry(transfer->transfer_list.prev,
910 struct spi_transfer,
911 transfer_list);
912 if (previous->delay_usecs)
913 udelay(previous->delay_usecs);
914
915 /* Drop chip select only if cs_change is requested */
916 if (previous->cs_change)
917 cs_deassert(drv_data);
918 }
919
920 /* Check for transfers that need multiple DMA segments */
921 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
922
923 /* reject already-mapped transfers; PIO won't always work */
924 if (message->is_dma_mapped
925 || transfer->rx_dma || transfer->tx_dma) {
926 dev_err(&drv_data->pdev->dev,
927 "pump_transfers: mapped transfer length "
928 "of %u is greater than %d\n",
929 transfer->len, MAX_DMA_LEN);
930 message->status = -EINVAL;
931 giveback(drv_data);
932 return;
933 }
934
935 /* warn ... we force this to PIO mode */
936 if (printk_ratelimit())
937 dev_warn(&message->spi->dev, "pump_transfers: "
938 "DMA disabled for transfer length %ld "
939 "greater than %d\n",
940 (long)drv_data->len, MAX_DMA_LEN);
941 }
942
943 /* Setup the transfer state based on the type of transfer */
944 if (flush(drv_data) == 0) {
945 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
946 message->status = -EIO;
947 giveback(drv_data);
948 return;
949 }
950 drv_data->n_bytes = chip->n_bytes;
951 drv_data->dma_width = chip->dma_width;
952 drv_data->tx = (void *)transfer->tx_buf;
953 drv_data->tx_end = drv_data->tx + transfer->len;
954 drv_data->rx = transfer->rx_buf;
955 drv_data->rx_end = drv_data->rx + transfer->len;
956 drv_data->rx_dma = transfer->rx_dma;
957 drv_data->tx_dma = transfer->tx_dma;
958 drv_data->len = transfer->len & DCMD_LENGTH;
959 drv_data->write = drv_data->tx ? chip->write : null_writer;
960 drv_data->read = drv_data->rx ? chip->read : null_reader;
961
962 /* Change speed and bit per word on a per transfer */
963 cr0 = chip->cr0;
964 if (transfer->speed_hz || transfer->bits_per_word) {
965
966 bits = chip->bits_per_word;
967 speed = chip->speed_hz;
968
969 if (transfer->speed_hz)
970 speed = transfer->speed_hz;
971
972 if (transfer->bits_per_word)
973 bits = transfer->bits_per_word;
974
975 clk_div = ssp_get_clk_div(ssp, speed);
976
977 if (bits <= 8) {
978 drv_data->n_bytes = 1;
979 drv_data->dma_width = DCMD_WIDTH1;
980 drv_data->read = drv_data->read != null_reader ?
981 u8_reader : null_reader;
982 drv_data->write = drv_data->write != null_writer ?
983 u8_writer : null_writer;
984 } else if (bits <= 16) {
985 drv_data->n_bytes = 2;
986 drv_data->dma_width = DCMD_WIDTH2;
987 drv_data->read = drv_data->read != null_reader ?
988 u16_reader : null_reader;
989 drv_data->write = drv_data->write != null_writer ?
990 u16_writer : null_writer;
991 } else if (bits <= 32) {
992 drv_data->n_bytes = 4;
993 drv_data->dma_width = DCMD_WIDTH4;
994 drv_data->read = drv_data->read != null_reader ?
995 u32_reader : null_reader;
996 drv_data->write = drv_data->write != null_writer ?
997 u32_writer : null_writer;
998 }
999 /* if bits/word is changed in dma mode, then must check the
1000 * thresholds and burst also */
1001 if (chip->enable_dma) {
1002 if (set_dma_burst_and_threshold(chip, message->spi,
1003 bits, &dma_burst,
1004 &dma_thresh))
1005 if (printk_ratelimit())
1006 dev_warn(&message->spi->dev,
1007 "pump_transfers: "
1008 "DMA burst size reduced to "
1009 "match bits_per_word\n");
1010 }
1011
1012 cr0 = clk_div
1013 | SSCR0_Motorola
1014 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
1015 | SSCR0_SSE
1016 | (bits > 16 ? SSCR0_EDSS : 0);
1017 }
1018
1019 message->state = RUNNING_STATE;
1020
1021 /* Try to map dma buffer and do a dma transfer if successful, but
1022 * only if the length is non-zero and less than MAX_DMA_LEN.
1023 *
1024 * Zero-length non-descriptor DMA is illegal on PXA2xx; force use
1025 * of PIO instead. Care is needed above because the transfer may
1026 * have have been passed with buffers that are already dma mapped.
1027 * A zero-length transfer in PIO mode will not try to write/read
1028 * to/from the buffers
1029 *
1030 * REVISIT large transfers are exactly where we most want to be
1031 * using DMA. If this happens much, split those transfers into
1032 * multiple DMA segments rather than forcing PIO.
1033 */
1034 drv_data->dma_mapped = 0;
1035 if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN)
1036 drv_data->dma_mapped = map_dma_buffers(drv_data);
1037 if (drv_data->dma_mapped) {
1038
1039 /* Ensure we have the correct interrupt handler */
1040 drv_data->transfer_handler = dma_transfer;
1041
1042 /* Setup rx DMA Channel */
1043 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
1044 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
1045 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
1046 if (drv_data->rx == drv_data->null_dma_buf)
1047 /* No target address increment */
1048 DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
1049 | drv_data->dma_width
1050 | dma_burst
1051 | drv_data->len;
1052 else
1053 DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
1054 | DCMD_FLOWSRC
1055 | drv_data->dma_width
1056 | dma_burst
1057 | drv_data->len;
1058
1059 /* Setup tx DMA Channel */
1060 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
1061 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
1062 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
1063 if (drv_data->tx == drv_data->null_dma_buf)
1064 /* No source address increment */
1065 DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
1066 | drv_data->dma_width
1067 | dma_burst
1068 | drv_data->len;
1069 else
1070 DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
1071 | DCMD_FLOWTRG
1072 | drv_data->dma_width
1073 | dma_burst
1074 | drv_data->len;
1075
1076 /* Enable dma end irqs on SSP to detect end of transfer */
1077 if (drv_data->ssp_type == PXA25x_SSP)
1078 DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
1079
1080 /* Clear status and start DMA engine */
1081 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1082 write_SSSR(drv_data->clear_sr, reg);
1083 DCSR(drv_data->rx_channel) |= DCSR_RUN;
1084 DCSR(drv_data->tx_channel) |= DCSR_RUN;
1085 } else {
1086 /* Ensure we have the correct interrupt handler */
1087 drv_data->transfer_handler = interrupt_transfer;
1088
1089 /* Clear status */
1090 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1091 write_SSSR(drv_data->clear_sr, reg);
1092 }
1093
1094 /* see if we need to reload the config registers */
1095 if ((read_SSCR0(reg) != cr0)
1096 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
1097 (cr1 & SSCR1_CHANGE_MASK)) {
1098
1099 /* stop the SSP, and update the other bits */
1100 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
1101 if (drv_data->ssp_type != PXA25x_SSP)
1102 write_SSTO(chip->timeout, reg);
1103 /* first set CR1 without interrupt and service enables */
1104 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
1105 /* restart the SSP */
1106 write_SSCR0(cr0, reg);
1107
1108 } else {
1109 if (drv_data->ssp_type != PXA25x_SSP)
1110 write_SSTO(chip->timeout, reg);
1111 }
1112
1113 cs_assert(drv_data);
1114
1115 /* after chip select, release the data by enabling service
1116 * requests and interrupts, without changing any mode bits */
1117 write_SSCR1(cr1, reg);
1118 }
1119
1120 static void pump_messages(struct work_struct *work)
1121 {
1122 struct driver_data *drv_data =
1123 container_of(work, struct driver_data, pump_messages);
1124 unsigned long flags;
1125
1126 /* Lock queue and check for queue work */
1127 spin_lock_irqsave(&drv_data->lock, flags);
1128 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1129 drv_data->busy = 0;
1130 spin_unlock_irqrestore(&drv_data->lock, flags);
1131 return;
1132 }
1133
1134 /* Make sure we are not already running a message */
1135 if (drv_data->cur_msg) {
1136 spin_unlock_irqrestore(&drv_data->lock, flags);
1137 return;
1138 }
1139
1140 /* Extract head of queue */
1141 drv_data->cur_msg = list_entry(drv_data->queue.next,
1142 struct spi_message, queue);
1143 list_del_init(&drv_data->cur_msg->queue);
1144
1145 /* Initial message state*/
1146 drv_data->cur_msg->state = START_STATE;
1147 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1148 struct spi_transfer,
1149 transfer_list);
1150
1151 /* prepare to setup the SSP, in pump_transfers, using the per
1152 * chip configuration */
1153 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1154
1155 /* Mark as busy and launch transfers */
1156 tasklet_schedule(&drv_data->pump_transfers);
1157
1158 drv_data->busy = 1;
1159 spin_unlock_irqrestore(&drv_data->lock, flags);
1160 }
1161
1162 static int transfer(struct spi_device *spi, struct spi_message *msg)
1163 {
1164 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1165 unsigned long flags;
1166
1167 spin_lock_irqsave(&drv_data->lock, flags);
1168
1169 if (drv_data->run == QUEUE_STOPPED) {
1170 spin_unlock_irqrestore(&drv_data->lock, flags);
1171 return -ESHUTDOWN;
1172 }
1173
1174 msg->actual_length = 0;
1175 msg->status = -EINPROGRESS;
1176 msg->state = START_STATE;
1177
1178 list_add_tail(&msg->queue, &drv_data->queue);
1179
1180 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1181 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1182
1183 spin_unlock_irqrestore(&drv_data->lock, flags);
1184
1185 return 0;
1186 }
1187
1188 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1189 struct pxa2xx_spi_chip *chip_info)
1190 {
1191 int err = 0;
1192
1193 if (chip == NULL || chip_info == NULL)
1194 return 0;
1195
1196 /* NOTE: setup() can be called multiple times, possibly with
1197 * different chip_info, release previously requested GPIO
1198 */
1199 if (gpio_is_valid(chip->gpio_cs))
1200 gpio_free(chip->gpio_cs);
1201
1202 /* If (*cs_control) is provided, ignore GPIO chip select */
1203 if (chip_info->cs_control) {
1204 chip->cs_control = chip_info->cs_control;
1205 return 0;
1206 }
1207
1208 if (gpio_is_valid(chip_info->gpio_cs)) {
1209 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1210 if (err) {
1211 dev_err(&spi->dev, "failed to request chip select "
1212 "GPIO%d\n", chip_info->gpio_cs);
1213 return err;
1214 }
1215
1216 chip->gpio_cs = chip_info->gpio_cs;
1217 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1218
1219 err = gpio_direction_output(chip->gpio_cs,
1220 !chip->gpio_cs_inverted);
1221 }
1222
1223 return err;
1224 }
1225
1226 static int setup(struct spi_device *spi)
1227 {
1228 struct pxa2xx_spi_chip *chip_info = NULL;
1229 struct chip_data *chip;
1230 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1231 struct ssp_device *ssp = drv_data->ssp;
1232 unsigned int clk_div;
1233 uint tx_thres = TX_THRESH_DFLT;
1234 uint rx_thres = RX_THRESH_DFLT;
1235
1236 if (drv_data->ssp_type != PXA25x_SSP
1237 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
1238 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1239 "b/w not 4-32 for type non-PXA25x_SSP\n",
1240 drv_data->ssp_type, spi->bits_per_word);
1241 return -EINVAL;
1242 }
1243 else if (drv_data->ssp_type == PXA25x_SSP
1244 && (spi->bits_per_word < 4
1245 || spi->bits_per_word > 16)) {
1246 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1247 "b/w not 4-16 for type PXA25x_SSP\n",
1248 drv_data->ssp_type, spi->bits_per_word);
1249 return -EINVAL;
1250 }
1251
1252 /* Only alloc on first setup */
1253 chip = spi_get_ctldata(spi);
1254 if (!chip) {
1255 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1256 if (!chip) {
1257 dev_err(&spi->dev,
1258 "failed setup: can't allocate chip data\n");
1259 return -ENOMEM;
1260 }
1261
1262 chip->gpio_cs = -1;
1263 chip->enable_dma = 0;
1264 chip->timeout = TIMOUT_DFLT;
1265 chip->dma_burst_size = drv_data->master_info->enable_dma ?
1266 DCMD_BURST8 : 0;
1267 }
1268
1269 /* protocol drivers may change the chip settings, so...
1270 * if chip_info exists, use it */
1271 chip_info = spi->controller_data;
1272
1273 /* chip_info isn't always needed */
1274 chip->cr1 = 0;
1275 if (chip_info) {
1276 if (chip_info->timeout)
1277 chip->timeout = chip_info->timeout;
1278 if (chip_info->tx_threshold)
1279 tx_thres = chip_info->tx_threshold;
1280 if (chip_info->rx_threshold)
1281 rx_thres = chip_info->rx_threshold;
1282 chip->enable_dma = drv_data->master_info->enable_dma;
1283 chip->dma_threshold = 0;
1284 if (chip_info->enable_loopback)
1285 chip->cr1 = SSCR1_LBM;
1286 }
1287
1288 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1289 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1290
1291 /* set dma burst and threshold outside of chip_info path so that if
1292 * chip_info goes away after setting chip->enable_dma, the
1293 * burst and threshold can still respond to changes in bits_per_word */
1294 if (chip->enable_dma) {
1295 /* set up legal burst and threshold for dma */
1296 if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
1297 &chip->dma_burst_size,
1298 &chip->dma_threshold)) {
1299 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
1300 "to match bits_per_word\n");
1301 }
1302 }
1303
1304 clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
1305 chip->speed_hz = spi->max_speed_hz;
1306
1307 chip->cr0 = clk_div
1308 | SSCR0_Motorola
1309 | SSCR0_DataSize(spi->bits_per_word > 16 ?
1310 spi->bits_per_word - 16 : spi->bits_per_word)
1311 | SSCR0_SSE
1312 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1313 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1314 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1315 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1316
1317 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1318 if (drv_data->ssp_type != PXA25x_SSP)
1319 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1320 clk_get_rate(ssp->clk)
1321 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1322 chip->enable_dma ? "DMA" : "PIO");
1323 else
1324 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1325 clk_get_rate(ssp->clk) / 2
1326 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1327 chip->enable_dma ? "DMA" : "PIO");
1328
1329 if (spi->bits_per_word <= 8) {
1330 chip->n_bytes = 1;
1331 chip->dma_width = DCMD_WIDTH1;
1332 chip->read = u8_reader;
1333 chip->write = u8_writer;
1334 } else if (spi->bits_per_word <= 16) {
1335 chip->n_bytes = 2;
1336 chip->dma_width = DCMD_WIDTH2;
1337 chip->read = u16_reader;
1338 chip->write = u16_writer;
1339 } else if (spi->bits_per_word <= 32) {
1340 chip->cr0 |= SSCR0_EDSS;
1341 chip->n_bytes = 4;
1342 chip->dma_width = DCMD_WIDTH4;
1343 chip->read = u32_reader;
1344 chip->write = u32_writer;
1345 } else {
1346 dev_err(&spi->dev, "invalid wordsize\n");
1347 return -ENODEV;
1348 }
1349 chip->bits_per_word = spi->bits_per_word;
1350
1351 spi_set_ctldata(spi, chip);
1352
1353 return setup_cs(spi, chip, chip_info);
1354 }
1355
1356 static void cleanup(struct spi_device *spi)
1357 {
1358 struct chip_data *chip = spi_get_ctldata(spi);
1359
1360 if (!chip)
1361 return;
1362
1363 if (gpio_is_valid(chip->gpio_cs))
1364 gpio_free(chip->gpio_cs);
1365
1366 kfree(chip);
1367 }
1368
1369 static int __init init_queue(struct driver_data *drv_data)
1370 {
1371 INIT_LIST_HEAD(&drv_data->queue);
1372 spin_lock_init(&drv_data->lock);
1373
1374 drv_data->run = QUEUE_STOPPED;
1375 drv_data->busy = 0;
1376
1377 tasklet_init(&drv_data->pump_transfers,
1378 pump_transfers, (unsigned long)drv_data);
1379
1380 INIT_WORK(&drv_data->pump_messages, pump_messages);
1381 drv_data->workqueue = create_singlethread_workqueue(
1382 dev_name(drv_data->master->dev.parent));
1383 if (drv_data->workqueue == NULL)
1384 return -EBUSY;
1385
1386 return 0;
1387 }
1388
1389 static int start_queue(struct driver_data *drv_data)
1390 {
1391 unsigned long flags;
1392
1393 spin_lock_irqsave(&drv_data->lock, flags);
1394
1395 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1396 spin_unlock_irqrestore(&drv_data->lock, flags);
1397 return -EBUSY;
1398 }
1399
1400 drv_data->run = QUEUE_RUNNING;
1401 drv_data->cur_msg = NULL;
1402 drv_data->cur_transfer = NULL;
1403 drv_data->cur_chip = NULL;
1404 spin_unlock_irqrestore(&drv_data->lock, flags);
1405
1406 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1407
1408 return 0;
1409 }
1410
1411 static int stop_queue(struct driver_data *drv_data)
1412 {
1413 unsigned long flags;
1414 unsigned limit = 500;
1415 int status = 0;
1416
1417 spin_lock_irqsave(&drv_data->lock, flags);
1418
1419 /* This is a bit lame, but is optimized for the common execution path.
1420 * A wait_queue on the drv_data->busy could be used, but then the common
1421 * execution path (pump_messages) would be required to call wake_up or
1422 * friends on every SPI message. Do this instead */
1423 drv_data->run = QUEUE_STOPPED;
1424 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1425 spin_unlock_irqrestore(&drv_data->lock, flags);
1426 msleep(10);
1427 spin_lock_irqsave(&drv_data->lock, flags);
1428 }
1429
1430 if (!list_empty(&drv_data->queue) || drv_data->busy)
1431 status = -EBUSY;
1432
1433 spin_unlock_irqrestore(&drv_data->lock, flags);
1434
1435 return status;
1436 }
1437
1438 static int destroy_queue(struct driver_data *drv_data)
1439 {
1440 int status;
1441
1442 status = stop_queue(drv_data);
1443 /* we are unloading the module or failing to load (only two calls
1444 * to this routine), and neither call can handle a return value.
1445 * However, destroy_workqueue calls flush_workqueue, and that will
1446 * block until all work is done. If the reason that stop_queue
1447 * timed out is that the work will never finish, then it does no
1448 * good to call destroy_workqueue, so return anyway. */
1449 if (status != 0)
1450 return status;
1451
1452 destroy_workqueue(drv_data->workqueue);
1453
1454 return 0;
1455 }
1456
1457 static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1458 {
1459 struct device *dev = &pdev->dev;
1460 struct pxa2xx_spi_master *platform_info;
1461 struct spi_master *master;
1462 struct driver_data *drv_data;
1463 struct ssp_device *ssp;
1464 int status;
1465
1466 platform_info = dev->platform_data;
1467
1468 ssp = ssp_request(pdev->id, pdev->name);
1469 if (ssp == NULL) {
1470 dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
1471 return -ENODEV;
1472 }
1473
1474 /* Allocate master with space for drv_data and null dma buffer */
1475 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1476 if (!master) {
1477 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1478 ssp_free(ssp);
1479 return -ENOMEM;
1480 }
1481 drv_data = spi_master_get_devdata(master);
1482 drv_data->master = master;
1483 drv_data->master_info = platform_info;
1484 drv_data->pdev = pdev;
1485 drv_data->ssp = ssp;
1486
1487 /* the spi->mode bits understood by this driver: */
1488 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1489
1490 master->bus_num = pdev->id;
1491 master->num_chipselect = platform_info->num_chipselect;
1492 master->dma_alignment = DMA_ALIGNMENT;
1493 master->cleanup = cleanup;
1494 master->setup = setup;
1495 master->transfer = transfer;
1496
1497 drv_data->ssp_type = ssp->type;
1498 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1499 sizeof(struct driver_data)), 8);
1500
1501 drv_data->ioaddr = ssp->mmio_base;
1502 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1503 if (ssp->type == PXA25x_SSP) {
1504 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1505 drv_data->dma_cr1 = 0;
1506 drv_data->clear_sr = SSSR_ROR;
1507 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1508 } else {
1509 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1510 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1511 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1512 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1513 }
1514
1515 status = request_irq(ssp->irq, ssp_int, 0, dev_name(dev), drv_data);
1516 if (status < 0) {
1517 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1518 goto out_error_master_alloc;
1519 }
1520
1521 /* Setup DMA if requested */
1522 drv_data->tx_channel = -1;
1523 drv_data->rx_channel = -1;
1524 if (platform_info->enable_dma) {
1525
1526 /* Get two DMA channels (rx and tx) */
1527 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1528 DMA_PRIO_HIGH,
1529 dma_handler,
1530 drv_data);
1531 if (drv_data->rx_channel < 0) {
1532 dev_err(dev, "problem (%d) requesting rx channel\n",
1533 drv_data->rx_channel);
1534 status = -ENODEV;
1535 goto out_error_irq_alloc;
1536 }
1537 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1538 DMA_PRIO_MEDIUM,
1539 dma_handler,
1540 drv_data);
1541 if (drv_data->tx_channel < 0) {
1542 dev_err(dev, "problem (%d) requesting tx channel\n",
1543 drv_data->tx_channel);
1544 status = -ENODEV;
1545 goto out_error_dma_alloc;
1546 }
1547
1548 DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
1549 DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
1550 }
1551
1552 /* Enable SOC clock */
1553 clk_enable(ssp->clk);
1554
1555 /* Load default SSP configuration */
1556 write_SSCR0(0, drv_data->ioaddr);
1557 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1558 SSCR1_TxTresh(TX_THRESH_DFLT),
1559 drv_data->ioaddr);
1560 write_SSCR0(SSCR0_SerClkDiv(2)
1561 | SSCR0_Motorola
1562 | SSCR0_DataSize(8),
1563 drv_data->ioaddr);
1564 if (drv_data->ssp_type != PXA25x_SSP)
1565 write_SSTO(0, drv_data->ioaddr);
1566 write_SSPSP(0, drv_data->ioaddr);
1567
1568 /* Initial and start queue */
1569 status = init_queue(drv_data);
1570 if (status != 0) {
1571 dev_err(&pdev->dev, "problem initializing queue\n");
1572 goto out_error_clock_enabled;
1573 }
1574 status = start_queue(drv_data);
1575 if (status != 0) {
1576 dev_err(&pdev->dev, "problem starting queue\n");
1577 goto out_error_clock_enabled;
1578 }
1579
1580 /* Register with the SPI framework */
1581 platform_set_drvdata(pdev, drv_data);
1582 status = spi_register_master(master);
1583 if (status != 0) {
1584 dev_err(&pdev->dev, "problem registering spi master\n");
1585 goto out_error_queue_alloc;
1586 }
1587
1588 return status;
1589
1590 out_error_queue_alloc:
1591 destroy_queue(drv_data);
1592
1593 out_error_clock_enabled:
1594 clk_disable(ssp->clk);
1595
1596 out_error_dma_alloc:
1597 if (drv_data->tx_channel != -1)
1598 pxa_free_dma(drv_data->tx_channel);
1599 if (drv_data->rx_channel != -1)
1600 pxa_free_dma(drv_data->rx_channel);
1601
1602 out_error_irq_alloc:
1603 free_irq(ssp->irq, drv_data);
1604
1605 out_error_master_alloc:
1606 spi_master_put(master);
1607 ssp_free(ssp);
1608 return status;
1609 }
1610
1611 static int pxa2xx_spi_remove(struct platform_device *pdev)
1612 {
1613 struct driver_data *drv_data = platform_get_drvdata(pdev);
1614 struct ssp_device *ssp;
1615 int status = 0;
1616
1617 if (!drv_data)
1618 return 0;
1619 ssp = drv_data->ssp;
1620
1621 /* Remove the queue */
1622 status = destroy_queue(drv_data);
1623 if (status != 0)
1624 /* the kernel does not check the return status of this
1625 * this routine (mod->exit, within the kernel). Therefore
1626 * nothing is gained by returning from here, the module is
1627 * going away regardless, and we should not leave any more
1628 * resources allocated than necessary. We cannot free the
1629 * message memory in drv_data->queue, but we can release the
1630 * resources below. I think the kernel should honor -EBUSY
1631 * returns but... */
1632 dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
1633 "complete, message memory not freed\n");
1634
1635 /* Disable the SSP at the peripheral and SOC level */
1636 write_SSCR0(0, drv_data->ioaddr);
1637 clk_disable(ssp->clk);
1638
1639 /* Release DMA */
1640 if (drv_data->master_info->enable_dma) {
1641 DRCMR(ssp->drcmr_rx) = 0;
1642 DRCMR(ssp->drcmr_tx) = 0;
1643 pxa_free_dma(drv_data->tx_channel);
1644 pxa_free_dma(drv_data->rx_channel);
1645 }
1646
1647 /* Release IRQ */
1648 free_irq(ssp->irq, drv_data);
1649
1650 /* Release SSP */
1651 ssp_free(ssp);
1652
1653 /* Disconnect from the SPI framework */
1654 spi_unregister_master(drv_data->master);
1655
1656 /* Prevent double remove */
1657 platform_set_drvdata(pdev, NULL);
1658
1659 return 0;
1660 }
1661
1662 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1663 {
1664 int status = 0;
1665
1666 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1667 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1668 }
1669
1670 #ifdef CONFIG_PM
1671 static int pxa2xx_spi_suspend(struct device *dev)
1672 {
1673 struct driver_data *drv_data = dev_get_drvdata(dev);
1674 struct ssp_device *ssp = drv_data->ssp;
1675 int status = 0;
1676
1677 status = stop_queue(drv_data);
1678 if (status != 0)
1679 return status;
1680 write_SSCR0(0, drv_data->ioaddr);
1681 clk_disable(ssp->clk);
1682
1683 return 0;
1684 }
1685
1686 static int pxa2xx_spi_resume(struct device *dev)
1687 {
1688 struct driver_data *drv_data = dev_get_drvdata(dev);
1689 struct ssp_device *ssp = drv_data->ssp;
1690 int status = 0;
1691
1692 if (drv_data->rx_channel != -1)
1693 DRCMR(drv_data->ssp->drcmr_rx) =
1694 DRCMR_MAPVLD | drv_data->rx_channel;
1695 if (drv_data->tx_channel != -1)
1696 DRCMR(drv_data->ssp->drcmr_tx) =
1697 DRCMR_MAPVLD | drv_data->tx_channel;
1698
1699 /* Enable the SSP clock */
1700 clk_enable(ssp->clk);
1701
1702 /* Start the queue running */
1703 status = start_queue(drv_data);
1704 if (status != 0) {
1705 dev_err(dev, "problem starting queue (%d)\n", status);
1706 return status;
1707 }
1708
1709 return 0;
1710 }
1711
1712 static struct dev_pm_ops pxa2xx_spi_pm_ops = {
1713 .suspend = pxa2xx_spi_suspend,
1714 .resume = pxa2xx_spi_resume,
1715 };
1716 #endif
1717
1718 static struct platform_driver driver = {
1719 .driver = {
1720 .name = "pxa2xx-spi",
1721 .owner = THIS_MODULE,
1722 #ifdef CONFIG_PM
1723 .pm = &pxa2xx_spi_pm_ops,
1724 #endif
1725 },
1726 .remove = pxa2xx_spi_remove,
1727 .shutdown = pxa2xx_spi_shutdown,
1728 };
1729
1730 static int __init pxa2xx_spi_init(void)
1731 {
1732 return platform_driver_probe(&driver, pxa2xx_spi_probe);
1733 }
1734 subsys_initcall(pxa2xx_spi_init);
1735
1736 static void __exit pxa2xx_spi_exit(void)
1737 {
1738 platform_driver_unregister(&driver);
1739 }
1740 module_exit(pxa2xx_spi_exit);
Linux with added FPC-III support