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x86/amd-iommu: Add per IOMMU reference counting
[linux/fpc-iii.git] / drivers / spi / spi_s3c24xx.c
blob33d94f76b9ef47fd92bddd54815e72262b6dffda
1 /* linux/drivers/spi/spi_s3c24xx.c
2 *
3 * Copyright (c) 2006 Ben Dooks
4 * Copyright (c) 2006 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13 #include <linux/init.h>
14 #include <linux/spinlock.h>
15 #include <linux/workqueue.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/platform_device.h>
22 #include <linux/gpio.h>
23 #include <linux/io.h>
24
25 #include <linux/spi/spi.h>
26 #include <linux/spi/spi_bitbang.h>
27
28 #include <plat/regs-spi.h>
29 #include <mach/spi.h>
30
31 /**
32 * s3c24xx_spi_devstate - per device data
33 * @hz: Last frequency calculated for @sppre field.
34 * @mode: Last mode setting for the @spcon field.
35 * @spcon: Value to write to the SPCON register.
36 * @sppre: Value to write to the SPPRE register.
37 */
38 struct s3c24xx_spi_devstate {
39 unsigned int hz;
40 unsigned int mode;
41 u8 spcon;
42 u8 sppre;
43 };
44
45 struct s3c24xx_spi {
46 /* bitbang has to be first */
47 struct spi_bitbang bitbang;
48 struct completion done;
49
50 void __iomem *regs;
51 int irq;
52 int len;
53 int count;
54
55 void (*set_cs)(struct s3c2410_spi_info *spi,
56 int cs, int pol);
57
58 /* data buffers */
59 const unsigned char *tx;
60 unsigned char *rx;
61
62 struct clk *clk;
63 struct resource *ioarea;
64 struct spi_master *master;
65 struct spi_device *curdev;
66 struct device *dev;
67 struct s3c2410_spi_info *pdata;
68 };
69
70 #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
71 #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
72
73 static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
74 {
75 return spi_master_get_devdata(sdev->master);
76 }
77
78 static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
79 {
80 gpio_set_value(spi->pin_cs, pol);
81 }
82
83 static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
84 {
85 struct s3c24xx_spi_devstate *cs = spi->controller_state;
86 struct s3c24xx_spi *hw = to_hw(spi);
87 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
88
89 /* change the chipselect state and the state of the spi engine clock */
90
91 switch (value) {
92 case BITBANG_CS_INACTIVE:
93 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
94 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
95 break;
96
97 case BITBANG_CS_ACTIVE:
98 writeb(cs->spcon | S3C2410_SPCON_ENSCK,
99 hw->regs + S3C2410_SPCON);
100 hw->set_cs(hw->pdata, spi->chip_select, cspol);
101 break;
102 }
103 }
104
105 static int s3c24xx_spi_update_state(struct spi_device *spi,
106 struct spi_transfer *t)
107 {
108 struct s3c24xx_spi *hw = to_hw(spi);
109 struct s3c24xx_spi_devstate *cs = spi->controller_state;
110 unsigned int bpw;
111 unsigned int hz;
112 unsigned int div;
113 unsigned long clk;
114
115 bpw = t ? t->bits_per_word : spi->bits_per_word;
116 hz = t ? t->speed_hz : spi->max_speed_hz;
117
118 if (!bpw)
119 bpw = 8;
120
121 if (!hz)
122 hz = spi->max_speed_hz;
123
124 if (bpw != 8) {
125 dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
126 return -EINVAL;
127 }
128
129 if (spi->mode != cs->mode) {
130 u8 spcon = SPCON_DEFAULT;
131
132 if (spi->mode & SPI_CPHA)
133 spcon |= S3C2410_SPCON_CPHA_FMTB;
134
135 if (spi->mode & SPI_CPOL)
136 spcon |= S3C2410_SPCON_CPOL_HIGH;
137
138 cs->mode = spi->mode;
139 cs->spcon = spcon;
140 }
141
142 if (cs->hz != hz) {
143 clk = clk_get_rate(hw->clk);
144 div = DIV_ROUND_UP(clk, hz * 2) - 1;
145
146 if (div > 255)
147 div = 255;
148
149 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
150 div, hz, clk / (2 * (div + 1)));
151
152 cs->hz = hz;
153 cs->sppre = div;
154 }
155
156 return 0;
157 }
158
159 static int s3c24xx_spi_setupxfer(struct spi_device *spi,
160 struct spi_transfer *t)
161 {
162 struct s3c24xx_spi_devstate *cs = spi->controller_state;
163 struct s3c24xx_spi *hw = to_hw(spi);
164 int ret;
165
166 ret = s3c24xx_spi_update_state(spi, t);
167 if (!ret)
168 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
169
170 return ret;
171 }
172
173 static int s3c24xx_spi_setup(struct spi_device *spi)
174 {
175 struct s3c24xx_spi_devstate *cs = spi->controller_state;
176 struct s3c24xx_spi *hw = to_hw(spi);
177 int ret;
178
179 /* allocate settings on the first call */
180 if (!cs) {
181 cs = kzalloc(sizeof(struct s3c24xx_spi_devstate), GFP_KERNEL);
182 if (!cs) {
183 dev_err(&spi->dev, "no memory for controller state\n");
184 return -ENOMEM;
185 }
186
187 cs->spcon = SPCON_DEFAULT;
188 cs->hz = -1;
189 spi->controller_state = cs;
190 }
191
192 /* initialise the state from the device */
193 ret = s3c24xx_spi_update_state(spi, NULL);
194 if (ret)
195 return ret;
196
197 spin_lock(&hw->bitbang.lock);
198 if (!hw->bitbang.busy) {
199 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
200 /* need to ndelay for 0.5 clocktick ? */
201 }
202 spin_unlock(&hw->bitbang.lock);
203
204 return 0;
205 }
206
207 static void s3c24xx_spi_cleanup(struct spi_device *spi)
208 {
209 kfree(spi->controller_state);
210 }
211
212 static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
213 {
214 return hw->tx ? hw->tx[count] : 0;
215 }
216
217 static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
218 {
219 struct s3c24xx_spi *hw = to_hw(spi);
220
221 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
222 t->tx_buf, t->rx_buf, t->len);
223
224 hw->tx = t->tx_buf;
225 hw->rx = t->rx_buf;
226 hw->len = t->len;
227 hw->count = 0;
228
229 init_completion(&hw->done);
230
231 /* send the first byte */
232 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
233
234 wait_for_completion(&hw->done);
235
236 return hw->count;
237 }
238
239 static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
240 {
241 struct s3c24xx_spi *hw = dev;
242 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
243 unsigned int count = hw->count;
244
245 if (spsta & S3C2410_SPSTA_DCOL) {
246 dev_dbg(hw->dev, "data-collision\n");
247 complete(&hw->done);
248 goto irq_done;
249 }
250
251 if (!(spsta & S3C2410_SPSTA_READY)) {
252 dev_dbg(hw->dev, "spi not ready for tx?\n");
253 complete(&hw->done);
254 goto irq_done;
255 }
256
257 hw->count++;
258
259 if (hw->rx)
260 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
261
262 count++;
263
264 if (count < hw->len)
265 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
266 else
267 complete(&hw->done);
268
269 irq_done:
270 return IRQ_HANDLED;
271 }
272
273 static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
274 {
275 /* for the moment, permanently enable the clock */
276
277 clk_enable(hw->clk);
278
279 /* program defaults into the registers */
280
281 writeb(0xff, hw->regs + S3C2410_SPPRE);
282 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
283 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
284
285 if (hw->pdata) {
286 if (hw->set_cs == s3c24xx_spi_gpiocs)
287 gpio_direction_output(hw->pdata->pin_cs, 1);
288
289 if (hw->pdata->gpio_setup)
290 hw->pdata->gpio_setup(hw->pdata, 1);
291 }
292 }
293
294 static int __init s3c24xx_spi_probe(struct platform_device *pdev)
295 {
296 struct s3c2410_spi_info *pdata;
297 struct s3c24xx_spi *hw;
298 struct spi_master *master;
299 struct resource *res;
300 int err = 0;
301
302 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
303 if (master == NULL) {
304 dev_err(&pdev->dev, "No memory for spi_master\n");
305 err = -ENOMEM;
306 goto err_nomem;
307 }
308
309 hw = spi_master_get_devdata(master);
310 memset(hw, 0, sizeof(struct s3c24xx_spi));
311
312 hw->master = spi_master_get(master);
313 hw->pdata = pdata = pdev->dev.platform_data;
314 hw->dev = &pdev->dev;
315
316 if (pdata == NULL) {
317 dev_err(&pdev->dev, "No platform data supplied\n");
318 err = -ENOENT;
319 goto err_no_pdata;
320 }
321
322 platform_set_drvdata(pdev, hw);
323 init_completion(&hw->done);
324
325 /* setup the master state. */
326
327 /* the spi->mode bits understood by this driver: */
328 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
329
330 master->num_chipselect = hw->pdata->num_cs;
331 master->bus_num = pdata->bus_num;
332
333 /* setup the state for the bitbang driver */
334
335 hw->bitbang.master = hw->master;
336 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
337 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
338 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
339
340 hw->master->setup = s3c24xx_spi_setup;
341 hw->master->cleanup = s3c24xx_spi_cleanup;
342
343 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
344
345 /* find and map our resources */
346
347 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
348 if (res == NULL) {
349 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
350 err = -ENOENT;
351 goto err_no_iores;
352 }
353
354 hw->ioarea = request_mem_region(res->start, resource_size(res),
355 pdev->name);
356
357 if (hw->ioarea == NULL) {
358 dev_err(&pdev->dev, "Cannot reserve region\n");
359 err = -ENXIO;
360 goto err_no_iores;
361 }
362
363 hw->regs = ioremap(res->start, resource_size(res));
364 if (hw->regs == NULL) {
365 dev_err(&pdev->dev, "Cannot map IO\n");
366 err = -ENXIO;
367 goto err_no_iomap;
368 }
369
370 hw->irq = platform_get_irq(pdev, 0);
371 if (hw->irq < 0) {
372 dev_err(&pdev->dev, "No IRQ specified\n");
373 err = -ENOENT;
374 goto err_no_irq;
375 }
376
377 err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
378 if (err) {
379 dev_err(&pdev->dev, "Cannot claim IRQ\n");
380 goto err_no_irq;
381 }
382
383 hw->clk = clk_get(&pdev->dev, "spi");
384 if (IS_ERR(hw->clk)) {
385 dev_err(&pdev->dev, "No clock for device\n");
386 err = PTR_ERR(hw->clk);
387 goto err_no_clk;
388 }
389
390 /* setup any gpio we can */
391
392 if (!pdata->set_cs) {
393 if (pdata->pin_cs < 0) {
394 dev_err(&pdev->dev, "No chipselect pin\n");
395 goto err_register;
396 }
397
398 err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev));
399 if (err) {
400 dev_err(&pdev->dev, "Failed to get gpio for cs\n");
401 goto err_register;
402 }
403
404 hw->set_cs = s3c24xx_spi_gpiocs;
405 gpio_direction_output(pdata->pin_cs, 1);
406 } else
407 hw->set_cs = pdata->set_cs;
408
409 s3c24xx_spi_initialsetup(hw);
410
411 /* register our spi controller */
412
413 err = spi_bitbang_start(&hw->bitbang);
414 if (err) {
415 dev_err(&pdev->dev, "Failed to register SPI master\n");
416 goto err_register;
417 }
418
419 return 0;
420
421 err_register:
422 if (hw->set_cs == s3c24xx_spi_gpiocs)
423 gpio_free(pdata->pin_cs);
424
425 clk_disable(hw->clk);
426 clk_put(hw->clk);
427
428 err_no_clk:
429 free_irq(hw->irq, hw);
430
431 err_no_irq:
432 iounmap(hw->regs);
433
434 err_no_iomap:
435 release_resource(hw->ioarea);
436 kfree(hw->ioarea);
437
438 err_no_iores:
439 err_no_pdata:
440 spi_master_put(hw->master);
441
442 err_nomem:
443 return err;
444 }
445
446 static int __exit s3c24xx_spi_remove(struct platform_device *dev)
447 {
448 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
449
450 platform_set_drvdata(dev, NULL);
451
452 spi_unregister_master(hw->master);
453
454 clk_disable(hw->clk);
455 clk_put(hw->clk);
456
457 free_irq(hw->irq, hw);
458 iounmap(hw->regs);
459
460 if (hw->set_cs == s3c24xx_spi_gpiocs)
461 gpio_free(hw->pdata->pin_cs);
462
463 release_resource(hw->ioarea);
464 kfree(hw->ioarea);
465
466 spi_master_put(hw->master);
467 return 0;
468 }
469
470
471 #ifdef CONFIG_PM
472
473 static int s3c24xx_spi_suspend(struct device *dev)
474 {
475 struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev));
476
477 if (hw->pdata && hw->pdata->gpio_setup)
478 hw->pdata->gpio_setup(hw->pdata, 0);
479
480 clk_disable(hw->clk);
481 return 0;
482 }
483
484 static int s3c24xx_spi_resume(struct device *dev)
485 {
486 struct s3c24xx_spi *hw = platform_get_drvdata(to_platform_device(dev));
487
488 s3c24xx_spi_initialsetup(hw);
489 return 0;
490 }
491
492 static struct dev_pm_ops s3c24xx_spi_pmops = {
493 .suspend = s3c24xx_spi_suspend,
494 .resume = s3c24xx_spi_resume,
495 };
496
497 #define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
498 #else
499 #define S3C24XX_SPI_PMOPS NULL
500 #endif /* CONFIG_PM */
501
502 MODULE_ALIAS("platform:s3c2410-spi");
503 static struct platform_driver s3c24xx_spi_driver = {
504 .remove = __exit_p(s3c24xx_spi_remove),
505 .driver = {
506 .name = "s3c2410-spi",
507 .owner = THIS_MODULE,
508 .pm = S3C24XX_SPI_PMOPS,
509 },
510 };
511
512 static int __init s3c24xx_spi_init(void)
513 {
514 return platform_driver_probe(&s3c24xx_spi_driver, s3c24xx_spi_probe);
515 }
516
517 static void __exit s3c24xx_spi_exit(void)
518 {
519 platform_driver_unregister(&s3c24xx_spi_driver);
520 }
521
522 module_init(s3c24xx_spi_init);
523 module_exit(s3c24xx_spi_exit);
524
525 MODULE_DESCRIPTION("S3C24XX SPI Driver");
526 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
527 MODULE_LICENSE("GPL");
Linux with added FPC-III support