drivers/gpu/drm/radeon/radeon_dp_mst.c

   1
   2 #include <drm/drmP.h>
   3 #include <drm/drm_dp_mst_helper.h>
   4 #include <drm/drm_fb_helper.h>
   5
   6 #include "radeon.h"
   7 #include "atom.h"
   8 #include "ni_reg.h"
   9
  10 static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector);
  11
  12 static int radeon_atom_set_enc_offset(int id)
  13 {
  14         static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET,
  15                                        EVERGREEN_CRTC1_REGISTER_OFFSET,
  16                                        EVERGREEN_CRTC2_REGISTER_OFFSET,
  17                                        EVERGREEN_CRTC3_REGISTER_OFFSET,
  18                                        EVERGREEN_CRTC4_REGISTER_OFFSET,
  19                                        EVERGREEN_CRTC5_REGISTER_OFFSET,
  20                                        0x13830 - 0x7030 };
  21
  22         return offsets[id];
  23 }
  24
  25 static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary,
  26                                      struct radeon_encoder_mst *mst_enc,
  27                                      enum radeon_hpd_id hpd, bool enable)
  28 {
  29         struct drm_device *dev = primary->base.dev;
  30         struct radeon_device *rdev = dev->dev_private;
  31         uint32_t reg;
  32         int retries = 0;
  33         uint32_t temp;
  34
  35         reg = RREG32(NI_DIG_BE_CNTL + primary->offset);
  36
  37         /* set MST mode */
  38         reg &= ~NI_DIG_FE_DIG_MODE(7);
  39         reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST);
  40
  41         if (enable)
  42                 reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
  43         else
  44                 reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
  45
  46         reg |= NI_DIG_HPD_SELECT(hpd);
  47         DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg);
  48         WREG32(NI_DIG_BE_CNTL + primary->offset, reg);
  49
  50         if (enable) {
  51                 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
  52
  53                 do {
  54                         temp = RREG32(NI_DIG_FE_CNTL + offset);
  55                 } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000);
  56                 if (retries == 10000)
  57                         DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe);
  58         }
  59         return 0;
  60 }
  61
  62 static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
  63                                            int stream_number,
  64                                            int fe,
  65                                            int slots)
  66 {
  67         struct drm_device *dev = primary->base.dev;
  68         struct radeon_device *rdev = dev->dev_private;
  69         u32 temp, val;
  70         int retries  = 0;
  71         int satreg, satidx;
  72
  73         satreg = stream_number >> 1;
  74         satidx = stream_number & 1;
  75
  76         temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset);
  77
  78         val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe);
  79
  80         val <<= (16 * satidx);
  81
  82         temp &= ~(0xffff << (16 * satidx));
  83
  84         temp |= val;
  85
  86         DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
  87         WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
  88
  89         WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
  90
  91         do {
  92                 unsigned value1, value2;
  93                 udelay(10);
  94                 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
  95
  96                 value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
  97                 value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
  98
  99                 if (!value1 && !value2)
 100                         break;
 101         } while (retries++ < 50);
 102
 103         if (retries == 10000)
 104                 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
 105
 106         /* MTP 16 ? */
 107         return 0;
 108 }
 109
 110 static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn,
 111                                                struct radeon_encoder *primary)
 112 {
 113         struct drm_device *dev = mst_conn->base.dev;
 114         struct stream_attribs new_attribs[6];
 115         int i;
 116         int idx = 0;
 117         struct radeon_connector *radeon_connector;
 118         struct drm_connector *connector;
 119
 120         memset(new_attribs, 0, sizeof(new_attribs));
 121         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 122                 struct radeon_encoder *subenc;
 123                 struct radeon_encoder_mst *mst_enc;
 124
 125                 radeon_connector = to_radeon_connector(connector);
 126                 if (!radeon_connector->is_mst_connector)
 127                         continue;
 128
 129                 if (radeon_connector->mst_port != mst_conn)
 130                         continue;
 131
 132                 subenc = radeon_connector->mst_encoder;
 133                 mst_enc = subenc->enc_priv;
 134
 135                 if (!mst_enc->enc_active)
 136                         continue;
 137
 138                 new_attribs[idx].fe = mst_enc->fe;
 139                 new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port);
 140                 idx++;
 141         }
 142
 143         for (i = 0; i < idx; i++) {
 144                 if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe ||
 145                     new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) {
 146                         radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots);
 147                         mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe;
 148                         mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots;
 149                 }
 150         }
 151
 152         for (i = idx; i < mst_conn->enabled_attribs; i++) {
 153                 radeon_dp_mst_set_stream_attrib(primary, i, 0, 0);
 154                 mst_conn->cur_stream_attribs[i].fe = 0;
 155                 mst_conn->cur_stream_attribs[i].slots = 0;
 156         }
 157         mst_conn->enabled_attribs = idx;
 158         return 0;
 159 }
 160
 161 static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
 162 {
 163         struct drm_device *dev = mst->base.dev;
 164         struct radeon_device *rdev = dev->dev_private;
 165         struct radeon_encoder_mst *mst_enc = mst->enc_priv;
 166         uint32_t val, temp;
 167         uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
 168         int retries = 0;
 169         uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
 170         uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
 171
 172         val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
 173
 174         WREG32(NI_DP_MSE_RATE_CNTL + offset, val);
 175
 176         do {
 177                 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
 178                 udelay(10);
 179         } while ((temp & 0x1) && (retries++ < 10000));
 180
 181         if (retries >= 10000)
 182                 DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe);
 183         return 0;
 184 }
 185
 186 static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector)
 187 {
 188         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 189         struct radeon_connector *master = radeon_connector->mst_port;
 190         struct edid *edid;
 191         int ret = 0;
 192
 193         edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port);
 194         radeon_connector->edid = edid;
 195         DRM_DEBUG_KMS("edid retrieved %p\n", edid);
 196         if (radeon_connector->edid) {
 197                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 198                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 199                 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
 200                 return ret;
 201         }
 202         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 203
 204         return ret;
 205 }
 206
 207 static int radeon_dp_mst_get_modes(struct drm_connector *connector)
 208 {
 209         return radeon_dp_mst_get_ddc_modes(connector);
 210 }
 211
 212 static enum drm_mode_status
 213 radeon_dp_mst_mode_valid(struct drm_connector *connector,
 214                         struct drm_display_mode *mode)
 215 {
 216         /* TODO - validate mode against available PBN for link */
 217         if (mode->clock < 10000)
 218                 return MODE_CLOCK_LOW;
 219
 220         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 221                 return MODE_H_ILLEGAL;
 222
 223         return MODE_OK;
 224 }
 225
 226 struct drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector)
 227 {
 228         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 229
 230         return &radeon_connector->mst_encoder->base;
 231 }
 232
 233 static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = {
 234         .get_modes = radeon_dp_mst_get_modes,
 235         .mode_valid = radeon_dp_mst_mode_valid,
 236         .best_encoder = radeon_mst_best_encoder,
 237 };
 238
 239 static enum drm_connector_status
 240 radeon_dp_mst_detect(struct drm_connector *connector, bool force)
 241 {
 242         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 243         struct radeon_connector *master = radeon_connector->mst_port;
 244
 245         return drm_dp_mst_detect_port(connector, &master->mst_mgr, radeon_connector->port);
 246 }
 247
 248 static void
 249 radeon_dp_mst_connector_destroy(struct drm_connector *connector)
 250 {
 251         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 252         struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder;
 253
 254         drm_encoder_cleanup(&radeon_encoder->base);
 255         kfree(radeon_encoder);
 256         drm_connector_cleanup(connector);
 257         kfree(radeon_connector);
 258 }
 259
 260 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
 261         .dpms = drm_helper_connector_dpms,
 262         .detect = radeon_dp_mst_detect,
 263         .fill_modes = drm_helper_probe_single_connector_modes,
 264         .destroy = radeon_dp_mst_connector_destroy,
 265 };
 266
 267 static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 268                                                          struct drm_dp_mst_port *port,
 269                                                          const char *pathprop)
 270 {
 271         struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
 272         struct drm_device *dev = master->base.dev;
 273         struct radeon_connector *radeon_connector;
 274         struct drm_connector *connector;
 275
 276         radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL);
 277         if (!radeon_connector)
 278                 return NULL;
 279
 280         radeon_connector->is_mst_connector = true;
 281         connector = &radeon_connector->base;
 282         radeon_connector->port = port;
 283         radeon_connector->mst_port = master;
 284         DRM_DEBUG_KMS("\n");
 285
 286         drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
 287         drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs);
 288         radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master);
 289
 290         drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
 291         drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0);
 292         drm_mode_connector_set_path_property(connector, pathprop);
 293
 294         return connector;
 295 }
 296
 297 static void radeon_dp_register_mst_connector(struct drm_connector *connector)
 298 {
 299         struct drm_device *dev = connector->dev;
 300         struct radeon_device *rdev = dev->dev_private;
 301
 302         drm_modeset_lock_all(dev);
 303         radeon_fb_add_connector(rdev, connector);
 304         drm_modeset_unlock_all(dev);
 305
 306         drm_connector_register(connector);
 307 }
 308
 309 static void radeon_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 310                                             struct drm_connector *connector)
 311 {
 312         struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
 313         struct drm_device *dev = master->base.dev;
 314         struct radeon_device *rdev = dev->dev_private;
 315
 316         drm_connector_unregister(connector);
 317         /* need to nuke the connector */
 318         drm_modeset_lock_all(dev);
 319         /* dpms off */
 320         radeon_fb_remove_connector(rdev, connector);
 321
 322         drm_connector_cleanup(connector);
 323         drm_modeset_unlock_all(dev);
 324
 325         kfree(connector);
 326         DRM_DEBUG_KMS("\n");
 327 }
 328
 329 static void radeon_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
 330 {
 331         struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
 332         struct drm_device *dev = master->base.dev;
 333
 334         drm_kms_helper_hotplug_event(dev);
 335 }
 336
 337 const struct drm_dp_mst_topology_cbs mst_cbs = {
 338         .add_connector = radeon_dp_add_mst_connector,
 339         .register_connector = radeon_dp_register_mst_connector,
 340         .destroy_connector = radeon_dp_destroy_mst_connector,
 341         .hotplug = radeon_dp_mst_hotplug,
 342 };
 343
 344 struct radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder)
 345 {
 346         struct drm_device *dev = encoder->dev;
 347         struct drm_connector *connector;
 348
 349         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 350                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 351                 if (!connector->encoder)
 352                         continue;
 353                 if (!radeon_connector->is_mst_connector)
 354                         continue;
 355
 356                 DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder);
 357                 if (connector->encoder == encoder)
 358                         return radeon_connector;
 359         }
 360         return NULL;
 361 }
 362
 363 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 364 {
 365         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 366         struct drm_device *dev = crtc->dev;
 367         struct radeon_device *rdev = dev->dev_private;
 368         struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder);
 369         struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
 370         struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base);
 371         int dp_clock;
 372         struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
 373
 374         if (radeon_connector) {
 375                 radeon_connector->pixelclock_for_modeset = mode->clock;
 376                 if (radeon_connector->base.display_info.bpc)
 377                         radeon_crtc->bpc = radeon_connector->base.display_info.bpc;
 378                 else
 379                         radeon_crtc->bpc = 8;
 380         }
 381
 382         DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock);
 383         dp_clock = dig_connector->dp_clock;
 384         radeon_crtc->ss_enabled =
 385                 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
 386                                                  ASIC_INTERNAL_SS_ON_DP,
 387                                                  dp_clock);
 388 }
 389
 390 static void
 391 radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
 392 {
 393         struct drm_device *dev = encoder->dev;
 394         struct radeon_device *rdev = dev->dev_private;
 395         struct radeon_encoder *radeon_encoder, *primary;
 396         struct radeon_encoder_mst *mst_enc;
 397         struct radeon_encoder_atom_dig *dig_enc;
 398         struct radeon_connector *radeon_connector;
 399         struct drm_crtc *crtc;
 400         struct radeon_crtc *radeon_crtc;
 401         int ret, slots;
 402         s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
 403         if (!ASIC_IS_DCE5(rdev)) {
 404                 DRM_ERROR("got mst dpms on non-DCE5\n");
 405                 return;
 406         }
 407
 408         radeon_connector = radeon_mst_find_connector(encoder);
 409         if (!radeon_connector)
 410                 return;
 411
 412         radeon_encoder = to_radeon_encoder(encoder);
 413
 414         mst_enc = radeon_encoder->enc_priv;
 415
 416         primary = mst_enc->primary;
 417
 418         dig_enc = primary->enc_priv;
 419
 420         crtc = encoder->crtc;
 421         DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links);
 422
 423         switch (mode) {
 424         case DRM_MODE_DPMS_ON:
 425                 dig_enc->active_mst_links++;
 426
 427                 radeon_crtc = to_radeon_crtc(crtc);
 428
 429                 if (dig_enc->active_mst_links == 1) {
 430                         mst_enc->fe = dig_enc->dig_encoder;
 431                         mst_enc->fe_from_be = true;
 432                         atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
 433
 434                         atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0);
 435                         atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE,
 436                                                         0, 0, dig_enc->dig_encoder);
 437
 438                         if (radeon_dp_needs_link_train(mst_enc->connector) ||
 439                             dig_enc->active_mst_links == 1) {
 440                                 radeon_dp_link_train(&primary->base, &mst_enc->connector->base);
 441                         }
 442
 443                 } else {
 444                         mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id);
 445                         if (mst_enc->fe == -1)
 446                                 DRM_ERROR("failed to get frontend for dig encoder\n");
 447                         mst_enc->fe_from_be = false;
 448                         atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
 449                 }
 450
 451                 DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder,
 452                               dig_enc->linkb, radeon_crtc->crtc_id);
 453
 454                 ret = drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr,
 455                                                radeon_connector->port,
 456                                                mst_enc->pbn, &slots);
 457                 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
 458
 459                 radeon_dp_mst_set_be_cntl(primary, mst_enc,
 460                                           radeon_connector->mst_port->hpd.hpd, true);
 461
 462                 mst_enc->enc_active = true;
 463                 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
 464
 465                 fixed_pbn = drm_int2fixp(mst_enc->pbn);
 466                 fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
 467                 avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
 468                 radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
 469
 470                 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
 471                                             mst_enc->fe);
 472                 ret = drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
 473
 474                 ret = drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
 475
 476                 break;
 477         case DRM_MODE_DPMS_STANDBY:
 478         case DRM_MODE_DPMS_SUSPEND:
 479         case DRM_MODE_DPMS_OFF:
 480                 DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links);
 481
 482                 if (!mst_enc->enc_active)
 483                         return;
 484
 485                 drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
 486                 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
 487
 488                 drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
 489                 /* and this can also fail */
 490                 drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
 491
 492                 drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
 493
 494                 mst_enc->enc_active = false;
 495                 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
 496
 497                 radeon_dp_mst_set_be_cntl(primary, mst_enc,
 498                                           radeon_connector->mst_port->hpd.hpd, false);
 499                 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0,
 500                                             mst_enc->fe);
 501
 502                 if (!mst_enc->fe_from_be)
 503                         radeon_atom_release_dig_encoder(rdev, mst_enc->fe);
 504
 505                 mst_enc->fe_from_be = false;
 506                 dig_enc->active_mst_links--;
 507                 if (dig_enc->active_mst_links == 0) {
 508                         /* drop link */
 509                 }
 510
 511                 break;
 512         }
 513
 514 }
 515
 516 static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
 517                                    const struct drm_display_mode *mode,
 518                                    struct drm_display_mode *adjusted_mode)
 519 {
 520         struct radeon_encoder_mst *mst_enc;
 521         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 522         struct radeon_connector_atom_dig *dig_connector;
 523         int bpp = 24;
 524
 525         mst_enc = radeon_encoder->enc_priv;
 526
 527         mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp);
 528
 529         mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices;
 530         DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
 531                       mst_enc->primary->active_device, mst_enc->primary->devices,
 532                       mst_enc->connector->devices, mst_enc->primary->base.encoder_type);
 533
 534
 535         drm_mode_set_crtcinfo(adjusted_mode, 0);
 536         dig_connector = mst_enc->connector->con_priv;
 537         dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
 538         dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
 539         DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
 540                       dig_connector->dp_lane_count, dig_connector->dp_clock);
 541         return true;
 542 }
 543
 544 static void radeon_mst_encoder_prepare(struct drm_encoder *encoder)
 545 {
 546         struct radeon_connector *radeon_connector;
 547         struct radeon_encoder *radeon_encoder, *primary;
 548         struct radeon_encoder_mst *mst_enc;
 549         struct radeon_encoder_atom_dig *dig_enc;
 550
 551         radeon_connector = radeon_mst_find_connector(encoder);
 552         if (!radeon_connector) {
 553                 DRM_DEBUG_KMS("failed to find connector %p\n", encoder);
 554                 return;
 555         }
 556         radeon_encoder = to_radeon_encoder(encoder);
 557
 558         radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
 559
 560         mst_enc = radeon_encoder->enc_priv;
 561
 562         primary = mst_enc->primary;
 563
 564         dig_enc = primary->enc_priv;
 565
 566         mst_enc->port = radeon_connector->port;
 567
 568         if (dig_enc->dig_encoder == -1) {
 569                 dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1);
 570                 primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder);
 571                 atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder);
 572
 573
 574         }
 575         DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset);
 576 }
 577
 578 static void
 579 radeon_mst_encoder_mode_set(struct drm_encoder *encoder,
 580                              struct drm_display_mode *mode,
 581                              struct drm_display_mode *adjusted_mode)
 582 {
 583         DRM_DEBUG_KMS("\n");
 584 }
 585
 586 static void radeon_mst_encoder_commit(struct drm_encoder *encoder)
 587 {
 588         radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
 589         DRM_DEBUG_KMS("\n");
 590 }
 591
 592 static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = {
 593         .dpms = radeon_mst_encoder_dpms,
 594         .mode_fixup = radeon_mst_mode_fixup,
 595         .prepare = radeon_mst_encoder_prepare,
 596         .mode_set = radeon_mst_encoder_mode_set,
 597         .commit = radeon_mst_encoder_commit,
 598 };
 599
 600 void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder)
 601 {
 602         drm_encoder_cleanup(encoder);
 603         kfree(encoder);
 604 }
 605
 606 static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = {
 607         .destroy = radeon_dp_mst_encoder_destroy,
 608 };
 609
 610 static struct radeon_encoder *
 611 radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector)
 612 {
 613         struct drm_device *dev = connector->base.dev;
 614         struct radeon_device *rdev = dev->dev_private;
 615         struct radeon_encoder *radeon_encoder;
 616         struct radeon_encoder_mst *mst_enc;
 617         struct drm_encoder *encoder;
 618         const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private;
 619         struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base);
 620
 621         DRM_DEBUG_KMS("enc master is %p\n", enc_master);
 622         radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL);
 623         if (!radeon_encoder)
 624                 return NULL;
 625
 626         radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL);
 627         if (!radeon_encoder->enc_priv) {
 628                 kfree(radeon_encoder);
 629                 return NULL;
 630         }
 631         encoder = &radeon_encoder->base;
 632         switch (rdev->num_crtc) {
 633         case 1:
 634                 encoder->possible_crtcs = 0x1;
 635                 break;
 636         case 2:
 637         default:
 638                 encoder->possible_crtcs = 0x3;
 639                 break;
 640         case 4:
 641                 encoder->possible_crtcs = 0xf;
 642                 break;
 643         case 6:
 644                 encoder->possible_crtcs = 0x3f;
 645                 break;
 646         }
 647
 648         drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs,
 649                          DRM_MODE_ENCODER_DPMST, NULL);
 650         drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs);
 651
 652         mst_enc = radeon_encoder->enc_priv;
 653         mst_enc->connector = connector;
 654         mst_enc->primary = to_radeon_encoder(enc_master);
 655         radeon_encoder->is_mst_encoder = true;
 656         return radeon_encoder;
 657 }
 658
 659 int
 660 radeon_dp_mst_init(struct radeon_connector *radeon_connector)
 661 {
 662         struct drm_device *dev = radeon_connector->base.dev;
 663
 664         if (!radeon_connector->ddc_bus->has_aux)
 665                 return 0;
 666
 667         radeon_connector->mst_mgr.cbs = &mst_cbs;
 668         return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev->dev,
 669                                             &radeon_connector->ddc_bus->aux, 16, 6,
 670                                             radeon_connector->base.base.id);
 671 }
 672
 673 int
 674 radeon_dp_mst_probe(struct radeon_connector *radeon_connector)
 675 {
 676         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 677         struct drm_device *dev = radeon_connector->base.dev;
 678         struct radeon_device *rdev = dev->dev_private;
 679         int ret;
 680         u8 msg[1];
 681
 682         if (!radeon_mst)
 683                 return 0;
 684
 685         if (!ASIC_IS_DCE5(rdev))
 686                 return 0;
 687
 688         if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)
 689                 return 0;
 690
 691         ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg,
 692                                1);
 693         if (ret) {
 694                 if (msg[0] & DP_MST_CAP) {
 695                         DRM_DEBUG_KMS("Sink is MST capable\n");
 696                         dig_connector->is_mst = true;
 697                 } else {
 698                         DRM_DEBUG_KMS("Sink is not MST capable\n");
 699                         dig_connector->is_mst = false;
 700                 }
 701
 702         }
 703         drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
 704                                         dig_connector->is_mst);
 705         return dig_connector->is_mst;
 706 }
 707
 708 int
 709 radeon_dp_mst_check_status(struct radeon_connector *radeon_connector)
 710 {
 711         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 712         int retry;
 713
 714         if (dig_connector->is_mst) {
 715                 u8 esi[16] = { 0 };
 716                 int dret;
 717                 int ret = 0;
 718                 bool handled;
 719
 720                 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
 721                                        DP_SINK_COUNT_ESI, esi, 8);
 722 go_again:
 723                 if (dret == 8) {
 724                         DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
 725                         ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled);
 726
 727                         if (handled) {
 728                                 for (retry = 0; retry < 3; retry++) {
 729                                         int wret;
 730                                         wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux,
 731                                                                  DP_SINK_COUNT_ESI + 1, &esi[1], 3);
 732                                         if (wret == 3)
 733                                                 break;
 734                                 }
 735
 736                                 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
 737                                                         DP_SINK_COUNT_ESI, esi, 8);
 738                                 if (dret == 8) {
 739                                         DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
 740                                         goto go_again;
 741                                 }
 742                         } else
 743                                 ret = 0;
 744
 745                         return ret;
 746                 } else {
 747                         DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret);
 748                         dig_connector->is_mst = false;
 749                         drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
 750                                                         dig_connector->is_mst);
 751                         /* send a hotplug event */
 752                 }
 753         }
 754         return -EINVAL;
 755 }
 756
 757 #if defined(CONFIG_DEBUG_FS)
 758
 759 static int radeon_debugfs_mst_info(struct seq_file *m, void *data)
 760 {
 761         struct drm_info_node *node = (struct drm_info_node *)m->private;
 762         struct drm_device *dev = node->minor->dev;
 763         struct drm_connector *connector;
 764         struct radeon_connector *radeon_connector;
 765         struct radeon_connector_atom_dig *dig_connector;
 766         int i;
 767
 768         drm_modeset_lock_all(dev);
 769         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 770                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 771                         continue;
 772
 773                 radeon_connector = to_radeon_connector(connector);
 774                 dig_connector = radeon_connector->con_priv;
 775                 if (radeon_connector->is_mst_connector)
 776                         continue;
 777                 if (!dig_connector->is_mst)
 778                         continue;
 779                 drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr);
 780
 781                 for (i = 0; i < radeon_connector->enabled_attribs; i++)
 782                         seq_printf(m, "attrib %d: %d %d\n", i,
 783                                    radeon_connector->cur_stream_attribs[i].fe,
 784                                    radeon_connector->cur_stream_attribs[i].slots);
 785         }
 786         drm_modeset_unlock_all(dev);
 787         return 0;
 788 }
 789
 790 static struct drm_info_list radeon_debugfs_mst_list[] = {
 791         {"radeon_mst_info", &radeon_debugfs_mst_info, 0, NULL},
 792 };
 793 #endif
 794
 795 int radeon_mst_debugfs_init(struct radeon_device *rdev)
 796 {
 797 #if defined(CONFIG_DEBUG_FS)
 798         return radeon_debugfs_add_files(rdev, radeon_debugfs_mst_list, 1);
 799 #endif
 800         return 0;
 801 }