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EDAC: i7core, sb_edac: Don't return NOTIFY_BAD from mce_decoder callback
[linux/fpc-iii.git] / drivers / infiniband / hw / mlx5 / cq.c
bloba00ba4418de9ba79875c5b17ce9192c3fff6ba9f
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/kref.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_user_verbs.h>
36 #include <rdma/ib_cache.h>
37 #include "mlx5_ib.h"
38 #include "user.h"
39
40 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq)
41 {
42 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
43
44 ibcq->comp_handler(ibcq, ibcq->cq_context);
45 }
46
47 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
48 {
49 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
50 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
51 struct ib_cq *ibcq = &cq->ibcq;
52 struct ib_event event;
53
54 if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
55 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
56 type, mcq->cqn);
57 return;
58 }
59
60 if (ibcq->event_handler) {
61 event.device = &dev->ib_dev;
62 event.event = IB_EVENT_CQ_ERR;
63 event.element.cq = ibcq;
64 ibcq->event_handler(&event, ibcq->cq_context);
65 }
66 }
67
68 static void *get_cqe_from_buf(struct mlx5_ib_cq_buf *buf, int n, int size)
69 {
70 return mlx5_buf_offset(&buf->buf, n * size);
71 }
72
73 static void *get_cqe(struct mlx5_ib_cq *cq, int n)
74 {
75 return get_cqe_from_buf(&cq->buf, n, cq->mcq.cqe_sz);
76 }
77
78 static u8 sw_ownership_bit(int n, int nent)
79 {
80 return (n & nent) ? 1 : 0;
81 }
82
83 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
84 {
85 void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
86 struct mlx5_cqe64 *cqe64;
87
88 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
89
90 if (likely((cqe64->op_own) >> 4 != MLX5_CQE_INVALID) &&
91 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
92 return cqe;
93 } else {
94 return NULL;
95 }
96 }
97
98 static void *next_cqe_sw(struct mlx5_ib_cq *cq)
99 {
100 return get_sw_cqe(cq, cq->mcq.cons_index);
101 }
102
103 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
104 {
105 switch (wq->wr_data[idx]) {
106 case MLX5_IB_WR_UMR:
107 return 0;
108
109 case IB_WR_LOCAL_INV:
110 return IB_WC_LOCAL_INV;
111
112 case IB_WR_REG_MR:
113 return IB_WC_REG_MR;
114
115 default:
116 pr_warn("unknown completion status\n");
117 return 0;
118 }
119 }
120
121 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
122 struct mlx5_ib_wq *wq, int idx)
123 {
124 wc->wc_flags = 0;
125 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
126 case MLX5_OPCODE_RDMA_WRITE_IMM:
127 wc->wc_flags |= IB_WC_WITH_IMM;
128 case MLX5_OPCODE_RDMA_WRITE:
129 wc->opcode = IB_WC_RDMA_WRITE;
130 break;
131 case MLX5_OPCODE_SEND_IMM:
132 wc->wc_flags |= IB_WC_WITH_IMM;
133 case MLX5_OPCODE_SEND:
134 case MLX5_OPCODE_SEND_INVAL:
135 wc->opcode = IB_WC_SEND;
136 break;
137 case MLX5_OPCODE_RDMA_READ:
138 wc->opcode = IB_WC_RDMA_READ;
139 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
140 break;
141 case MLX5_OPCODE_ATOMIC_CS:
142 wc->opcode = IB_WC_COMP_SWAP;
143 wc->byte_len = 8;
144 break;
145 case MLX5_OPCODE_ATOMIC_FA:
146 wc->opcode = IB_WC_FETCH_ADD;
147 wc->byte_len = 8;
148 break;
149 case MLX5_OPCODE_ATOMIC_MASKED_CS:
150 wc->opcode = IB_WC_MASKED_COMP_SWAP;
151 wc->byte_len = 8;
152 break;
153 case MLX5_OPCODE_ATOMIC_MASKED_FA:
154 wc->opcode = IB_WC_MASKED_FETCH_ADD;
155 wc->byte_len = 8;
156 break;
157 case MLX5_OPCODE_UMR:
158 wc->opcode = get_umr_comp(wq, idx);
159 break;
160 }
161 }
162
163 enum {
164 MLX5_GRH_IN_BUFFER = 1,
165 MLX5_GRH_IN_CQE = 2,
166 };
167
168 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
169 struct mlx5_ib_qp *qp)
170 {
171 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1);
172 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
173 struct mlx5_ib_srq *srq;
174 struct mlx5_ib_wq *wq;
175 u16 wqe_ctr;
176 u8 g;
177
178 if (qp->ibqp.srq || qp->ibqp.xrcd) {
179 struct mlx5_core_srq *msrq = NULL;
180
181 if (qp->ibqp.xrcd) {
182 msrq = mlx5_core_get_srq(dev->mdev,
183 be32_to_cpu(cqe->srqn));
184 srq = to_mibsrq(msrq);
185 } else {
186 srq = to_msrq(qp->ibqp.srq);
187 }
188 if (srq) {
189 wqe_ctr = be16_to_cpu(cqe->wqe_counter);
190 wc->wr_id = srq->wrid[wqe_ctr];
191 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
192 if (msrq && atomic_dec_and_test(&msrq->refcount))
193 complete(&msrq->free);
194 }
195 } else {
196 wq = &qp->rq;
197 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
198 ++wq->tail;
199 }
200 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
201
202 switch (cqe->op_own >> 4) {
203 case MLX5_CQE_RESP_WR_IMM:
204 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
205 wc->wc_flags = IB_WC_WITH_IMM;
206 wc->ex.imm_data = cqe->imm_inval_pkey;
207 break;
208 case MLX5_CQE_RESP_SEND:
209 wc->opcode = IB_WC_RECV;
210 wc->wc_flags = IB_WC_IP_CSUM_OK;
211 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) &&
212 (cqe->hds_ip_ext & CQE_L4_OK))))
213 wc->wc_flags = 0;
214 break;
215 case MLX5_CQE_RESP_SEND_IMM:
216 wc->opcode = IB_WC_RECV;
217 wc->wc_flags = IB_WC_WITH_IMM;
218 wc->ex.imm_data = cqe->imm_inval_pkey;
219 break;
220 case MLX5_CQE_RESP_SEND_INV:
221 wc->opcode = IB_WC_RECV;
222 wc->wc_flags = IB_WC_WITH_INVALIDATE;
223 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey);
224 break;
225 }
226 wc->slid = be16_to_cpu(cqe->slid);
227 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
228 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
229 wc->dlid_path_bits = cqe->ml_path;
230 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
231 wc->wc_flags |= g ? IB_WC_GRH : 0;
232 if (unlikely(is_qp1(qp->ibqp.qp_type))) {
233 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff;
234
235 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
236 &wc->pkey_index);
237 } else {
238 wc->pkey_index = 0;
239 }
240
241 if (ll != IB_LINK_LAYER_ETHERNET)
242 return;
243
244 switch (wc->sl & 0x3) {
245 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH:
246 wc->network_hdr_type = RDMA_NETWORK_IB;
247 break;
248 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6:
249 wc->network_hdr_type = RDMA_NETWORK_IPV6;
250 break;
251 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4:
252 wc->network_hdr_type = RDMA_NETWORK_IPV4;
253 break;
254 }
255 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
256 }
257
258 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
259 {
260 __be32 *p = (__be32 *)cqe;
261 int i;
262
263 mlx5_ib_warn(dev, "dump error cqe\n");
264 for (i = 0; i < sizeof(*cqe) / 16; i++, p += 4)
265 pr_info("%08x %08x %08x %08x\n", be32_to_cpu(p[0]),
266 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
267 be32_to_cpu(p[3]));
268 }
269
270 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
271 struct mlx5_err_cqe *cqe,
272 struct ib_wc *wc)
273 {
274 int dump = 1;
275
276 switch (cqe->syndrome) {
277 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
278 wc->status = IB_WC_LOC_LEN_ERR;
279 break;
280 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
281 wc->status = IB_WC_LOC_QP_OP_ERR;
282 break;
283 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
284 wc->status = IB_WC_LOC_PROT_ERR;
285 break;
286 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
287 dump = 0;
288 wc->status = IB_WC_WR_FLUSH_ERR;
289 break;
290 case MLX5_CQE_SYNDROME_MW_BIND_ERR:
291 wc->status = IB_WC_MW_BIND_ERR;
292 break;
293 case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
294 wc->status = IB_WC_BAD_RESP_ERR;
295 break;
296 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
297 wc->status = IB_WC_LOC_ACCESS_ERR;
298 break;
299 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
300 wc->status = IB_WC_REM_INV_REQ_ERR;
301 break;
302 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
303 wc->status = IB_WC_REM_ACCESS_ERR;
304 break;
305 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
306 wc->status = IB_WC_REM_OP_ERR;
307 break;
308 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
309 wc->status = IB_WC_RETRY_EXC_ERR;
310 dump = 0;
311 break;
312 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
313 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
314 dump = 0;
315 break;
316 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
317 wc->status = IB_WC_REM_ABORT_ERR;
318 break;
319 default:
320 wc->status = IB_WC_GENERAL_ERR;
321 break;
322 }
323
324 wc->vendor_err = cqe->vendor_err_synd;
325 if (dump)
326 dump_cqe(dev, cqe);
327 }
328
329 static int is_atomic_response(struct mlx5_ib_qp *qp, uint16_t idx)
330 {
331 /* TBD: waiting decision
332 */
333 return 0;
334 }
335
336 static void *mlx5_get_atomic_laddr(struct mlx5_ib_qp *qp, uint16_t idx)
337 {
338 struct mlx5_wqe_data_seg *dpseg;
339 void *addr;
340
341 dpseg = mlx5_get_send_wqe(qp, idx) + sizeof(struct mlx5_wqe_ctrl_seg) +
342 sizeof(struct mlx5_wqe_raddr_seg) +
343 sizeof(struct mlx5_wqe_atomic_seg);
344 addr = (void *)(unsigned long)be64_to_cpu(dpseg->addr);
345 return addr;
346 }
347
348 static void handle_atomic(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
349 uint16_t idx)
350 {
351 void *addr;
352 int byte_count;
353 int i;
354
355 if (!is_atomic_response(qp, idx))
356 return;
357
358 byte_count = be32_to_cpu(cqe64->byte_cnt);
359 addr = mlx5_get_atomic_laddr(qp, idx);
360
361 if (byte_count == 4) {
362 *(uint32_t *)addr = be32_to_cpu(*((__be32 *)addr));
363 } else {
364 for (i = 0; i < byte_count; i += 8) {
365 *(uint64_t *)addr = be64_to_cpu(*((__be64 *)addr));
366 addr += 8;
367 }
368 }
369
370 return;
371 }
372
373 static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
374 u16 tail, u16 head)
375 {
376 u16 idx;
377
378 do {
379 idx = tail & (qp->sq.wqe_cnt - 1);
380 handle_atomic(qp, cqe64, idx);
381 if (idx == head)
382 break;
383
384 tail = qp->sq.w_list[idx].next;
385 } while (1);
386 tail = qp->sq.w_list[idx].next;
387 qp->sq.last_poll = tail;
388 }
389
390 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
391 {
392 mlx5_buf_free(dev->mdev, &buf->buf);
393 }
394
395 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
396 struct ib_sig_err *item)
397 {
398 u16 syndrome = be16_to_cpu(cqe->syndrome);
399
400 #define GUARD_ERR (1 << 13)
401 #define APPTAG_ERR (1 << 12)
402 #define REFTAG_ERR (1 << 11)
403
404 if (syndrome & GUARD_ERR) {
405 item->err_type = IB_SIG_BAD_GUARD;
406 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
407 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
408 } else
409 if (syndrome & REFTAG_ERR) {
410 item->err_type = IB_SIG_BAD_REFTAG;
411 item->expected = be32_to_cpu(cqe->expected_reftag);
412 item->actual = be32_to_cpu(cqe->actual_reftag);
413 } else
414 if (syndrome & APPTAG_ERR) {
415 item->err_type = IB_SIG_BAD_APPTAG;
416 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
417 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
418 } else {
419 pr_err("Got signature completion error with bad syndrome %04x\n",
420 syndrome);
421 }
422
423 item->sig_err_offset = be64_to_cpu(cqe->err_offset);
424 item->key = be32_to_cpu(cqe->mkey);
425 }
426
427 static int mlx5_poll_one(struct mlx5_ib_cq *cq,
428 struct mlx5_ib_qp **cur_qp,
429 struct ib_wc *wc)
430 {
431 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
432 struct mlx5_err_cqe *err_cqe;
433 struct mlx5_cqe64 *cqe64;
434 struct mlx5_core_qp *mqp;
435 struct mlx5_ib_wq *wq;
436 struct mlx5_sig_err_cqe *sig_err_cqe;
437 struct mlx5_core_mkey *mmkey;
438 struct mlx5_ib_mr *mr;
439 uint8_t opcode;
440 uint32_t qpn;
441 u16 wqe_ctr;
442 void *cqe;
443 int idx;
444
445 repoll:
446 cqe = next_cqe_sw(cq);
447 if (!cqe)
448 return -EAGAIN;
449
450 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
451
452 ++cq->mcq.cons_index;
453
454 /* Make sure we read CQ entry contents after we've checked the
455 * ownership bit.
456 */
457 rmb();
458
459 opcode = cqe64->op_own >> 4;
460 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
461 if (likely(cq->resize_buf)) {
462 free_cq_buf(dev, &cq->buf);
463 cq->buf = *cq->resize_buf;
464 kfree(cq->resize_buf);
465 cq->resize_buf = NULL;
466 goto repoll;
467 } else {
468 mlx5_ib_warn(dev, "unexpected resize cqe\n");
469 }
470 }
471
472 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
473 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
474 /* We do not have to take the QP table lock here,
475 * because CQs will be locked while QPs are removed
476 * from the table.
477 */
478 mqp = __mlx5_qp_lookup(dev->mdev, qpn);
479 if (unlikely(!mqp)) {
480 mlx5_ib_warn(dev, "CQE@CQ %06x for unknown QPN %6x\n",
481 cq->mcq.cqn, qpn);
482 return -EINVAL;
483 }
484
485 *cur_qp = to_mibqp(mqp);
486 }
487
488 wc->qp = &(*cur_qp)->ibqp;
489 switch (opcode) {
490 case MLX5_CQE_REQ:
491 wq = &(*cur_qp)->sq;
492 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
493 idx = wqe_ctr & (wq->wqe_cnt - 1);
494 handle_good_req(wc, cqe64, wq, idx);
495 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
496 wc->wr_id = wq->wrid[idx];
497 wq->tail = wq->wqe_head[idx] + 1;
498 wc->status = IB_WC_SUCCESS;
499 break;
500 case MLX5_CQE_RESP_WR_IMM:
501 case MLX5_CQE_RESP_SEND:
502 case MLX5_CQE_RESP_SEND_IMM:
503 case MLX5_CQE_RESP_SEND_INV:
504 handle_responder(wc, cqe64, *cur_qp);
505 wc->status = IB_WC_SUCCESS;
506 break;
507 case MLX5_CQE_RESIZE_CQ:
508 break;
509 case MLX5_CQE_REQ_ERR:
510 case MLX5_CQE_RESP_ERR:
511 err_cqe = (struct mlx5_err_cqe *)cqe64;
512 mlx5_handle_error_cqe(dev, err_cqe, wc);
513 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
514 opcode == MLX5_CQE_REQ_ERR ?
515 "Requestor" : "Responder", cq->mcq.cqn);
516 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
517 err_cqe->syndrome, err_cqe->vendor_err_synd);
518 if (opcode == MLX5_CQE_REQ_ERR) {
519 wq = &(*cur_qp)->sq;
520 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
521 idx = wqe_ctr & (wq->wqe_cnt - 1);
522 wc->wr_id = wq->wrid[idx];
523 wq->tail = wq->wqe_head[idx] + 1;
524 } else {
525 struct mlx5_ib_srq *srq;
526
527 if ((*cur_qp)->ibqp.srq) {
528 srq = to_msrq((*cur_qp)->ibqp.srq);
529 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
530 wc->wr_id = srq->wrid[wqe_ctr];
531 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
532 } else {
533 wq = &(*cur_qp)->rq;
534 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
535 ++wq->tail;
536 }
537 }
538 break;
539 case MLX5_CQE_SIG_ERR:
540 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64;
541
542 read_lock(&dev->mdev->priv.mkey_table.lock);
543 mmkey = __mlx5_mr_lookup(dev->mdev,
544 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
545 if (unlikely(!mmkey)) {
546 read_unlock(&dev->mdev->priv.mkey_table.lock);
547 mlx5_ib_warn(dev, "CQE@CQ %06x for unknown MR %6x\n",
548 cq->mcq.cqn, be32_to_cpu(sig_err_cqe->mkey));
549 return -EINVAL;
550 }
551
552 mr = to_mibmr(mmkey);
553 get_sig_err_item(sig_err_cqe, &mr->sig->err_item);
554 mr->sig->sig_err_exists = true;
555 mr->sig->sigerr_count++;
556
557 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
558 cq->mcq.cqn, mr->sig->err_item.key,
559 mr->sig->err_item.err_type,
560 mr->sig->err_item.sig_err_offset,
561 mr->sig->err_item.expected,
562 mr->sig->err_item.actual);
563
564 read_unlock(&dev->mdev->priv.mkey_table.lock);
565 goto repoll;
566 }
567
568 return 0;
569 }
570
571 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries,
572 struct ib_wc *wc)
573 {
574 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
575 struct mlx5_ib_wc *soft_wc, *next;
576 int npolled = 0;
577
578 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) {
579 if (npolled >= num_entries)
580 break;
581
582 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n",
583 cq->mcq.cqn);
584
585 wc[npolled++] = soft_wc->wc;
586 list_del(&soft_wc->list);
587 kfree(soft_wc);
588 }
589
590 return npolled;
591 }
592
593 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
594 {
595 struct mlx5_ib_cq *cq = to_mcq(ibcq);
596 struct mlx5_ib_qp *cur_qp = NULL;
597 unsigned long flags;
598 int soft_polled = 0;
599 int npolled;
600 int err = 0;
601
602 spin_lock_irqsave(&cq->lock, flags);
603
604 if (unlikely(!list_empty(&cq->wc_list)))
605 soft_polled = poll_soft_wc(cq, num_entries, wc);
606
607 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) {
608 err = mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled);
609 if (err)
610 break;
611 }
612
613 if (npolled)
614 mlx5_cq_set_ci(&cq->mcq);
615
616 spin_unlock_irqrestore(&cq->lock, flags);
617
618 if (err == 0 || err == -EAGAIN)
619 return soft_polled + npolled;
620 else
621 return err;
622 }
623
624 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
625 {
626 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
627 struct mlx5_ib_cq *cq = to_mcq(ibcq);
628 void __iomem *uar_page = mdev->priv.uuari.uars[0].map;
629 unsigned long irq_flags;
630 int ret = 0;
631
632 spin_lock_irqsave(&cq->lock, irq_flags);
633 if (cq->notify_flags != IB_CQ_NEXT_COMP)
634 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK;
635
636 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list))
637 ret = 1;
638 spin_unlock_irqrestore(&cq->lock, irq_flags);
639
640 mlx5_cq_arm(&cq->mcq,
641 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
642 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
643 uar_page,
644 MLX5_GET_DOORBELL_LOCK(&mdev->priv.cq_uar_lock),
645 to_mcq(ibcq)->mcq.cons_index);
646
647 return ret;
648 }
649
650 static int alloc_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf,
651 int nent, int cqe_size)
652 {
653 int err;
654
655 err = mlx5_buf_alloc(dev->mdev, nent * cqe_size, &buf->buf);
656 if (err)
657 return err;
658
659 buf->cqe_size = cqe_size;
660 buf->nent = nent;
661
662 return 0;
663 }
664
665 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
666 struct ib_ucontext *context, struct mlx5_ib_cq *cq,
667 int entries, struct mlx5_create_cq_mbox_in **cqb,
668 int *cqe_size, int *index, int *inlen)
669 {
670 struct mlx5_ib_create_cq ucmd;
671 size_t ucmdlen;
672 int page_shift;
673 int npages;
674 int ncont;
675 int err;
676
677 ucmdlen =
678 (udata->inlen - sizeof(struct ib_uverbs_cmd_hdr) <
679 sizeof(ucmd)) ? (sizeof(ucmd) -
680 sizeof(ucmd.reserved)) : sizeof(ucmd);
681
682 if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
683 return -EFAULT;
684
685 if (ucmdlen == sizeof(ucmd) &&
686 ucmd.reserved != 0)
687 return -EINVAL;
688
689 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128)
690 return -EINVAL;
691
692 *cqe_size = ucmd.cqe_size;
693
694 cq->buf.umem = ib_umem_get(context, ucmd.buf_addr,
695 entries * ucmd.cqe_size,
696 IB_ACCESS_LOCAL_WRITE, 1);
697 if (IS_ERR(cq->buf.umem)) {
698 err = PTR_ERR(cq->buf.umem);
699 return err;
700 }
701
702 err = mlx5_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
703 &cq->db);
704 if (err)
705 goto err_umem;
706
707 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, &npages, &page_shift,
708 &ncont, NULL);
709 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
710 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
711
712 *inlen = sizeof(**cqb) + sizeof(*(*cqb)->pas) * ncont;
713 *cqb = mlx5_vzalloc(*inlen);
714 if (!*cqb) {
715 err = -ENOMEM;
716 goto err_db;
717 }
718 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, (*cqb)->pas, 0);
719 (*cqb)->ctx.log_pg_sz = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
720
721 *index = to_mucontext(context)->uuari.uars[0].index;
722
723 return 0;
724
725 err_db:
726 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
727
728 err_umem:
729 ib_umem_release(cq->buf.umem);
730 return err;
731 }
732
733 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_ucontext *context)
734 {
735 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
736 ib_umem_release(cq->buf.umem);
737 }
738
739 static void init_cq_buf(struct mlx5_ib_cq *cq, struct mlx5_ib_cq_buf *buf)
740 {
741 int i;
742 void *cqe;
743 struct mlx5_cqe64 *cqe64;
744
745 for (i = 0; i < buf->nent; i++) {
746 cqe = get_cqe_from_buf(buf, i, buf->cqe_size);
747 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
748 cqe64->op_own = MLX5_CQE_INVALID << 4;
749 }
750 }
751
752 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
753 int entries, int cqe_size,
754 struct mlx5_create_cq_mbox_in **cqb,
755 int *index, int *inlen)
756 {
757 int err;
758
759 err = mlx5_db_alloc(dev->mdev, &cq->db);
760 if (err)
761 return err;
762
763 cq->mcq.set_ci_db = cq->db.db;
764 cq->mcq.arm_db = cq->db.db + 1;
765 cq->mcq.cqe_sz = cqe_size;
766
767 err = alloc_cq_buf(dev, &cq->buf, entries, cqe_size);
768 if (err)
769 goto err_db;
770
771 init_cq_buf(cq, &cq->buf);
772
773 *inlen = sizeof(**cqb) + sizeof(*(*cqb)->pas) * cq->buf.buf.npages;
774 *cqb = mlx5_vzalloc(*inlen);
775 if (!*cqb) {
776 err = -ENOMEM;
777 goto err_buf;
778 }
779 mlx5_fill_page_array(&cq->buf.buf, (*cqb)->pas);
780
781 (*cqb)->ctx.log_pg_sz = cq->buf.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT;
782 *index = dev->mdev->priv.uuari.uars[0].index;
783
784 return 0;
785
786 err_buf:
787 free_cq_buf(dev, &cq->buf);
788
789 err_db:
790 mlx5_db_free(dev->mdev, &cq->db);
791 return err;
792 }
793
794 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
795 {
796 free_cq_buf(dev, &cq->buf);
797 mlx5_db_free(dev->mdev, &cq->db);
798 }
799
800 static void notify_soft_wc_handler(struct work_struct *work)
801 {
802 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq,
803 notify_work);
804
805 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
806 }
807
808 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
809 const struct ib_cq_init_attr *attr,
810 struct ib_ucontext *context,
811 struct ib_udata *udata)
812 {
813 int entries = attr->cqe;
814 int vector = attr->comp_vector;
815 struct mlx5_create_cq_mbox_in *cqb = NULL;
816 struct mlx5_ib_dev *dev = to_mdev(ibdev);
817 struct mlx5_ib_cq *cq;
818 int uninitialized_var(index);
819 int uninitialized_var(inlen);
820 int cqe_size;
821 unsigned int irqn;
822 int eqn;
823 int err;
824
825 if (entries < 0)
826 return ERR_PTR(-EINVAL);
827
828 if (check_cq_create_flags(attr->flags))
829 return ERR_PTR(-EOPNOTSUPP);
830
831 entries = roundup_pow_of_two(entries + 1);
832 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
833 return ERR_PTR(-EINVAL);
834
835 cq = kzalloc(sizeof(*cq), GFP_KERNEL);
836 if (!cq)
837 return ERR_PTR(-ENOMEM);
838
839 cq->ibcq.cqe = entries - 1;
840 mutex_init(&cq->resize_mutex);
841 spin_lock_init(&cq->lock);
842 cq->resize_buf = NULL;
843 cq->resize_umem = NULL;
844 cq->create_flags = attr->flags;
845
846 if (context) {
847 err = create_cq_user(dev, udata, context, cq, entries,
848 &cqb, &cqe_size, &index, &inlen);
849 if (err)
850 goto err_create;
851 } else {
852 /* for now choose 64 bytes till we have a proper interface */
853 cqe_size = 64;
854 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
855 &index, &inlen);
856 if (err)
857 goto err_create;
858
859 INIT_WORK(&cq->notify_work, notify_soft_wc_handler);
860 }
861
862 cq->cqe_size = cqe_size;
863 cqb->ctx.cqe_sz_flags = cqe_sz_to_mlx_sz(cqe_size) << 5;
864
865 if (cq->create_flags & IB_CQ_FLAGS_IGNORE_OVERRUN)
866 cqb->ctx.cqe_sz_flags |= (1 << 1);
867
868 cqb->ctx.log_sz_usr_page = cpu_to_be32((ilog2(entries) << 24) | index);
869 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn);
870 if (err)
871 goto err_cqb;
872
873 cqb->ctx.c_eqn = cpu_to_be16(eqn);
874 cqb->ctx.db_record_addr = cpu_to_be64(cq->db.dma);
875
876 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen);
877 if (err)
878 goto err_cqb;
879
880 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
881 cq->mcq.irqn = irqn;
882 cq->mcq.comp = mlx5_ib_cq_comp;
883 cq->mcq.event = mlx5_ib_cq_event;
884
885 INIT_LIST_HEAD(&cq->wc_list);
886
887 if (context)
888 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
889 err = -EFAULT;
890 goto err_cmd;
891 }
892
893
894 kvfree(cqb);
895 return &cq->ibcq;
896
897 err_cmd:
898 mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
899
900 err_cqb:
901 kvfree(cqb);
902 if (context)
903 destroy_cq_user(cq, context);
904 else
905 destroy_cq_kernel(dev, cq);
906
907 err_create:
908 kfree(cq);
909
910 return ERR_PTR(err);
911 }
912
913
914 int mlx5_ib_destroy_cq(struct ib_cq *cq)
915 {
916 struct mlx5_ib_dev *dev = to_mdev(cq->device);
917 struct mlx5_ib_cq *mcq = to_mcq(cq);
918 struct ib_ucontext *context = NULL;
919
920 if (cq->uobject)
921 context = cq->uobject->context;
922
923 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
924 if (context)
925 destroy_cq_user(mcq, context);
926 else
927 destroy_cq_kernel(dev, mcq);
928
929 kfree(mcq);
930
931 return 0;
932 }
933
934 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
935 {
936 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
937 }
938
939 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
940 {
941 struct mlx5_cqe64 *cqe64, *dest64;
942 void *cqe, *dest;
943 u32 prod_index;
944 int nfreed = 0;
945 u8 owner_bit;
946
947 if (!cq)
948 return;
949
950 /* First we need to find the current producer index, so we
951 * know where to start cleaning from. It doesn't matter if HW
952 * adds new entries after this loop -- the QP we're worried
953 * about is already in RESET, so the new entries won't come
954 * from our QP and therefore don't need to be checked.
955 */
956 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
957 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
958 break;
959
960 /* Now sweep backwards through the CQ, removing CQ entries
961 * that match our QP by copying older entries on top of them.
962 */
963 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
964 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
965 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
966 if (is_equal_rsn(cqe64, rsn)) {
967 if (srq && (ntohl(cqe64->srqn) & 0xffffff))
968 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
969 ++nfreed;
970 } else if (nfreed) {
971 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
972 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
973 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
974 memcpy(dest, cqe, cq->mcq.cqe_sz);
975 dest64->op_own = owner_bit |
976 (dest64->op_own & ~MLX5_CQE_OWNER_MASK);
977 }
978 }
979
980 if (nfreed) {
981 cq->mcq.cons_index += nfreed;
982 /* Make sure update of buffer contents is done before
983 * updating consumer index.
984 */
985 wmb();
986 mlx5_cq_set_ci(&cq->mcq);
987 }
988 }
989
990 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
991 {
992 if (!cq)
993 return;
994
995 spin_lock_irq(&cq->lock);
996 __mlx5_ib_cq_clean(cq, qpn, srq);
997 spin_unlock_irq(&cq->lock);
998 }
999
1000 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1001 {
1002 struct mlx5_modify_cq_mbox_in *in;
1003 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1004 struct mlx5_ib_cq *mcq = to_mcq(cq);
1005 int err;
1006 u32 fsel;
1007
1008 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
1009 return -ENOSYS;
1010
1011 in = kzalloc(sizeof(*in), GFP_KERNEL);
1012 if (!in)
1013 return -ENOMEM;
1014
1015 in->cqn = cpu_to_be32(mcq->mcq.cqn);
1016 fsel = (MLX5_CQ_MODIFY_PERIOD | MLX5_CQ_MODIFY_COUNT);
1017 in->ctx.cq_period = cpu_to_be16(cq_period);
1018 in->ctx.cq_max_count = cpu_to_be16(cq_count);
1019 in->field_select = cpu_to_be32(fsel);
1020 err = mlx5_core_modify_cq(dev->mdev, &mcq->mcq, in, sizeof(*in));
1021 kfree(in);
1022
1023 if (err)
1024 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
1025
1026 return err;
1027 }
1028
1029 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1030 int entries, struct ib_udata *udata, int *npas,
1031 int *page_shift, int *cqe_size)
1032 {
1033 struct mlx5_ib_resize_cq ucmd;
1034 struct ib_umem *umem;
1035 int err;
1036 int npages;
1037 struct ib_ucontext *context = cq->buf.umem->context;
1038
1039 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
1040 if (err)
1041 return err;
1042
1043 if (ucmd.reserved0 || ucmd.reserved1)
1044 return -EINVAL;
1045
1046 umem = ib_umem_get(context, ucmd.buf_addr, entries * ucmd.cqe_size,
1047 IB_ACCESS_LOCAL_WRITE, 1);
1048 if (IS_ERR(umem)) {
1049 err = PTR_ERR(umem);
1050 return err;
1051 }
1052
1053 mlx5_ib_cont_pages(umem, ucmd.buf_addr, &npages, page_shift,
1054 npas, NULL);
1055
1056 cq->resize_umem = umem;
1057 *cqe_size = ucmd.cqe_size;
1058
1059 return 0;
1060 }
1061
1062 static void un_resize_user(struct mlx5_ib_cq *cq)
1063 {
1064 ib_umem_release(cq->resize_umem);
1065 }
1066
1067 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1068 int entries, int cqe_size)
1069 {
1070 int err;
1071
1072 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1073 if (!cq->resize_buf)
1074 return -ENOMEM;
1075
1076 err = alloc_cq_buf(dev, cq->resize_buf, entries, cqe_size);
1077 if (err)
1078 goto ex;
1079
1080 init_cq_buf(cq, cq->resize_buf);
1081
1082 return 0;
1083
1084 ex:
1085 kfree(cq->resize_buf);
1086 return err;
1087 }
1088
1089 static void un_resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
1090 {
1091 free_cq_buf(dev, cq->resize_buf);
1092 cq->resize_buf = NULL;
1093 }
1094
1095 static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1096 {
1097 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1098 struct mlx5_cqe64 *scqe64;
1099 struct mlx5_cqe64 *dcqe64;
1100 void *start_cqe;
1101 void *scqe;
1102 void *dcqe;
1103 int ssize;
1104 int dsize;
1105 int i;
1106 u8 sw_own;
1107
1108 ssize = cq->buf.cqe_size;
1109 dsize = cq->resize_buf->cqe_size;
1110 if (ssize != dsize) {
1111 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1112 return -EINVAL;
1113 }
1114
1115 i = cq->mcq.cons_index;
1116 scqe = get_sw_cqe(cq, i);
1117 scqe64 = ssize == 64 ? scqe : scqe + 64;
1118 start_cqe = scqe;
1119 if (!scqe) {
1120 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1121 return -EINVAL;
1122 }
1123
1124 while ((scqe64->op_own >> 4) != MLX5_CQE_RESIZE_CQ) {
1125 dcqe = get_cqe_from_buf(cq->resize_buf,
1126 (i + 1) & (cq->resize_buf->nent),
1127 dsize);
1128 dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1129 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1130 memcpy(dcqe, scqe, dsize);
1131 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1132
1133 ++i;
1134 scqe = get_sw_cqe(cq, i);
1135 scqe64 = ssize == 64 ? scqe : scqe + 64;
1136 if (!scqe) {
1137 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1138 return -EINVAL;
1139 }
1140
1141 if (scqe == start_cqe) {
1142 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1143 cq->mcq.cqn);
1144 return -ENOMEM;
1145 }
1146 }
1147 ++cq->mcq.cons_index;
1148 return 0;
1149 }
1150
1151 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1152 {
1153 struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1154 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1155 struct mlx5_modify_cq_mbox_in *in;
1156 int err;
1157 int npas;
1158 int page_shift;
1159 int inlen;
1160 int uninitialized_var(cqe_size);
1161 unsigned long flags;
1162
1163 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
1164 pr_info("Firmware does not support resize CQ\n");
1165 return -ENOSYS;
1166 }
1167
1168 if (entries < 1)
1169 return -EINVAL;
1170
1171 entries = roundup_pow_of_two(entries + 1);
1172 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
1173 return -EINVAL;
1174
1175 if (entries == ibcq->cqe + 1)
1176 return 0;
1177
1178 mutex_lock(&cq->resize_mutex);
1179 if (udata) {
1180 err = resize_user(dev, cq, entries, udata, &npas, &page_shift,
1181 &cqe_size);
1182 } else {
1183 cqe_size = 64;
1184 err = resize_kernel(dev, cq, entries, cqe_size);
1185 if (!err) {
1186 npas = cq->resize_buf->buf.npages;
1187 page_shift = cq->resize_buf->buf.page_shift;
1188 }
1189 }
1190
1191 if (err)
1192 goto ex;
1193
1194 inlen = sizeof(*in) + npas * sizeof(in->pas[0]);
1195 in = mlx5_vzalloc(inlen);
1196 if (!in) {
1197 err = -ENOMEM;
1198 goto ex_resize;
1199 }
1200
1201 if (udata)
1202 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift,
1203 in->pas, 0);
1204 else
1205 mlx5_fill_page_array(&cq->resize_buf->buf, in->pas);
1206
1207 in->field_select = cpu_to_be32(MLX5_MODIFY_CQ_MASK_LOG_SIZE |
1208 MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1209 MLX5_MODIFY_CQ_MASK_PG_SIZE);
1210 in->ctx.log_pg_sz = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
1211 in->ctx.cqe_sz_flags = cqe_sz_to_mlx_sz(cqe_size) << 5;
1212 in->ctx.page_offset = 0;
1213 in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(entries) << 24);
1214 in->hdr.opmod = cpu_to_be16(MLX5_CQ_OPMOD_RESIZE);
1215 in->cqn = cpu_to_be32(cq->mcq.cqn);
1216
1217 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
1218 if (err)
1219 goto ex_alloc;
1220
1221 if (udata) {
1222 cq->ibcq.cqe = entries - 1;
1223 ib_umem_release(cq->buf.umem);
1224 cq->buf.umem = cq->resize_umem;
1225 cq->resize_umem = NULL;
1226 } else {
1227 struct mlx5_ib_cq_buf tbuf;
1228 int resized = 0;
1229
1230 spin_lock_irqsave(&cq->lock, flags);
1231 if (cq->resize_buf) {
1232 err = copy_resize_cqes(cq);
1233 if (!err) {
1234 tbuf = cq->buf;
1235 cq->buf = *cq->resize_buf;
1236 kfree(cq->resize_buf);
1237 cq->resize_buf = NULL;
1238 resized = 1;
1239 }
1240 }
1241 cq->ibcq.cqe = entries - 1;
1242 spin_unlock_irqrestore(&cq->lock, flags);
1243 if (resized)
1244 free_cq_buf(dev, &tbuf);
1245 }
1246 mutex_unlock(&cq->resize_mutex);
1247
1248 kvfree(in);
1249 return 0;
1250
1251 ex_alloc:
1252 kvfree(in);
1253
1254 ex_resize:
1255 if (udata)
1256 un_resize_user(cq);
1257 else
1258 un_resize_kernel(dev, cq);
1259 ex:
1260 mutex_unlock(&cq->resize_mutex);
1261 return err;
1262 }
1263
1264 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq)
1265 {
1266 struct mlx5_ib_cq *cq;
1267
1268 if (!ibcq)
1269 return 128;
1270
1271 cq = to_mcq(ibcq);
1272 return cq->cqe_size;
1273 }
1274
1275 /* Called from atomic context */
1276 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc)
1277 {
1278 struct mlx5_ib_wc *soft_wc;
1279 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1280 unsigned long flags;
1281
1282 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC);
1283 if (!soft_wc)
1284 return -ENOMEM;
1285
1286 soft_wc->wc = *wc;
1287 spin_lock_irqsave(&cq->lock, flags);
1288 list_add_tail(&soft_wc->list, &cq->wc_list);
1289 if (cq->notify_flags == IB_CQ_NEXT_COMP ||
1290 wc->status != IB_WC_SUCCESS) {
1291 cq->notify_flags = 0;
1292 schedule_work(&cq->notify_work);
1293 }
1294 spin_unlock_irqrestore(&cq->lock, flags);
1295
1296 return 0;
1297 }
Linux with added FPC-III support