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EDAC: i7core, sb_edac: Don't return NOTIFY_BAD from mce_decoder callback
[linux/fpc-iii.git] / drivers / scsi / lpfc / lpfc_hw.h
blobdd20412c7e4c5aea1f33a888055808827609c91e
1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2004-2015 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
20
21 #define FDMI_DID 0xfffffaU
22 #define NameServer_DID 0xfffffcU
23 #define SCR_DID 0xfffffdU
24 #define Fabric_DID 0xfffffeU
25 #define Bcast_DID 0xffffffU
26 #define Mask_DID 0xffffffU
27 #define CT_DID_MASK 0xffff00U
28 #define Fabric_DID_MASK 0xfff000U
29 #define WELL_KNOWN_DID_MASK 0xfffff0U
30
31 #define PT2PT_LocalID 1
32 #define PT2PT_RemoteID 2
33
34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36 #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */
37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
38
39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
40 0 */
41
42 #define FCELSSIZE 1024 /* maximum ELS transfer size */
43
44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47 #define LPFC_FCP_NEXT_RING 3
48 #define LPFC_FCP_OAS_RING 3
49
50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
57 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
58 #define SLI2_IOCB_CMD_R3_ENTRIES 0
59 #define SLI2_IOCB_RSP_R3_ENTRIES 0
60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62
63 #define SLI2_IOCB_CMD_SIZE 32
64 #define SLI2_IOCB_RSP_SIZE 32
65 #define SLI3_IOCB_CMD_SIZE 128
66 #define SLI3_IOCB_RSP_SIZE 64
67
68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
70
71 /* vendor ID used in SCSI netlink calls */
72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
73
74 #define FW_REV_STR_SIZE 32
75 /* Common Transport structures and definitions */
76
77 union CtRevisionId {
78 /* Structure is in Big Endian format */
79 struct {
80 uint32_t Revision:8;
81 uint32_t InId:24;
82 } bits;
83 uint32_t word;
84 };
85
86 union CtCommandResponse {
87 /* Structure is in Big Endian format */
88 struct {
89 uint32_t CmdRsp:16;
90 uint32_t Size:16;
91 } bits;
92 uint32_t word;
93 };
94
95 #define FC4_FEATURE_INIT 0x2
96 #define FC4_FEATURE_TARGET 0x1
97
98 struct lpfc_sli_ct_request {
99 /* Structure is in Big Endian format */
100 union CtRevisionId RevisionId;
101 uint8_t FsType;
102 uint8_t FsSubType;
103 uint8_t Options;
104 uint8_t Rsrvd1;
105 union CtCommandResponse CommandResponse;
106 uint8_t Rsrvd2;
107 uint8_t ReasonCode;
108 uint8_t Explanation;
109 uint8_t VendorUnique;
110 #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */
111
112 union {
113 uint32_t PortID;
114 struct gid {
115 uint8_t PortType; /* for GID_PT requests */
116 uint8_t DomainScope;
117 uint8_t AreaScope;
118 uint8_t Fc4Type; /* for GID_FT requests */
119 } gid;
120 struct rft {
121 uint32_t PortId; /* For RFT_ID requests */
122
123 #ifdef __BIG_ENDIAN_BITFIELD
124 uint32_t rsvd0:16;
125 uint32_t rsvd1:7;
126 uint32_t fcpReg:1; /* Type 8 */
127 uint32_t rsvd2:2;
128 uint32_t ipReg:1; /* Type 5 */
129 uint32_t rsvd3:5;
130 #else /* __LITTLE_ENDIAN_BITFIELD */
131 uint32_t rsvd0:16;
132 uint32_t fcpReg:1; /* Type 8 */
133 uint32_t rsvd1:7;
134 uint32_t rsvd3:5;
135 uint32_t ipReg:1; /* Type 5 */
136 uint32_t rsvd2:2;
137 #endif
138
139 uint32_t rsvd[7];
140 } rft;
141 struct rnn {
142 uint32_t PortId; /* For RNN_ID requests */
143 uint8_t wwnn[8];
144 } rnn;
145 struct rsnn { /* For RSNN_ID requests */
146 uint8_t wwnn[8];
147 uint8_t len;
148 uint8_t symbname[255];
149 } rsnn;
150 struct da_id { /* For DA_ID requests */
151 uint32_t port_id;
152 } da_id;
153 struct rspn { /* For RSPN_ID requests */
154 uint32_t PortId;
155 uint8_t len;
156 uint8_t symbname[255];
157 } rspn;
158 struct gff {
159 uint32_t PortId;
160 } gff;
161 struct gff_acc {
162 uint8_t fbits[128];
163 } gff_acc;
164 #define FCP_TYPE_FEATURE_OFFSET 7
165 struct rff {
166 uint32_t PortId;
167 uint8_t reserved[2];
168 uint8_t fbits;
169 uint8_t type_code; /* type=8 for FCP */
170 } rff;
171 } un;
172 };
173
174 #define LPFC_MAX_CT_SIZE (60 * 4096)
175
176 #define SLI_CT_REVISION 1
177 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
178 sizeof(struct gid))
179 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
180 sizeof(struct gff))
181 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
182 sizeof(struct rft))
183 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
184 sizeof(struct rff))
185 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
186 sizeof(struct rnn))
187 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
188 sizeof(struct rsnn))
189 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
190 sizeof(struct da_id))
191 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
192 sizeof(struct rspn))
193
194 /*
195 * FsType Definitions
196 */
197
198 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
199 #define SLI_CT_TIME_SERVICE 0xFB
200 #define SLI_CT_DIRECTORY_SERVICE 0xFC
201 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
202
203 /*
204 * Directory Service Subtypes
205 */
206
207 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
208
209 /*
210 * Response Codes
211 */
212
213 #define SLI_CT_RESPONSE_FS_RJT 0x8001
214 #define SLI_CT_RESPONSE_FS_ACC 0x8002
215
216 /*
217 * Reason Codes
218 */
219
220 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
221 #define SLI_CT_INVALID_COMMAND 0x01
222 #define SLI_CT_INVALID_VERSION 0x02
223 #define SLI_CT_LOGICAL_ERROR 0x03
224 #define SLI_CT_INVALID_IU_SIZE 0x04
225 #define SLI_CT_LOGICAL_BUSY 0x05
226 #define SLI_CT_PROTOCOL_ERROR 0x07
227 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
228 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
229 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
230 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
231 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
232 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
233 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
234 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
235 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
236 #define SLI_CT_VENDOR_UNIQUE 0xff
237
238 /*
239 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
240 */
241
242 #define SLI_CT_NO_PORT_ID 0x01
243 #define SLI_CT_NO_PORT_NAME 0x02
244 #define SLI_CT_NO_NODE_NAME 0x03
245 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
246 #define SLI_CT_NO_IP_ADDRESS 0x05
247 #define SLI_CT_NO_IPA 0x06
248 #define SLI_CT_NO_FC4_TYPES 0x07
249 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
250 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
251 #define SLI_CT_NO_PORT_TYPE 0x0A
252 #define SLI_CT_ACCESS_DENIED 0x10
253 #define SLI_CT_INVALID_PORT_ID 0x11
254 #define SLI_CT_DATABASE_EMPTY 0x12
255
256 /*
257 * Name Server Command Codes
258 */
259
260 #define SLI_CTNS_GA_NXT 0x0100
261 #define SLI_CTNS_GPN_ID 0x0112
262 #define SLI_CTNS_GNN_ID 0x0113
263 #define SLI_CTNS_GCS_ID 0x0114
264 #define SLI_CTNS_GFT_ID 0x0117
265 #define SLI_CTNS_GSPN_ID 0x0118
266 #define SLI_CTNS_GPT_ID 0x011A
267 #define SLI_CTNS_GFF_ID 0x011F
268 #define SLI_CTNS_GID_PN 0x0121
269 #define SLI_CTNS_GID_NN 0x0131
270 #define SLI_CTNS_GIP_NN 0x0135
271 #define SLI_CTNS_GIPA_NN 0x0136
272 #define SLI_CTNS_GSNN_NN 0x0139
273 #define SLI_CTNS_GNN_IP 0x0153
274 #define SLI_CTNS_GIPA_IP 0x0156
275 #define SLI_CTNS_GID_FT 0x0171
276 #define SLI_CTNS_GID_PT 0x01A1
277 #define SLI_CTNS_RPN_ID 0x0212
278 #define SLI_CTNS_RNN_ID 0x0213
279 #define SLI_CTNS_RCS_ID 0x0214
280 #define SLI_CTNS_RFT_ID 0x0217
281 #define SLI_CTNS_RSPN_ID 0x0218
282 #define SLI_CTNS_RPT_ID 0x021A
283 #define SLI_CTNS_RFF_ID 0x021F
284 #define SLI_CTNS_RIP_NN 0x0235
285 #define SLI_CTNS_RIPA_NN 0x0236
286 #define SLI_CTNS_RSNN_NN 0x0239
287 #define SLI_CTNS_DA_ID 0x0300
288
289 /*
290 * Port Types
291 */
292
293 #define SLI_CTPT_N_PORT 0x01
294 #define SLI_CTPT_NL_PORT 0x02
295 #define SLI_CTPT_FNL_PORT 0x03
296 #define SLI_CTPT_IP 0x04
297 #define SLI_CTPT_FCP 0x08
298 #define SLI_CTPT_NX_PORT 0x7F
299 #define SLI_CTPT_F_PORT 0x81
300 #define SLI_CTPT_FL_PORT 0x82
301 #define SLI_CTPT_E_PORT 0x84
302
303 #define SLI_CT_LAST_ENTRY 0x80000000
304
305 /* Fibre Channel Service Parameter definitions */
306
307 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
308 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
309 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
310 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
311
312 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
313 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
314 #define FC_PH3 0x20 /* FC-PH-3 version */
315
316 #define FF_FRAME_SIZE 2048
317
318 struct lpfc_name {
319 union {
320 struct {
321 #ifdef __BIG_ENDIAN_BITFIELD
322 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
323 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
324 8:11 of IEEE ext */
325 #else /* __LITTLE_ENDIAN_BITFIELD */
326 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
327 8:11 of IEEE ext */
328 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
329 #endif
330
331 #define NAME_IEEE 0x1 /* IEEE name - nameType */
332 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
333 #define NAME_FC_TYPE 0x3 /* FC native name type */
334 #define NAME_IP_TYPE 0x4 /* IP address */
335 #define NAME_CCITT_TYPE 0xC
336 #define NAME_CCITT_GR_TYPE 0xE
337 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
338 extended Lsb */
339 uint8_t IEEE[6]; /* FC IEEE address */
340 } s;
341 uint8_t wwn[8];
342 } u;
343 };
344
345 struct csp {
346 uint8_t fcphHigh; /* FC Word 0, byte 0 */
347 uint8_t fcphLow;
348 uint8_t bbCreditMsb;
349 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
350
351 /*
352 * Word 1 Bit 31 in common service parameter is overloaded.
353 * Word 1 Bit 31 in FLOGI request is multiple NPort request
354 * Word 1 Bit 31 in FLOGI response is clean address bit
355 */
356 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
357 /*
358 * Word 1 Bit 30 in common service parameter is overloaded.
359 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
360 * Word 1 Bit 30 in PLOGI request is random offset
361 */
362 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */
363 #ifdef __BIG_ENDIAN_BITFIELD
364 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
365 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
366 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
367 uint16_t fPort:1; /* FC Word 1, bit 28 */
368 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
369 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
370 uint16_t multicast:1; /* FC Word 1, bit 25 */
371 uint16_t broadcast:1; /* FC Word 1, bit 24 */
372
373 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
374 uint16_t simplex:1; /* FC Word 1, bit 22 */
375 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
376 uint16_t dhd:1; /* FC Word 1, bit 18 */
377 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
378 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
379 #else /* __LITTLE_ENDIAN_BITFIELD */
380 uint16_t broadcast:1; /* FC Word 1, bit 24 */
381 uint16_t multicast:1; /* FC Word 1, bit 25 */
382 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
383 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
384 uint16_t fPort:1; /* FC Word 1, bit 28 */
385 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
386 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
387 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
388
389 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
390 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
391 uint16_t dhd:1; /* FC Word 1, bit 18 */
392 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
393 uint16_t simplex:1; /* FC Word 1, bit 22 */
394 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
395 #endif
396
397 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
398 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
399 union {
400 struct {
401 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
402
403 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
404 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
405
406 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
407 } nPort;
408 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
409 } w2;
410
411 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
412 };
413
414 struct class_parms {
415 #ifdef __BIG_ENDIAN_BITFIELD
416 uint8_t classValid:1; /* FC Word 0, bit 31 */
417 uint8_t intermix:1; /* FC Word 0, bit 30 */
418 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
419 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
420 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
421 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
422 #else /* __LITTLE_ENDIAN_BITFIELD */
423 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
424 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
425 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
426 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
427 uint8_t intermix:1; /* FC Word 0, bit 30 */
428 uint8_t classValid:1; /* FC Word 0, bit 31 */
429
430 #endif
431
432 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
433
434 #ifdef __BIG_ENDIAN_BITFIELD
435 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
436 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
437 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
438 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
439 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
440 #else /* __LITTLE_ENDIAN_BITFIELD */
441 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
442 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
443 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
444 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
445 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
446 #endif
447
448 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
449
450 #ifdef __BIG_ENDIAN_BITFIELD
451 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
452 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
453 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
454 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
455 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
456 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
457 #else /* __LITTLE_ENDIAN_BITFIELD */
458 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
459 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
460 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
461 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
462 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
463 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
464 #endif
465
466 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
467 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
468 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
469
470 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
471 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
472 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
473 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
474
475 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
476 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
477 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
478 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
479 };
480
481 struct serv_parm { /* Structure is in Big Endian format */
482 struct csp cmn;
483 struct lpfc_name portName;
484 struct lpfc_name nodeName;
485 struct class_parms cls1;
486 struct class_parms cls2;
487 struct class_parms cls3;
488 struct class_parms cls4;
489 uint8_t vendorVersion[16];
490 };
491
492 /*
493 * Virtual Fabric Tagging Header
494 */
495 struct fc_vft_header {
496 uint32_t word0;
497 #define fc_vft_hdr_r_ctl_SHIFT 24
498 #define fc_vft_hdr_r_ctl_MASK 0xFF
499 #define fc_vft_hdr_r_ctl_WORD word0
500 #define fc_vft_hdr_ver_SHIFT 22
501 #define fc_vft_hdr_ver_MASK 0x3
502 #define fc_vft_hdr_ver_WORD word0
503 #define fc_vft_hdr_type_SHIFT 18
504 #define fc_vft_hdr_type_MASK 0xF
505 #define fc_vft_hdr_type_WORD word0
506 #define fc_vft_hdr_e_SHIFT 16
507 #define fc_vft_hdr_e_MASK 0x1
508 #define fc_vft_hdr_e_WORD word0
509 #define fc_vft_hdr_priority_SHIFT 13
510 #define fc_vft_hdr_priority_MASK 0x7
511 #define fc_vft_hdr_priority_WORD word0
512 #define fc_vft_hdr_vf_id_SHIFT 1
513 #define fc_vft_hdr_vf_id_MASK 0xFFF
514 #define fc_vft_hdr_vf_id_WORD word0
515 uint32_t word1;
516 #define fc_vft_hdr_hopct_SHIFT 24
517 #define fc_vft_hdr_hopct_MASK 0xFF
518 #define fc_vft_hdr_hopct_WORD word1
519 };
520
521 /*
522 * Extended Link Service LS_COMMAND codes (Payload Word 0)
523 */
524 #ifdef __BIG_ENDIAN_BITFIELD
525 #define ELS_CMD_MASK 0xffff0000
526 #define ELS_RSP_MASK 0xff000000
527 #define ELS_CMD_LS_RJT 0x01000000
528 #define ELS_CMD_ACC 0x02000000
529 #define ELS_CMD_PLOGI 0x03000000
530 #define ELS_CMD_FLOGI 0x04000000
531 #define ELS_CMD_LOGO 0x05000000
532 #define ELS_CMD_ABTX 0x06000000
533 #define ELS_CMD_RCS 0x07000000
534 #define ELS_CMD_RES 0x08000000
535 #define ELS_CMD_RSS 0x09000000
536 #define ELS_CMD_RSI 0x0A000000
537 #define ELS_CMD_ESTS 0x0B000000
538 #define ELS_CMD_ESTC 0x0C000000
539 #define ELS_CMD_ADVC 0x0D000000
540 #define ELS_CMD_RTV 0x0E000000
541 #define ELS_CMD_RLS 0x0F000000
542 #define ELS_CMD_ECHO 0x10000000
543 #define ELS_CMD_TEST 0x11000000
544 #define ELS_CMD_RRQ 0x12000000
545 #define ELS_CMD_REC 0x13000000
546 #define ELS_CMD_RDP 0x18000000
547 #define ELS_CMD_PRLI 0x20100014
548 #define ELS_CMD_PRLO 0x21100014
549 #define ELS_CMD_PRLO_ACC 0x02100014
550 #define ELS_CMD_PDISC 0x50000000
551 #define ELS_CMD_FDISC 0x51000000
552 #define ELS_CMD_ADISC 0x52000000
553 #define ELS_CMD_FARP 0x54000000
554 #define ELS_CMD_FARPR 0x55000000
555 #define ELS_CMD_RPS 0x56000000
556 #define ELS_CMD_RPL 0x57000000
557 #define ELS_CMD_FAN 0x60000000
558 #define ELS_CMD_RSCN 0x61040000
559 #define ELS_CMD_SCR 0x62000000
560 #define ELS_CMD_RNID 0x78000000
561 #define ELS_CMD_LIRR 0x7A000000
562 #define ELS_CMD_LCB 0x81000000
563 #else /* __LITTLE_ENDIAN_BITFIELD */
564 #define ELS_CMD_MASK 0xffff
565 #define ELS_RSP_MASK 0xff
566 #define ELS_CMD_LS_RJT 0x01
567 #define ELS_CMD_ACC 0x02
568 #define ELS_CMD_PLOGI 0x03
569 #define ELS_CMD_FLOGI 0x04
570 #define ELS_CMD_LOGO 0x05
571 #define ELS_CMD_ABTX 0x06
572 #define ELS_CMD_RCS 0x07
573 #define ELS_CMD_RES 0x08
574 #define ELS_CMD_RSS 0x09
575 #define ELS_CMD_RSI 0x0A
576 #define ELS_CMD_ESTS 0x0B
577 #define ELS_CMD_ESTC 0x0C
578 #define ELS_CMD_ADVC 0x0D
579 #define ELS_CMD_RTV 0x0E
580 #define ELS_CMD_RLS 0x0F
581 #define ELS_CMD_ECHO 0x10
582 #define ELS_CMD_TEST 0x11
583 #define ELS_CMD_RRQ 0x12
584 #define ELS_CMD_REC 0x13
585 #define ELS_CMD_RDP 0x18
586 #define ELS_CMD_PRLI 0x14001020
587 #define ELS_CMD_PRLO 0x14001021
588 #define ELS_CMD_PRLO_ACC 0x14001002
589 #define ELS_CMD_PDISC 0x50
590 #define ELS_CMD_FDISC 0x51
591 #define ELS_CMD_ADISC 0x52
592 #define ELS_CMD_FARP 0x54
593 #define ELS_CMD_FARPR 0x55
594 #define ELS_CMD_RPS 0x56
595 #define ELS_CMD_RPL 0x57
596 #define ELS_CMD_FAN 0x60
597 #define ELS_CMD_RSCN 0x0461
598 #define ELS_CMD_SCR 0x62
599 #define ELS_CMD_RNID 0x78
600 #define ELS_CMD_LIRR 0x7A
601 #define ELS_CMD_LCB 0x81
602 #endif
603
604 /*
605 * LS_RJT Payload Definition
606 */
607
608 struct ls_rjt { /* Structure is in Big Endian format */
609 union {
610 uint32_t lsRjtError;
611 struct {
612 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
613
614 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
615 /* LS_RJT reason codes */
616 #define LSRJT_INVALID_CMD 0x01
617 #define LSRJT_LOGICAL_ERR 0x03
618 #define LSRJT_LOGICAL_BSY 0x05
619 #define LSRJT_PROTOCOL_ERR 0x07
620 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
621 #define LSRJT_CMD_UNSUPPORTED 0x0B
622 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
623
624 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
625 /* LS_RJT reason explanation */
626 #define LSEXP_NOTHING_MORE 0x00
627 #define LSEXP_SPARM_OPTIONS 0x01
628 #define LSEXP_SPARM_ICTL 0x03
629 #define LSEXP_SPARM_RCTL 0x05
630 #define LSEXP_SPARM_RCV_SIZE 0x07
631 #define LSEXP_SPARM_CONCUR_SEQ 0x09
632 #define LSEXP_SPARM_CREDIT 0x0B
633 #define LSEXP_INVALID_PNAME 0x0D
634 #define LSEXP_INVALID_NNAME 0x0E
635 #define LSEXP_INVALID_CSP 0x0F
636 #define LSEXP_INVALID_ASSOC_HDR 0x11
637 #define LSEXP_ASSOC_HDR_REQ 0x13
638 #define LSEXP_INVALID_O_SID 0x15
639 #define LSEXP_INVALID_OX_RX 0x17
640 #define LSEXP_CMD_IN_PROGRESS 0x19
641 #define LSEXP_PORT_LOGIN_REQ 0x1E
642 #define LSEXP_INVALID_NPORT_ID 0x1F
643 #define LSEXP_INVALID_SEQ_ID 0x21
644 #define LSEXP_INVALID_XCHG 0x23
645 #define LSEXP_INACTIVE_XCHG 0x25
646 #define LSEXP_RQ_REQUIRED 0x27
647 #define LSEXP_OUT_OF_RESOURCE 0x29
648 #define LSEXP_CANT_GIVE_DATA 0x2A
649 #define LSEXP_REQ_UNSUPPORTED 0x2C
650 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
651 } b;
652 } un;
653 };
654
655 /*
656 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
657 */
658
659 typedef struct _LOGO { /* Structure is in Big Endian format */
660 union {
661 uint32_t nPortId32; /* Access nPortId as a word */
662 struct {
663 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
664 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
665 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
666 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
667 } b;
668 } un;
669 struct lpfc_name portName; /* N_port name field */
670 } LOGO;
671
672 /*
673 * FCP Login (PRLI Request / ACC) Payload Definition
674 */
675
676 #define PRLX_PAGE_LEN 0x10
677 #define TPRLO_PAGE_LEN 0x14
678
679 typedef struct _PRLI { /* Structure is in Big Endian format */
680 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
681
682 #define PRLI_FCP_TYPE 0x08
683 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
684
685 #ifdef __BIG_ENDIAN_BITFIELD
686 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
687 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
688 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
689
690 /* ACC = imagePairEstablished */
691 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
692 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
693 #else /* __LITTLE_ENDIAN_BITFIELD */
694 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
695 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
696 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
697 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
698 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
699 /* ACC = imagePairEstablished */
700 #endif
701
702 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
703 #define PRLI_NO_RESOURCES 0x2
704 #define PRLI_INIT_INCOMPLETE 0x3
705 #define PRLI_NO_SUCH_PA 0x4
706 #define PRLI_PREDEF_CONFIG 0x5
707 #define PRLI_PARTIAL_SUCCESS 0x6
708 #define PRLI_INVALID_PAGE_CNT 0x7
709 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
710
711 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
712
713 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
714
715 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
716 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
717
718 #ifdef __BIG_ENDIAN_BITFIELD
719 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
720 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
721 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
722 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
723 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
724 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
725 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
726 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
727 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
728 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
729 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
730 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
731 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
732 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
733 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
734 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
735 #else /* __LITTLE_ENDIAN_BITFIELD */
736 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
737 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
738 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
739 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
740 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
741 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
742 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
743 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
744 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
745 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
746 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
747 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
748 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
749 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
750 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
751 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
752 #endif
753 } PRLI;
754
755 /*
756 * FCP Logout (PRLO Request / ACC) Payload Definition
757 */
758
759 typedef struct _PRLO { /* Structure is in Big Endian format */
760 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
761
762 #define PRLO_FCP_TYPE 0x08
763 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
764
765 #ifdef __BIG_ENDIAN_BITFIELD
766 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
767 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
768 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
769 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
770 #else /* __LITTLE_ENDIAN_BITFIELD */
771 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
772 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
773 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
774 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
775 #endif
776
777 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
778 #define PRLO_NO_SUCH_IMAGE 0x4
779 #define PRLO_INVALID_PAGE_CNT 0x7
780
781 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
782
783 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
784
785 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
786
787 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
788 } PRLO;
789
790 typedef struct _ADISC { /* Structure is in Big Endian format */
791 uint32_t hardAL_PA;
792 struct lpfc_name portName;
793 struct lpfc_name nodeName;
794 uint32_t DID;
795 } ADISC;
796
797 typedef struct _FARP { /* Structure is in Big Endian format */
798 uint32_t Mflags:8;
799 uint32_t Odid:24;
800 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
801 action */
802 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
803 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
804 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
805 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
806 supported */
807 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
808 supported */
809 uint32_t Rflags:8;
810 uint32_t Rdid:24;
811 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
812 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
813 struct lpfc_name OportName;
814 struct lpfc_name OnodeName;
815 struct lpfc_name RportName;
816 struct lpfc_name RnodeName;
817 uint8_t Oipaddr[16];
818 uint8_t Ripaddr[16];
819 } FARP;
820
821 typedef struct _FAN { /* Structure is in Big Endian format */
822 uint32_t Fdid;
823 struct lpfc_name FportName;
824 struct lpfc_name FnodeName;
825 } FAN;
826
827 typedef struct _SCR { /* Structure is in Big Endian format */
828 uint8_t resvd1;
829 uint8_t resvd2;
830 uint8_t resvd3;
831 uint8_t Function;
832 #define SCR_FUNC_FABRIC 0x01
833 #define SCR_FUNC_NPORT 0x02
834 #define SCR_FUNC_FULL 0x03
835 #define SCR_CLEAR 0xff
836 } SCR;
837
838 typedef struct _RNID_TOP_DISC {
839 struct lpfc_name portName;
840 uint8_t resvd[8];
841 uint32_t unitType;
842 #define RNID_HBA 0x7
843 #define RNID_HOST 0xa
844 #define RNID_DRIVER 0xd
845 uint32_t physPort;
846 uint32_t attachedNodes;
847 uint16_t ipVersion;
848 #define RNID_IPV4 0x1
849 #define RNID_IPV6 0x2
850 uint16_t UDPport;
851 uint8_t ipAddr[16];
852 uint16_t resvd1;
853 uint16_t flags;
854 #define RNID_TD_SUPPORT 0x1
855 #define RNID_LP_VALID 0x2
856 } RNID_TOP_DISC;
857
858 typedef struct _RNID { /* Structure is in Big Endian format */
859 uint8_t Format;
860 #define RNID_TOPOLOGY_DISC 0xdf
861 uint8_t CommonLen;
862 uint8_t resvd1;
863 uint8_t SpecificLen;
864 struct lpfc_name portName;
865 struct lpfc_name nodeName;
866 union {
867 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
868 } un;
869 } RNID;
870
871 typedef struct _RPS { /* Structure is in Big Endian format */
872 union {
873 uint32_t portNum;
874 struct lpfc_name portName;
875 } un;
876 } RPS;
877
878 typedef struct _RPS_RSP { /* Structure is in Big Endian format */
879 uint16_t rsvd1;
880 uint16_t portStatus;
881 uint32_t linkFailureCnt;
882 uint32_t lossSyncCnt;
883 uint32_t lossSignalCnt;
884 uint32_t primSeqErrCnt;
885 uint32_t invalidXmitWord;
886 uint32_t crcCnt;
887 } RPS_RSP;
888
889 struct RLS { /* Structure is in Big Endian format */
890 uint32_t rls;
891 #define rls_rsvd_SHIFT 24
892 #define rls_rsvd_MASK 0x000000ff
893 #define rls_rsvd_WORD rls
894 #define rls_did_SHIFT 0
895 #define rls_did_MASK 0x00ffffff
896 #define rls_did_WORD rls
897 };
898
899 struct RLS_RSP { /* Structure is in Big Endian format */
900 uint32_t linkFailureCnt;
901 uint32_t lossSyncCnt;
902 uint32_t lossSignalCnt;
903 uint32_t primSeqErrCnt;
904 uint32_t invalidXmitWord;
905 uint32_t crcCnt;
906 };
907
908 struct RRQ { /* Structure is in Big Endian format */
909 uint32_t rrq;
910 #define rrq_rsvd_SHIFT 24
911 #define rrq_rsvd_MASK 0x000000ff
912 #define rrq_rsvd_WORD rrq
913 #define rrq_did_SHIFT 0
914 #define rrq_did_MASK 0x00ffffff
915 #define rrq_did_WORD rrq
916 uint32_t rrq_exchg;
917 #define rrq_oxid_SHIFT 16
918 #define rrq_oxid_MASK 0xffff
919 #define rrq_oxid_WORD rrq_exchg
920 #define rrq_rxid_SHIFT 0
921 #define rrq_rxid_MASK 0xffff
922 #define rrq_rxid_WORD rrq_exchg
923 };
924
925 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */
926 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
927
928 struct RTV_RSP { /* Structure is in Big Endian format */
929 uint32_t ratov;
930 uint32_t edtov;
931 uint32_t qtov;
932 #define qtov_rsvd0_SHIFT 28
933 #define qtov_rsvd0_MASK 0x0000000f
934 #define qtov_rsvd0_WORD qtov /* reserved */
935 #define qtov_edtovres_SHIFT 27
936 #define qtov_edtovres_MASK 0x00000001
937 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
938 #define qtov__rsvd1_SHIFT 19
939 #define qtov_rsvd1_MASK 0x0000003f
940 #define qtov_rsvd1_WORD qtov /* reserved */
941 #define qtov_rttov_SHIFT 18
942 #define qtov_rttov_MASK 0x00000001
943 #define qtov_rttov_WORD qtov /* R_T_TOV value */
944 #define qtov_rsvd2_SHIFT 0
945 #define qtov_rsvd2_MASK 0x0003ffff
946 #define qtov_rsvd2_WORD qtov /* reserved */
947 };
948
949
950 typedef struct _RPL { /* Structure is in Big Endian format */
951 uint32_t maxsize;
952 uint32_t index;
953 } RPL;
954
955 typedef struct _PORT_NUM_BLK {
956 uint32_t portNum;
957 uint32_t portID;
958 struct lpfc_name portName;
959 } PORT_NUM_BLK;
960
961 typedef struct _RPL_RSP { /* Structure is in Big Endian format */
962 uint32_t listLen;
963 uint32_t index;
964 PORT_NUM_BLK port_num_blk;
965 } RPL_RSP;
966
967 /* This is used for RSCN command */
968 typedef struct _D_ID { /* Structure is in Big Endian format */
969 union {
970 uint32_t word;
971 struct {
972 #ifdef __BIG_ENDIAN_BITFIELD
973 uint8_t resv;
974 uint8_t domain;
975 uint8_t area;
976 uint8_t id;
977 #else /* __LITTLE_ENDIAN_BITFIELD */
978 uint8_t id;
979 uint8_t area;
980 uint8_t domain;
981 uint8_t resv;
982 #endif
983 } b;
984 } un;
985 } D_ID;
986
987 #define RSCN_ADDRESS_FORMAT_PORT 0x0
988 #define RSCN_ADDRESS_FORMAT_AREA 0x1
989 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
990 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3
991 #define RSCN_ADDRESS_FORMAT_MASK 0x3
992
993 /*
994 * Structure to define all ELS Payload types
995 */
996
997 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
998 uint8_t elsCode; /* FC Word 0, bit 24:31 */
999 uint8_t elsByte1;
1000 uint8_t elsByte2;
1001 uint8_t elsByte3;
1002 union {
1003 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
1004 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
1005 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
1006 PRLI prli; /* Payload for PRLI/ACC */
1007 PRLO prlo; /* Payload for PRLO/ACC */
1008 ADISC adisc; /* Payload for ADISC/ACC */
1009 FARP farp; /* Payload for FARP/ACC */
1010 FAN fan; /* Payload for FAN */
1011 SCR scr; /* Payload for SCR/ACC */
1012 RNID rnid; /* Payload for RNID */
1013 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
1014 } un;
1015 } ELS_PKT;
1016
1017 /*
1018 * Link Cable Beacon (LCB) ELS Frame
1019 */
1020
1021 struct fc_lcb_request_frame {
1022 uint32_t lcb_command; /* ELS command opcode (0x81) */
1023 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1024 #define LPFC_LCB_ON 0x1
1025 #define LPFC_LCB_OFF 0x2
1026 uint8_t reserved[3];
1027
1028 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1029 #define LPFC_LCB_GREEN 0x1
1030 #define LPFC_LCB_AMBER 0x2
1031 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1032 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1033 };
1034
1035 /*
1036 * Link Cable Beacon (LCB) ELS Response Frame
1037 */
1038 struct fc_lcb_res_frame {
1039 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */
1040 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1041 uint8_t reserved[3];
1042 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1043 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1044 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1045 };
1046
1047 /*
1048 * Read Diagnostic Parameters (RDP) ELS frame.
1049 */
1050 #define SFF_PG0_IDENT_SFP 0x3
1051
1052 #define SFP_FLAG_PT_OPTICAL 0x0
1053 #define SFP_FLAG_PT_SWLASER 0x01
1054 #define SFP_FLAG_PT_LWLASER_LC1310 0x02
1055 #define SFP_FLAG_PT_LWLASER_LL1550 0x03
1056 #define SFP_FLAG_PT_MASK 0x0F
1057 #define SFP_FLAG_PT_SHIFT 0
1058
1059 #define SFP_FLAG_IS_OPTICAL_PORT 0x01
1060 #define SFP_FLAG_IS_OPTICAL_MASK 0x010
1061 #define SFP_FLAG_IS_OPTICAL_SHIFT 4
1062
1063 #define SFP_FLAG_IS_DESC_VALID 0x01
1064 #define SFP_FLAG_IS_DESC_VALID_MASK 0x020
1065 #define SFP_FLAG_IS_DESC_VALID_SHIFT 5
1066
1067 #define SFP_FLAG_CT_UNKNOWN 0x0
1068 #define SFP_FLAG_CT_SFP_PLUS 0x01
1069 #define SFP_FLAG_CT_MASK 0x3C
1070 #define SFP_FLAG_CT_SHIFT 6
1071
1072 struct fc_rdp_port_name_info {
1073 uint8_t wwnn[8];
1074 uint8_t wwpn[8];
1075 };
1076
1077
1078 /*
1079 * Link Error Status Block Structure (FC-FS-3) for RDP
1080 * This similar to RPS ELS
1081 */
1082 struct fc_link_status {
1083 uint32_t link_failure_cnt;
1084 uint32_t loss_of_synch_cnt;
1085 uint32_t loss_of_signal_cnt;
1086 uint32_t primitive_seq_proto_err;
1087 uint32_t invalid_trans_word;
1088 uint32_t invalid_crc_cnt;
1089
1090 };
1091
1092 #define RDP_PORT_NAMES_DESC_TAG 0x00010003
1093 struct fc_rdp_port_name_desc {
1094 uint32_t tag; /* 0001 0003h */
1095 uint32_t length; /* set to size of payload struct */
1096 struct fc_rdp_port_name_info port_names;
1097 };
1098
1099
1100 struct fc_rdp_fec_info {
1101 uint32_t CorrectedBlocks;
1102 uint32_t UncorrectableBlocks;
1103 };
1104
1105 #define RDP_FEC_DESC_TAG 0x00010005
1106 struct fc_fec_rdp_desc {
1107 uint32_t tag;
1108 uint32_t length;
1109 struct fc_rdp_fec_info info;
1110 };
1111
1112 struct fc_rdp_link_error_status_payload_info {
1113 struct fc_link_status link_status; /* 24 bytes */
1114 uint32_t port_type; /* bits 31-30 only */
1115 };
1116
1117 #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002
1118 struct fc_rdp_link_error_status_desc {
1119 uint32_t tag; /* 0001 0002h */
1120 uint32_t length; /* set to size of payload struct */
1121 struct fc_rdp_link_error_status_payload_info info;
1122 };
1123
1124 #define VN_PT_PHY_UNKNOWN 0x00
1125 #define VN_PT_PHY_PF_PORT 0x01
1126 #define VN_PT_PHY_ETH_MAC 0x10
1127 #define VN_PT_PHY_SHIFT 30
1128
1129 #define RDP_PS_1GB 0x8000
1130 #define RDP_PS_2GB 0x4000
1131 #define RDP_PS_4GB 0x2000
1132 #define RDP_PS_10GB 0x1000
1133 #define RDP_PS_8GB 0x0800
1134 #define RDP_PS_16GB 0x0400
1135 #define RDP_PS_32GB 0x0200
1136
1137 #define RDP_CAP_UNKNOWN 0x0001
1138 #define RDP_PS_UNKNOWN 0x0002
1139 #define RDP_PS_NOT_ESTABLISHED 0x0001
1140
1141 struct fc_rdp_port_speed {
1142 uint16_t capabilities;
1143 uint16_t speed;
1144 };
1145
1146 struct fc_rdp_port_speed_info {
1147 struct fc_rdp_port_speed port_speed;
1148 };
1149
1150 #define RDP_PORT_SPEED_DESC_TAG 0x00010001
1151 struct fc_rdp_port_speed_desc {
1152 uint32_t tag; /* 00010001h */
1153 uint32_t length; /* set to size of payload struct */
1154 struct fc_rdp_port_speed_info info;
1155 };
1156
1157 #define RDP_NPORT_ID_SIZE 4
1158 #define RDP_N_PORT_DESC_TAG 0x00000003
1159 struct fc_rdp_nport_desc {
1160 uint32_t tag; /* 0000 0003h, big endian */
1161 uint32_t length; /* size of RDP_N_PORT_ID struct */
1162 uint32_t nport_id : 12;
1163 uint32_t reserved : 8;
1164 };
1165
1166
1167 struct fc_rdp_link_service_info {
1168 uint32_t els_req; /* Request payload word 0 value.*/
1169 };
1170
1171 #define RDP_LINK_SERVICE_DESC_TAG 0x00000001
1172 struct fc_rdp_link_service_desc {
1173 uint32_t tag; /* Descriptor tag 1 */
1174 uint32_t length; /* set to size of payload struct. */
1175 struct fc_rdp_link_service_info payload;
1176 /* must be ELS req Word 0(0x18) */
1177 };
1178
1179 struct fc_rdp_sfp_info {
1180 uint16_t temperature;
1181 uint16_t vcc;
1182 uint16_t tx_bias;
1183 uint16_t tx_power;
1184 uint16_t rx_power;
1185 uint16_t flags;
1186 };
1187
1188 #define RDP_SFP_DESC_TAG 0x00010000
1189 struct fc_rdp_sfp_desc {
1190 uint32_t tag;
1191 uint32_t length; /* set to size of sfp_info struct */
1192 struct fc_rdp_sfp_info sfp_info;
1193 };
1194
1195 struct fc_rdp_req_frame {
1196 uint32_t rdp_command; /* ELS command opcode (0x18)*/
1197 uint32_t rdp_des_length; /* RDP Payload Word 1 */
1198 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
1199 };
1200
1201
1202 struct fc_rdp_res_frame {
1203 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */
1204 uint32_t length; /* FC Word 1 */
1205 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */
1206 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */
1207 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10-12 */
1208 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13-21 */
1209 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22-27 */
1210 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28-33 */
1211 struct fc_fec_rdp_desc fec_desc; /* FC Word 34 - 37 */
1212 };
1213
1214
1215 #define RDP_DESC_PAYLOAD_SIZE (sizeof(struct fc_rdp_link_service_desc) \
1216 + sizeof(struct fc_rdp_sfp_desc) \
1217 + sizeof(struct fc_rdp_port_speed_desc) \
1218 + sizeof(struct fc_rdp_link_error_status_desc) \
1219 + (sizeof(struct fc_rdp_port_name_desc) * 2))
1220
1221
1222 /******** FDMI ********/
1223
1224 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
1225 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */
1226
1227 /*
1228 * Registered Port List Format
1229 */
1230 struct lpfc_fdmi_reg_port_list {
1231 uint32_t EntryCnt;
1232 uint32_t pe; /* Variable-length array */
1233 };
1234
1235
1236 /* Definitions for HBA / Port attribute entries */
1237
1238 struct lpfc_fdmi_attr_def { /* Defined in TLV format */
1239 /* Structure is in Big Endian format */
1240 uint32_t AttrType:16;
1241 uint32_t AttrLen:16;
1242 uint32_t AttrValue; /* Marks start of Value (ATTRIBUTE_ENTRY) */
1243 };
1244
1245
1246 /* Attribute Entry */
1247 struct lpfc_fdmi_attr_entry {
1248 union {
1249 uint32_t AttrInt;
1250 uint8_t AttrTypes[32];
1251 uint8_t AttrString[256];
1252 struct lpfc_name AttrWWN;
1253 } un;
1254 };
1255
1256 #define LPFC_FDMI_MAX_AE_SIZE sizeof(struct lpfc_fdmi_attr_entry)
1257
1258 /*
1259 * HBA Attribute Block
1260 */
1261 struct lpfc_fdmi_attr_block {
1262 uint32_t EntryCnt; /* Number of HBA attribute entries */
1263 struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */
1264 };
1265
1266 /*
1267 * Port Entry
1268 */
1269 struct lpfc_fdmi_port_entry {
1270 struct lpfc_name PortName;
1271 };
1272
1273 /*
1274 * HBA Identifier
1275 */
1276 struct lpfc_fdmi_hba_ident {
1277 struct lpfc_name PortName;
1278 };
1279
1280 /*
1281 * Register HBA(RHBA)
1282 */
1283 struct lpfc_fdmi_reg_hba {
1284 struct lpfc_fdmi_hba_ident hi;
1285 struct lpfc_fdmi_reg_port_list rpl; /* variable-length array */
1286 /* struct lpfc_fdmi_attr_block ab; */
1287 };
1288
1289 /*
1290 * Register HBA Attributes (RHAT)
1291 */
1292 struct lpfc_fdmi_reg_hbaattr {
1293 struct lpfc_name HBA_PortName;
1294 struct lpfc_fdmi_attr_block ab;
1295 };
1296
1297 /*
1298 * Register Port Attributes (RPA)
1299 */
1300 struct lpfc_fdmi_reg_portattr {
1301 struct lpfc_name PortName;
1302 struct lpfc_fdmi_attr_block ab;
1303 };
1304
1305 /*
1306 * HBA MAnagement Operations Command Codes
1307 */
1308 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
1309 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
1310 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
1311 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
1312 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */
1313 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
1314 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
1315 #define SLI_MGMT_RPRT 0x210 /* Register Port */
1316 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1317 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1318 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */
1319 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
1320 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */
1321
1322 #define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */
1323
1324 /*
1325 * HBA Attribute Types
1326 */
1327 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */
1328 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */
1329 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */
1330 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */
1331 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */
1332 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */
1333 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */
1334 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1335 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */
1336 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */
1337 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1338 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */
1339 #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */
1340 #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */
1341 #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */
1342 #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */
1343 #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */
1344 #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */
1345
1346 /* Bit mask for all individual HBA attributes */
1347 #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001
1348 #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002
1349 #define LPFC_FDMI_HBA_ATTR_sn 0x00000004
1350 #define LPFC_FDMI_HBA_ATTR_model 0x00000008
1351 #define LPFC_FDMI_HBA_ATTR_description 0x00000010
1352 #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020
1353 #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040
1354 #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080
1355 #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100
1356 #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200
1357 #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400
1358 #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800
1359 #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */
1360 #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000
1361 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000
1362 #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000
1363 #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */
1364 #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000
1365
1366 /* Bit mask for FDMI-1 defined HBA attributes */
1367 #define LPFC_FDMI1_HBA_ATTR 0x000007ff
1368
1369 /* Bit mask for FDMI-2 defined HBA attributes */
1370 /* Skip vendor_info and bios_state */
1371 #define LPFC_FDMI2_HBA_ATTR 0x0002efff
1372
1373 /*
1374 * Port Attrubute Types
1375 */
1376 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */
1377 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */
1378 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */
1379 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */
1380 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */
1381 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */
1382 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */
1383 #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */
1384 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */
1385 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */
1386 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */
1387 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */
1388 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */
1389 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */
1390 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */
1391 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */
1392 #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */
1393 #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */
1394 #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */
1395 #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */
1396 #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */
1397 #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */
1398 #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */
1399
1400 /* Bit mask for all individual PORT attributes */
1401 #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001
1402 #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002
1403 #define LPFC_FDMI_PORT_ATTR_speed 0x00000004
1404 #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008
1405 #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010
1406 #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020
1407 #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040
1408 #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080
1409 #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100
1410 #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200
1411 #define LPFC_FDMI_PORT_ATTR_class 0x00000400
1412 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800
1413 #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000
1414 #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000
1415 #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000
1416 #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000
1417 #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */
1418 #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */
1419 #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */
1420 #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */
1421 #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */
1422 #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */
1423 #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */
1424
1425 /* Bit mask for FDMI-1 defined PORT attributes */
1426 #define LPFC_FDMI1_PORT_ATTR 0x0000003f
1427
1428 /* Bit mask for FDMI-2 defined PORT attributes */
1429 #define LPFC_FDMI2_PORT_ATTR 0x0000ffff
1430
1431 /* Bit mask for Smart SAN defined PORT attributes */
1432 #define LPFC_FDMI2_SMART_ATTR 0x007fffff
1433
1434 /* Defines for PORT port state attribute */
1435 #define LPFC_FDMI_PORTSTATE_UNKNOWN 1
1436 #define LPFC_FDMI_PORTSTATE_ONLINE 2
1437
1438 /* Defines for PORT port type attribute */
1439 #define LPFC_FDMI_PORTTYPE_UNKNOWN 0
1440 #define LPFC_FDMI_PORTTYPE_NPORT 1
1441 #define LPFC_FDMI_PORTTYPE_NLPORT 2
1442
1443 /*
1444 * Begin HBA configuration parameters.
1445 * The PCI configuration register BAR assignments are:
1446 * BAR0, offset 0x10 - SLIM base memory address
1447 * BAR1, offset 0x14 - SLIM base memory high address
1448 * BAR2, offset 0x18 - REGISTER base memory address
1449 * BAR3, offset 0x1c - REGISTER base memory high address
1450 * BAR4, offset 0x20 - BIU I/O registers
1451 * BAR5, offset 0x24 - REGISTER base io high address
1452 */
1453
1454 /* Number of rings currently used and available. */
1455 #define MAX_SLI3_CONFIGURED_RINGS 3
1456 #define MAX_SLI3_RINGS 4
1457
1458 /* IOCB / Mailbox is owned by FireFly */
1459 #define OWN_CHIP 1
1460
1461 /* IOCB / Mailbox is owned by Host */
1462 #define OWN_HOST 0
1463
1464 /* Number of 4-byte words in an IOCB. */
1465 #define IOCB_WORD_SZ 8
1466
1467 /* network headers for Dfctl field */
1468 #define FC_NET_HDR 0x20
1469
1470 /* Start FireFly Register definitions */
1471 #define PCI_VENDOR_ID_EMULEX 0x10df
1472 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1473 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1474 #define PCI_DEVICE_ID_BALIUS 0xe131
1475 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1476 #define PCI_DEVICE_ID_LANCER_FC 0xe200
1477 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
1478 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1479 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1480 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300
1481 #define PCI_DEVICE_ID_SAT_SMB 0xf011
1482 #define PCI_DEVICE_ID_SAT_MID 0xf015
1483 #define PCI_DEVICE_ID_RFLY 0xf095
1484 #define PCI_DEVICE_ID_PFLY 0xf098
1485 #define PCI_DEVICE_ID_LP101 0xf0a1
1486 #define PCI_DEVICE_ID_TFLY 0xf0a5
1487 #define PCI_DEVICE_ID_BSMB 0xf0d1
1488 #define PCI_DEVICE_ID_BMID 0xf0d5
1489 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1490 #define PCI_DEVICE_ID_ZMID 0xf0e5
1491 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1492 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1493 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1494 #define PCI_DEVICE_ID_SAT 0xf100
1495 #define PCI_DEVICE_ID_SAT_SCSP 0xf111
1496 #define PCI_DEVICE_ID_SAT_DCSP 0xf112
1497 #define PCI_DEVICE_ID_FALCON 0xf180
1498 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1499 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1500 #define PCI_DEVICE_ID_CENTAUR 0xf900
1501 #define PCI_DEVICE_ID_PEGASUS 0xf980
1502 #define PCI_DEVICE_ID_THOR 0xfa00
1503 #define PCI_DEVICE_ID_VIPER 0xfb00
1504 #define PCI_DEVICE_ID_LP10000S 0xfc00
1505 #define PCI_DEVICE_ID_LP11000S 0xfc10
1506 #define PCI_DEVICE_ID_LPE11000S 0xfc20
1507 #define PCI_DEVICE_ID_SAT_S 0xfc40
1508 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1509 #define PCI_DEVICE_ID_HELIOS 0xfd00
1510 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1511 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1512 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1513 #define PCI_DEVICE_ID_HORNET 0xfe05
1514 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1515 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1516 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1517 #define PCI_DEVICE_ID_TIGERSHARK 0x0704
1518 #define PCI_DEVICE_ID_TOMCAT 0x0714
1519 #define PCI_DEVICE_ID_SKYHAWK 0x0724
1520 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
1521
1522 #define JEDEC_ID_ADDRESS 0x0080001c
1523 #define FIREFLY_JEDEC_ID 0x1ACC
1524 #define SUPERFLY_JEDEC_ID 0x0020
1525 #define DRAGONFLY_JEDEC_ID 0x0021
1526 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1527 #define CENTAUR_2G_JEDEC_ID 0x0026
1528 #define CENTAUR_1G_JEDEC_ID 0x0028
1529 #define PEGASUS_ORION_JEDEC_ID 0x0036
1530 #define PEGASUS_JEDEC_ID 0x0038
1531 #define THOR_JEDEC_ID 0x0012
1532 #define HELIOS_JEDEC_ID 0x0364
1533 #define ZEPHYR_JEDEC_ID 0x0577
1534 #define VIPER_JEDEC_ID 0x4838
1535 #define SATURN_JEDEC_ID 0x1004
1536 #define HORNET_JDEC_ID 0x2057706D
1537
1538 #define JEDEC_ID_MASK 0x0FFFF000
1539 #define JEDEC_ID_SHIFT 12
1540 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1541
1542 typedef struct { /* FireFly BIU registers */
1543 uint32_t hostAtt; /* See definitions for Host Attention
1544 register */
1545 uint32_t chipAtt; /* See definitions for Chip Attention
1546 register */
1547 uint32_t hostStatus; /* See definitions for Host Status register */
1548 uint32_t hostControl; /* See definitions for Host Control register */
1549 uint32_t buiConfig; /* See definitions for BIU configuration
1550 register */
1551 } FF_REGS;
1552
1553 /* IO Register size in bytes */
1554 #define FF_REG_AREA_SIZE 256
1555
1556 /* Host Attention Register */
1557
1558 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1559
1560 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1561 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1562 #define HA_R0ATT 0x00000008 /* Bit 3 */
1563 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1564 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1565 #define HA_R1ATT 0x00000080 /* Bit 7 */
1566 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1567 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1568 #define HA_R2ATT 0x00000800 /* Bit 11 */
1569 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1570 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1571 #define HA_R3ATT 0x00008000 /* Bit 15 */
1572 #define HA_LATT 0x20000000 /* Bit 29 */
1573 #define HA_MBATT 0x40000000 /* Bit 30 */
1574 #define HA_ERATT 0x80000000 /* Bit 31 */
1575
1576 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1577 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1578 #define HA_RXATT 0x00000008 /* Bit 3 */
1579 #define HA_RXMASK 0x0000000f
1580
1581 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1582 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1583 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1584 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1585
1586 #define HA_R0_POS 3
1587 #define HA_R1_POS 7
1588 #define HA_R2_POS 11
1589 #define HA_R3_POS 15
1590 #define HA_LE_POS 29
1591 #define HA_MB_POS 30
1592 #define HA_ER_POS 31
1593 /* Chip Attention Register */
1594
1595 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1596
1597 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1598 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1599 #define CA_R0ATT 0x00000008 /* Bit 3 */
1600 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1601 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1602 #define CA_R1ATT 0x00000080 /* Bit 7 */
1603 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1604 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1605 #define CA_R2ATT 0x00000800 /* Bit 11 */
1606 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1607 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1608 #define CA_R3ATT 0x00008000 /* Bit 15 */
1609 #define CA_MBATT 0x40000000 /* Bit 30 */
1610
1611 /* Host Status Register */
1612
1613 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1614
1615 #define HS_MBRDY 0x00400000 /* Bit 22 */
1616 #define HS_FFRDY 0x00800000 /* Bit 23 */
1617 #define HS_FFER8 0x01000000 /* Bit 24 */
1618 #define HS_FFER7 0x02000000 /* Bit 25 */
1619 #define HS_FFER6 0x04000000 /* Bit 26 */
1620 #define HS_FFER5 0x08000000 /* Bit 27 */
1621 #define HS_FFER4 0x10000000 /* Bit 28 */
1622 #define HS_FFER3 0x20000000 /* Bit 29 */
1623 #define HS_FFER2 0x40000000 /* Bit 30 */
1624 #define HS_FFER1 0x80000000 /* Bit 31 */
1625 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1626 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1627 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
1628 /* Host Control Register */
1629
1630 #define HC_REG_OFFSET 12 /* Byte offset from register base address */
1631
1632 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1633 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1634 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1635 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1636 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1637 #define HC_INITHBI 0x02000000 /* Bit 25 */
1638 #define HC_INITMB 0x04000000 /* Bit 26 */
1639 #define HC_INITFF 0x08000000 /* Bit 27 */
1640 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1641 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1642
1643 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1644 #define MSIX_DFLT_ID 0
1645 #define MSIX_RNG0_ID 0
1646 #define MSIX_RNG1_ID 1
1647 #define MSIX_RNG2_ID 2
1648 #define MSIX_RNG3_ID 3
1649
1650 #define MSIX_LINK_ID 4
1651 #define MSIX_MBOX_ID 5
1652
1653 #define MSIX_SPARE0_ID 6
1654 #define MSIX_SPARE1_ID 7
1655
1656 /* Mailbox Commands */
1657 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1658 #define MBX_LOAD_SM 0x01
1659 #define MBX_READ_NV 0x02
1660 #define MBX_WRITE_NV 0x03
1661 #define MBX_RUN_BIU_DIAG 0x04
1662 #define MBX_INIT_LINK 0x05
1663 #define MBX_DOWN_LINK 0x06
1664 #define MBX_CONFIG_LINK 0x07
1665 #define MBX_CONFIG_RING 0x09
1666 #define MBX_RESET_RING 0x0A
1667 #define MBX_READ_CONFIG 0x0B
1668 #define MBX_READ_RCONFIG 0x0C
1669 #define MBX_READ_SPARM 0x0D
1670 #define MBX_READ_STATUS 0x0E
1671 #define MBX_READ_RPI 0x0F
1672 #define MBX_READ_XRI 0x10
1673 #define MBX_READ_REV 0x11
1674 #define MBX_READ_LNK_STAT 0x12
1675 #define MBX_REG_LOGIN 0x13
1676 #define MBX_UNREG_LOGIN 0x14
1677 #define MBX_CLEAR_LA 0x16
1678 #define MBX_DUMP_MEMORY 0x17
1679 #define MBX_DUMP_CONTEXT 0x18
1680 #define MBX_RUN_DIAGS 0x19
1681 #define MBX_RESTART 0x1A
1682 #define MBX_UPDATE_CFG 0x1B
1683 #define MBX_DOWN_LOAD 0x1C
1684 #define MBX_DEL_LD_ENTRY 0x1D
1685 #define MBX_RUN_PROGRAM 0x1E
1686 #define MBX_SET_MASK 0x20
1687 #define MBX_SET_VARIABLE 0x21
1688 #define MBX_UNREG_D_ID 0x23
1689 #define MBX_KILL_BOARD 0x24
1690 #define MBX_CONFIG_FARP 0x25
1691 #define MBX_BEACON 0x2A
1692 #define MBX_CONFIG_MSI 0x30
1693 #define MBX_HEARTBEAT 0x31
1694 #define MBX_WRITE_VPARMS 0x32
1695 #define MBX_ASYNCEVT_ENABLE 0x33
1696 #define MBX_READ_EVENT_LOG_STATUS 0x37
1697 #define MBX_READ_EVENT_LOG 0x38
1698 #define MBX_WRITE_EVENT_LOG 0x39
1699
1700 #define MBX_PORT_CAPABILITIES 0x3B
1701 #define MBX_PORT_IOV_CONTROL 0x3C
1702
1703 #define MBX_CONFIG_HBQ 0x7C
1704 #define MBX_LOAD_AREA 0x81
1705 #define MBX_RUN_BIU_DIAG64 0x84
1706 #define MBX_CONFIG_PORT 0x88
1707 #define MBX_READ_SPARM64 0x8D
1708 #define MBX_READ_RPI64 0x8F
1709 #define MBX_REG_LOGIN64 0x93
1710 #define MBX_READ_TOPOLOGY 0x95
1711 #define MBX_REG_VPI 0x96
1712 #define MBX_UNREG_VPI 0x97
1713
1714 #define MBX_WRITE_WWN 0x98
1715 #define MBX_SET_DEBUG 0x99
1716 #define MBX_LOAD_EXP_ROM 0x9C
1717 #define MBX_SLI4_CONFIG 0x9B
1718 #define MBX_SLI4_REQ_FTRS 0x9D
1719 #define MBX_MAX_CMDS 0x9E
1720 #define MBX_RESUME_RPI 0x9E
1721 #define MBX_SLI2_CMD_MASK 0x80
1722 #define MBX_REG_VFI 0x9F
1723 #define MBX_REG_FCFI 0xA0
1724 #define MBX_UNREG_VFI 0xA1
1725 #define MBX_UNREG_FCFI 0xA2
1726 #define MBX_INIT_VFI 0xA3
1727 #define MBX_INIT_VPI 0xA4
1728 #define MBX_ACCESS_VDATA 0xA5
1729
1730 #define MBX_AUTH_PORT 0xF8
1731 #define MBX_SECURITY_MGMT 0xF9
1732
1733 /* IOCB Commands */
1734
1735 #define CMD_RCV_SEQUENCE_CX 0x01
1736 #define CMD_XMIT_SEQUENCE_CR 0x02
1737 #define CMD_XMIT_SEQUENCE_CX 0x03
1738 #define CMD_XMIT_BCAST_CN 0x04
1739 #define CMD_XMIT_BCAST_CX 0x05
1740 #define CMD_QUE_RING_BUF_CN 0x06
1741 #define CMD_QUE_XRI_BUF_CX 0x07
1742 #define CMD_IOCB_CONTINUE_CN 0x08
1743 #define CMD_RET_XRI_BUF_CX 0x09
1744 #define CMD_ELS_REQUEST_CR 0x0A
1745 #define CMD_ELS_REQUEST_CX 0x0B
1746 #define CMD_RCV_ELS_REQ_CX 0x0D
1747 #define CMD_ABORT_XRI_CN 0x0E
1748 #define CMD_ABORT_XRI_CX 0x0F
1749 #define CMD_CLOSE_XRI_CN 0x10
1750 #define CMD_CLOSE_XRI_CX 0x11
1751 #define CMD_CREATE_XRI_CR 0x12
1752 #define CMD_CREATE_XRI_CX 0x13
1753 #define CMD_GET_RPI_CN 0x14
1754 #define CMD_XMIT_ELS_RSP_CX 0x15
1755 #define CMD_GET_RPI_CR 0x16
1756 #define CMD_XRI_ABORTED_CX 0x17
1757 #define CMD_FCP_IWRITE_CR 0x18
1758 #define CMD_FCP_IWRITE_CX 0x19
1759 #define CMD_FCP_IREAD_CR 0x1A
1760 #define CMD_FCP_IREAD_CX 0x1B
1761 #define CMD_FCP_ICMND_CR 0x1C
1762 #define CMD_FCP_ICMND_CX 0x1D
1763 #define CMD_FCP_TSEND_CX 0x1F
1764 #define CMD_FCP_TRECEIVE_CX 0x21
1765 #define CMD_FCP_TRSP_CX 0x23
1766 #define CMD_FCP_AUTO_TRSP_CX 0x29
1767
1768 #define CMD_ADAPTER_MSG 0x20
1769 #define CMD_ADAPTER_DUMP 0x22
1770
1771 /* SLI_2 IOCB Command Set */
1772
1773 #define CMD_ASYNC_STATUS 0x7C
1774 #define CMD_RCV_SEQUENCE64_CX 0x81
1775 #define CMD_XMIT_SEQUENCE64_CR 0x82
1776 #define CMD_XMIT_SEQUENCE64_CX 0x83
1777 #define CMD_XMIT_BCAST64_CN 0x84
1778 #define CMD_XMIT_BCAST64_CX 0x85
1779 #define CMD_QUE_RING_BUF64_CN 0x86
1780 #define CMD_QUE_XRI_BUF64_CX 0x87
1781 #define CMD_IOCB_CONTINUE64_CN 0x88
1782 #define CMD_RET_XRI_BUF64_CX 0x89
1783 #define CMD_ELS_REQUEST64_CR 0x8A
1784 #define CMD_ELS_REQUEST64_CX 0x8B
1785 #define CMD_ABORT_MXRI64_CN 0x8C
1786 #define CMD_RCV_ELS_REQ64_CX 0x8D
1787 #define CMD_XMIT_ELS_RSP64_CX 0x95
1788 #define CMD_XMIT_BLS_RSP64_CX 0x97
1789 #define CMD_FCP_IWRITE64_CR 0x98
1790 #define CMD_FCP_IWRITE64_CX 0x99
1791 #define CMD_FCP_IREAD64_CR 0x9A
1792 #define CMD_FCP_IREAD64_CX 0x9B
1793 #define CMD_FCP_ICMND64_CR 0x9C
1794 #define CMD_FCP_ICMND64_CX 0x9D
1795 #define CMD_FCP_TSEND64_CX 0x9F
1796 #define CMD_FCP_TRECEIVE64_CX 0xA1
1797 #define CMD_FCP_TRSP64_CX 0xA3
1798
1799 #define CMD_QUE_XRI64_CX 0xB3
1800 #define CMD_IOCB_RCV_SEQ64_CX 0xB5
1801 #define CMD_IOCB_RCV_ELS64_CX 0xB7
1802 #define CMD_IOCB_RET_XRI64_CX 0xB9
1803 #define CMD_IOCB_RCV_CONT64_CX 0xBB
1804
1805 #define CMD_GEN_REQUEST64_CR 0xC2
1806 #define CMD_GEN_REQUEST64_CX 0xC3
1807
1808 /* Unhandled SLI-3 Commands */
1809 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1810 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1811 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1812 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1813 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1814 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1815 #define CMD_IOCB_RET_HBQE64_CN 0xCA
1816 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1817 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1818 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1819 #define CMD_IOCB_LOGENTRY_CN 0x94
1820 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1821
1822 /* Data Security SLI Commands */
1823 #define DSSCMD_IWRITE64_CR 0xF8
1824 #define DSSCMD_IWRITE64_CX 0xF9
1825 #define DSSCMD_IREAD64_CR 0xFA
1826 #define DSSCMD_IREAD64_CX 0xFB
1827
1828 #define CMD_MAX_IOCB_CMD 0xFB
1829 #define CMD_IOCB_MASK 0xff
1830
1831 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1832 iocb */
1833 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
1834 /*
1835 * Define Status
1836 */
1837 #define MBX_SUCCESS 0
1838 #define MBXERR_NUM_RINGS 1
1839 #define MBXERR_NUM_IOCBS 2
1840 #define MBXERR_IOCBS_EXCEEDED 3
1841 #define MBXERR_BAD_RING_NUMBER 4
1842 #define MBXERR_MASK_ENTRIES_RANGE 5
1843 #define MBXERR_MASKS_EXCEEDED 6
1844 #define MBXERR_BAD_PROFILE 7
1845 #define MBXERR_BAD_DEF_CLASS 8
1846 #define MBXERR_BAD_MAX_RESPONDER 9
1847 #define MBXERR_BAD_MAX_ORIGINATOR 10
1848 #define MBXERR_RPI_REGISTERED 11
1849 #define MBXERR_RPI_FULL 12
1850 #define MBXERR_NO_RESOURCES 13
1851 #define MBXERR_BAD_RCV_LENGTH 14
1852 #define MBXERR_DMA_ERROR 15
1853 #define MBXERR_ERROR 16
1854 #define MBXERR_LINK_DOWN 0x33
1855 #define MBXERR_SEC_NO_PERMISSION 0xF02
1856 #define MBX_NOT_FINISHED 255
1857
1858 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1859 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1860
1861 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1862
1863 /*
1864 * return code Fail
1865 */
1866 #define FAILURE 1
1867
1868 /*
1869 * Begin Structure Definitions for Mailbox Commands
1870 */
1871
1872 typedef struct {
1873 #ifdef __BIG_ENDIAN_BITFIELD
1874 uint8_t tval;
1875 uint8_t tmask;
1876 uint8_t rval;
1877 uint8_t rmask;
1878 #else /* __LITTLE_ENDIAN_BITFIELD */
1879 uint8_t rmask;
1880 uint8_t rval;
1881 uint8_t tmask;
1882 uint8_t tval;
1883 #endif
1884 } RR_REG;
1885
1886 struct ulp_bde {
1887 uint32_t bdeAddress;
1888 #ifdef __BIG_ENDIAN_BITFIELD
1889 uint32_t bdeReserved:4;
1890 uint32_t bdeAddrHigh:4;
1891 uint32_t bdeSize:24;
1892 #else /* __LITTLE_ENDIAN_BITFIELD */
1893 uint32_t bdeSize:24;
1894 uint32_t bdeAddrHigh:4;
1895 uint32_t bdeReserved:4;
1896 #endif
1897 };
1898
1899 typedef struct ULP_BDL { /* SLI-2 */
1900 #ifdef __BIG_ENDIAN_BITFIELD
1901 uint32_t bdeFlags:8; /* BDL Flags */
1902 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1903 #else /* __LITTLE_ENDIAN_BITFIELD */
1904 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1905 uint32_t bdeFlags:8; /* BDL Flags */
1906 #endif
1907
1908 uint32_t addrLow; /* Address 0:31 */
1909 uint32_t addrHigh; /* Address 32:63 */
1910 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1911 } ULP_BDL;
1912
1913 /*
1914 * BlockGuard Definitions
1915 */
1916
1917 enum lpfc_protgrp_type {
1918 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
1919 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
1920 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
1921 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
1922 };
1923
1924 /* PDE Descriptors */
1925 #define LPFC_PDE5_DESCRIPTOR 0x85
1926 #define LPFC_PDE6_DESCRIPTOR 0x86
1927 #define LPFC_PDE7_DESCRIPTOR 0x87
1928
1929 /* BlockGuard Opcodes */
1930 #define BG_OP_IN_NODIF_OUT_CRC 0x0
1931 #define BG_OP_IN_CRC_OUT_NODIF 0x1
1932 #define BG_OP_IN_NODIF_OUT_CSUM 0x2
1933 #define BG_OP_IN_CSUM_OUT_NODIF 0x3
1934 #define BG_OP_IN_CRC_OUT_CRC 0x4
1935 #define BG_OP_IN_CSUM_OUT_CSUM 0x5
1936 #define BG_OP_IN_CRC_OUT_CSUM 0x6
1937 #define BG_OP_IN_CSUM_OUT_CRC 0x7
1938 #define BG_OP_RAW_MODE 0x8
1939
1940 struct lpfc_pde5 {
1941 uint32_t word0;
1942 #define pde5_type_SHIFT 24
1943 #define pde5_type_MASK 0x000000ff
1944 #define pde5_type_WORD word0
1945 #define pde5_rsvd0_SHIFT 0
1946 #define pde5_rsvd0_MASK 0x00ffffff
1947 #define pde5_rsvd0_WORD word0
1948 uint32_t reftag; /* Reference Tag Value */
1949 uint32_t reftagtr; /* Reference Tag Translation Value */
1950 };
1951
1952 struct lpfc_pde6 {
1953 uint32_t word0;
1954 #define pde6_type_SHIFT 24
1955 #define pde6_type_MASK 0x000000ff
1956 #define pde6_type_WORD word0
1957 #define pde6_rsvd0_SHIFT 0
1958 #define pde6_rsvd0_MASK 0x00ffffff
1959 #define pde6_rsvd0_WORD word0
1960 uint32_t word1;
1961 #define pde6_rsvd1_SHIFT 26
1962 #define pde6_rsvd1_MASK 0x0000003f
1963 #define pde6_rsvd1_WORD word1
1964 #define pde6_na_SHIFT 25
1965 #define pde6_na_MASK 0x00000001
1966 #define pde6_na_WORD word1
1967 #define pde6_rsvd2_SHIFT 16
1968 #define pde6_rsvd2_MASK 0x000001FF
1969 #define pde6_rsvd2_WORD word1
1970 #define pde6_apptagtr_SHIFT 0
1971 #define pde6_apptagtr_MASK 0x0000ffff
1972 #define pde6_apptagtr_WORD word1
1973 uint32_t word2;
1974 #define pde6_optx_SHIFT 28
1975 #define pde6_optx_MASK 0x0000000f
1976 #define pde6_optx_WORD word2
1977 #define pde6_oprx_SHIFT 24
1978 #define pde6_oprx_MASK 0x0000000f
1979 #define pde6_oprx_WORD word2
1980 #define pde6_nr_SHIFT 23
1981 #define pde6_nr_MASK 0x00000001
1982 #define pde6_nr_WORD word2
1983 #define pde6_ce_SHIFT 22
1984 #define pde6_ce_MASK 0x00000001
1985 #define pde6_ce_WORD word2
1986 #define pde6_re_SHIFT 21
1987 #define pde6_re_MASK 0x00000001
1988 #define pde6_re_WORD word2
1989 #define pde6_ae_SHIFT 20
1990 #define pde6_ae_MASK 0x00000001
1991 #define pde6_ae_WORD word2
1992 #define pde6_ai_SHIFT 19
1993 #define pde6_ai_MASK 0x00000001
1994 #define pde6_ai_WORD word2
1995 #define pde6_bs_SHIFT 16
1996 #define pde6_bs_MASK 0x00000007
1997 #define pde6_bs_WORD word2
1998 #define pde6_apptagval_SHIFT 0
1999 #define pde6_apptagval_MASK 0x0000ffff
2000 #define pde6_apptagval_WORD word2
2001 };
2002
2003 struct lpfc_pde7 {
2004 uint32_t word0;
2005 #define pde7_type_SHIFT 24
2006 #define pde7_type_MASK 0x000000ff
2007 #define pde7_type_WORD word0
2008 #define pde7_rsvd0_SHIFT 0
2009 #define pde7_rsvd0_MASK 0x00ffffff
2010 #define pde7_rsvd0_WORD word0
2011 uint32_t addrHigh;
2012 uint32_t addrLow;
2013 };
2014
2015 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
2016
2017 typedef struct {
2018 #ifdef __BIG_ENDIAN_BITFIELD
2019 uint32_t rsvd2:25;
2020 uint32_t acknowledgment:1;
2021 uint32_t version:1;
2022 uint32_t erase_or_prog:1;
2023 uint32_t update_flash:1;
2024 uint32_t update_ram:1;
2025 uint32_t method:1;
2026 uint32_t load_cmplt:1;
2027 #else /* __LITTLE_ENDIAN_BITFIELD */
2028 uint32_t load_cmplt:1;
2029 uint32_t method:1;
2030 uint32_t update_ram:1;
2031 uint32_t update_flash:1;
2032 uint32_t erase_or_prog:1;
2033 uint32_t version:1;
2034 uint32_t acknowledgment:1;
2035 uint32_t rsvd2:25;
2036 #endif
2037
2038 uint32_t dl_to_adr_low;
2039 uint32_t dl_to_adr_high;
2040 uint32_t dl_len;
2041 union {
2042 uint32_t dl_from_mbx_offset;
2043 struct ulp_bde dl_from_bde;
2044 struct ulp_bde64 dl_from_bde64;
2045 } un;
2046
2047 } LOAD_SM_VAR;
2048
2049 /* Structure for MB Command READ_NVPARM (02) */
2050
2051 typedef struct {
2052 uint32_t rsvd1[3]; /* Read as all one's */
2053 uint32_t rsvd2; /* Read as all zero's */
2054 uint32_t portname[2]; /* N_PORT name */
2055 uint32_t nodename[2]; /* NODE name */
2056
2057 #ifdef __BIG_ENDIAN_BITFIELD
2058 uint32_t pref_DID:24;
2059 uint32_t hardAL_PA:8;
2060 #else /* __LITTLE_ENDIAN_BITFIELD */
2061 uint32_t hardAL_PA:8;
2062 uint32_t pref_DID:24;
2063 #endif
2064
2065 uint32_t rsvd3[21]; /* Read as all one's */
2066 } READ_NV_VAR;
2067
2068 /* Structure for MB Command WRITE_NVPARMS (03) */
2069
2070 typedef struct {
2071 uint32_t rsvd1[3]; /* Must be all one's */
2072 uint32_t rsvd2; /* Must be all zero's */
2073 uint32_t portname[2]; /* N_PORT name */
2074 uint32_t nodename[2]; /* NODE name */
2075
2076 #ifdef __BIG_ENDIAN_BITFIELD
2077 uint32_t pref_DID:24;
2078 uint32_t hardAL_PA:8;
2079 #else /* __LITTLE_ENDIAN_BITFIELD */
2080 uint32_t hardAL_PA:8;
2081 uint32_t pref_DID:24;
2082 #endif
2083
2084 uint32_t rsvd3[21]; /* Must be all one's */
2085 } WRITE_NV_VAR;
2086
2087 /* Structure for MB Command RUN_BIU_DIAG (04) */
2088 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2089
2090 typedef struct {
2091 uint32_t rsvd1;
2092 union {
2093 struct {
2094 struct ulp_bde xmit_bde;
2095 struct ulp_bde rcv_bde;
2096 } s1;
2097 struct {
2098 struct ulp_bde64 xmit_bde64;
2099 struct ulp_bde64 rcv_bde64;
2100 } s2;
2101 } un;
2102 } BIU_DIAG_VAR;
2103
2104 /* Structure for MB command READ_EVENT_LOG (0x38) */
2105 struct READ_EVENT_LOG_VAR {
2106 uint32_t word1;
2107 #define lpfc_event_log_SHIFT 29
2108 #define lpfc_event_log_MASK 0x00000001
2109 #define lpfc_event_log_WORD word1
2110 #define USE_MAILBOX_RESPONSE 1
2111 uint32_t offset;
2112 struct ulp_bde64 rcv_bde64;
2113 };
2114
2115 /* Structure for MB Command INIT_LINK (05) */
2116
2117 typedef struct {
2118 #ifdef __BIG_ENDIAN_BITFIELD
2119 uint32_t rsvd1:24;
2120 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2121 #else /* __LITTLE_ENDIAN_BITFIELD */
2122 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2123 uint32_t rsvd1:24;
2124 #endif
2125
2126 #ifdef __BIG_ENDIAN_BITFIELD
2127 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2128 uint8_t rsvd2;
2129 uint16_t link_flags;
2130 #else /* __LITTLE_ENDIAN_BITFIELD */
2131 uint16_t link_flags;
2132 uint8_t rsvd2;
2133 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2134 #endif
2135
2136 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
2137 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
2138 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
2139 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
2140 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
2141 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
2142 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
2143
2144 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
2145 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
2146 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
2147
2148 uint32_t link_speed;
2149 #define LINK_SPEED_AUTO 0x0 /* Auto selection */
2150 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
2151 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
2152 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
2153 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
2154 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
2155 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
2156 #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */
2157
2158 } INIT_LINK_VAR;
2159
2160 /* Structure for MB Command DOWN_LINK (06) */
2161
2162 typedef struct {
2163 uint32_t rsvd1;
2164 } DOWN_LINK_VAR;
2165
2166 /* Structure for MB Command CONFIG_LINK (07) */
2167
2168 typedef struct {
2169 #ifdef __BIG_ENDIAN_BITFIELD
2170 uint32_t cr:1;
2171 uint32_t ci:1;
2172 uint32_t cr_delay:6;
2173 uint32_t cr_count:8;
2174 uint32_t rsvd1:8;
2175 uint32_t MaxBBC:8;
2176 #else /* __LITTLE_ENDIAN_BITFIELD */
2177 uint32_t MaxBBC:8;
2178 uint32_t rsvd1:8;
2179 uint32_t cr_count:8;
2180 uint32_t cr_delay:6;
2181 uint32_t ci:1;
2182 uint32_t cr:1;
2183 #endif
2184
2185 uint32_t myId;
2186 uint32_t rsvd2;
2187 uint32_t edtov;
2188 uint32_t arbtov;
2189 uint32_t ratov;
2190 uint32_t rttov;
2191 uint32_t altov;
2192 uint32_t crtov;
2193 uint32_t citov;
2194 #ifdef __BIG_ENDIAN_BITFIELD
2195 uint32_t rrq_enable:1;
2196 uint32_t rrq_immed:1;
2197 uint32_t rsvd4:29;
2198 uint32_t ack0_enable:1;
2199 #else /* __LITTLE_ENDIAN_BITFIELD */
2200 uint32_t ack0_enable:1;
2201 uint32_t rsvd4:29;
2202 uint32_t rrq_immed:1;
2203 uint32_t rrq_enable:1;
2204 #endif
2205 } CONFIG_LINK;
2206
2207 /* Structure for MB Command PART_SLIM (08)
2208 * will be removed since SLI1 is no longer supported!
2209 */
2210 typedef struct {
2211 #ifdef __BIG_ENDIAN_BITFIELD
2212 uint16_t offCiocb;
2213 uint16_t numCiocb;
2214 uint16_t offRiocb;
2215 uint16_t numRiocb;
2216 #else /* __LITTLE_ENDIAN_BITFIELD */
2217 uint16_t numCiocb;
2218 uint16_t offCiocb;
2219 uint16_t numRiocb;
2220 uint16_t offRiocb;
2221 #endif
2222 } RING_DEF;
2223
2224 typedef struct {
2225 #ifdef __BIG_ENDIAN_BITFIELD
2226 uint32_t unused1:24;
2227 uint32_t numRing:8;
2228 #else /* __LITTLE_ENDIAN_BITFIELD */
2229 uint32_t numRing:8;
2230 uint32_t unused1:24;
2231 #endif
2232
2233 RING_DEF ringdef[4];
2234 uint32_t hbainit;
2235 } PART_SLIM_VAR;
2236
2237 /* Structure for MB Command CONFIG_RING (09) */
2238
2239 typedef struct {
2240 #ifdef __BIG_ENDIAN_BITFIELD
2241 uint32_t unused2:6;
2242 uint32_t recvSeq:1;
2243 uint32_t recvNotify:1;
2244 uint32_t numMask:8;
2245 uint32_t profile:8;
2246 uint32_t unused1:4;
2247 uint32_t ring:4;
2248 #else /* __LITTLE_ENDIAN_BITFIELD */
2249 uint32_t ring:4;
2250 uint32_t unused1:4;
2251 uint32_t profile:8;
2252 uint32_t numMask:8;
2253 uint32_t recvNotify:1;
2254 uint32_t recvSeq:1;
2255 uint32_t unused2:6;
2256 #endif
2257
2258 #ifdef __BIG_ENDIAN_BITFIELD
2259 uint16_t maxRespXchg;
2260 uint16_t maxOrigXchg;
2261 #else /* __LITTLE_ENDIAN_BITFIELD */
2262 uint16_t maxOrigXchg;
2263 uint16_t maxRespXchg;
2264 #endif
2265
2266 RR_REG rrRegs[6];
2267 } CONFIG_RING_VAR;
2268
2269 /* Structure for MB Command RESET_RING (10) */
2270
2271 typedef struct {
2272 uint32_t ring_no;
2273 } RESET_RING_VAR;
2274
2275 /* Structure for MB Command READ_CONFIG (11) */
2276
2277 typedef struct {
2278 #ifdef __BIG_ENDIAN_BITFIELD
2279 uint32_t cr:1;
2280 uint32_t ci:1;
2281 uint32_t cr_delay:6;
2282 uint32_t cr_count:8;
2283 uint32_t InitBBC:8;
2284 uint32_t MaxBBC:8;
2285 #else /* __LITTLE_ENDIAN_BITFIELD */
2286 uint32_t MaxBBC:8;
2287 uint32_t InitBBC:8;
2288 uint32_t cr_count:8;
2289 uint32_t cr_delay:6;
2290 uint32_t ci:1;
2291 uint32_t cr:1;
2292 #endif
2293
2294 #ifdef __BIG_ENDIAN_BITFIELD
2295 uint32_t topology:8;
2296 uint32_t myDid:24;
2297 #else /* __LITTLE_ENDIAN_BITFIELD */
2298 uint32_t myDid:24;
2299 uint32_t topology:8;
2300 #endif
2301
2302 /* Defines for topology (defined previously) */
2303 #ifdef __BIG_ENDIAN_BITFIELD
2304 uint32_t AR:1;
2305 uint32_t IR:1;
2306 uint32_t rsvd1:29;
2307 uint32_t ack0:1;
2308 #else /* __LITTLE_ENDIAN_BITFIELD */
2309 uint32_t ack0:1;
2310 uint32_t rsvd1:29;
2311 uint32_t IR:1;
2312 uint32_t AR:1;
2313 #endif
2314
2315 uint32_t edtov;
2316 uint32_t arbtov;
2317 uint32_t ratov;
2318 uint32_t rttov;
2319 uint32_t altov;
2320 uint32_t lmt;
2321 #define LMT_RESERVED 0x000 /* Not used */
2322 #define LMT_1Gb 0x004
2323 #define LMT_2Gb 0x008
2324 #define LMT_4Gb 0x040
2325 #define LMT_8Gb 0x080
2326 #define LMT_10Gb 0x100
2327 #define LMT_16Gb 0x200
2328 #define LMT_32Gb 0x400
2329 uint32_t rsvd2;
2330 uint32_t rsvd3;
2331 uint32_t max_xri;
2332 uint32_t max_iocb;
2333 uint32_t max_rpi;
2334 uint32_t avail_xri;
2335 uint32_t avail_iocb;
2336 uint32_t avail_rpi;
2337 uint32_t max_vpi;
2338 uint32_t rsvd4;
2339 uint32_t rsvd5;
2340 uint32_t avail_vpi;
2341 } READ_CONFIG_VAR;
2342
2343 /* Structure for MB Command READ_RCONFIG (12) */
2344
2345 typedef struct {
2346 #ifdef __BIG_ENDIAN_BITFIELD
2347 uint32_t rsvd2:7;
2348 uint32_t recvNotify:1;
2349 uint32_t numMask:8;
2350 uint32_t profile:8;
2351 uint32_t rsvd1:4;
2352 uint32_t ring:4;
2353 #else /* __LITTLE_ENDIAN_BITFIELD */
2354 uint32_t ring:4;
2355 uint32_t rsvd1:4;
2356 uint32_t profile:8;
2357 uint32_t numMask:8;
2358 uint32_t recvNotify:1;
2359 uint32_t rsvd2:7;
2360 #endif
2361
2362 #ifdef __BIG_ENDIAN_BITFIELD
2363 uint16_t maxResp;
2364 uint16_t maxOrig;
2365 #else /* __LITTLE_ENDIAN_BITFIELD */
2366 uint16_t maxOrig;
2367 uint16_t maxResp;
2368 #endif
2369
2370 RR_REG rrRegs[6];
2371
2372 #ifdef __BIG_ENDIAN_BITFIELD
2373 uint16_t cmdRingOffset;
2374 uint16_t cmdEntryCnt;
2375 uint16_t rspRingOffset;
2376 uint16_t rspEntryCnt;
2377 uint16_t nextCmdOffset;
2378 uint16_t rsvd3;
2379 uint16_t nextRspOffset;
2380 uint16_t rsvd4;
2381 #else /* __LITTLE_ENDIAN_BITFIELD */
2382 uint16_t cmdEntryCnt;
2383 uint16_t cmdRingOffset;
2384 uint16_t rspEntryCnt;
2385 uint16_t rspRingOffset;
2386 uint16_t rsvd3;
2387 uint16_t nextCmdOffset;
2388 uint16_t rsvd4;
2389 uint16_t nextRspOffset;
2390 #endif
2391 } READ_RCONF_VAR;
2392
2393 /* Structure for MB Command READ_SPARM (13) */
2394 /* Structure for MB Command READ_SPARM64 (0x8D) */
2395
2396 typedef struct {
2397 uint32_t rsvd1;
2398 uint32_t rsvd2;
2399 union {
2400 struct ulp_bde sp; /* This BDE points to struct serv_parm
2401 structure */
2402 struct ulp_bde64 sp64;
2403 } un;
2404 #ifdef __BIG_ENDIAN_BITFIELD
2405 uint16_t rsvd3;
2406 uint16_t vpi;
2407 #else /* __LITTLE_ENDIAN_BITFIELD */
2408 uint16_t vpi;
2409 uint16_t rsvd3;
2410 #endif
2411 } READ_SPARM_VAR;
2412
2413 /* Structure for MB Command READ_STATUS (14) */
2414
2415 typedef struct {
2416 #ifdef __BIG_ENDIAN_BITFIELD
2417 uint32_t rsvd1:31;
2418 uint32_t clrCounters:1;
2419 uint16_t activeXriCnt;
2420 uint16_t activeRpiCnt;
2421 #else /* __LITTLE_ENDIAN_BITFIELD */
2422 uint32_t clrCounters:1;
2423 uint32_t rsvd1:31;
2424 uint16_t activeRpiCnt;
2425 uint16_t activeXriCnt;
2426 #endif
2427
2428 uint32_t xmitByteCnt;
2429 uint32_t rcvByteCnt;
2430 uint32_t xmitFrameCnt;
2431 uint32_t rcvFrameCnt;
2432 uint32_t xmitSeqCnt;
2433 uint32_t rcvSeqCnt;
2434 uint32_t totalOrigExchanges;
2435 uint32_t totalRespExchanges;
2436 uint32_t rcvPbsyCnt;
2437 uint32_t rcvFbsyCnt;
2438 } READ_STATUS_VAR;
2439
2440 /* Structure for MB Command READ_RPI (15) */
2441 /* Structure for MB Command READ_RPI64 (0x8F) */
2442
2443 typedef struct {
2444 #ifdef __BIG_ENDIAN_BITFIELD
2445 uint16_t nextRpi;
2446 uint16_t reqRpi;
2447 uint32_t rsvd2:8;
2448 uint32_t DID:24;
2449 #else /* __LITTLE_ENDIAN_BITFIELD */
2450 uint16_t reqRpi;
2451 uint16_t nextRpi;
2452 uint32_t DID:24;
2453 uint32_t rsvd2:8;
2454 #endif
2455
2456 union {
2457 struct ulp_bde sp;
2458 struct ulp_bde64 sp64;
2459 } un;
2460
2461 } READ_RPI_VAR;
2462
2463 /* Structure for MB Command READ_XRI (16) */
2464
2465 typedef struct {
2466 #ifdef __BIG_ENDIAN_BITFIELD
2467 uint16_t nextXri;
2468 uint16_t reqXri;
2469 uint16_t rsvd1;
2470 uint16_t rpi;
2471 uint32_t rsvd2:8;
2472 uint32_t DID:24;
2473 uint32_t rsvd3:8;
2474 uint32_t SID:24;
2475 uint32_t rsvd4;
2476 uint8_t seqId;
2477 uint8_t rsvd5;
2478 uint16_t seqCount;
2479 uint16_t oxId;
2480 uint16_t rxId;
2481 uint32_t rsvd6:30;
2482 uint32_t si:1;
2483 uint32_t exchOrig:1;
2484 #else /* __LITTLE_ENDIAN_BITFIELD */
2485 uint16_t reqXri;
2486 uint16_t nextXri;
2487 uint16_t rpi;
2488 uint16_t rsvd1;
2489 uint32_t DID:24;
2490 uint32_t rsvd2:8;
2491 uint32_t SID:24;
2492 uint32_t rsvd3:8;
2493 uint32_t rsvd4;
2494 uint16_t seqCount;
2495 uint8_t rsvd5;
2496 uint8_t seqId;
2497 uint16_t rxId;
2498 uint16_t oxId;
2499 uint32_t exchOrig:1;
2500 uint32_t si:1;
2501 uint32_t rsvd6:30;
2502 #endif
2503 } READ_XRI_VAR;
2504
2505 /* Structure for MB Command READ_REV (17) */
2506
2507 typedef struct {
2508 #ifdef __BIG_ENDIAN_BITFIELD
2509 uint32_t cv:1;
2510 uint32_t rr:1;
2511 uint32_t rsvd2:2;
2512 uint32_t v3req:1;
2513 uint32_t v3rsp:1;
2514 uint32_t rsvd1:25;
2515 uint32_t rv:1;
2516 #else /* __LITTLE_ENDIAN_BITFIELD */
2517 uint32_t rv:1;
2518 uint32_t rsvd1:25;
2519 uint32_t v3rsp:1;
2520 uint32_t v3req:1;
2521 uint32_t rsvd2:2;
2522 uint32_t rr:1;
2523 uint32_t cv:1;
2524 #endif
2525
2526 uint32_t biuRev;
2527 uint32_t smRev;
2528 union {
2529 uint32_t smFwRev;
2530 struct {
2531 #ifdef __BIG_ENDIAN_BITFIELD
2532 uint8_t ProgType;
2533 uint8_t ProgId;
2534 uint16_t ProgVer:4;
2535 uint16_t ProgRev:4;
2536 uint16_t ProgFixLvl:2;
2537 uint16_t ProgDistType:2;
2538 uint16_t DistCnt:4;
2539 #else /* __LITTLE_ENDIAN_BITFIELD */
2540 uint16_t DistCnt:4;
2541 uint16_t ProgDistType:2;
2542 uint16_t ProgFixLvl:2;
2543 uint16_t ProgRev:4;
2544 uint16_t ProgVer:4;
2545 uint8_t ProgId;
2546 uint8_t ProgType;
2547 #endif
2548
2549 } b;
2550 } un;
2551 uint32_t endecRev;
2552 #ifdef __BIG_ENDIAN_BITFIELD
2553 uint8_t feaLevelHigh;
2554 uint8_t feaLevelLow;
2555 uint8_t fcphHigh;
2556 uint8_t fcphLow;
2557 #else /* __LITTLE_ENDIAN_BITFIELD */
2558 uint8_t fcphLow;
2559 uint8_t fcphHigh;
2560 uint8_t feaLevelLow;
2561 uint8_t feaLevelHigh;
2562 #endif
2563
2564 uint32_t postKernRev;
2565 uint32_t opFwRev;
2566 uint8_t opFwName[16];
2567 uint32_t sli1FwRev;
2568 uint8_t sli1FwName[16];
2569 uint32_t sli2FwRev;
2570 uint8_t sli2FwName[16];
2571 uint32_t sli3Feat;
2572 uint32_t RandomData[6];
2573 } READ_REV_VAR;
2574
2575 /* Structure for MB Command READ_LINK_STAT (18) */
2576
2577 typedef struct {
2578 uint32_t word0;
2579
2580 #define lpfc_read_link_stat_rec_SHIFT 0
2581 #define lpfc_read_link_stat_rec_MASK 0x1
2582 #define lpfc_read_link_stat_rec_WORD word0
2583
2584 #define lpfc_read_link_stat_gec_SHIFT 1
2585 #define lpfc_read_link_stat_gec_MASK 0x1
2586 #define lpfc_read_link_stat_gec_WORD word0
2587
2588 #define lpfc_read_link_stat_w02oftow23of_SHIFT 2
2589 #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF
2590 #define lpfc_read_link_stat_w02oftow23of_WORD word0
2591
2592 #define lpfc_read_link_stat_rsvd_SHIFT 24
2593 #define lpfc_read_link_stat_rsvd_MASK 0x1F
2594 #define lpfc_read_link_stat_rsvd_WORD word0
2595
2596 #define lpfc_read_link_stat_gec2_SHIFT 29
2597 #define lpfc_read_link_stat_gec2_MASK 0x1
2598 #define lpfc_read_link_stat_gec2_WORD word0
2599
2600 #define lpfc_read_link_stat_clrc_SHIFT 30
2601 #define lpfc_read_link_stat_clrc_MASK 0x1
2602 #define lpfc_read_link_stat_clrc_WORD word0
2603
2604 #define lpfc_read_link_stat_clof_SHIFT 31
2605 #define lpfc_read_link_stat_clof_MASK 0x1
2606 #define lpfc_read_link_stat_clof_WORD word0
2607
2608 uint32_t linkFailureCnt;
2609 uint32_t lossSyncCnt;
2610 uint32_t lossSignalCnt;
2611 uint32_t primSeqErrCnt;
2612 uint32_t invalidXmitWord;
2613 uint32_t crcCnt;
2614 uint32_t primSeqTimeout;
2615 uint32_t elasticOverrun;
2616 uint32_t arbTimeout;
2617 uint32_t advRecBufCredit;
2618 uint32_t curRecBufCredit;
2619 uint32_t advTransBufCredit;
2620 uint32_t curTransBufCredit;
2621 uint32_t recEofCount;
2622 uint32_t recEofdtiCount;
2623 uint32_t recEofniCount;
2624 uint32_t recSofcount;
2625 uint32_t rsvd1;
2626 uint32_t rsvd2;
2627 uint32_t recDrpXriCount;
2628 uint32_t fecCorrBlkCount;
2629 uint32_t fecUncorrBlkCount;
2630 } READ_LNK_VAR;
2631
2632 /* Structure for MB Command REG_LOGIN (19) */
2633 /* Structure for MB Command REG_LOGIN64 (0x93) */
2634
2635 typedef struct {
2636 #ifdef __BIG_ENDIAN_BITFIELD
2637 uint16_t rsvd1;
2638 uint16_t rpi;
2639 uint32_t rsvd2:8;
2640 uint32_t did:24;
2641 #else /* __LITTLE_ENDIAN_BITFIELD */
2642 uint16_t rpi;
2643 uint16_t rsvd1;
2644 uint32_t did:24;
2645 uint32_t rsvd2:8;
2646 #endif
2647
2648 union {
2649 struct ulp_bde sp;
2650 struct ulp_bde64 sp64;
2651 } un;
2652
2653 #ifdef __BIG_ENDIAN_BITFIELD
2654 uint16_t rsvd6;
2655 uint16_t vpi;
2656 #else /* __LITTLE_ENDIAN_BITFIELD */
2657 uint16_t vpi;
2658 uint16_t rsvd6;
2659 #endif
2660
2661 } REG_LOGIN_VAR;
2662
2663 /* Word 30 contents for REG_LOGIN */
2664 typedef union {
2665 struct {
2666 #ifdef __BIG_ENDIAN_BITFIELD
2667 uint16_t rsvd1:12;
2668 uint16_t wd30_class:4;
2669 uint16_t xri;
2670 #else /* __LITTLE_ENDIAN_BITFIELD */
2671 uint16_t xri;
2672 uint16_t wd30_class:4;
2673 uint16_t rsvd1:12;
2674 #endif
2675 } f;
2676 uint32_t word;
2677 } REG_WD30;
2678
2679 /* Structure for MB Command UNREG_LOGIN (20) */
2680
2681 typedef struct {
2682 #ifdef __BIG_ENDIAN_BITFIELD
2683 uint16_t rsvd1;
2684 uint16_t rpi;
2685 uint32_t rsvd2;
2686 uint32_t rsvd3;
2687 uint32_t rsvd4;
2688 uint32_t rsvd5;
2689 uint16_t rsvd6;
2690 uint16_t vpi;
2691 #else /* __LITTLE_ENDIAN_BITFIELD */
2692 uint16_t rpi;
2693 uint16_t rsvd1;
2694 uint32_t rsvd2;
2695 uint32_t rsvd3;
2696 uint32_t rsvd4;
2697 uint32_t rsvd5;
2698 uint16_t vpi;
2699 uint16_t rsvd6;
2700 #endif
2701 } UNREG_LOGIN_VAR;
2702
2703 /* Structure for MB Command REG_VPI (0x96) */
2704 typedef struct {
2705 #ifdef __BIG_ENDIAN_BITFIELD
2706 uint32_t rsvd1;
2707 uint32_t rsvd2:7;
2708 uint32_t upd:1;
2709 uint32_t sid:24;
2710 uint32_t wwn[2];
2711 uint32_t rsvd5;
2712 uint16_t vfi;
2713 uint16_t vpi;
2714 #else /* __LITTLE_ENDIAN */
2715 uint32_t rsvd1;
2716 uint32_t sid:24;
2717 uint32_t upd:1;
2718 uint32_t rsvd2:7;
2719 uint32_t wwn[2];
2720 uint32_t rsvd5;
2721 uint16_t vpi;
2722 uint16_t vfi;
2723 #endif
2724 } REG_VPI_VAR;
2725
2726 /* Structure for MB Command UNREG_VPI (0x97) */
2727 typedef struct {
2728 uint32_t rsvd1;
2729 #ifdef __BIG_ENDIAN_BITFIELD
2730 uint16_t rsvd2;
2731 uint16_t sli4_vpi;
2732 #else /* __LITTLE_ENDIAN */
2733 uint16_t sli4_vpi;
2734 uint16_t rsvd2;
2735 #endif
2736 uint32_t rsvd3;
2737 uint32_t rsvd4;
2738 uint32_t rsvd5;
2739 #ifdef __BIG_ENDIAN_BITFIELD
2740 uint16_t rsvd6;
2741 uint16_t vpi;
2742 #else /* __LITTLE_ENDIAN */
2743 uint16_t vpi;
2744 uint16_t rsvd6;
2745 #endif
2746 } UNREG_VPI_VAR;
2747
2748 /* Structure for MB Command UNREG_D_ID (0x23) */
2749
2750 typedef struct {
2751 uint32_t did;
2752 uint32_t rsvd2;
2753 uint32_t rsvd3;
2754 uint32_t rsvd4;
2755 uint32_t rsvd5;
2756 #ifdef __BIG_ENDIAN_BITFIELD
2757 uint16_t rsvd6;
2758 uint16_t vpi;
2759 #else
2760 uint16_t vpi;
2761 uint16_t rsvd6;
2762 #endif
2763 } UNREG_D_ID_VAR;
2764
2765 /* Structure for MB Command READ_TOPOLOGY (0x95) */
2766 struct lpfc_mbx_read_top {
2767 uint32_t eventTag; /* Event tag */
2768 uint32_t word2;
2769 #define lpfc_mbx_read_top_fa_SHIFT 12
2770 #define lpfc_mbx_read_top_fa_MASK 0x00000001
2771 #define lpfc_mbx_read_top_fa_WORD word2
2772 #define lpfc_mbx_read_top_mm_SHIFT 11
2773 #define lpfc_mbx_read_top_mm_MASK 0x00000001
2774 #define lpfc_mbx_read_top_mm_WORD word2
2775 #define lpfc_mbx_read_top_pb_SHIFT 9
2776 #define lpfc_mbx_read_top_pb_MASK 0X00000001
2777 #define lpfc_mbx_read_top_pb_WORD word2
2778 #define lpfc_mbx_read_top_il_SHIFT 8
2779 #define lpfc_mbx_read_top_il_MASK 0x00000001
2780 #define lpfc_mbx_read_top_il_WORD word2
2781 #define lpfc_mbx_read_top_att_type_SHIFT 0
2782 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF
2783 #define lpfc_mbx_read_top_att_type_WORD word2
2784 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
2785 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */
2786 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
2787 uint32_t word3;
2788 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24
2789 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
2790 #define lpfc_mbx_read_top_alpa_granted_WORD word3
2791 #define lpfc_mbx_read_top_lip_alps_SHIFT 16
2792 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
2793 #define lpfc_mbx_read_top_lip_alps_WORD word3
2794 #define lpfc_mbx_read_top_lip_type_SHIFT 8
2795 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
2796 #define lpfc_mbx_read_top_lip_type_WORD word3
2797 #define lpfc_mbx_read_top_topology_SHIFT 0
2798 #define lpfc_mbx_read_top_topology_MASK 0x000000FF
2799 #define lpfc_mbx_read_top_topology_WORD word3
2800 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2801 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2802 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */
2803 /* store the LILP AL_PA position map into */
2804 struct ulp_bde64 lilpBde64;
2805 #define LPFC_ALPA_MAP_SIZE 128
2806 uint32_t word7;
2807 #define lpfc_mbx_read_top_ld_lu_SHIFT 31
2808 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
2809 #define lpfc_mbx_read_top_ld_lu_WORD word7
2810 #define lpfc_mbx_read_top_ld_tf_SHIFT 30
2811 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
2812 #define lpfc_mbx_read_top_ld_tf_WORD word7
2813 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
2814 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
2815 #define lpfc_mbx_read_top_ld_link_spd_WORD word7
2816 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
2817 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
2818 #define lpfc_mbx_read_top_ld_nl_port_WORD word7
2819 #define lpfc_mbx_read_top_ld_tx_SHIFT 2
2820 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
2821 #define lpfc_mbx_read_top_ld_tx_WORD word7
2822 #define lpfc_mbx_read_top_ld_rx_SHIFT 0
2823 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
2824 #define lpfc_mbx_read_top_ld_rx_WORD word7
2825 uint32_t word8;
2826 #define lpfc_mbx_read_top_lu_SHIFT 31
2827 #define lpfc_mbx_read_top_lu_MASK 0x00000001
2828 #define lpfc_mbx_read_top_lu_WORD word8
2829 #define lpfc_mbx_read_top_tf_SHIFT 30
2830 #define lpfc_mbx_read_top_tf_MASK 0x00000001
2831 #define lpfc_mbx_read_top_tf_WORD word8
2832 #define lpfc_mbx_read_top_link_spd_SHIFT 8
2833 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
2834 #define lpfc_mbx_read_top_link_spd_WORD word8
2835 #define lpfc_mbx_read_top_nl_port_SHIFT 4
2836 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
2837 #define lpfc_mbx_read_top_nl_port_WORD word8
2838 #define lpfc_mbx_read_top_tx_SHIFT 2
2839 #define lpfc_mbx_read_top_tx_MASK 0x00000003
2840 #define lpfc_mbx_read_top_tx_WORD word8
2841 #define lpfc_mbx_read_top_rx_SHIFT 0
2842 #define lpfc_mbx_read_top_rx_MASK 0x00000003
2843 #define lpfc_mbx_read_top_rx_WORD word8
2844 #define LPFC_LINK_SPEED_UNKNOWN 0x0
2845 #define LPFC_LINK_SPEED_1GHZ 0x04
2846 #define LPFC_LINK_SPEED_2GHZ 0x08
2847 #define LPFC_LINK_SPEED_4GHZ 0x10
2848 #define LPFC_LINK_SPEED_8GHZ 0x20
2849 #define LPFC_LINK_SPEED_10GHZ 0x40
2850 #define LPFC_LINK_SPEED_16GHZ 0x80
2851 #define LPFC_LINK_SPEED_32GHZ 0x90
2852 };
2853
2854 /* Structure for MB Command CLEAR_LA (22) */
2855
2856 typedef struct {
2857 uint32_t eventTag; /* Event tag */
2858 uint32_t rsvd1;
2859 } CLEAR_LA_VAR;
2860
2861 /* Structure for MB Command DUMP */
2862
2863 typedef struct {
2864 #ifdef __BIG_ENDIAN_BITFIELD
2865 uint32_t rsvd:25;
2866 uint32_t ra:1;
2867 uint32_t co:1;
2868 uint32_t cv:1;
2869 uint32_t type:4;
2870 uint32_t entry_index:16;
2871 uint32_t region_id:16;
2872 #else /* __LITTLE_ENDIAN_BITFIELD */
2873 uint32_t type:4;
2874 uint32_t cv:1;
2875 uint32_t co:1;
2876 uint32_t ra:1;
2877 uint32_t rsvd:25;
2878 uint32_t region_id:16;
2879 uint32_t entry_index:16;
2880 #endif
2881
2882 uint32_t sli4_length;
2883 uint32_t word_cnt;
2884 uint32_t resp_offset;
2885 } DUMP_VAR;
2886
2887 #define DMP_MEM_REG 0x1
2888 #define DMP_NV_PARAMS 0x2
2889 #define DMP_LMSD 0x3 /* Link Module Serial Data */
2890 #define DMP_WELL_KNOWN 0x4
2891
2892 #define DMP_REGION_VPD 0xe
2893 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2894 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2895 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2896
2897 #define DMP_REGION_VPORT 0x16 /* VPort info region */
2898 #define DMP_VPORT_REGION_SIZE 0x200
2899 #define DMP_MBOX_OFFSET_WORD 0x5
2900
2901 #define DMP_REGION_23 0x17 /* fcoe param and port state region */
2902 #define DMP_RGN23_SIZE 0x400
2903
2904 #define WAKE_UP_PARMS_REGION_ID 4
2905 #define WAKE_UP_PARMS_WORD_SIZE 15
2906
2907 struct vport_rec {
2908 uint8_t wwpn[8];
2909 uint8_t wwnn[8];
2910 };
2911
2912 #define VPORT_INFO_SIG 0x32324752
2913 #define VPORT_INFO_REV_MASK 0xff
2914 #define VPORT_INFO_REV 0x1
2915 #define MAX_STATIC_VPORT_COUNT 16
2916 struct static_vport_info {
2917 uint32_t signature;
2918 uint32_t rev;
2919 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
2920 uint32_t resvd[66];
2921 };
2922
2923 /* Option rom version structure */
2924 struct prog_id {
2925 #ifdef __BIG_ENDIAN_BITFIELD
2926 uint8_t type;
2927 uint8_t id;
2928 uint32_t ver:4; /* Major Version */
2929 uint32_t rev:4; /* Revision */
2930 uint32_t lev:2; /* Level */
2931 uint32_t dist:2; /* Dist Type */
2932 uint32_t num:4; /* number after dist type */
2933 #else /* __LITTLE_ENDIAN_BITFIELD */
2934 uint32_t num:4; /* number after dist type */
2935 uint32_t dist:2; /* Dist Type */
2936 uint32_t lev:2; /* Level */
2937 uint32_t rev:4; /* Revision */
2938 uint32_t ver:4; /* Major Version */
2939 uint8_t id;
2940 uint8_t type;
2941 #endif
2942 };
2943
2944 /* Structure for MB Command UPDATE_CFG (0x1B) */
2945
2946 struct update_cfg_var {
2947 #ifdef __BIG_ENDIAN_BITFIELD
2948 uint32_t rsvd2:16;
2949 uint32_t type:8;
2950 uint32_t rsvd:1;
2951 uint32_t ra:1;
2952 uint32_t co:1;
2953 uint32_t cv:1;
2954 uint32_t req:4;
2955 uint32_t entry_length:16;
2956 uint32_t region_id:16;
2957 #else /* __LITTLE_ENDIAN_BITFIELD */
2958 uint32_t req:4;
2959 uint32_t cv:1;
2960 uint32_t co:1;
2961 uint32_t ra:1;
2962 uint32_t rsvd:1;
2963 uint32_t type:8;
2964 uint32_t rsvd2:16;
2965 uint32_t region_id:16;
2966 uint32_t entry_length:16;
2967 #endif
2968
2969 uint32_t resp_info;
2970 uint32_t byte_cnt;
2971 uint32_t data_offset;
2972 };
2973
2974 struct hbq_mask {
2975 #ifdef __BIG_ENDIAN_BITFIELD
2976 uint8_t tmatch;
2977 uint8_t tmask;
2978 uint8_t rctlmatch;
2979 uint8_t rctlmask;
2980 #else /* __LITTLE_ENDIAN */
2981 uint8_t rctlmask;
2982 uint8_t rctlmatch;
2983 uint8_t tmask;
2984 uint8_t tmatch;
2985 #endif
2986 };
2987
2988
2989 /* Structure for MB Command CONFIG_HBQ (7c) */
2990
2991 struct config_hbq_var {
2992 #ifdef __BIG_ENDIAN_BITFIELD
2993 uint32_t rsvd1 :7;
2994 uint32_t recvNotify :1; /* Receive Notification */
2995 uint32_t numMask :8; /* # Mask Entries */
2996 uint32_t profile :8; /* Selection Profile */
2997 uint32_t rsvd2 :8;
2998 #else /* __LITTLE_ENDIAN */
2999 uint32_t rsvd2 :8;
3000 uint32_t profile :8; /* Selection Profile */
3001 uint32_t numMask :8; /* # Mask Entries */
3002 uint32_t recvNotify :1; /* Receive Notification */
3003 uint32_t rsvd1 :7;
3004 #endif
3005
3006 #ifdef __BIG_ENDIAN_BITFIELD
3007 uint32_t hbqId :16;
3008 uint32_t rsvd3 :12;
3009 uint32_t ringMask :4;
3010 #else /* __LITTLE_ENDIAN */
3011 uint32_t ringMask :4;
3012 uint32_t rsvd3 :12;
3013 uint32_t hbqId :16;
3014 #endif
3015
3016 #ifdef __BIG_ENDIAN_BITFIELD
3017 uint32_t entry_count :16;
3018 uint32_t rsvd4 :8;
3019 uint32_t headerLen :8;
3020 #else /* __LITTLE_ENDIAN */
3021 uint32_t headerLen :8;
3022 uint32_t rsvd4 :8;
3023 uint32_t entry_count :16;
3024 #endif
3025
3026 uint32_t hbqaddrLow;
3027 uint32_t hbqaddrHigh;
3028
3029 #ifdef __BIG_ENDIAN_BITFIELD
3030 uint32_t rsvd5 :31;
3031 uint32_t logEntry :1;
3032 #else /* __LITTLE_ENDIAN */
3033 uint32_t logEntry :1;
3034 uint32_t rsvd5 :31;
3035 #endif
3036
3037 uint32_t rsvd6; /* w7 */
3038 uint32_t rsvd7; /* w8 */
3039 uint32_t rsvd8; /* w9 */
3040
3041 struct hbq_mask hbqMasks[6];
3042
3043
3044 union {
3045 uint32_t allprofiles[12];
3046
3047 struct {
3048 #ifdef __BIG_ENDIAN_BITFIELD
3049 uint32_t seqlenoff :16;
3050 uint32_t maxlen :16;
3051 #else /* __LITTLE_ENDIAN */
3052 uint32_t maxlen :16;
3053 uint32_t seqlenoff :16;
3054 #endif
3055 #ifdef __BIG_ENDIAN_BITFIELD
3056 uint32_t rsvd1 :28;
3057 uint32_t seqlenbcnt :4;
3058 #else /* __LITTLE_ENDIAN */
3059 uint32_t seqlenbcnt :4;
3060 uint32_t rsvd1 :28;
3061 #endif
3062 uint32_t rsvd[10];
3063 } profile2;
3064
3065 struct {
3066 #ifdef __BIG_ENDIAN_BITFIELD
3067 uint32_t seqlenoff :16;
3068 uint32_t maxlen :16;
3069 #else /* __LITTLE_ENDIAN */
3070 uint32_t maxlen :16;
3071 uint32_t seqlenoff :16;
3072 #endif
3073 #ifdef __BIG_ENDIAN_BITFIELD
3074 uint32_t cmdcodeoff :28;
3075 uint32_t rsvd1 :12;
3076 uint32_t seqlenbcnt :4;
3077 #else /* __LITTLE_ENDIAN */
3078 uint32_t seqlenbcnt :4;
3079 uint32_t rsvd1 :12;
3080 uint32_t cmdcodeoff :28;
3081 #endif
3082 uint32_t cmdmatch[8];
3083
3084 uint32_t rsvd[2];
3085 } profile3;
3086
3087 struct {
3088 #ifdef __BIG_ENDIAN_BITFIELD
3089 uint32_t seqlenoff :16;
3090 uint32_t maxlen :16;
3091 #else /* __LITTLE_ENDIAN */
3092 uint32_t maxlen :16;
3093 uint32_t seqlenoff :16;
3094 #endif
3095 #ifdef __BIG_ENDIAN_BITFIELD
3096 uint32_t cmdcodeoff :28;
3097 uint32_t rsvd1 :12;
3098 uint32_t seqlenbcnt :4;
3099 #else /* __LITTLE_ENDIAN */
3100 uint32_t seqlenbcnt :4;
3101 uint32_t rsvd1 :12;
3102 uint32_t cmdcodeoff :28;
3103 #endif
3104 uint32_t cmdmatch[8];
3105
3106 uint32_t rsvd[2];
3107 } profile5;
3108
3109 } profiles;
3110
3111 };
3112
3113
3114
3115 /* Structure for MB Command CONFIG_PORT (0x88) */
3116 typedef struct {
3117 #ifdef __BIG_ENDIAN_BITFIELD
3118 uint32_t cBE : 1;
3119 uint32_t cET : 1;
3120 uint32_t cHpcb : 1;
3121 uint32_t cMA : 1;
3122 uint32_t sli_mode : 4;
3123 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3124 * config block */
3125 #else /* __LITTLE_ENDIAN */
3126 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3127 * config block */
3128 uint32_t sli_mode : 4;
3129 uint32_t cMA : 1;
3130 uint32_t cHpcb : 1;
3131 uint32_t cET : 1;
3132 uint32_t cBE : 1;
3133 #endif
3134
3135 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
3136 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
3137 uint32_t hbainit[5];
3138 #ifdef __BIG_ENDIAN_BITFIELD
3139 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3140 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3141 #else /* __LITTLE_ENDIAN */
3142 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3143 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3144 #endif
3145
3146 #ifdef __BIG_ENDIAN_BITFIELD
3147 uint32_t rsvd1 : 19; /* Reserved */
3148 uint32_t cdss : 1; /* Configure Data Security SLI */
3149 uint32_t casabt : 1; /* Configure async abts status notice */
3150 uint32_t rsvd2 : 2; /* Reserved */
3151 uint32_t cbg : 1; /* Configure BlockGuard */
3152 uint32_t cmv : 1; /* Configure Max VPIs */
3153 uint32_t ccrp : 1; /* Config Command Ring Polling */
3154 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3155 uint32_t chbs : 1; /* Cofigure Host Backing store */
3156 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3157 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3158 uint32_t cmx : 1; /* Configure Max XRIs */
3159 uint32_t cmr : 1; /* Configure Max RPIs */
3160 #else /* __LITTLE_ENDIAN */
3161 uint32_t cmr : 1; /* Configure Max RPIs */
3162 uint32_t cmx : 1; /* Configure Max XRIs */
3163 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3164 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3165 uint32_t chbs : 1; /* Cofigure Host Backing store */
3166 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3167 uint32_t ccrp : 1; /* Config Command Ring Polling */
3168 uint32_t cmv : 1; /* Configure Max VPIs */
3169 uint32_t cbg : 1; /* Configure BlockGuard */
3170 uint32_t rsvd2 : 2; /* Reserved */
3171 uint32_t casabt : 1; /* Configure async abts status notice */
3172 uint32_t cdss : 1; /* Configure Data Security SLI */
3173 uint32_t rsvd1 : 19; /* Reserved */
3174 #endif
3175 #ifdef __BIG_ENDIAN_BITFIELD
3176 uint32_t rsvd3 : 19; /* Reserved */
3177 uint32_t gdss : 1; /* Configure Data Security SLI */
3178 uint32_t gasabt : 1; /* Grant async abts status notice */
3179 uint32_t rsvd4 : 2; /* Reserved */
3180 uint32_t gbg : 1; /* Grant BlockGuard */
3181 uint32_t gmv : 1; /* Grant Max VPIs */
3182 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3183 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3184 uint32_t ghbs : 1; /* Grant Host Backing Store */
3185 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3186 uint32_t gerbm : 1; /* Grant ERBM Request */
3187 uint32_t gmx : 1; /* Grant Max XRIs */
3188 uint32_t gmr : 1; /* Grant Max RPIs */
3189 #else /* __LITTLE_ENDIAN */
3190 uint32_t gmr : 1; /* Grant Max RPIs */
3191 uint32_t gmx : 1; /* Grant Max XRIs */
3192 uint32_t gerbm : 1; /* Grant ERBM Request */
3193 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3194 uint32_t ghbs : 1; /* Grant Host Backing Store */
3195 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3196 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3197 uint32_t gmv : 1; /* Grant Max VPIs */
3198 uint32_t gbg : 1; /* Grant BlockGuard */
3199 uint32_t rsvd4 : 2; /* Reserved */
3200 uint32_t gasabt : 1; /* Grant async abts status notice */
3201 uint32_t gdss : 1; /* Configure Data Security SLI */
3202 uint32_t rsvd3 : 19; /* Reserved */
3203 #endif
3204
3205 #ifdef __BIG_ENDIAN_BITFIELD
3206 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3207 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3208 #else /* __LITTLE_ENDIAN */
3209 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3210 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3211 #endif
3212
3213 #ifdef __BIG_ENDIAN_BITFIELD
3214 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3215 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3216 #else /* __LITTLE_ENDIAN */
3217 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3218 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3219 #endif
3220
3221 uint32_t rsvd6; /* Reserved */
3222
3223 #ifdef __BIG_ENDIAN_BITFIELD
3224 uint32_t fips_rev : 3; /* FIPS Spec Revision */
3225 uint32_t fips_level : 4; /* FIPS Level */
3226 uint32_t sec_err : 9; /* security crypto error */
3227 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3228 #else /* __LITTLE_ENDIAN */
3229 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3230 uint32_t sec_err : 9; /* security crypto error */
3231 uint32_t fips_level : 4; /* FIPS Level */
3232 uint32_t fips_rev : 3; /* FIPS Spec Revision */
3233 #endif
3234
3235 } CONFIG_PORT_VAR;
3236
3237 /* Structure for MB Command CONFIG_MSI (0x30) */
3238 struct config_msi_var {
3239 #ifdef __BIG_ENDIAN_BITFIELD
3240 uint32_t dfltMsgNum:8; /* Default message number */
3241 uint32_t rsvd1:11; /* Reserved */
3242 uint32_t NID:5; /* Number of secondary attention IDs */
3243 uint32_t rsvd2:5; /* Reserved */
3244 uint32_t dfltPresent:1; /* Default message number present */
3245 uint32_t addFlag:1; /* Add association flag */
3246 uint32_t reportFlag:1; /* Report association flag */
3247 #else /* __LITTLE_ENDIAN_BITFIELD */
3248 uint32_t reportFlag:1; /* Report association flag */
3249 uint32_t addFlag:1; /* Add association flag */
3250 uint32_t dfltPresent:1; /* Default message number present */
3251 uint32_t rsvd2:5; /* Reserved */
3252 uint32_t NID:5; /* Number of secondary attention IDs */
3253 uint32_t rsvd1:11; /* Reserved */
3254 uint32_t dfltMsgNum:8; /* Default message number */
3255 #endif
3256 uint32_t attentionConditions[2];
3257 uint8_t attentionId[16];
3258 uint8_t messageNumberByHA[64];
3259 uint8_t messageNumberByID[16];
3260 uint32_t autoClearHA[2];
3261 #ifdef __BIG_ENDIAN_BITFIELD
3262 uint32_t rsvd3:16;
3263 uint32_t autoClearID:16;
3264 #else /* __LITTLE_ENDIAN_BITFIELD */
3265 uint32_t autoClearID:16;
3266 uint32_t rsvd3:16;
3267 #endif
3268 uint32_t rsvd4;
3269 };
3270
3271 /* SLI-2 Port Control Block */
3272
3273 /* SLIM POINTER */
3274 #define SLIMOFF 0x30 /* WORD */
3275
3276 typedef struct _SLI2_RDSC {
3277 uint32_t cmdEntries;
3278 uint32_t cmdAddrLow;
3279 uint32_t cmdAddrHigh;
3280
3281 uint32_t rspEntries;
3282 uint32_t rspAddrLow;
3283 uint32_t rspAddrHigh;
3284 } SLI2_RDSC;
3285
3286 typedef struct _PCB {
3287 #ifdef __BIG_ENDIAN_BITFIELD
3288 uint32_t type:8;
3289 #define TYPE_NATIVE_SLI2 0x01
3290 uint32_t feature:8;
3291 #define FEATURE_INITIAL_SLI2 0x01
3292 uint32_t rsvd:12;
3293 uint32_t maxRing:4;
3294 #else /* __LITTLE_ENDIAN_BITFIELD */
3295 uint32_t maxRing:4;
3296 uint32_t rsvd:12;
3297 uint32_t feature:8;
3298 #define FEATURE_INITIAL_SLI2 0x01
3299 uint32_t type:8;
3300 #define TYPE_NATIVE_SLI2 0x01
3301 #endif
3302
3303 uint32_t mailBoxSize;
3304 uint32_t mbAddrLow;
3305 uint32_t mbAddrHigh;
3306
3307 uint32_t hgpAddrLow;
3308 uint32_t hgpAddrHigh;
3309
3310 uint32_t pgpAddrLow;
3311 uint32_t pgpAddrHigh;
3312 SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3313 } PCB_t;
3314
3315 /* NEW_FEATURE */
3316 typedef struct {
3317 #ifdef __BIG_ENDIAN_BITFIELD
3318 uint32_t rsvd0:27;
3319 uint32_t discardFarp:1;
3320 uint32_t IPEnable:1;
3321 uint32_t nodeName:1;
3322 uint32_t portName:1;
3323 uint32_t filterEnable:1;
3324 #else /* __LITTLE_ENDIAN_BITFIELD */
3325 uint32_t filterEnable:1;
3326 uint32_t portName:1;
3327 uint32_t nodeName:1;
3328 uint32_t IPEnable:1;
3329 uint32_t discardFarp:1;
3330 uint32_t rsvd:27;
3331 #endif
3332
3333 uint8_t portname[8]; /* Used to be struct lpfc_name */
3334 uint8_t nodename[8];
3335 uint32_t rsvd1;
3336 uint32_t rsvd2;
3337 uint32_t rsvd3;
3338 uint32_t IPAddress;
3339 } CONFIG_FARP_VAR;
3340
3341 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3342
3343 typedef struct {
3344 #ifdef __BIG_ENDIAN_BITFIELD
3345 uint32_t rsvd:30;
3346 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3347 #else /* __LITTLE_ENDIAN */
3348 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3349 uint32_t rsvd:30;
3350 #endif
3351 } ASYNCEVT_ENABLE_VAR;
3352
3353 /* Union of all Mailbox Command types */
3354 #define MAILBOX_CMD_WSIZE 32
3355 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3356 /* ext_wsize times 4 bytes should not be greater than max xmit size */
3357 #define MAILBOX_EXT_WSIZE 512
3358 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3359 #define MAILBOX_HBA_EXT_OFFSET 0x100
3360 /* max mbox xmit size is a page size for sysfs IO operations */
3361 #define MAILBOX_SYSFS_MAX 4096
3362
3363 typedef union {
3364 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3365 * feature/max ring number
3366 */
3367 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
3368 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
3369 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
3370 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
3371 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
3372 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
3373 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
3374 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
3375 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
3376 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
3377 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
3378 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
3379 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
3380 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
3381 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
3382 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
3383 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
3384 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
3385 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
3386 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
3387 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
3388 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
3389 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3390 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3391 * NEW_FEATURE
3392 */
3393 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
3394 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3395 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
3396 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3397 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3398 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
3399 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3400 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3401 * (READ_EVENT_LOG)
3402 */
3403 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
3404 } MAILVARIANTS;
3405
3406 /*
3407 * SLI-2 specific structures
3408 */
3409
3410 struct lpfc_hgp {
3411 __le32 cmdPutInx;
3412 __le32 rspGetInx;
3413 };
3414
3415 struct lpfc_pgp {
3416 __le32 cmdGetInx;
3417 __le32 rspPutInx;
3418 };
3419
3420 struct sli2_desc {
3421 uint32_t unused1[16];
3422 struct lpfc_hgp host[MAX_SLI3_RINGS];
3423 struct lpfc_pgp port[MAX_SLI3_RINGS];
3424 };
3425
3426 struct sli3_desc {
3427 struct lpfc_hgp host[MAX_SLI3_RINGS];
3428 uint32_t reserved[8];
3429 uint32_t hbq_put[16];
3430 };
3431
3432 struct sli3_pgp {
3433 struct lpfc_pgp port[MAX_SLI3_RINGS];
3434 uint32_t hbq_get[16];
3435 };
3436
3437 union sli_var {
3438 struct sli2_desc s2;
3439 struct sli3_desc s3;
3440 struct sli3_pgp s3_pgp;
3441 };
3442
3443 typedef struct {
3444 #ifdef __BIG_ENDIAN_BITFIELD
3445 uint16_t mbxStatus;
3446 uint8_t mbxCommand;
3447 uint8_t mbxReserved:6;
3448 uint8_t mbxHc:1;
3449 uint8_t mbxOwner:1; /* Low order bit first word */
3450 #else /* __LITTLE_ENDIAN_BITFIELD */
3451 uint8_t mbxOwner:1; /* Low order bit first word */
3452 uint8_t mbxHc:1;
3453 uint8_t mbxReserved:6;
3454 uint8_t mbxCommand;
3455 uint16_t mbxStatus;
3456 #endif
3457
3458 MAILVARIANTS un;
3459 union sli_var us;
3460 } MAILBOX_t;
3461
3462 /*
3463 * Begin Structure Definitions for IOCB Commands
3464 */
3465
3466 typedef struct {
3467 #ifdef __BIG_ENDIAN_BITFIELD
3468 uint8_t statAction;
3469 uint8_t statRsn;
3470 uint8_t statBaExp;
3471 uint8_t statLocalError;
3472 #else /* __LITTLE_ENDIAN_BITFIELD */
3473 uint8_t statLocalError;
3474 uint8_t statBaExp;
3475 uint8_t statRsn;
3476 uint8_t statAction;
3477 #endif
3478 /* statRsn P/F_RJT reason codes */
3479 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3480 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3481 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3482 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3483 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3484 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3485 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3486 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3487 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3488 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3489 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3490 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3491 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3492 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3493 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3494 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
3495 #define RJT_XCHG_ERR 0x11 /* Exchange error */
3496 #define RJT_PROT_ERR 0x12 /* Protocol error */
3497 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3498 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3499 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3500 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3501 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3502 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3503 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3504 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3505
3506 #define IOERR_SUCCESS 0x00 /* statLocalError */
3507 #define IOERR_MISSING_CONTINUE 0x01
3508 #define IOERR_SEQUENCE_TIMEOUT 0x02
3509 #define IOERR_INTERNAL_ERROR 0x03
3510 #define IOERR_INVALID_RPI 0x04
3511 #define IOERR_NO_XRI 0x05
3512 #define IOERR_ILLEGAL_COMMAND 0x06
3513 #define IOERR_XCHG_DROPPED 0x07
3514 #define IOERR_ILLEGAL_FIELD 0x08
3515 #define IOERR_BAD_CONTINUE 0x09
3516 #define IOERR_TOO_MANY_BUFFERS 0x0A
3517 #define IOERR_RCV_BUFFER_WAITING 0x0B
3518 #define IOERR_NO_CONNECTION 0x0C
3519 #define IOERR_TX_DMA_FAILED 0x0D
3520 #define IOERR_RX_DMA_FAILED 0x0E
3521 #define IOERR_ILLEGAL_FRAME 0x0F
3522 #define IOERR_EXTRA_DATA 0x10
3523 #define IOERR_NO_RESOURCES 0x11
3524 #define IOERR_RESERVED 0x12
3525 #define IOERR_ILLEGAL_LENGTH 0x13
3526 #define IOERR_UNSUPPORTED_FEATURE 0x14
3527 #define IOERR_ABORT_IN_PROGRESS 0x15
3528 #define IOERR_ABORT_REQUESTED 0x16
3529 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3530 #define IOERR_LOOP_OPEN_FAILURE 0x18
3531 #define IOERR_RING_RESET 0x19
3532 #define IOERR_LINK_DOWN 0x1A
3533 #define IOERR_CORRUPTED_DATA 0x1B
3534 #define IOERR_CORRUPTED_RPI 0x1C
3535 #define IOERR_OUT_OF_ORDER_DATA 0x1D
3536 #define IOERR_OUT_OF_ORDER_ACK 0x1E
3537 #define IOERR_DUP_FRAME 0x1F
3538 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3539 #define IOERR_BAD_HOST_ADDRESS 0x21
3540 #define IOERR_RCV_HDRBUF_WAITING 0x22
3541 #define IOERR_MISSING_HDR_BUFFER 0x23
3542 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3543 #define IOERR_ABORTMULT_REQUESTED 0x25
3544 #define IOERR_BUFFER_SHORTAGE 0x28
3545 #define IOERR_DEFAULT 0x29
3546 #define IOERR_CNT 0x2A
3547 #define IOERR_SLER_FAILURE 0x46
3548 #define IOERR_SLER_CMD_RCV_FAILURE 0x47
3549 #define IOERR_SLER_REC_RJT_ERR 0x48
3550 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3551 #define IOERR_SLER_SRR_RJT_ERR 0x4A
3552 #define IOERR_SLER_RRQ_RJT_ERR 0x4C
3553 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3554 #define IOERR_SLER_ABTS_ERR 0x4E
3555 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3556 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3557 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3558 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
3559 #define IOERR_DRVR_MASK 0x100
3560 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3561 #define IOERR_SLI_BRESET 0x102
3562 #define IOERR_SLI_ABORTED 0x103
3563 #define IOERR_PARAM_MASK 0x1ff
3564 } PARM_ERR;
3565
3566 typedef union {
3567 struct {
3568 #ifdef __BIG_ENDIAN_BITFIELD
3569 uint8_t Rctl; /* R_CTL field */
3570 uint8_t Type; /* TYPE field */
3571 uint8_t Dfctl; /* DF_CTL field */
3572 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3573 #else /* __LITTLE_ENDIAN_BITFIELD */
3574 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3575 uint8_t Dfctl; /* DF_CTL field */
3576 uint8_t Type; /* TYPE field */
3577 uint8_t Rctl; /* R_CTL field */
3578 #endif
3579
3580 #define BC 0x02 /* Broadcast Received - Fctl */
3581 #define SI 0x04 /* Sequence Initiative */
3582 #define LA 0x08 /* Ignore Link Attention state */
3583 #define LS 0x80 /* Last Sequence */
3584 } hcsw;
3585 uint32_t reserved;
3586 } WORD5;
3587
3588 /* IOCB Command template for a generic response */
3589 typedef struct {
3590 uint32_t reserved[4];
3591 PARM_ERR perr;
3592 } GENERIC_RSP;
3593
3594 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3595 typedef struct {
3596 struct ulp_bde xrsqbde[2];
3597 uint32_t xrsqRo; /* Starting Relative Offset */
3598 WORD5 w5; /* Header control/status word */
3599 } XR_SEQ_FIELDS;
3600
3601 /* IOCB Command template for ELS_REQUEST */
3602 typedef struct {
3603 struct ulp_bde elsReq;
3604 struct ulp_bde elsRsp;
3605
3606 #ifdef __BIG_ENDIAN_BITFIELD
3607 uint32_t word4Rsvd:7;
3608 uint32_t fl:1;
3609 uint32_t myID:24;
3610 uint32_t word5Rsvd:8;
3611 uint32_t remoteID:24;
3612 #else /* __LITTLE_ENDIAN_BITFIELD */
3613 uint32_t myID:24;
3614 uint32_t fl:1;
3615 uint32_t word4Rsvd:7;
3616 uint32_t remoteID:24;
3617 uint32_t word5Rsvd:8;
3618 #endif
3619 } ELS_REQUEST;
3620
3621 /* IOCB Command template for RCV_ELS_REQ */
3622 typedef struct {
3623 struct ulp_bde elsReq[2];
3624 uint32_t parmRo;
3625
3626 #ifdef __BIG_ENDIAN_BITFIELD
3627 uint32_t word5Rsvd:8;
3628 uint32_t remoteID:24;
3629 #else /* __LITTLE_ENDIAN_BITFIELD */
3630 uint32_t remoteID:24;
3631 uint32_t word5Rsvd:8;
3632 #endif
3633 } RCV_ELS_REQ;
3634
3635 /* IOCB Command template for ABORT / CLOSE_XRI */
3636 typedef struct {
3637 uint32_t rsvd[3];
3638 uint32_t abortType;
3639 #define ABORT_TYPE_ABTX 0x00000000
3640 #define ABORT_TYPE_ABTS 0x00000001
3641 uint32_t parm;
3642 #ifdef __BIG_ENDIAN_BITFIELD
3643 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3644 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3645 #else /* __LITTLE_ENDIAN_BITFIELD */
3646 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3647 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3648 #endif
3649 } AC_XRI;
3650
3651 /* IOCB Command template for ABORT_MXRI64 */
3652 typedef struct {
3653 uint32_t rsvd[3];
3654 uint32_t abortType;
3655 uint32_t parm;
3656 uint32_t iotag32;
3657 } A_MXRI64;
3658
3659 /* IOCB Command template for GET_RPI */
3660 typedef struct {
3661 uint32_t rsvd[4];
3662 uint32_t parmRo;
3663 #ifdef __BIG_ENDIAN_BITFIELD
3664 uint32_t word5Rsvd:8;
3665 uint32_t remoteID:24;
3666 #else /* __LITTLE_ENDIAN_BITFIELD */
3667 uint32_t remoteID:24;
3668 uint32_t word5Rsvd:8;
3669 #endif
3670 } GET_RPI;
3671
3672 /* IOCB Command template for all FCP Initiator commands */
3673 typedef struct {
3674 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3675 struct ulp_bde fcpi_rsp; /* Rcv buffer */
3676 uint32_t fcpi_parm;
3677 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3678 } FCPI_FIELDS;
3679
3680 /* IOCB Command template for all FCP Target commands */
3681 typedef struct {
3682 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3683 uint32_t fcpt_Offset;
3684 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3685 } FCPT_FIELDS;
3686
3687 /* SLI-2 IOCB structure definitions */
3688
3689 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3690 typedef struct {
3691 ULP_BDL bdl;
3692 uint32_t xrsqRo; /* Starting Relative Offset */
3693 WORD5 w5; /* Header control/status word */
3694 } XMT_SEQ_FIELDS64;
3695
3696 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3697 #define xmit_els_remoteID xrsqRo
3698
3699 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3700 typedef struct {
3701 struct ulp_bde64 rcvBde;
3702 uint32_t rsvd1;
3703 uint32_t xrsqRo; /* Starting Relative Offset */
3704 WORD5 w5; /* Header control/status word */
3705 } RCV_SEQ_FIELDS64;
3706
3707 /* IOCB Command template for ELS_REQUEST64 */
3708 typedef struct {
3709 ULP_BDL bdl;
3710 #ifdef __BIG_ENDIAN_BITFIELD
3711 uint32_t word4Rsvd:7;
3712 uint32_t fl:1;
3713 uint32_t myID:24;
3714 uint32_t word5Rsvd:8;
3715 uint32_t remoteID:24;
3716 #else /* __LITTLE_ENDIAN_BITFIELD */
3717 uint32_t myID:24;
3718 uint32_t fl:1;
3719 uint32_t word4Rsvd:7;
3720 uint32_t remoteID:24;
3721 uint32_t word5Rsvd:8;
3722 #endif
3723 } ELS_REQUEST64;
3724
3725 /* IOCB Command template for GEN_REQUEST64 */
3726 typedef struct {
3727 ULP_BDL bdl;
3728 uint32_t xrsqRo; /* Starting Relative Offset */
3729 WORD5 w5; /* Header control/status word */
3730 } GEN_REQUEST64;
3731
3732 /* IOCB Command template for RCV_ELS_REQ64 */
3733 typedef struct {
3734 struct ulp_bde64 elsReq;
3735 uint32_t rcvd1;
3736 uint32_t parmRo;
3737
3738 #ifdef __BIG_ENDIAN_BITFIELD
3739 uint32_t word5Rsvd:8;
3740 uint32_t remoteID:24;
3741 #else /* __LITTLE_ENDIAN_BITFIELD */
3742 uint32_t remoteID:24;
3743 uint32_t word5Rsvd:8;
3744 #endif
3745 } RCV_ELS_REQ64;
3746
3747 /* IOCB Command template for RCV_SEQ64 */
3748 struct rcv_seq64 {
3749 struct ulp_bde64 elsReq;
3750 uint32_t hbq_1;
3751 uint32_t parmRo;
3752 #ifdef __BIG_ENDIAN_BITFIELD
3753 uint32_t rctl:8;
3754 uint32_t type:8;
3755 uint32_t dfctl:8;
3756 uint32_t ls:1;
3757 uint32_t fs:1;
3758 uint32_t rsvd2:3;
3759 uint32_t si:1;
3760 uint32_t bc:1;
3761 uint32_t rsvd3:1;
3762 #else /* __LITTLE_ENDIAN_BITFIELD */
3763 uint32_t rsvd3:1;
3764 uint32_t bc:1;
3765 uint32_t si:1;
3766 uint32_t rsvd2:3;
3767 uint32_t fs:1;
3768 uint32_t ls:1;
3769 uint32_t dfctl:8;
3770 uint32_t type:8;
3771 uint32_t rctl:8;
3772 #endif
3773 };
3774
3775 /* IOCB Command template for all 64 bit FCP Initiator commands */
3776 typedef struct {
3777 ULP_BDL bdl;
3778 uint32_t fcpi_parm;
3779 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3780 } FCPI_FIELDS64;
3781
3782 /* IOCB Command template for all 64 bit FCP Target commands */
3783 typedef struct {
3784 ULP_BDL bdl;
3785 uint32_t fcpt_Offset;
3786 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3787 } FCPT_FIELDS64;
3788
3789 /* IOCB Command template for Async Status iocb commands */
3790 typedef struct {
3791 uint32_t rsvd[4];
3792 uint32_t param;
3793 #ifdef __BIG_ENDIAN_BITFIELD
3794 uint16_t evt_code; /* High order bits word 5 */
3795 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3796 #else /* __LITTLE_ENDIAN_BITFIELD */
3797 uint16_t sub_ctxt_tag; /* High order bits word 5 */
3798 uint16_t evt_code; /* Low order bits word 5 */
3799 #endif
3800 } ASYNCSTAT_FIELDS;
3801 #define ASYNC_TEMP_WARN 0x100
3802 #define ASYNC_TEMP_SAFE 0x101
3803 #define ASYNC_STATUS_CN 0x102
3804
3805 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3806 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3807
3808 struct rcv_sli3 {
3809 #ifdef __BIG_ENDIAN_BITFIELD
3810 uint16_t ox_id;
3811 uint16_t seq_cnt;
3812
3813 uint16_t vpi;
3814 uint16_t word9Rsvd;
3815 #else /* __LITTLE_ENDIAN */
3816 uint16_t seq_cnt;
3817 uint16_t ox_id;
3818
3819 uint16_t word9Rsvd;
3820 uint16_t vpi;
3821 #endif
3822 uint32_t word10Rsvd;
3823 uint32_t acc_len; /* accumulated length */
3824 struct ulp_bde64 bde2;
3825 };
3826
3827 /* Structure used for a single HBQ entry */
3828 struct lpfc_hbq_entry {
3829 struct ulp_bde64 bde;
3830 uint32_t buffer_tag;
3831 };
3832
3833 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3834 typedef struct {
3835 struct lpfc_hbq_entry buff;
3836 uint32_t rsvd;
3837 uint32_t rsvd1;
3838 } QUE_XRI64_CX_FIELDS;
3839
3840 struct que_xri64cx_ext_fields {
3841 uint32_t iotag64_low;
3842 uint32_t iotag64_high;
3843 uint32_t ebde_count;
3844 uint32_t rsvd;
3845 struct lpfc_hbq_entry buff[5];
3846 };
3847
3848 struct sli3_bg_fields {
3849 uint32_t filler[6]; /* word 8-13 in IOCB */
3850 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
3851 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3852 #define BGS_BIDIR_BG_PROF_MASK 0xff000000
3853 #define BGS_BIDIR_BG_PROF_SHIFT 24
3854 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3855 #define BGS_BIDIR_ERR_COND_SHIFT 16
3856 #define BGS_BG_PROFILE_MASK 0x0000ff00
3857 #define BGS_BG_PROFILE_SHIFT 8
3858 #define BGS_INVALID_PROF_MASK 0x00000020
3859 #define BGS_INVALID_PROF_SHIFT 5
3860 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3861 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4
3862 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
3863 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3864 #define BGS_REFTAG_ERR_MASK 0x00000004
3865 #define BGS_REFTAG_ERR_SHIFT 2
3866 #define BGS_APPTAG_ERR_MASK 0x00000002
3867 #define BGS_APPTAG_ERR_SHIFT 1
3868 #define BGS_GUARD_ERR_MASK 0x00000001
3869 #define BGS_GUARD_ERR_SHIFT 0
3870 uint32_t bgstat; /* word 15 - BlockGuard Status */
3871 };
3872
3873 static inline uint32_t
3874 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3875 {
3876 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
3877 BGS_BIDIR_BG_PROF_SHIFT;
3878 }
3879
3880 static inline uint32_t
3881 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3882 {
3883 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
3884 BGS_BIDIR_ERR_COND_SHIFT;
3885 }
3886
3887 static inline uint32_t
3888 lpfc_bgs_get_bg_prof(uint32_t bgstat)
3889 {
3890 return (bgstat & BGS_BG_PROFILE_MASK) >>
3891 BGS_BG_PROFILE_SHIFT;
3892 }
3893
3894 static inline uint32_t
3895 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
3896 {
3897 return (bgstat & BGS_INVALID_PROF_MASK) >>
3898 BGS_INVALID_PROF_SHIFT;
3899 }
3900
3901 static inline uint32_t
3902 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
3903 {
3904 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
3905 BGS_UNINIT_DIF_BLOCK_SHIFT;
3906 }
3907
3908 static inline uint32_t
3909 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
3910 {
3911 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
3912 BGS_HI_WATER_MARK_PRESENT_SHIFT;
3913 }
3914
3915 static inline uint32_t
3916 lpfc_bgs_get_reftag_err(uint32_t bgstat)
3917 {
3918 return (bgstat & BGS_REFTAG_ERR_MASK) >>
3919 BGS_REFTAG_ERR_SHIFT;
3920 }
3921
3922 static inline uint32_t
3923 lpfc_bgs_get_apptag_err(uint32_t bgstat)
3924 {
3925 return (bgstat & BGS_APPTAG_ERR_MASK) >>
3926 BGS_APPTAG_ERR_SHIFT;
3927 }
3928
3929 static inline uint32_t
3930 lpfc_bgs_get_guard_err(uint32_t bgstat)
3931 {
3932 return (bgstat & BGS_GUARD_ERR_MASK) >>
3933 BGS_GUARD_ERR_SHIFT;
3934 }
3935
3936 #define LPFC_EXT_DATA_BDE_COUNT 3
3937 struct fcp_irw_ext {
3938 uint32_t io_tag64_low;
3939 uint32_t io_tag64_high;
3940 #ifdef __BIG_ENDIAN_BITFIELD
3941 uint8_t reserved1;
3942 uint8_t reserved2;
3943 uint8_t reserved3;
3944 uint8_t ebde_count;
3945 #else /* __LITTLE_ENDIAN */
3946 uint8_t ebde_count;
3947 uint8_t reserved3;
3948 uint8_t reserved2;
3949 uint8_t reserved1;
3950 #endif
3951 uint32_t reserved4;
3952 struct ulp_bde64 rbde; /* response bde */
3953 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
3954 uint8_t icd[32]; /* immediate command data (32 bytes) */
3955 };
3956
3957 typedef struct _IOCB { /* IOCB structure */
3958 union {
3959 GENERIC_RSP grsp; /* Generic response */
3960 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
3961 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
3962 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
3963 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
3964 A_MXRI64 amxri; /* abort multiple xri command overlay */
3965 GET_RPI getrpi; /* GET_RPI template */
3966 FCPI_FIELDS fcpi; /* FCP Initiator template */
3967 FCPT_FIELDS fcpt; /* FCP target template */
3968
3969 /* SLI-2 structures */
3970
3971 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
3972 * bde_64s */
3973 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
3974 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
3975 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
3976 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
3977 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
3978 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
3979 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
3980 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
3981 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
3982 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
3983 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
3984 } un;
3985 union {
3986 struct {
3987 #ifdef __BIG_ENDIAN_BITFIELD
3988 uint16_t ulpContext; /* High order bits word 6 */
3989 uint16_t ulpIoTag; /* Low order bits word 6 */
3990 #else /* __LITTLE_ENDIAN_BITFIELD */
3991 uint16_t ulpIoTag; /* Low order bits word 6 */
3992 uint16_t ulpContext; /* High order bits word 6 */
3993 #endif
3994 } t1;
3995 struct {
3996 #ifdef __BIG_ENDIAN_BITFIELD
3997 uint16_t ulpContext; /* High order bits word 6 */
3998 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3999 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4000 #else /* __LITTLE_ENDIAN_BITFIELD */
4001 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4002 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4003 uint16_t ulpContext; /* High order bits word 6 */
4004 #endif
4005 } t2;
4006 } un1;
4007 #define ulpContext un1.t1.ulpContext
4008 #define ulpIoTag un1.t1.ulpIoTag
4009 #define ulpIoTag0 un1.t2.ulpIoTag0
4010
4011 #ifdef __BIG_ENDIAN_BITFIELD
4012 uint32_t ulpTimeout:8;
4013 uint32_t ulpXS:1;
4014 uint32_t ulpFCP2Rcvy:1;
4015 uint32_t ulpPU:2;
4016 uint32_t ulpIr:1;
4017 uint32_t ulpClass:3;
4018 uint32_t ulpCommand:8;
4019 uint32_t ulpStatus:4;
4020 uint32_t ulpBdeCount:2;
4021 uint32_t ulpLe:1;
4022 uint32_t ulpOwner:1; /* Low order bit word 7 */
4023 #else /* __LITTLE_ENDIAN_BITFIELD */
4024 uint32_t ulpOwner:1; /* Low order bit word 7 */
4025 uint32_t ulpLe:1;
4026 uint32_t ulpBdeCount:2;
4027 uint32_t ulpStatus:4;
4028 uint32_t ulpCommand:8;
4029 uint32_t ulpClass:3;
4030 uint32_t ulpIr:1;
4031 uint32_t ulpPU:2;
4032 uint32_t ulpFCP2Rcvy:1;
4033 uint32_t ulpXS:1;
4034 uint32_t ulpTimeout:8;
4035 #endif
4036
4037 union {
4038 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
4039
4040 /* words 8-31 used for que_xri_cx iocb */
4041 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
4042 struct fcp_irw_ext fcp_ext;
4043 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
4044
4045 /* words 8-15 for BlockGuard */
4046 struct sli3_bg_fields sli3_bg;
4047 } unsli3;
4048
4049 #define ulpCt_h ulpXS
4050 #define ulpCt_l ulpFCP2Rcvy
4051
4052 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
4053 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
4054 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
4055 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
4056 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
4057 #define PARM_NPIV_DID 3
4058 #define CLASS1 0 /* Class 1 */
4059 #define CLASS2 1 /* Class 2 */
4060 #define CLASS3 2 /* Class 3 */
4061 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
4062
4063 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
4064 #define IOSTAT_FCP_RSP_ERROR 0x1
4065 #define IOSTAT_REMOTE_STOP 0x2
4066 #define IOSTAT_LOCAL_REJECT 0x3
4067 #define IOSTAT_NPORT_RJT 0x4
4068 #define IOSTAT_FABRIC_RJT 0x5
4069 #define IOSTAT_NPORT_BSY 0x6
4070 #define IOSTAT_FABRIC_BSY 0x7
4071 #define IOSTAT_INTERMED_RSP 0x8
4072 #define IOSTAT_LS_RJT 0x9
4073 #define IOSTAT_BA_RJT 0xA
4074 #define IOSTAT_RSVD1 0xB
4075 #define IOSTAT_RSVD2 0xC
4076 #define IOSTAT_RSVD3 0xD
4077 #define IOSTAT_RSVD4 0xE
4078 #define IOSTAT_NEED_BUFFER 0xF
4079 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
4080 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
4081 #define IOSTAT_CNT 0x11
4082
4083 } IOCB_t;
4084
4085
4086 #define SLI1_SLIM_SIZE (4 * 1024)
4087
4088 /* Up to 498 IOCBs will fit into 16k
4089 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
4090 */
4091 #define SLI2_SLIM_SIZE (64 * 1024)
4092
4093 /* Maximum IOCBs that will fit in SLI2 slim */
4094 #define MAX_SLI2_IOCB 498
4095 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
4096 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
4097 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
4098
4099 /* HBQ entries are 4 words each = 4k */
4100 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
4101 lpfc_sli_hbq_count())
4102
4103 struct lpfc_sli2_slim {
4104 MAILBOX_t mbx;
4105 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
4106 PCB_t pcb;
4107 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
4108 };
4109
4110 /*
4111 * This function checks PCI device to allow special handling for LC HBAs.
4112 *
4113 * Parameters:
4114 * device : struct pci_dev 's device field
4115 *
4116 * return 1 => TRUE
4117 * 0 => FALSE
4118 */
4119 static inline int
4120 lpfc_is_LC_HBA(unsigned short device)
4121 {
4122 if ((device == PCI_DEVICE_ID_TFLY) ||
4123 (device == PCI_DEVICE_ID_PFLY) ||
4124 (device == PCI_DEVICE_ID_LP101) ||
4125 (device == PCI_DEVICE_ID_BMID) ||
4126 (device == PCI_DEVICE_ID_BSMB) ||
4127 (device == PCI_DEVICE_ID_ZMID) ||
4128 (device == PCI_DEVICE_ID_ZSMB) ||
4129 (device == PCI_DEVICE_ID_SAT_MID) ||
4130 (device == PCI_DEVICE_ID_SAT_SMB) ||
4131 (device == PCI_DEVICE_ID_RFLY))
4132 return 1;
4133 else
4134 return 0;
4135 }
4136
4137 /*
4138 * Determine if an IOCB failed because of a link event or firmware reset.
4139 */
4140
4141 static inline int
4142 lpfc_error_lost_link(IOCB_t *iocbp)
4143 {
4144 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
4145 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
4146 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
4147 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
4148 }
4149
4150 #define MENLO_TRANSPORT_TYPE 0xfe
4151 #define MENLO_CONTEXT 0
4152 #define MENLO_PU 3
4153 #define MENLO_TIMEOUT 30
4154 #define SETVAR_MLOMNT 0x103107
4155 #define SETVAR_MLORST 0x103007
4156
4157 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
Linux with added FPC-III support