drivers/usb/host/xhci-pci.c

   1 /*
   2  * xHCI host controller driver PCI Bus Glue.
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/pci.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/acpi.h>
  27
  28 #include "xhci.h"
  29 #include "xhci-trace.h"
  30
  31 #define SSIC_PORT_NUM           2
  32 #define SSIC_PORT_CFG2          0x880c
  33 #define SSIC_PORT_CFG2_OFFSET   0x30
  34 #define PROG_DONE               (1 << 30)
  35 #define SSIC_PORT_UNUSED        (1 << 31)
  36
  37 /* Device for a quirk */
  38 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  41
  42 #define PCI_VENDOR_ID_ETRON             0x1b6f
  43 #define PCI_DEVICE_ID_EJ168             0x7023
  44
  45 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  47 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  48 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  49 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  50 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  51 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  52
  53 static const char hcd_name[] = "xhci_hcd";
  54
  55 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  56
  57 static int xhci_pci_setup(struct usb_hcd *hcd);
  58
  59 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  60         .reset = xhci_pci_setup,
  61 };
  62
  63 /* called after powerup, by probe or system-pm "wakeup" */
  64 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  65 {
  66         /*
  67          * TODO: Implement finding debug ports later.
  68          * TODO: see if there are any quirks that need to be added to handle
  69          * new extended capabilities.
  70          */
  71
  72         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  73         if (!pci_set_mwi(pdev))
  74                 xhci_dbg(xhci, "MWI active\n");
  75
  76         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  77         return 0;
  78 }
  79
  80 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  81 {
  82         struct pci_dev          *pdev = to_pci_dev(dev);
  83
  84         /* Look for vendor-specific quirks */
  85         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  86                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  87                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  88                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  89                                 pdev->revision == 0x0) {
  90                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
  91                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  92                                 "QUIRK: Fresco Logic xHC needs configure"
  93                                 " endpoint cmd after reset endpoint");
  94                 }
  95                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  96                                 pdev->revision == 0x4) {
  97                         xhci->quirks |= XHCI_SLOW_SUSPEND;
  98                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  99                                 "QUIRK: Fresco Logic xHC revision %u"
 100                                 "must be suspended extra slowly",
 101                                 pdev->revision);
 102                 }
 103                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 104                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 105                 /* Fresco Logic confirms: all revisions of this chip do not
 106                  * support MSI, even though some of them claim to in their PCI
 107                  * capabilities.
 108                  */
 109                 xhci->quirks |= XHCI_BROKEN_MSI;
 110                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 111                                 "QUIRK: Fresco Logic revision %u "
 112                                 "has broken MSI implementation",
 113                                 pdev->revision);
 114                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 115         }
 116
 117         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 118                 xhci->quirks |= XHCI_NEC_HOST;
 119
 120         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 121                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 122
 123         /* AMD PLL quirk */
 124         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 125                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 126
 127         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 128                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 129
 130         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 131                 xhci->quirks |= XHCI_LPM_SUPPORT;
 132                 xhci->quirks |= XHCI_INTEL_HOST;
 133                 xhci->quirks |= XHCI_AVOID_BEI;
 134         }
 135         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 136                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 137                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 138                 xhci->limit_active_eps = 64;
 139                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 140                 /*
 141                  * PPT desktop boards DH77EB and DH77DF will power back on after
 142                  * a few seconds of being shutdown.  The fix for this is to
 143                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 144                  * DMI information to find those particular boards (since each
 145                  * vendor will change the board name), so we have to key off all
 146                  * PPT chipsets.
 147                  */
 148                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 149         }
 150         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 151                 pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
 152                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 153                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 154         }
 155         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 156                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 157                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 158                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 159                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 160                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI)) {
 161                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 162         }
 163         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 164                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
 165                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 166         }
 167         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 168                         pdev->device == PCI_DEVICE_ID_EJ168) {
 169                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 170                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 171                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 172         }
 173         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 174                         pdev->device == 0x0015)
 175                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 176         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 177                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 178
 179         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 180         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 181                         pdev->device == 0x3432)
 182                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 183
 184         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 185                         pdev->device == 0x1042)
 186                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 187
 188         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 189                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 190                                 "QUIRK: Resetting on resume");
 191 }
 192
 193 #ifdef CONFIG_ACPI
 194 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 195 {
 196         static const u8 intel_dsm_uuid[] = {
 197                 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
 198                 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
 199         };
 200         union acpi_object *obj;
 201
 202         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1,
 203                                 NULL);
 204         ACPI_FREE(obj);
 205 }
 206 #else
 207 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 208 #endif /* CONFIG_ACPI */
 209
 210 /* called during probe() after chip reset completes */
 211 static int xhci_pci_setup(struct usb_hcd *hcd)
 212 {
 213         struct xhci_hcd         *xhci;
 214         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 215         int                     retval;
 216
 217         xhci = hcd_to_xhci(hcd);
 218         if (!xhci->sbrn)
 219                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 220
 221         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 222         if (retval)
 223                 return retval;
 224
 225         if (!usb_hcd_is_primary_hcd(hcd))
 226                 return 0;
 227
 228         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 229
 230         /* Find any debug ports */
 231         retval = xhci_pci_reinit(xhci, pdev);
 232         if (!retval)
 233                 return retval;
 234
 235         return retval;
 236 }
 237
 238 /*
 239  * We need to register our own PCI probe function (instead of the USB core's
 240  * function) in order to create a second roothub under xHCI.
 241  */
 242 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 243 {
 244         int retval;
 245         struct xhci_hcd *xhci;
 246         struct hc_driver *driver;
 247         struct usb_hcd *hcd;
 248
 249         driver = (struct hc_driver *)id->driver_data;
 250
 251         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 252         pm_runtime_get_noresume(&dev->dev);
 253
 254         /* Register the USB 2.0 roothub.
 255          * FIXME: USB core must know to register the USB 2.0 roothub first.
 256          * This is sort of silly, because we could just set the HCD driver flags
 257          * to say USB 2.0, but I'm not sure what the implications would be in
 258          * the other parts of the HCD code.
 259          */
 260         retval = usb_hcd_pci_probe(dev, id);
 261
 262         if (retval)
 263                 goto put_runtime_pm;
 264
 265         /* USB 2.0 roothub is stored in the PCI device now. */
 266         hcd = dev_get_drvdata(&dev->dev);
 267         xhci = hcd_to_xhci(hcd);
 268         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 269                                 pci_name(dev), hcd);
 270         if (!xhci->shared_hcd) {
 271                 retval = -ENOMEM;
 272                 goto dealloc_usb2_hcd;
 273         }
 274
 275         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 276                         IRQF_SHARED);
 277         if (retval)
 278                 goto put_usb3_hcd;
 279         /* Roothub already marked as USB 3.0 speed */
 280
 281         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 282                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 283                 xhci->shared_hcd->can_do_streams = 1;
 284
 285         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 286                 xhci_pme_acpi_rtd3_enable(dev);
 287
 288         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 289         pm_runtime_put_noidle(&dev->dev);
 290
 291         return 0;
 292
 293 put_usb3_hcd:
 294         usb_put_hcd(xhci->shared_hcd);
 295 dealloc_usb2_hcd:
 296         usb_hcd_pci_remove(dev);
 297 put_runtime_pm:
 298         pm_runtime_put_noidle(&dev->dev);
 299         return retval;
 300 }
 301
 302 static void xhci_pci_remove(struct pci_dev *dev)
 303 {
 304         struct xhci_hcd *xhci;
 305
 306         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 307         xhci->xhc_state |= XHCI_STATE_REMOVING;
 308         if (xhci->shared_hcd) {
 309                 usb_remove_hcd(xhci->shared_hcd);
 310                 usb_put_hcd(xhci->shared_hcd);
 311         }
 312         usb_hcd_pci_remove(dev);
 313
 314         /* Workaround for spurious wakeups at shutdown with HSW */
 315         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 316                 pci_set_power_state(dev, PCI_D3hot);
 317 }
 318
 319 #ifdef CONFIG_PM
 320 /*
 321  * In some Intel xHCI controllers, in order to get D3 working,
 322  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 323  * SSIC PORT need to be marked as "unused" before putting xHCI
 324  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 325  * Without this change, xHCI might not enter D3 state.
 326  */
 327 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 328 {
 329         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 330         u32 val;
 331         void __iomem *reg;
 332         int i;
 333
 334         for (i = 0; i < SSIC_PORT_NUM; i++) {
 335                 reg = (void __iomem *) xhci->cap_regs +
 336                                 SSIC_PORT_CFG2 +
 337                                 i * SSIC_PORT_CFG2_OFFSET;
 338
 339                 /* Notify SSIC that SSIC profile programming is not done. */
 340                 val = readl(reg) & ~PROG_DONE;
 341                 writel(val, reg);
 342
 343                 /* Mark SSIC port as unused(suspend) or used(resume) */
 344                 val = readl(reg);
 345                 if (suspend)
 346                         val |= SSIC_PORT_UNUSED;
 347                 else
 348                         val &= ~SSIC_PORT_UNUSED;
 349                 writel(val, reg);
 350
 351                 /* Notify SSIC that SSIC profile programming is done */
 352                 val = readl(reg) | PROG_DONE;
 353                 writel(val, reg);
 354                 readl(reg);
 355         }
 356 }
 357
 358 /*
 359  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 360  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 361  */
 362 static void xhci_pme_quirk(struct usb_hcd *hcd)
 363 {
 364         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 365         void __iomem *reg;
 366         u32 val;
 367
 368         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 369         val = readl(reg);
 370         writel(val | BIT(28), reg);
 371         readl(reg);
 372 }
 373
 374 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 375 {
 376         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 377         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 378         int                     ret;
 379
 380         /*
 381          * Systems with the TI redriver that loses port status change events
 382          * need to have the registers polled during D3, so avoid D3cold.
 383          */
 384         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 385                 pdev->no_d3cold = true;
 386
 387         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 388                 xhci_pme_quirk(hcd);
 389
 390         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 391                 xhci_ssic_port_unused_quirk(hcd, true);
 392
 393         ret = xhci_suspend(xhci, do_wakeup);
 394         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 395                 xhci_ssic_port_unused_quirk(hcd, false);
 396
 397         return ret;
 398 }
 399
 400 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 401 {
 402         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 403         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 404         int                     retval = 0;
 405
 406         /* The BIOS on systems with the Intel Panther Point chipset may or may
 407          * not support xHCI natively.  That means that during system resume, it
 408          * may switch the ports back to EHCI so that users can use their
 409          * keyboard to select a kernel from GRUB after resume from hibernate.
 410          *
 411          * The BIOS is supposed to remember whether the OS had xHCI ports
 412          * enabled before resume, and switch the ports back to xHCI when the
 413          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 414          * writers.
 415          *
 416          * Unconditionally switch the ports back to xHCI after a system resume.
 417          * It should not matter whether the EHCI or xHCI controller is
 418          * resumed first. It's enough to do the switchover in xHCI because
 419          * USB core won't notice anything as the hub driver doesn't start
 420          * running again until after all the devices (including both EHCI and
 421          * xHCI host controllers) have been resumed.
 422          */
 423
 424         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 425                 usb_enable_intel_xhci_ports(pdev);
 426
 427         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 428                 xhci_ssic_port_unused_quirk(hcd, false);
 429
 430         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 431                 xhci_pme_quirk(hcd);
 432
 433         retval = xhci_resume(xhci, hibernated);
 434         return retval;
 435 }
 436 #endif /* CONFIG_PM */
 437
 438 /*-------------------------------------------------------------------------*/
 439
 440 /* PCI driver selection metadata; PCI hotplugging uses this */
 441 static const struct pci_device_id pci_ids[] = { {
 442         /* handle any USB 3.0 xHCI controller */
 443         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 444         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 445         },
 446         { /* end: all zeroes */ }
 447 };
 448 MODULE_DEVICE_TABLE(pci, pci_ids);
 449
 450 /* pci driver glue; this is a "new style" PCI driver module */
 451 static struct pci_driver xhci_pci_driver = {
 452         .name =         (char *) hcd_name,
 453         .id_table =     pci_ids,
 454
 455         .probe =        xhci_pci_probe,
 456         .remove =       xhci_pci_remove,
 457         /* suspend and resume implemented later */
 458
 459         .shutdown =     usb_hcd_pci_shutdown,
 460 #ifdef CONFIG_PM
 461         .driver = {
 462                 .pm = &usb_hcd_pci_pm_ops
 463         },
 464 #endif
 465 };
 466
 467 static int __init xhci_pci_init(void)
 468 {
 469         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 470 #ifdef CONFIG_PM
 471         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 472         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 473 #endif
 474         return pci_register_driver(&xhci_pci_driver);
 475 }
 476 module_init(xhci_pci_init);
 477
 478 static void __exit xhci_pci_exit(void)
 479 {
 480         pci_unregister_driver(&xhci_pci_driver);
 481 }
 482 module_exit(xhci_pci_exit);
 483
 484 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 485 MODULE_LICENSE("GPL");