2 * Sony CXD2820R demodulator driver
4 * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "cxd2820r_priv.h"
24 int cxd2820r_set_frontend_t2(struct dvb_frontend
*fe
)
26 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
27 struct dtv_frontend_properties
*c
= &fe
->dtv_property_cache
;
32 u8 bw_params1
[][5] = {
33 { 0x1c, 0xb3, 0x33, 0x33, 0x33 }, /* 5 MHz */
34 { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
35 { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
36 { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
38 struct reg_val_mask tab
[] = {
39 { 0x00080, 0x02, 0xff },
40 { 0x00081, 0x20, 0xff },
41 { 0x00085, 0x07, 0xff },
42 { 0x00088, 0x01, 0xff },
43 { 0x02069, 0x01, 0xff },
45 { 0x0207f, 0x2a, 0xff },
46 { 0x02082, 0x0a, 0xff },
47 { 0x02083, 0x0a, 0xff },
48 { 0x020cb, priv
->cfg
.if_agc_polarity
<< 6, 0x40 },
49 { 0x02070, priv
->cfg
.ts_mode
, 0xff },
50 { 0x02071, !priv
->cfg
.ts_clock_inv
<< 6, 0x40 },
51 { 0x020b5, priv
->cfg
.spec_inv
<< 4, 0x10 },
52 { 0x02567, 0x07, 0x0f },
53 { 0x02569, 0x03, 0x03 },
54 { 0x02595, 0x1a, 0xff },
55 { 0x02596, 0x50, 0xff },
56 { 0x02a8c, 0x00, 0xff },
57 { 0x02a8d, 0x34, 0xff },
58 { 0x02a45, 0x06, 0x07 },
59 { 0x03f10, 0x0d, 0xff },
60 { 0x03f11, 0x02, 0xff },
61 { 0x03f12, 0x01, 0xff },
62 { 0x03f23, 0x2c, 0xff },
63 { 0x03f51, 0x13, 0xff },
64 { 0x03f52, 0x01, 0xff },
65 { 0x03f53, 0x00, 0xff },
66 { 0x027e6, 0x14, 0xff },
67 { 0x02786, 0x02, 0x07 },
68 { 0x02787, 0x40, 0xe0 },
69 { 0x027ef, 0x10, 0x18 },
72 dev_dbg(&priv
->i2c
->dev
, "%s: frequency=%d bandwidth_hz=%d\n", __func__
,
73 c
->frequency
, c
->bandwidth_hz
);
75 switch (c
->bandwidth_hz
) {
97 if (fe
->ops
.tuner_ops
.set_params
)
98 fe
->ops
.tuner_ops
.set_params(fe
);
100 if (priv
->delivery_system
!= SYS_DVBT2
) {
101 for (i
= 0; i
< ARRAY_SIZE(tab
); i
++) {
102 ret
= cxd2820r_wr_reg_mask(priv
, tab
[i
].reg
,
103 tab
[i
].val
, tab
[i
].mask
);
109 priv
->delivery_system
= SYS_DVBT2
;
111 /* program IF frequency */
112 if (fe
->ops
.tuner_ops
.get_if_frequency
) {
113 ret
= fe
->ops
.tuner_ops
.get_if_frequency(fe
, &if_freq
);
119 dev_dbg(&priv
->i2c
->dev
, "%s: if_freq=%d\n", __func__
, if_freq
);
121 num
= if_freq
/ 1000; /* Hz => kHz */
123 if_ctl
= DIV_ROUND_CLOSEST_ULL(num
, 41000);
124 buf
[0] = ((if_ctl
>> 16) & 0xff);
125 buf
[1] = ((if_ctl
>> 8) & 0xff);
126 buf
[2] = ((if_ctl
>> 0) & 0xff);
129 if (c
->stream_id
> 255) {
130 dev_dbg(&priv
->i2c
->dev
, "%s: Disable PLP filtering\n", __func__
);
131 ret
= cxd2820r_wr_reg(priv
, 0x023ad , 0);
135 dev_dbg(&priv
->i2c
->dev
, "%s: Enable PLP filtering = %d\n", __func__
,
137 ret
= cxd2820r_wr_reg(priv
, 0x023af , c
->stream_id
& 0xFF);
140 ret
= cxd2820r_wr_reg(priv
, 0x023ad , 1);
145 ret
= cxd2820r_wr_regs(priv
, 0x020b6, buf
, 3);
149 ret
= cxd2820r_wr_regs(priv
, 0x0209f, bw_params1
[bw_i
], 5);
153 ret
= cxd2820r_wr_reg_mask(priv
, 0x020d7, bw_param
<< 6, 0xc0);
157 ret
= cxd2820r_wr_reg(priv
, 0x000ff, 0x08);
161 ret
= cxd2820r_wr_reg(priv
, 0x000fe, 0x01);
167 dev_dbg(&priv
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
172 int cxd2820r_get_frontend_t2(struct dvb_frontend
*fe
)
174 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
175 struct dtv_frontend_properties
*c
= &fe
->dtv_property_cache
;
179 ret
= cxd2820r_rd_regs(priv
, 0x0205c, buf
, 2);
183 switch ((buf
[0] >> 0) & 0x07) {
185 c
->transmission_mode
= TRANSMISSION_MODE_2K
;
188 c
->transmission_mode
= TRANSMISSION_MODE_8K
;
191 c
->transmission_mode
= TRANSMISSION_MODE_4K
;
194 c
->transmission_mode
= TRANSMISSION_MODE_1K
;
197 c
->transmission_mode
= TRANSMISSION_MODE_16K
;
200 c
->transmission_mode
= TRANSMISSION_MODE_32K
;
204 switch ((buf
[1] >> 4) & 0x07) {
206 c
->guard_interval
= GUARD_INTERVAL_1_32
;
209 c
->guard_interval
= GUARD_INTERVAL_1_16
;
212 c
->guard_interval
= GUARD_INTERVAL_1_8
;
215 c
->guard_interval
= GUARD_INTERVAL_1_4
;
218 c
->guard_interval
= GUARD_INTERVAL_1_128
;
221 c
->guard_interval
= GUARD_INTERVAL_19_128
;
224 c
->guard_interval
= GUARD_INTERVAL_19_256
;
228 ret
= cxd2820r_rd_regs(priv
, 0x0225b, buf
, 2);
232 switch ((buf
[0] >> 0) & 0x07) {
234 c
->fec_inner
= FEC_1_2
;
237 c
->fec_inner
= FEC_3_5
;
240 c
->fec_inner
= FEC_2_3
;
243 c
->fec_inner
= FEC_3_4
;
246 c
->fec_inner
= FEC_4_5
;
249 c
->fec_inner
= FEC_5_6
;
253 switch ((buf
[1] >> 0) & 0x07) {
255 c
->modulation
= QPSK
;
258 c
->modulation
= QAM_16
;
261 c
->modulation
= QAM_64
;
264 c
->modulation
= QAM_256
;
268 ret
= cxd2820r_rd_reg(priv
, 0x020b5, &buf
[0]);
272 switch ((buf
[0] >> 4) & 0x01) {
274 c
->inversion
= INVERSION_OFF
;
277 c
->inversion
= INVERSION_ON
;
283 dev_dbg(&priv
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
287 int cxd2820r_read_status_t2(struct dvb_frontend
*fe
, enum fe_status
*status
)
289 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
294 ret
= cxd2820r_rd_reg(priv
, 0x02010 , &buf
[0]);
298 if ((buf
[0] & 0x07) == 6) {
299 if (((buf
[0] >> 5) & 0x01) == 1) {
300 *status
|= FE_HAS_SIGNAL
| FE_HAS_CARRIER
|
301 FE_HAS_VITERBI
| FE_HAS_SYNC
| FE_HAS_LOCK
;
303 *status
|= FE_HAS_SIGNAL
| FE_HAS_CARRIER
|
304 FE_HAS_VITERBI
| FE_HAS_SYNC
;
308 dev_dbg(&priv
->i2c
->dev
, "%s: lock=%02x\n", __func__
, buf
[0]);
312 dev_dbg(&priv
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
316 int cxd2820r_read_ber_t2(struct dvb_frontend
*fe
, u32
*ber
)
318 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
321 unsigned int errbits
;
323 /* FIXME: correct calculation */
325 ret
= cxd2820r_rd_regs(priv
, 0x02039, buf
, sizeof(buf
));
329 if ((buf
[0] >> 4) & 0x01) {
330 errbits
= (buf
[0] & 0x0f) << 24 | buf
[1] << 16 |
331 buf
[2] << 8 | buf
[3];
334 *ber
= errbits
* 64 / 16588800;
339 dev_dbg(&priv
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
343 int cxd2820r_read_signal_strength_t2(struct dvb_frontend
*fe
,
346 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
351 ret
= cxd2820r_rd_regs(priv
, 0x02026, buf
, sizeof(buf
));
355 tmp
= (buf
[0] & 0x0f) << 8 | buf
[1];
358 /* scale value to 0x0000-0xffff from 0x0000-0x0fff */
359 *strength
= tmp
* 0xffff / 0x0fff;
363 dev_dbg(&priv
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
367 int cxd2820r_read_snr_t2(struct dvb_frontend
*fe
, u16
*snr
)
369 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
373 /* report SNR in dB * 10 */
375 ret
= cxd2820r_rd_regs(priv
, 0x02028, buf
, sizeof(buf
));
379 tmp
= (buf
[0] & 0x0f) << 8 | buf
[1];
380 #define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */
382 *snr
= (intlog10(tmp
) - CXD2820R_LOG10_8_24
) / ((1 << 24)
387 dev_dbg(&priv
->i2c
->dev
, "%s: dBx10=%d val=%04x\n", __func__
, *snr
,
392 dev_dbg(&priv
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
396 int cxd2820r_read_ucblocks_t2(struct dvb_frontend
*fe
, u32
*ucblocks
)
399 /* no way to read ? */
403 int cxd2820r_sleep_t2(struct dvb_frontend
*fe
)
405 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
407 struct reg_val_mask tab
[] = {
408 { 0x000ff, 0x1f, 0xff },
409 { 0x00085, 0x00, 0xff },
410 { 0x00088, 0x01, 0xff },
411 { 0x02069, 0x00, 0xff },
412 { 0x00081, 0x00, 0xff },
413 { 0x00080, 0x00, 0xff },
416 dev_dbg(&priv
->i2c
->dev
, "%s\n", __func__
);
418 for (i
= 0; i
< ARRAY_SIZE(tab
); i
++) {
419 ret
= cxd2820r_wr_reg_mask(priv
, tab
[i
].reg
, tab
[i
].val
,
425 priv
->delivery_system
= SYS_UNDEFINED
;
429 dev_dbg(&priv
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
433 int cxd2820r_get_tune_settings_t2(struct dvb_frontend
*fe
,
434 struct dvb_frontend_tune_settings
*s
)
436 s
->min_delay_ms
= 1500;
437 s
->step_size
= fe
->ops
.info
.frequency_stepsize
* 2;
438 s
->max_drift
= (fe
->ops
.info
.frequency_stepsize
* 2) + 1;