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ARC: thp: unbork !CONFIG_TRANSPARENT_HUGEPAGE build
[linux/fpc-iii.git] / drivers / media / dvb-frontends / rtl2832.c
blob10f2119935da8b69402dc21cae1c040e6f8aadf4
1 /*
2 * Realtek RTL2832 DVB-T demodulator driver
3 *
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
5 * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22 #include "rtl2832_priv.h"
23
24 #define REG_MASK(b) (BIT(b + 1) - 1)
25
26 static const struct rtl2832_reg_entry registers[] = {
27 [DVBT_SOFT_RST] = {0x101, 2, 2},
28 [DVBT_IIC_REPEAT] = {0x101, 3, 3},
29 [DVBT_TR_WAIT_MIN_8K] = {0x188, 11, 2},
30 [DVBT_RSD_BER_FAIL_VAL] = {0x18f, 15, 0},
31 [DVBT_EN_BK_TRK] = {0x1a6, 7, 7},
32 [DVBT_AD_EN_REG] = {0x008, 7, 7},
33 [DVBT_AD_EN_REG1] = {0x008, 6, 6},
34 [DVBT_EN_BBIN] = {0x1b1, 0, 0},
35 [DVBT_MGD_THD0] = {0x195, 7, 0},
36 [DVBT_MGD_THD1] = {0x196, 7, 0},
37 [DVBT_MGD_THD2] = {0x197, 7, 0},
38 [DVBT_MGD_THD3] = {0x198, 7, 0},
39 [DVBT_MGD_THD4] = {0x199, 7, 0},
40 [DVBT_MGD_THD5] = {0x19a, 7, 0},
41 [DVBT_MGD_THD6] = {0x19b, 7, 0},
42 [DVBT_MGD_THD7] = {0x19c, 7, 0},
43 [DVBT_EN_CACQ_NOTCH] = {0x161, 4, 4},
44 [DVBT_AD_AV_REF] = {0x009, 6, 0},
45 [DVBT_REG_PI] = {0x00a, 2, 0},
46 [DVBT_PIP_ON] = {0x021, 3, 3},
47 [DVBT_SCALE1_B92] = {0x292, 7, 0},
48 [DVBT_SCALE1_B93] = {0x293, 7, 0},
49 [DVBT_SCALE1_BA7] = {0x2a7, 7, 0},
50 [DVBT_SCALE1_BA9] = {0x2a9, 7, 0},
51 [DVBT_SCALE1_BAA] = {0x2aa, 7, 0},
52 [DVBT_SCALE1_BAB] = {0x2ab, 7, 0},
53 [DVBT_SCALE1_BAC] = {0x2ac, 7, 0},
54 [DVBT_SCALE1_BB0] = {0x2b0, 7, 0},
55 [DVBT_SCALE1_BB1] = {0x2b1, 7, 0},
56 [DVBT_KB_P1] = {0x164, 3, 1},
57 [DVBT_KB_P2] = {0x164, 6, 4},
58 [DVBT_KB_P3] = {0x165, 2, 0},
59 [DVBT_OPT_ADC_IQ] = {0x006, 5, 4},
60 [DVBT_AD_AVI] = {0x009, 1, 0},
61 [DVBT_AD_AVQ] = {0x009, 3, 2},
62 [DVBT_K1_CR_STEP12] = {0x2ad, 9, 4},
63 [DVBT_TRK_KS_P2] = {0x16f, 2, 0},
64 [DVBT_TRK_KS_I2] = {0x170, 5, 3},
65 [DVBT_TR_THD_SET2] = {0x172, 3, 0},
66 [DVBT_TRK_KC_P2] = {0x173, 5, 3},
67 [DVBT_TRK_KC_I2] = {0x175, 2, 0},
68 [DVBT_CR_THD_SET2] = {0x176, 7, 6},
69 [DVBT_PSET_IFFREQ] = {0x119, 21, 0},
70 [DVBT_SPEC_INV] = {0x115, 0, 0},
71 [DVBT_RSAMP_RATIO] = {0x19f, 27, 2},
72 [DVBT_CFREQ_OFF_RATIO] = {0x19d, 23, 4},
73 [DVBT_FSM_STAGE] = {0x351, 6, 3},
74 [DVBT_RX_CONSTEL] = {0x33c, 3, 2},
75 [DVBT_RX_HIER] = {0x33c, 6, 4},
76 [DVBT_RX_C_RATE_LP] = {0x33d, 2, 0},
77 [DVBT_RX_C_RATE_HP] = {0x33d, 5, 3},
78 [DVBT_GI_IDX] = {0x351, 1, 0},
79 [DVBT_FFT_MODE_IDX] = {0x351, 2, 2},
80 [DVBT_RSD_BER_EST] = {0x34e, 15, 0},
81 [DVBT_CE_EST_EVM] = {0x40c, 15, 0},
82 [DVBT_RF_AGC_VAL] = {0x35b, 13, 0},
83 [DVBT_IF_AGC_VAL] = {0x359, 13, 0},
84 [DVBT_DAGC_VAL] = {0x305, 7, 0},
85 [DVBT_SFREQ_OFF] = {0x318, 13, 0},
86 [DVBT_CFREQ_OFF] = {0x35f, 17, 0},
87 [DVBT_POLAR_RF_AGC] = {0x00e, 1, 1},
88 [DVBT_POLAR_IF_AGC] = {0x00e, 0, 0},
89 [DVBT_AAGC_HOLD] = {0x104, 5, 5},
90 [DVBT_EN_RF_AGC] = {0x104, 6, 6},
91 [DVBT_EN_IF_AGC] = {0x104, 7, 7},
92 [DVBT_IF_AGC_MIN] = {0x108, 7, 0},
93 [DVBT_IF_AGC_MAX] = {0x109, 7, 0},
94 [DVBT_RF_AGC_MIN] = {0x10a, 7, 0},
95 [DVBT_RF_AGC_MAX] = {0x10b, 7, 0},
96 [DVBT_IF_AGC_MAN] = {0x10c, 6, 6},
97 [DVBT_IF_AGC_MAN_VAL] = {0x10c, 13, 0},
98 [DVBT_RF_AGC_MAN] = {0x10e, 6, 6},
99 [DVBT_RF_AGC_MAN_VAL] = {0x10e, 13, 0},
100 [DVBT_DAGC_TRG_VAL] = {0x112, 7, 0},
101 [DVBT_AGC_TARG_VAL_0] = {0x102, 0, 0},
102 [DVBT_AGC_TARG_VAL_8_1] = {0x103, 7, 0},
103 [DVBT_AAGC_LOOP_GAIN] = {0x1c7, 5, 1},
104 [DVBT_LOOP_GAIN2_3_0] = {0x104, 4, 1},
105 [DVBT_LOOP_GAIN2_4] = {0x105, 7, 7},
106 [DVBT_LOOP_GAIN3] = {0x1c8, 4, 0},
107 [DVBT_VTOP1] = {0x106, 5, 0},
108 [DVBT_VTOP2] = {0x1c9, 5, 0},
109 [DVBT_VTOP3] = {0x1ca, 5, 0},
110 [DVBT_KRF1] = {0x1cb, 7, 0},
111 [DVBT_KRF2] = {0x107, 7, 0},
112 [DVBT_KRF3] = {0x1cd, 7, 0},
113 [DVBT_KRF4] = {0x1ce, 7, 0},
114 [DVBT_EN_GI_PGA] = {0x1e5, 0, 0},
115 [DVBT_THD_LOCK_UP] = {0x1d9, 8, 0},
116 [DVBT_THD_LOCK_DW] = {0x1db, 8, 0},
117 [DVBT_THD_UP1] = {0x1dd, 7, 0},
118 [DVBT_THD_DW1] = {0x1de, 7, 0},
119 [DVBT_INTER_CNT_LEN] = {0x1d8, 3, 0},
120 [DVBT_GI_PGA_STATE] = {0x1e6, 3, 3},
121 [DVBT_EN_AGC_PGA] = {0x1d7, 0, 0},
122 [DVBT_CKOUTPAR] = {0x17b, 5, 5},
123 [DVBT_CKOUT_PWR] = {0x17b, 6, 6},
124 [DVBT_SYNC_DUR] = {0x17b, 7, 7},
125 [DVBT_ERR_DUR] = {0x17c, 0, 0},
126 [DVBT_SYNC_LVL] = {0x17c, 1, 1},
127 [DVBT_ERR_LVL] = {0x17c, 2, 2},
128 [DVBT_VAL_LVL] = {0x17c, 3, 3},
129 [DVBT_SERIAL] = {0x17c, 4, 4},
130 [DVBT_SER_LSB] = {0x17c, 5, 5},
131 [DVBT_CDIV_PH0] = {0x17d, 3, 0},
132 [DVBT_CDIV_PH1] = {0x17d, 7, 4},
133 [DVBT_MPEG_IO_OPT_2_2] = {0x006, 7, 7},
134 [DVBT_MPEG_IO_OPT_1_0] = {0x007, 7, 6},
135 [DVBT_CKOUTPAR_PIP] = {0x0b7, 4, 4},
136 [DVBT_CKOUT_PWR_PIP] = {0x0b7, 3, 3},
137 [DVBT_SYNC_LVL_PIP] = {0x0b7, 2, 2},
138 [DVBT_ERR_LVL_PIP] = {0x0b7, 1, 1},
139 [DVBT_VAL_LVL_PIP] = {0x0b7, 0, 0},
140 [DVBT_CKOUTPAR_PID] = {0x0b9, 4, 4},
141 [DVBT_CKOUT_PWR_PID] = {0x0b9, 3, 3},
142 [DVBT_SYNC_LVL_PID] = {0x0b9, 2, 2},
143 [DVBT_ERR_LVL_PID] = {0x0b9, 1, 1},
144 [DVBT_VAL_LVL_PID] = {0x0b9, 0, 0},
145 [DVBT_SM_PASS] = {0x193, 11, 0},
146 [DVBT_AD7_SETTING] = {0x011, 15, 0},
147 [DVBT_RSSI_R] = {0x301, 6, 0},
148 [DVBT_ACI_DET_IND] = {0x312, 0, 0},
149 [DVBT_REG_MON] = {0x00d, 1, 0},
150 [DVBT_REG_MONSEL] = {0x00d, 2, 2},
151 [DVBT_REG_GPE] = {0x00d, 7, 7},
152 [DVBT_REG_GPO] = {0x010, 0, 0},
153 [DVBT_REG_4MSEL] = {0x013, 0, 0},
154 };
155
156 /* Our regmap is bypassing I2C adapter lock, thus we do it! */
157 static int rtl2832_bulk_write(struct i2c_client *client, unsigned int reg,
158 const void *val, size_t val_count)
159 {
160 struct rtl2832_dev *dev = i2c_get_clientdata(client);
161 int ret;
162
163 i2c_lock_adapter(client->adapter);
164 ret = regmap_bulk_write(dev->regmap, reg, val, val_count);
165 i2c_unlock_adapter(client->adapter);
166 return ret;
167 }
168
169 static int rtl2832_update_bits(struct i2c_client *client, unsigned int reg,
170 unsigned int mask, unsigned int val)
171 {
172 struct rtl2832_dev *dev = i2c_get_clientdata(client);
173 int ret;
174
175 i2c_lock_adapter(client->adapter);
176 ret = regmap_update_bits(dev->regmap, reg, mask, val);
177 i2c_unlock_adapter(client->adapter);
178 return ret;
179 }
180
181 static int rtl2832_bulk_read(struct i2c_client *client, unsigned int reg,
182 void *val, size_t val_count)
183 {
184 struct rtl2832_dev *dev = i2c_get_clientdata(client);
185 int ret;
186
187 i2c_lock_adapter(client->adapter);
188 ret = regmap_bulk_read(dev->regmap, reg, val, val_count);
189 i2c_unlock_adapter(client->adapter);
190 return ret;
191 }
192
193 static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val)
194 {
195 struct i2c_client *client = dev->client;
196 int ret, i;
197 u16 reg_start_addr;
198 u8 msb, lsb, reading[4], len;
199 u32 reading_tmp, mask;
200
201 reg_start_addr = registers[reg].start_address;
202 msb = registers[reg].msb;
203 lsb = registers[reg].lsb;
204 len = (msb >> 3) + 1;
205 mask = REG_MASK(msb - lsb);
206
207 ret = rtl2832_bulk_read(client, reg_start_addr, reading, len);
208 if (ret)
209 goto err;
210
211 reading_tmp = 0;
212 for (i = 0; i < len; i++)
213 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
214
215 *val = (reading_tmp >> lsb) & mask;
216
217 return 0;
218 err:
219 dev_dbg(&client->dev, "failed=%d\n", ret);
220 return ret;
221 }
222
223 static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
224 {
225 struct i2c_client *client = dev->client;
226 int ret, i;
227 u16 reg_start_addr;
228 u8 msb, lsb, reading[4], writing[4], len;
229 u32 reading_tmp, writing_tmp, mask;
230
231 reg_start_addr = registers[reg].start_address;
232 msb = registers[reg].msb;
233 lsb = registers[reg].lsb;
234 len = (msb >> 3) + 1;
235 mask = REG_MASK(msb - lsb);
236
237 ret = rtl2832_bulk_read(client, reg_start_addr, reading, len);
238 if (ret)
239 goto err;
240
241 reading_tmp = 0;
242 for (i = 0; i < len; i++)
243 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
244
245 writing_tmp = reading_tmp & ~(mask << lsb);
246 writing_tmp |= ((val & mask) << lsb);
247
248 for (i = 0; i < len; i++)
249 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
250
251 ret = rtl2832_bulk_write(client, reg_start_addr, writing, len);
252 if (ret)
253 goto err;
254
255 return 0;
256 err:
257 dev_dbg(&client->dev, "failed=%d\n", ret);
258 return ret;
259 }
260
261 static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
262 {
263 struct rtl2832_dev *dev = fe->demodulator_priv;
264 struct i2c_client *client = dev->client;
265 int ret;
266 u64 pset_iffreq;
267 u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
268
269 /*
270 * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
271 * / CrystalFreqHz)
272 */
273 pset_iffreq = if_freq % dev->pdata->clk;
274 pset_iffreq *= 0x400000;
275 pset_iffreq = div_u64(pset_iffreq, dev->pdata->clk);
276 pset_iffreq = -pset_iffreq;
277 pset_iffreq = pset_iffreq & 0x3fffff;
278 dev_dbg(&client->dev, "if_frequency=%d pset_iffreq=%08x\n",
279 if_freq, (unsigned)pset_iffreq);
280
281 ret = rtl2832_wr_demod_reg(dev, DVBT_EN_BBIN, en_bbin);
282 if (ret)
283 goto err;
284
285 ret = rtl2832_wr_demod_reg(dev, DVBT_PSET_IFFREQ, pset_iffreq);
286 if (ret)
287 goto err;
288
289 return 0;
290 err:
291 dev_dbg(&client->dev, "failed=%d\n", ret);
292 return ret;
293 }
294
295 static int rtl2832_init(struct dvb_frontend *fe)
296 {
297 struct rtl2832_dev *dev = fe->demodulator_priv;
298 struct i2c_client *client = dev->client;
299 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
300 const struct rtl2832_reg_value *init;
301 int i, ret, len;
302 /* initialization values for the demodulator registers */
303 struct rtl2832_reg_value rtl2832_initial_regs[] = {
304 {DVBT_AD_EN_REG, 0x1},
305 {DVBT_AD_EN_REG1, 0x1},
306 {DVBT_RSD_BER_FAIL_VAL, 0x2800},
307 {DVBT_MGD_THD0, 0x10},
308 {DVBT_MGD_THD1, 0x20},
309 {DVBT_MGD_THD2, 0x20},
310 {DVBT_MGD_THD3, 0x40},
311 {DVBT_MGD_THD4, 0x22},
312 {DVBT_MGD_THD5, 0x32},
313 {DVBT_MGD_THD6, 0x37},
314 {DVBT_MGD_THD7, 0x39},
315 {DVBT_EN_BK_TRK, 0x0},
316 {DVBT_EN_CACQ_NOTCH, 0x0},
317 {DVBT_AD_AV_REF, 0x2a},
318 {DVBT_REG_PI, 0x6},
319 {DVBT_PIP_ON, 0x0},
320 {DVBT_CDIV_PH0, 0x8},
321 {DVBT_CDIV_PH1, 0x8},
322 {DVBT_SCALE1_B92, 0x4},
323 {DVBT_SCALE1_B93, 0xb0},
324 {DVBT_SCALE1_BA7, 0x78},
325 {DVBT_SCALE1_BA9, 0x28},
326 {DVBT_SCALE1_BAA, 0x59},
327 {DVBT_SCALE1_BAB, 0x83},
328 {DVBT_SCALE1_BAC, 0xd4},
329 {DVBT_SCALE1_BB0, 0x65},
330 {DVBT_SCALE1_BB1, 0x43},
331 {DVBT_KB_P1, 0x1},
332 {DVBT_KB_P2, 0x4},
333 {DVBT_KB_P3, 0x7},
334 {DVBT_K1_CR_STEP12, 0xa},
335 {DVBT_REG_GPE, 0x1},
336 {DVBT_SERIAL, 0x0},
337 {DVBT_CDIV_PH0, 0x9},
338 {DVBT_CDIV_PH1, 0x9},
339 {DVBT_MPEG_IO_OPT_2_2, 0x0},
340 {DVBT_MPEG_IO_OPT_1_0, 0x0},
341 {DVBT_TRK_KS_P2, 0x4},
342 {DVBT_TRK_KS_I2, 0x7},
343 {DVBT_TR_THD_SET2, 0x6},
344 {DVBT_TRK_KC_I2, 0x5},
345 {DVBT_CR_THD_SET2, 0x1},
346 };
347
348 dev_dbg(&client->dev, "\n");
349
350 for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
351 ret = rtl2832_wr_demod_reg(dev, rtl2832_initial_regs[i].reg,
352 rtl2832_initial_regs[i].value);
353 if (ret)
354 goto err;
355 }
356
357 /* load tuner specific settings */
358 dev_dbg(&client->dev, "load settings for tuner=%02x\n",
359 dev->pdata->tuner);
360 switch (dev->pdata->tuner) {
361 case RTL2832_TUNER_FC2580:
362 len = ARRAY_SIZE(rtl2832_tuner_init_fc2580);
363 init = rtl2832_tuner_init_fc2580;
364 break;
365 case RTL2832_TUNER_FC0012:
366 case RTL2832_TUNER_FC0013:
367 len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
368 init = rtl2832_tuner_init_fc0012;
369 break;
370 case RTL2832_TUNER_TUA9001:
371 len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
372 init = rtl2832_tuner_init_tua9001;
373 break;
374 case RTL2832_TUNER_E4000:
375 len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
376 init = rtl2832_tuner_init_e4000;
377 break;
378 case RTL2832_TUNER_R820T:
379 case RTL2832_TUNER_R828D:
380 len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
381 init = rtl2832_tuner_init_r820t;
382 break;
383 case RTL2832_TUNER_SI2157:
384 len = ARRAY_SIZE(rtl2832_tuner_init_si2157);
385 init = rtl2832_tuner_init_si2157;
386 break;
387 default:
388 ret = -EINVAL;
389 goto err;
390 }
391
392 for (i = 0; i < len; i++) {
393 ret = rtl2832_wr_demod_reg(dev, init[i].reg, init[i].value);
394 if (ret)
395 goto err;
396 }
397
398 /* init stats here in order signal app which stats are supported */
399 c->strength.len = 1;
400 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
401 c->cnr.len = 1;
402 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
403 c->post_bit_error.len = 1;
404 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
405 c->post_bit_count.len = 1;
406 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
407 /* start statistics polling */
408 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
409 dev->sleeping = false;
410
411 return 0;
412 err:
413 dev_dbg(&client->dev, "failed=%d\n", ret);
414 return ret;
415 }
416
417 static int rtl2832_sleep(struct dvb_frontend *fe)
418 {
419 struct rtl2832_dev *dev = fe->demodulator_priv;
420 struct i2c_client *client = dev->client;
421 int ret;
422
423 dev_dbg(&client->dev, "\n");
424
425 dev->sleeping = true;
426 /* stop statistics polling */
427 cancel_delayed_work_sync(&dev->stat_work);
428 dev->fe_status = 0;
429
430 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
431 if (ret)
432 goto err;
433
434 return 0;
435 err:
436 dev_dbg(&client->dev, "failed=%d\n", ret);
437 return ret;
438 }
439
440 static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
441 struct dvb_frontend_tune_settings *s)
442 {
443 struct rtl2832_dev *dev = fe->demodulator_priv;
444 struct i2c_client *client = dev->client;
445
446 dev_dbg(&client->dev, "\n");
447 s->min_delay_ms = 1000;
448 s->step_size = fe->ops.info.frequency_stepsize * 2;
449 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
450 return 0;
451 }
452
453 static int rtl2832_set_frontend(struct dvb_frontend *fe)
454 {
455 struct rtl2832_dev *dev = fe->demodulator_priv;
456 struct i2c_client *client = dev->client;
457 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
458 int ret, i, j;
459 u64 bw_mode, num, num2;
460 u32 resamp_ratio, cfreq_off_ratio;
461 static u8 bw_params[3][32] = {
462 /* 6 MHz bandwidth */
463 {
464 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
465 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
466 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
467 0x19, 0xe0,
468 },
469
470 /* 7 MHz bandwidth */
471 {
472 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
473 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
474 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
475 0x19, 0x10,
476 },
477
478 /* 8 MHz bandwidth */
479 {
480 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
481 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
482 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
483 0x19, 0xe0,
484 },
485 };
486
487 dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u inversion=%u\n",
488 c->frequency, c->bandwidth_hz, c->inversion);
489
490 /* program tuner */
491 if (fe->ops.tuner_ops.set_params)
492 fe->ops.tuner_ops.set_params(fe);
493
494 /* PIP mode related */
495 ret = rtl2832_bulk_write(client, 0x192, "\x00\x0f\xff", 3);
496 if (ret)
497 goto err;
498
499 /* If the frontend has get_if_frequency(), use it */
500 if (fe->ops.tuner_ops.get_if_frequency) {
501 u32 if_freq;
502
503 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
504 if (ret)
505 goto err;
506
507 ret = rtl2832_set_if(fe, if_freq);
508 if (ret)
509 goto err;
510 }
511
512 switch (c->bandwidth_hz) {
513 case 6000000:
514 i = 0;
515 bw_mode = 48000000;
516 break;
517 case 7000000:
518 i = 1;
519 bw_mode = 56000000;
520 break;
521 case 8000000:
522 i = 2;
523 bw_mode = 64000000;
524 break;
525 default:
526 dev_err(&client->dev, "invalid bandwidth_hz %u\n",
527 c->bandwidth_hz);
528 ret = -EINVAL;
529 goto err;
530 }
531
532 for (j = 0; j < sizeof(bw_params[0]); j++) {
533 ret = rtl2832_bulk_write(client, 0x11c + j, &bw_params[i][j], 1);
534 if (ret)
535 goto err;
536 }
537
538 /* calculate and set resample ratio
539 * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
540 * / ConstWithBandwidthMode)
541 */
542 num = dev->pdata->clk * 7;
543 num *= 0x400000;
544 num = div_u64(num, bw_mode);
545 resamp_ratio = num & 0x3ffffff;
546 ret = rtl2832_wr_demod_reg(dev, DVBT_RSAMP_RATIO, resamp_ratio);
547 if (ret)
548 goto err;
549
550 /* calculate and set cfreq off ratio
551 * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
552 * / (CrystalFreqHz * 7))
553 */
554 num = bw_mode << 20;
555 num2 = dev->pdata->clk * 7;
556 num = div_u64(num, num2);
557 num = -num;
558 cfreq_off_ratio = num & 0xfffff;
559 ret = rtl2832_wr_demod_reg(dev, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
560 if (ret)
561 goto err;
562
563 /* soft reset */
564 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
565 if (ret)
566 goto err;
567
568 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
569 if (ret)
570 goto err;
571
572 return 0;
573 err:
574 dev_dbg(&client->dev, "failed=%d\n", ret);
575 return ret;
576 }
577
578 static int rtl2832_get_frontend(struct dvb_frontend *fe)
579 {
580 struct rtl2832_dev *dev = fe->demodulator_priv;
581 struct i2c_client *client = dev->client;
582 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
583 int ret;
584 u8 buf[3];
585
586 if (dev->sleeping)
587 return 0;
588
589 ret = rtl2832_bulk_read(client, 0x33c, buf, 2);
590 if (ret)
591 goto err;
592
593 ret = rtl2832_bulk_read(client, 0x351, &buf[2], 1);
594 if (ret)
595 goto err;
596
597 dev_dbg(&client->dev, "TPS=%*ph\n", 3, buf);
598
599 switch ((buf[0] >> 2) & 3) {
600 case 0:
601 c->modulation = QPSK;
602 break;
603 case 1:
604 c->modulation = QAM_16;
605 break;
606 case 2:
607 c->modulation = QAM_64;
608 break;
609 }
610
611 switch ((buf[2] >> 2) & 1) {
612 case 0:
613 c->transmission_mode = TRANSMISSION_MODE_2K;
614 break;
615 case 1:
616 c->transmission_mode = TRANSMISSION_MODE_8K;
617 }
618
619 switch ((buf[2] >> 0) & 3) {
620 case 0:
621 c->guard_interval = GUARD_INTERVAL_1_32;
622 break;
623 case 1:
624 c->guard_interval = GUARD_INTERVAL_1_16;
625 break;
626 case 2:
627 c->guard_interval = GUARD_INTERVAL_1_8;
628 break;
629 case 3:
630 c->guard_interval = GUARD_INTERVAL_1_4;
631 break;
632 }
633
634 switch ((buf[0] >> 4) & 7) {
635 case 0:
636 c->hierarchy = HIERARCHY_NONE;
637 break;
638 case 1:
639 c->hierarchy = HIERARCHY_1;
640 break;
641 case 2:
642 c->hierarchy = HIERARCHY_2;
643 break;
644 case 3:
645 c->hierarchy = HIERARCHY_4;
646 break;
647 }
648
649 switch ((buf[1] >> 3) & 7) {
650 case 0:
651 c->code_rate_HP = FEC_1_2;
652 break;
653 case 1:
654 c->code_rate_HP = FEC_2_3;
655 break;
656 case 2:
657 c->code_rate_HP = FEC_3_4;
658 break;
659 case 3:
660 c->code_rate_HP = FEC_5_6;
661 break;
662 case 4:
663 c->code_rate_HP = FEC_7_8;
664 break;
665 }
666
667 switch ((buf[1] >> 0) & 7) {
668 case 0:
669 c->code_rate_LP = FEC_1_2;
670 break;
671 case 1:
672 c->code_rate_LP = FEC_2_3;
673 break;
674 case 2:
675 c->code_rate_LP = FEC_3_4;
676 break;
677 case 3:
678 c->code_rate_LP = FEC_5_6;
679 break;
680 case 4:
681 c->code_rate_LP = FEC_7_8;
682 break;
683 }
684
685 return 0;
686 err:
687 dev_dbg(&client->dev, "failed=%d\n", ret);
688 return ret;
689 }
690
691 static int rtl2832_read_status(struct dvb_frontend *fe, enum fe_status *status)
692 {
693 struct rtl2832_dev *dev = fe->demodulator_priv;
694 struct i2c_client *client = dev->client;
695 int ret;
696 u32 uninitialized_var(tmp);
697
698 dev_dbg(&client->dev, "\n");
699
700 *status = 0;
701 if (dev->sleeping)
702 return 0;
703
704 ret = rtl2832_rd_demod_reg(dev, DVBT_FSM_STAGE, &tmp);
705 if (ret)
706 goto err;
707
708 if (tmp == 11) {
709 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
710 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
711 } else if (tmp == 10) {
712 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
713 FE_HAS_VITERBI;
714 }
715
716 dev->fe_status = *status;
717 return 0;
718 err:
719 dev_dbg(&client->dev, "failed=%d\n", ret);
720 return ret;
721 }
722
723 static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
724 {
725 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
726
727 /* report SNR in resolution of 0.1 dB */
728 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
729 *snr = div_s64(c->cnr.stat[0].svalue, 100);
730 else
731 *snr = 0;
732
733 return 0;
734 }
735
736 static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
737 {
738 struct rtl2832_dev *dev = fe->demodulator_priv;
739
740 *ber = (dev->post_bit_error - dev->post_bit_error_prev);
741 dev->post_bit_error_prev = dev->post_bit_error;
742
743 return 0;
744 }
745
746 static void rtl2832_stat_work(struct work_struct *work)
747 {
748 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, stat_work.work);
749 struct i2c_client *client = dev->client;
750 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
751 int ret, tmp;
752 u8 u8tmp, buf[2];
753 u16 u16tmp;
754
755 dev_dbg(&client->dev, "\n");
756
757 /* signal strength */
758 if (dev->fe_status & FE_HAS_SIGNAL) {
759 /* read digital AGC */
760 ret = rtl2832_bulk_read(client, 0x305, &u8tmp, 1);
761 if (ret)
762 goto err;
763
764 dev_dbg(&client->dev, "digital agc=%02x", u8tmp);
765
766 u8tmp = ~u8tmp;
767 u16tmp = u8tmp << 8 | u8tmp << 0;
768
769 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
770 c->strength.stat[0].uvalue = u16tmp;
771 } else {
772 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
773 }
774
775 /* CNR */
776 if (dev->fe_status & FE_HAS_VITERBI) {
777 unsigned hierarchy, constellation;
778 #define CONSTELLATION_NUM 3
779 #define HIERARCHY_NUM 4
780 static const u32 constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
781 {85387325, 85387325, 85387325, 85387325},
782 {86676178, 86676178, 87167949, 87795660},
783 {87659938, 87659938, 87885178, 88241743},
784 };
785
786 ret = rtl2832_bulk_read(client, 0x33c, &u8tmp, 1);
787 if (ret)
788 goto err;
789
790 constellation = (u8tmp >> 2) & 0x03; /* [3:2] */
791 if (constellation > CONSTELLATION_NUM - 1)
792 goto err_schedule_delayed_work;
793
794 hierarchy = (u8tmp >> 4) & 0x07; /* [6:4] */
795 if (hierarchy > HIERARCHY_NUM - 1)
796 goto err_schedule_delayed_work;
797
798 ret = rtl2832_bulk_read(client, 0x40c, buf, 2);
799 if (ret)
800 goto err;
801
802 u16tmp = buf[0] << 8 | buf[1] << 0;
803 if (u16tmp)
804 tmp = (constant[constellation][hierarchy] -
805 intlog10(u16tmp)) / ((1 << 24) / 10000);
806 else
807 tmp = 0;
808
809 dev_dbg(&client->dev, "cnr raw=%u\n", u16tmp);
810
811 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
812 c->cnr.stat[0].svalue = tmp;
813 } else {
814 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
815 }
816
817 /* BER */
818 if (dev->fe_status & FE_HAS_LOCK) {
819 ret = rtl2832_bulk_read(client, 0x34e, buf, 2);
820 if (ret)
821 goto err;
822
823 u16tmp = buf[0] << 8 | buf[1] << 0;
824 dev->post_bit_error += u16tmp;
825 dev->post_bit_count += 1000000;
826
827 dev_dbg(&client->dev, "ber errors=%u total=1000000\n", u16tmp);
828
829 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
830 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
831 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
832 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
833 } else {
834 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
835 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
836 }
837
838 err_schedule_delayed_work:
839 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
840 return;
841 err:
842 dev_dbg(&client->dev, "failed=%d\n", ret);
843 }
844
845 /*
846 * I2C gate/mux/repeater logic
847 * We must use unlocked __i2c_transfer() here (through regmap) because of I2C
848 * adapter lock is already taken by tuner driver.
849 * There is delay mechanism to avoid unneeded I2C gate open / close. Gate close
850 * is delayed here a little bit in order to see if there is sequence of I2C
851 * messages sent to same I2C bus.
852 */
853 static void rtl2832_i2c_gate_work(struct work_struct *work)
854 {
855 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, i2c_gate_work.work);
856 struct i2c_client *client = dev->client;
857 int ret;
858
859 /* close gate */
860 ret = rtl2832_update_bits(dev->client, 0x101, 0x08, 0x00);
861 if (ret)
862 goto err;
863
864 return;
865 err:
866 dev_dbg(&client->dev, "failed=%d\n", ret);
867 }
868
869 static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id)
870 {
871 struct rtl2832_dev *dev = mux_priv;
872 struct i2c_client *client = dev->client;
873 int ret;
874
875 /* terminate possible gate closing */
876 cancel_delayed_work(&dev->i2c_gate_work);
877
878 /*
879 * I2C adapter lock is already taken and due to that we will use
880 * regmap_update_bits() which does not lock again I2C adapter.
881 */
882 ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);
883 if (ret)
884 goto err;
885
886 return 0;
887 err:
888 dev_dbg(&client->dev, "failed=%d\n", ret);
889 return ret;
890 }
891
892 static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv,
893 u32 chan_id)
894 {
895 struct rtl2832_dev *dev = mux_priv;
896
897 schedule_delayed_work(&dev->i2c_gate_work, usecs_to_jiffies(100));
898 return 0;
899 }
900
901 static struct dvb_frontend_ops rtl2832_ops = {
902 .delsys = { SYS_DVBT },
903 .info = {
904 .name = "Realtek RTL2832 (DVB-T)",
905 .frequency_min = 174000000,
906 .frequency_max = 862000000,
907 .frequency_stepsize = 166667,
908 .caps = FE_CAN_FEC_1_2 |
909 FE_CAN_FEC_2_3 |
910 FE_CAN_FEC_3_4 |
911 FE_CAN_FEC_5_6 |
912 FE_CAN_FEC_7_8 |
913 FE_CAN_FEC_AUTO |
914 FE_CAN_QPSK |
915 FE_CAN_QAM_16 |
916 FE_CAN_QAM_64 |
917 FE_CAN_QAM_AUTO |
918 FE_CAN_TRANSMISSION_MODE_AUTO |
919 FE_CAN_GUARD_INTERVAL_AUTO |
920 FE_CAN_HIERARCHY_AUTO |
921 FE_CAN_RECOVER |
922 FE_CAN_MUTE_TS
923 },
924
925 .init = rtl2832_init,
926 .sleep = rtl2832_sleep,
927
928 .get_tune_settings = rtl2832_get_tune_settings,
929
930 .set_frontend = rtl2832_set_frontend,
931 .get_frontend = rtl2832_get_frontend,
932
933 .read_status = rtl2832_read_status,
934 .read_snr = rtl2832_read_snr,
935 .read_ber = rtl2832_read_ber,
936 };
937
938 static bool rtl2832_volatile_reg(struct device *dev, unsigned int reg)
939 {
940 switch (reg) {
941 case 0x305:
942 case 0x33c:
943 case 0x34e:
944 case 0x351:
945 case 0x40c ... 0x40d:
946 return true;
947 default:
948 break;
949 }
950
951 return false;
952 }
953
954 /*
955 * We implement own I2C access routines for regmap in order to get manual access
956 * to I2C adapter lock, which is needed for I2C mux adapter.
957 */
958 static int rtl2832_regmap_read(void *context, const void *reg_buf,
959 size_t reg_size, void *val_buf, size_t val_size)
960 {
961 struct i2c_client *client = context;
962 int ret;
963 struct i2c_msg msg[2] = {
964 {
965 .addr = client->addr,
966 .flags = 0,
967 .len = reg_size,
968 .buf = (u8 *)reg_buf,
969 }, {
970 .addr = client->addr,
971 .flags = I2C_M_RD,
972 .len = val_size,
973 .buf = val_buf,
974 }
975 };
976
977 ret = __i2c_transfer(client->adapter, msg, 2);
978 if (ret != 2) {
979 dev_warn(&client->dev, "i2c reg read failed %d reg %02x\n",
980 ret, *(u8 *)reg_buf);
981 if (ret >= 0)
982 ret = -EREMOTEIO;
983 return ret;
984 }
985 return 0;
986 }
987
988 static int rtl2832_regmap_write(void *context, const void *data, size_t count)
989 {
990 struct i2c_client *client = context;
991 int ret;
992 struct i2c_msg msg[1] = {
993 {
994 .addr = client->addr,
995 .flags = 0,
996 .len = count,
997 .buf = (u8 *)data,
998 }
999 };
1000
1001 ret = __i2c_transfer(client->adapter, msg, 1);
1002 if (ret != 1) {
1003 dev_warn(&client->dev, "i2c reg write failed %d reg %02x\n",
1004 ret, *(u8 *)data);
1005 if (ret >= 0)
1006 ret = -EREMOTEIO;
1007 return ret;
1008 }
1009 return 0;
1010 }
1011
1012 static int rtl2832_regmap_gather_write(void *context, const void *reg,
1013 size_t reg_len, const void *val,
1014 size_t val_len)
1015 {
1016 struct i2c_client *client = context;
1017 int ret;
1018 u8 buf[256];
1019 struct i2c_msg msg[1] = {
1020 {
1021 .addr = client->addr,
1022 .flags = 0,
1023 .len = 1 + val_len,
1024 .buf = buf,
1025 }
1026 };
1027
1028 buf[0] = *(u8 const *)reg;
1029 memcpy(&buf[1], val, val_len);
1030
1031 ret = __i2c_transfer(client->adapter, msg, 1);
1032 if (ret != 1) {
1033 dev_warn(&client->dev, "i2c reg write failed %d reg %02x\n",
1034 ret, *(u8 const *)reg);
1035 if (ret >= 0)
1036 ret = -EREMOTEIO;
1037 return ret;
1038 }
1039 return 0;
1040 }
1041
1042 /*
1043 * FIXME: Hack. Implement own regmap locking in order to silence lockdep
1044 * recursive lock warning. That happens when regmap I2C client calls I2C mux
1045 * adapter, which leads demod I2C repeater enable via demod regmap. Operation
1046 * takes two regmap locks recursively - but those are different regmap instances
1047 * in a two different I2C drivers, so it is not deadlock. Proper fix is to make
1048 * regmap aware of lockdep.
1049 */
1050 static void rtl2832_regmap_lock(void *__dev)
1051 {
1052 struct rtl2832_dev *dev = __dev;
1053 struct i2c_client *client = dev->client;
1054
1055 dev_dbg(&client->dev, "\n");
1056 mutex_lock(&dev->regmap_mutex);
1057 }
1058
1059 static void rtl2832_regmap_unlock(void *__dev)
1060 {
1061 struct rtl2832_dev *dev = __dev;
1062 struct i2c_client *client = dev->client;
1063
1064 dev_dbg(&client->dev, "\n");
1065 mutex_unlock(&dev->regmap_mutex);
1066 }
1067
1068 static struct dvb_frontend *rtl2832_get_dvb_frontend(struct i2c_client *client)
1069 {
1070 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1071
1072 dev_dbg(&client->dev, "\n");
1073 return &dev->fe;
1074 }
1075
1076 static struct i2c_adapter *rtl2832_get_i2c_adapter(struct i2c_client *client)
1077 {
1078 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1079
1080 dev_dbg(&client->dev, "\n");
1081 return dev->i2c_adapter_tuner;
1082 }
1083
1084 static int rtl2832_enable_slave_ts(struct i2c_client *client)
1085 {
1086 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1087 int ret;
1088
1089 dev_dbg(&client->dev, "\n");
1090
1091 ret = rtl2832_bulk_write(client, 0x10c, "\x5f\xff", 2);
1092 if (ret)
1093 goto err;
1094
1095 ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x1);
1096 if (ret)
1097 goto err;
1098
1099 ret = rtl2832_bulk_write(client, 0x0bc, "\x18", 1);
1100 if (ret)
1101 goto err;
1102
1103 ret = rtl2832_bulk_write(client, 0x192, "\x7f\xf7\xff", 3);
1104 if (ret)
1105 goto err;
1106
1107 /* soft reset */
1108 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
1109 if (ret)
1110 goto err;
1111
1112 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
1113 if (ret)
1114 goto err;
1115
1116 return 0;
1117 err:
1118 dev_dbg(&client->dev, "failed=%d\n", ret);
1119 return ret;
1120 }
1121
1122 static int rtl2832_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
1123 {
1124 struct rtl2832_dev *dev = fe->demodulator_priv;
1125 struct i2c_client *client = dev->client;
1126 int ret;
1127 u8 u8tmp;
1128
1129 dev_dbg(&client->dev, "onoff=%d\n", onoff);
1130
1131 /* enable / disable PID filter */
1132 if (onoff)
1133 u8tmp = 0x80;
1134 else
1135 u8tmp = 0x00;
1136
1137 ret = rtl2832_update_bits(client, 0x061, 0xc0, u8tmp);
1138 if (ret)
1139 goto err;
1140
1141 return 0;
1142 err:
1143 dev_dbg(&client->dev, "failed=%d\n", ret);
1144 return ret;
1145 }
1146
1147 static int rtl2832_pid_filter(struct dvb_frontend *fe, u8 index, u16 pid,
1148 int onoff)
1149 {
1150 struct rtl2832_dev *dev = fe->demodulator_priv;
1151 struct i2c_client *client = dev->client;
1152 int ret;
1153 u8 buf[4];
1154
1155 dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n",
1156 index, pid, onoff);
1157
1158 /* skip invalid PIDs (0x2000) */
1159 if (pid > 0x1fff || index > 32)
1160 return 0;
1161
1162 if (onoff)
1163 set_bit(index, &dev->filters);
1164 else
1165 clear_bit(index, &dev->filters);
1166
1167 /* enable / disable PIDs */
1168 buf[0] = (dev->filters >> 0) & 0xff;
1169 buf[1] = (dev->filters >> 8) & 0xff;
1170 buf[2] = (dev->filters >> 16) & 0xff;
1171 buf[3] = (dev->filters >> 24) & 0xff;
1172 ret = rtl2832_bulk_write(client, 0x062, buf, 4);
1173 if (ret)
1174 goto err;
1175
1176 /* add PID */
1177 buf[0] = (pid >> 8) & 0xff;
1178 buf[1] = (pid >> 0) & 0xff;
1179 ret = rtl2832_bulk_write(client, 0x066 + 2 * index, buf, 2);
1180 if (ret)
1181 goto err;
1182
1183 return 0;
1184 err:
1185 dev_dbg(&client->dev, "failed=%d\n", ret);
1186 return ret;
1187 }
1188
1189 static int rtl2832_probe(struct i2c_client *client,
1190 const struct i2c_device_id *id)
1191 {
1192 struct rtl2832_platform_data *pdata = client->dev.platform_data;
1193 struct i2c_adapter *i2c = client->adapter;
1194 struct rtl2832_dev *dev;
1195 int ret;
1196 u8 tmp;
1197 static const struct regmap_bus regmap_bus = {
1198 .read = rtl2832_regmap_read,
1199 .write = rtl2832_regmap_write,
1200 .gather_write = rtl2832_regmap_gather_write,
1201 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
1202 };
1203 static const struct regmap_range_cfg regmap_range_cfg[] = {
1204 {
1205 .selector_reg = 0x00,
1206 .selector_mask = 0xff,
1207 .selector_shift = 0,
1208 .window_start = 0,
1209 .window_len = 0x100,
1210 .range_min = 0 * 0x100,
1211 .range_max = 5 * 0x100,
1212 },
1213 };
1214
1215 dev_dbg(&client->dev, "\n");
1216
1217 /* allocate memory for the internal state */
1218 dev = kzalloc(sizeof(struct rtl2832_dev), GFP_KERNEL);
1219 if (dev == NULL) {
1220 ret = -ENOMEM;
1221 goto err;
1222 }
1223
1224 /* setup the state */
1225 i2c_set_clientdata(client, dev);
1226 dev->client = client;
1227 dev->pdata = client->dev.platform_data;
1228 dev->sleeping = true;
1229 INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);
1230 INIT_DELAYED_WORK(&dev->stat_work, rtl2832_stat_work);
1231 /* create regmap */
1232 mutex_init(&dev->regmap_mutex);
1233 dev->regmap_config.reg_bits = 8,
1234 dev->regmap_config.val_bits = 8,
1235 dev->regmap_config.lock = rtl2832_regmap_lock,
1236 dev->regmap_config.unlock = rtl2832_regmap_unlock,
1237 dev->regmap_config.lock_arg = dev,
1238 dev->regmap_config.volatile_reg = rtl2832_volatile_reg,
1239 dev->regmap_config.max_register = 5 * 0x100,
1240 dev->regmap_config.ranges = regmap_range_cfg,
1241 dev->regmap_config.num_ranges = ARRAY_SIZE(regmap_range_cfg),
1242 dev->regmap_config.cache_type = REGCACHE_NONE,
1243 dev->regmap = regmap_init(&client->dev, &regmap_bus, client,
1244 &dev->regmap_config);
1245 if (IS_ERR(dev->regmap)) {
1246 ret = PTR_ERR(dev->regmap);
1247 goto err_kfree;
1248 }
1249
1250 /* check if the demod is there */
1251 ret = rtl2832_bulk_read(client, 0x000, &tmp, 1);
1252 if (ret)
1253 goto err_regmap_exit;
1254
1255 /* create muxed i2c adapter for demod tuner bus */
1256 dev->i2c_adapter_tuner = i2c_add_mux_adapter(i2c, &i2c->dev, dev,
1257 0, 0, 0, rtl2832_select, rtl2832_deselect);
1258 if (dev->i2c_adapter_tuner == NULL) {
1259 ret = -ENODEV;
1260 goto err_regmap_exit;
1261 }
1262
1263 /* create dvb_frontend */
1264 memcpy(&dev->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
1265 dev->fe.demodulator_priv = dev;
1266
1267 /* setup callbacks */
1268 pdata->get_dvb_frontend = rtl2832_get_dvb_frontend;
1269 pdata->get_i2c_adapter = rtl2832_get_i2c_adapter;
1270 pdata->enable_slave_ts = rtl2832_enable_slave_ts;
1271 pdata->pid_filter = rtl2832_pid_filter;
1272 pdata->pid_filter_ctrl = rtl2832_pid_filter_ctrl;
1273 pdata->bulk_read = rtl2832_bulk_read;
1274 pdata->bulk_write = rtl2832_bulk_write;
1275 pdata->update_bits = rtl2832_update_bits;
1276
1277 dev_info(&client->dev, "Realtek RTL2832 successfully attached\n");
1278 return 0;
1279 err_regmap_exit:
1280 regmap_exit(dev->regmap);
1281 err_kfree:
1282 kfree(dev);
1283 err:
1284 dev_dbg(&client->dev, "failed=%d\n", ret);
1285 return ret;
1286 }
1287
1288 static int rtl2832_remove(struct i2c_client *client)
1289 {
1290 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1291
1292 dev_dbg(&client->dev, "\n");
1293
1294 cancel_delayed_work_sync(&dev->i2c_gate_work);
1295
1296 i2c_del_mux_adapter(dev->i2c_adapter_tuner);
1297
1298 regmap_exit(dev->regmap);
1299
1300 kfree(dev);
1301
1302 return 0;
1303 }
1304
1305 static const struct i2c_device_id rtl2832_id_table[] = {
1306 {"rtl2832", 0},
1307 {}
1308 };
1309 MODULE_DEVICE_TABLE(i2c, rtl2832_id_table);
1310
1311 static struct i2c_driver rtl2832_driver = {
1312 .driver = {
1313 .name = "rtl2832",
1314 },
1315 .probe = rtl2832_probe,
1316 .remove = rtl2832_remove,
1317 .id_table = rtl2832_id_table,
1318 };
1319
1320 module_i2c_driver(rtl2832_driver);
1321
1322 MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
1323 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1324 MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
1325 MODULE_LICENSE("GPL");
Linux with added FPC-III support