drivers/clk/clk-asm9260.c

   1 /*
   2  * Copyright (c) 2014 Oleksij Rempel <linux@rempel-privat.de>.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clkdev.h>
  19 #include <linux/err.h>
  20 #include <linux/io.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <dt-bindings/clock/alphascale,asm9260.h>
  26
  27 #define HW_AHBCLKCTRL0          0x0020
  28 #define HW_AHBCLKCTRL1          0x0030
  29 #define HW_SYSPLLCTRL           0x0100
  30 #define HW_MAINCLKSEL           0x0120
  31 #define HW_MAINCLKUEN           0x0124
  32 #define HW_UARTCLKSEL           0x0128
  33 #define HW_UARTCLKUEN           0x012c
  34 #define HW_I2S0CLKSEL           0x0130
  35 #define HW_I2S0CLKUEN           0x0134
  36 #define HW_I2S1CLKSEL           0x0138
  37 #define HW_I2S1CLKUEN           0x013c
  38 #define HW_WDTCLKSEL            0x0160
  39 #define HW_WDTCLKUEN            0x0164
  40 #define HW_CLKOUTCLKSEL         0x0170
  41 #define HW_CLKOUTCLKUEN         0x0174
  42 #define HW_CPUCLKDIV            0x017c
  43 #define HW_SYSAHBCLKDIV         0x0180
  44 #define HW_I2S0MCLKDIV          0x0190
  45 #define HW_I2S0SCLKDIV          0x0194
  46 #define HW_I2S1MCLKDIV          0x0188
  47 #define HW_I2S1SCLKDIV          0x018c
  48 #define HW_UART0CLKDIV          0x0198
  49 #define HW_UART1CLKDIV          0x019c
  50 #define HW_UART2CLKDIV          0x01a0
  51 #define HW_UART3CLKDIV          0x01a4
  52 #define HW_UART4CLKDIV          0x01a8
  53 #define HW_UART5CLKDIV          0x01ac
  54 #define HW_UART6CLKDIV          0x01b0
  55 #define HW_UART7CLKDIV          0x01b4
  56 #define HW_UART8CLKDIV          0x01b8
  57 #define HW_UART9CLKDIV          0x01bc
  58 #define HW_SPI0CLKDIV           0x01c0
  59 #define HW_SPI1CLKDIV           0x01c4
  60 #define HW_QUADSPICLKDIV        0x01c8
  61 #define HW_SSP0CLKDIV           0x01d0
  62 #define HW_NANDCLKDIV           0x01d4
  63 #define HW_TRACECLKDIV          0x01e0
  64 #define HW_CAMMCLKDIV           0x01e8
  65 #define HW_WDTCLKDIV            0x01ec
  66 #define HW_CLKOUTCLKDIV         0x01f4
  67 #define HW_MACCLKDIV            0x01f8
  68 #define HW_LCDCLKDIV            0x01fc
  69 #define HW_ADCANACLKDIV         0x0200
  70
  71 static struct clk_hw_onecell_data *clk_data;
  72 static DEFINE_SPINLOCK(asm9260_clk_lock);
  73
  74 struct asm9260_div_clk {
  75         unsigned int idx;
  76         const char *name;
  77         const char *parent_name;
  78         u32 reg;
  79 };
  80
  81 struct asm9260_gate_data {
  82         unsigned int idx;
  83         const char *name;
  84         const char *parent_name;
  85         u32 reg;
  86         u8 bit_idx;
  87         unsigned long flags;
  88 };
  89
  90 struct asm9260_mux_clock {
  91         u8                      mask;
  92         u32                     *table;
  93         const char              *name;
  94         const char              **parent_names;
  95         u8                      num_parents;
  96         unsigned long           offset;
  97         unsigned long           flags;
  98 };
  99
 100 static void __iomem *base;
 101
 102 static const struct asm9260_div_clk asm9260_div_clks[] __initconst = {
 103         { CLKID_SYS_CPU,        "cpu_div", "main_gate", HW_CPUCLKDIV },
 104         { CLKID_SYS_AHB,        "ahb_div", "cpu_div", HW_SYSAHBCLKDIV },
 105
 106         /* i2s has two deviders: one for only external mclk and internal
 107          * devider for all clks. */
 108         { CLKID_SYS_I2S0M,      "i2s0m_div", "i2s0_mclk",  HW_I2S0MCLKDIV },
 109         { CLKID_SYS_I2S1M,      "i2s1m_div", "i2s1_mclk",  HW_I2S1MCLKDIV },
 110         { CLKID_SYS_I2S0S,      "i2s0s_div", "i2s0_gate",  HW_I2S0SCLKDIV },
 111         { CLKID_SYS_I2S1S,      "i2s1s_div", "i2s0_gate",  HW_I2S1SCLKDIV },
 112
 113         { CLKID_SYS_UART0,      "uart0_div", "uart_gate", HW_UART0CLKDIV },
 114         { CLKID_SYS_UART1,      "uart1_div", "uart_gate", HW_UART1CLKDIV },
 115         { CLKID_SYS_UART2,      "uart2_div", "uart_gate", HW_UART2CLKDIV },
 116         { CLKID_SYS_UART3,      "uart3_div", "uart_gate", HW_UART3CLKDIV },
 117         { CLKID_SYS_UART4,      "uart4_div", "uart_gate", HW_UART4CLKDIV },
 118         { CLKID_SYS_UART5,      "uart5_div", "uart_gate", HW_UART5CLKDIV },
 119         { CLKID_SYS_UART6,      "uart6_div", "uart_gate", HW_UART6CLKDIV },
 120         { CLKID_SYS_UART7,      "uart7_div", "uart_gate", HW_UART7CLKDIV },
 121         { CLKID_SYS_UART8,      "uart8_div", "uart_gate", HW_UART8CLKDIV },
 122         { CLKID_SYS_UART9,      "uart9_div", "uart_gate", HW_UART9CLKDIV },
 123
 124         { CLKID_SYS_SPI0,       "spi0_div",     "main_gate", HW_SPI0CLKDIV },
 125         { CLKID_SYS_SPI1,       "spi1_div",     "main_gate", HW_SPI1CLKDIV },
 126         { CLKID_SYS_QUADSPI,    "quadspi_div",  "main_gate", HW_QUADSPICLKDIV },
 127         { CLKID_SYS_SSP0,       "ssp0_div",     "main_gate", HW_SSP0CLKDIV },
 128         { CLKID_SYS_NAND,       "nand_div",     "main_gate", HW_NANDCLKDIV },
 129         { CLKID_SYS_TRACE,      "trace_div",    "main_gate", HW_TRACECLKDIV },
 130         { CLKID_SYS_CAMM,       "camm_div",     "main_gate", HW_CAMMCLKDIV },
 131         { CLKID_SYS_MAC,        "mac_div",      "main_gate", HW_MACCLKDIV },
 132         { CLKID_SYS_LCD,        "lcd_div",      "main_gate", HW_LCDCLKDIV },
 133         { CLKID_SYS_ADCANA,     "adcana_div",   "main_gate", HW_ADCANACLKDIV },
 134
 135         { CLKID_SYS_WDT,        "wdt_div",      "wdt_gate",    HW_WDTCLKDIV },
 136         { CLKID_SYS_CLKOUT,     "clkout_div",   "clkout_gate", HW_CLKOUTCLKDIV },
 137 };
 138
 139 static const struct asm9260_gate_data asm9260_mux_gates[] __initconst = {
 140         { 0, "main_gate",       "main_mux",     HW_MAINCLKUEN,  0 },
 141         { 0, "uart_gate",       "uart_mux",     HW_UARTCLKUEN,  0 },
 142         { 0, "i2s0_gate",       "i2s0_mux",     HW_I2S0CLKUEN,  0 },
 143         { 0, "i2s1_gate",       "i2s1_mux",     HW_I2S1CLKUEN,  0 },
 144         { 0, "wdt_gate",        "wdt_mux",      HW_WDTCLKUEN,   0 },
 145         { 0, "clkout_gate",     "clkout_mux",   HW_CLKOUTCLKUEN, 0 },
 146 };
 147 static const struct asm9260_gate_data asm9260_ahb_gates[] __initconst = {
 148         /* ahb gates */
 149         { CLKID_AHB_ROM,        "rom",          "ahb_div",
 150                 HW_AHBCLKCTRL0, 1, CLK_IGNORE_UNUSED},
 151         { CLKID_AHB_RAM,        "ram",          "ahb_div",
 152                 HW_AHBCLKCTRL0, 2, CLK_IGNORE_UNUSED},
 153         { CLKID_AHB_GPIO,       "gpio",         "ahb_div",
 154                 HW_AHBCLKCTRL0, 4 },
 155         { CLKID_AHB_MAC,        "mac",          "ahb_div",
 156                 HW_AHBCLKCTRL0, 5 },
 157         { CLKID_AHB_EMI,        "emi",          "ahb_div",
 158                 HW_AHBCLKCTRL0, 6, CLK_IGNORE_UNUSED},
 159         { CLKID_AHB_USB0,       "usb0",         "ahb_div",
 160                 HW_AHBCLKCTRL0, 7 },
 161         { CLKID_AHB_USB1,       "usb1",         "ahb_div",
 162                 HW_AHBCLKCTRL0, 8 },
 163         { CLKID_AHB_DMA0,       "dma0",         "ahb_div",
 164                 HW_AHBCLKCTRL0, 9 },
 165         { CLKID_AHB_DMA1,       "dma1",         "ahb_div",
 166                 HW_AHBCLKCTRL0, 10 },
 167         { CLKID_AHB_UART0,      "uart0",        "ahb_div",
 168                 HW_AHBCLKCTRL0, 11 },
 169         { CLKID_AHB_UART1,      "uart1",        "ahb_div",
 170                 HW_AHBCLKCTRL0, 12 },
 171         { CLKID_AHB_UART2,      "uart2",        "ahb_div",
 172                 HW_AHBCLKCTRL0, 13 },
 173         { CLKID_AHB_UART3,      "uart3",        "ahb_div",
 174                 HW_AHBCLKCTRL0, 14 },
 175         { CLKID_AHB_UART4,      "uart4",        "ahb_div",
 176                 HW_AHBCLKCTRL0, 15 },
 177         { CLKID_AHB_UART5,      "uart5",        "ahb_div",
 178                 HW_AHBCLKCTRL0, 16 },
 179         { CLKID_AHB_UART6,      "uart6",        "ahb_div",
 180                 HW_AHBCLKCTRL0, 17 },
 181         { CLKID_AHB_UART7,      "uart7",        "ahb_div",
 182                 HW_AHBCLKCTRL0, 18 },
 183         { CLKID_AHB_UART8,      "uart8",        "ahb_div",
 184                 HW_AHBCLKCTRL0, 19 },
 185         { CLKID_AHB_UART9,      "uart9",        "ahb_div",
 186                 HW_AHBCLKCTRL0, 20 },
 187         { CLKID_AHB_I2S0,       "i2s0",         "ahb_div",
 188                 HW_AHBCLKCTRL0, 21 },
 189         { CLKID_AHB_I2C0,       "i2c0",         "ahb_div",
 190                 HW_AHBCLKCTRL0, 22 },
 191         { CLKID_AHB_I2C1,       "i2c1",         "ahb_div",
 192                 HW_AHBCLKCTRL0, 23 },
 193         { CLKID_AHB_SSP0,       "ssp0",         "ahb_div",
 194                 HW_AHBCLKCTRL0, 24 },
 195         { CLKID_AHB_IOCONFIG,   "ioconf",       "ahb_div",
 196                 HW_AHBCLKCTRL0, 25 },
 197         { CLKID_AHB_WDT,        "wdt",          "ahb_div",
 198                 HW_AHBCLKCTRL0, 26 },
 199         { CLKID_AHB_CAN0,       "can0",         "ahb_div",
 200                 HW_AHBCLKCTRL0, 27 },
 201         { CLKID_AHB_CAN1,       "can1",         "ahb_div",
 202                 HW_AHBCLKCTRL0, 28 },
 203         { CLKID_AHB_MPWM,       "mpwm",         "ahb_div",
 204                 HW_AHBCLKCTRL0, 29 },
 205         { CLKID_AHB_SPI0,       "spi0",         "ahb_div",
 206                 HW_AHBCLKCTRL0, 30 },
 207         { CLKID_AHB_SPI1,       "spi1",         "ahb_div",
 208                 HW_AHBCLKCTRL0, 31 },
 209
 210         { CLKID_AHB_QEI,        "qei",          "ahb_div",
 211                 HW_AHBCLKCTRL1, 0 },
 212         { CLKID_AHB_QUADSPI0,   "quadspi0",     "ahb_div",
 213                 HW_AHBCLKCTRL1, 1 },
 214         { CLKID_AHB_CAMIF,      "capmif",       "ahb_div",
 215                 HW_AHBCLKCTRL1, 2 },
 216         { CLKID_AHB_LCDIF,      "lcdif",        "ahb_div",
 217                 HW_AHBCLKCTRL1, 3 },
 218         { CLKID_AHB_TIMER0,     "timer0",       "ahb_div",
 219                 HW_AHBCLKCTRL1, 4 },
 220         { CLKID_AHB_TIMER1,     "timer1",       "ahb_div",
 221                 HW_AHBCLKCTRL1, 5 },
 222         { CLKID_AHB_TIMER2,     "timer2",       "ahb_div",
 223                 HW_AHBCLKCTRL1, 6 },
 224         { CLKID_AHB_TIMER3,     "timer3",       "ahb_div",
 225                 HW_AHBCLKCTRL1, 7 },
 226         { CLKID_AHB_IRQ,        "irq",          "ahb_div",
 227                 HW_AHBCLKCTRL1, 8, CLK_IGNORE_UNUSED},
 228         { CLKID_AHB_RTC,        "rtc",          "ahb_div",
 229                 HW_AHBCLKCTRL1, 9 },
 230         { CLKID_AHB_NAND,       "nand",         "ahb_div",
 231                 HW_AHBCLKCTRL1, 10 },
 232         { CLKID_AHB_ADC0,       "adc0",         "ahb_div",
 233                 HW_AHBCLKCTRL1, 11 },
 234         { CLKID_AHB_LED,        "led",          "ahb_div",
 235                 HW_AHBCLKCTRL1, 12 },
 236         { CLKID_AHB_DAC0,       "dac0",         "ahb_div",
 237                 HW_AHBCLKCTRL1, 13 },
 238         { CLKID_AHB_LCD,        "lcd",          "ahb_div",
 239                 HW_AHBCLKCTRL1, 14 },
 240         { CLKID_AHB_I2S1,       "i2s1",         "ahb_div",
 241                 HW_AHBCLKCTRL1, 15 },
 242         { CLKID_AHB_MAC1,       "mac1",         "ahb_div",
 243                 HW_AHBCLKCTRL1, 16 },
 244 };
 245
 246 static const char __initdata *main_mux_p[] =   { NULL, NULL };
 247 static const char __initdata *i2s0_mux_p[] =   { NULL, NULL, "i2s0m_div"};
 248 static const char __initdata *i2s1_mux_p[] =   { NULL, NULL, "i2s1m_div"};
 249 static const char __initdata *clkout_mux_p[] = { NULL, NULL, "rtc"};
 250 static u32 three_mux_table[] = {0, 1, 3};
 251
 252 static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = {
 253         { 1, three_mux_table, "main_mux",       main_mux_p,
 254                 ARRAY_SIZE(main_mux_p), HW_MAINCLKSEL, },
 255         { 1, three_mux_table, "uart_mux",       main_mux_p,
 256                 ARRAY_SIZE(main_mux_p), HW_UARTCLKSEL, },
 257         { 1, three_mux_table, "wdt_mux",        main_mux_p,
 258                 ARRAY_SIZE(main_mux_p), HW_WDTCLKSEL, },
 259         { 3, three_mux_table, "i2s0_mux",       i2s0_mux_p,
 260                 ARRAY_SIZE(i2s0_mux_p), HW_I2S0CLKSEL, },
 261         { 3, three_mux_table, "i2s1_mux",       i2s1_mux_p,
 262                 ARRAY_SIZE(i2s1_mux_p), HW_I2S1CLKSEL, },
 263         { 3, three_mux_table, "clkout_mux",     clkout_mux_p,
 264                 ARRAY_SIZE(clkout_mux_p), HW_CLKOUTCLKSEL, },
 265 };
 266
 267 static void __init asm9260_acc_init(struct device_node *np)
 268 {
 269         struct clk_hw *hw;
 270         struct clk_hw **hws;
 271         const char *ref_clk, *pll_clk = "pll";
 272         u32 rate;
 273         int n;
 274         u32 accuracy = 0;
 275
 276         clk_data = kzalloc(sizeof(*clk_data) +
 277                            sizeof(*clk_data->hws) * MAX_CLKS, GFP_KERNEL);
 278         if (!clk_data)
 279                 return;
 280         clk_data->num = MAX_CLKS;
 281         hws = clk_data->hws;
 282
 283         base = of_io_request_and_map(np, 0, np->name);
 284         if (IS_ERR(base))
 285                 panic("%s: unable to map resource", np->name);
 286
 287         /* register pll */
 288         rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000;
 289
 290         ref_clk = of_clk_get_parent_name(np, 0);
 291         accuracy = clk_get_accuracy(__clk_lookup(ref_clk));
 292         hw = clk_hw_register_fixed_rate_with_accuracy(NULL, pll_clk,
 293                         ref_clk, 0, rate, accuracy);
 294
 295         if (IS_ERR(hw))
 296                 panic("%s: can't register REFCLK. Check DT!", np->name);
 297
 298         for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) {
 299                 const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n];
 300
 301                 mc->parent_names[0] = ref_clk;
 302                 mc->parent_names[1] = pll_clk;
 303                 hw = clk_hw_register_mux_table(NULL, mc->name, mc->parent_names,
 304                                 mc->num_parents, mc->flags, base + mc->offset,
 305                                 0, mc->mask, 0, mc->table, &asm9260_clk_lock);
 306         }
 307
 308         /* clock mux gate cells */
 309         for (n = 0; n < ARRAY_SIZE(asm9260_mux_gates); n++) {
 310                 const struct asm9260_gate_data *gd = &asm9260_mux_gates[n];
 311
 312                 hw = clk_hw_register_gate(NULL, gd->name,
 313                         gd->parent_name, gd->flags | CLK_SET_RATE_PARENT,
 314                         base + gd->reg, gd->bit_idx, 0, &asm9260_clk_lock);
 315         }
 316
 317         /* clock div cells */
 318         for (n = 0; n < ARRAY_SIZE(asm9260_div_clks); n++) {
 319                 const struct asm9260_div_clk *dc = &asm9260_div_clks[n];
 320
 321                 hws[dc->idx] = clk_hw_register_divider(NULL, dc->name,
 322                                 dc->parent_name, CLK_SET_RATE_PARENT,
 323                                 base + dc->reg, 0, 8, CLK_DIVIDER_ONE_BASED,
 324                                 &asm9260_clk_lock);
 325         }
 326
 327         /* clock ahb gate cells */
 328         for (n = 0; n < ARRAY_SIZE(asm9260_ahb_gates); n++) {
 329                 const struct asm9260_gate_data *gd = &asm9260_ahb_gates[n];
 330
 331                 hws[gd->idx] = clk_hw_register_gate(NULL, gd->name,
 332                                 gd->parent_name, gd->flags, base + gd->reg,
 333                                 gd->bit_idx, 0, &asm9260_clk_lock);
 334         }
 335
 336         /* check for errors on leaf clocks */
 337         for (n = 0; n < MAX_CLKS; n++) {
 338                 if (!IS_ERR(hws[n]))
 339                         continue;
 340
 341                 pr_err("%s: Unable to register leaf clock %d\n",
 342                                 np->full_name, n);
 343                 goto fail;
 344         }
 345
 346         /* register clk-provider */
 347         of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
 348         return;
 349 fail:
 350         iounmap(base);
 351 }
 352 CLK_OF_DECLARE(asm9260_acc, "alphascale,asm9260-clock-controller",
 353                 asm9260_acc_init);