drivers/clk/qcom/clk-pll.h

   1 /*
   2  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #ifndef __QCOM_CLK_PLL_H__
  15 #define __QCOM_CLK_PLL_H__
  16
  17 #include <linux/clk-provider.h>
  18 #include "clk-regmap.h"
  19
  20 /**
  21  * struct pll_freq_tbl - PLL frequency table
  22  * @l: L value
  23  * @m: M value
  24  * @n: N value
  25  * @ibits: internal values
  26  */
  27 struct pll_freq_tbl {
  28         unsigned long freq;
  29         u16 l;
  30         u16 m;
  31         u16 n;
  32         u32 ibits;
  33 };
  34
  35 /**
  36  * struct clk_pll - phase locked loop (PLL)
  37  * @l_reg: L register
  38  * @m_reg: M register
  39  * @n_reg: N register
  40  * @config_reg: config register
  41  * @mode_reg: mode register
  42  * @status_reg: status register
  43  * @status_bit: ANDed with @status_reg to determine if PLL is enabled
  44  * @freq_tbl: PLL frequency table
  45  * @hw: handle between common and hardware-specific interfaces
  46  */
  47 struct clk_pll {
  48         u32     l_reg;
  49         u32     m_reg;
  50         u32     n_reg;
  51         u32     config_reg;
  52         u32     mode_reg;
  53         u32     status_reg;
  54         u8      status_bit;
  55         u8      post_div_width;
  56         u8      post_div_shift;
  57
  58         const struct pll_freq_tbl *freq_tbl;
  59
  60         struct clk_regmap clkr;
  61 };
  62
  63 extern const struct clk_ops clk_pll_ops;
  64 extern const struct clk_ops clk_pll_vote_ops;
  65 extern const struct clk_ops clk_pll_sr2_ops;
  66
  67 #define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr)
  68
  69 struct pll_config {
  70         u16 l;
  71         u32 m;
  72         u32 n;
  73         u32 vco_val;
  74         u32 vco_mask;
  75         u32 pre_div_val;
  76         u32 pre_div_mask;
  77         u32 post_div_val;
  78         u32 post_div_mask;
  79         u32 mn_ena_mask;
  80         u32 main_output_mask;
  81         u32 aux_output_mask;
  82 };
  83
  84 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
  85                 const struct pll_config *config, bool fsm_mode);
  86 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
  87                 const struct pll_config *config, bool fsm_mode);
  88
  89 #endif