2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/bug.h>
18 #include <linux/export.h>
19 #include <linux/clk-provider.h>
20 #include <linux/delay.h>
21 #include <linux/regmap.h>
22 #include <linux/math64.h>
24 #include <asm/div64.h>
30 #define CMD_UPDATE BIT(0)
31 #define CMD_ROOT_EN BIT(1)
32 #define CMD_DIRTY_CFG BIT(4)
33 #define CMD_DIRTY_N BIT(5)
34 #define CMD_DIRTY_M BIT(6)
35 #define CMD_DIRTY_D BIT(7)
36 #define CMD_ROOT_OFF BIT(31)
39 #define CFG_SRC_DIV_SHIFT 0
40 #define CFG_SRC_SEL_SHIFT 8
41 #define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
42 #define CFG_MODE_SHIFT 12
43 #define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
44 #define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
50 static int clk_rcg2_is_enabled(struct clk_hw
*hw
)
52 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
56 ret
= regmap_read(rcg
->clkr
.regmap
, rcg
->cmd_rcgr
+ CMD_REG
, &cmd
);
60 return (cmd
& CMD_ROOT_OFF
) == 0;
63 static u8
clk_rcg2_get_parent(struct clk_hw
*hw
)
65 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
66 int num_parents
= clk_hw_get_num_parents(hw
);
70 ret
= regmap_read(rcg
->clkr
.regmap
, rcg
->cmd_rcgr
+ CFG_REG
, &cfg
);
74 cfg
&= CFG_SRC_SEL_MASK
;
75 cfg
>>= CFG_SRC_SEL_SHIFT
;
77 for (i
= 0; i
< num_parents
; i
++)
78 if (cfg
== rcg
->parent_map
[i
].cfg
)
82 pr_debug("%s: Clock %s has invalid parent, using default.\n",
83 __func__
, clk_hw_get_name(hw
));
87 static int update_config(struct clk_rcg2
*rcg
)
91 struct clk_hw
*hw
= &rcg
->clkr
.hw
;
92 const char *name
= clk_hw_get_name(hw
);
94 ret
= regmap_update_bits(rcg
->clkr
.regmap
, rcg
->cmd_rcgr
+ CMD_REG
,
95 CMD_UPDATE
, CMD_UPDATE
);
99 /* Wait for update to take effect */
100 for (count
= 500; count
> 0; count
--) {
101 ret
= regmap_read(rcg
->clkr
.regmap
, rcg
->cmd_rcgr
+ CMD_REG
, &cmd
);
104 if (!(cmd
& CMD_UPDATE
))
109 WARN(1, "%s: rcg didn't update its configuration.", name
);
113 static int clk_rcg2_set_parent(struct clk_hw
*hw
, u8 index
)
115 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
117 u32 cfg
= rcg
->parent_map
[index
].cfg
<< CFG_SRC_SEL_SHIFT
;
119 ret
= regmap_update_bits(rcg
->clkr
.regmap
, rcg
->cmd_rcgr
+ CFG_REG
,
120 CFG_SRC_SEL_MASK
, cfg
);
124 return update_config(rcg
);
128 * Calculate m/n:d rate
131 * rate = ----------- x ---
135 calc_rate(unsigned long rate
, u32 m
, u32 n
, u32 mode
, u32 hid_div
)
153 clk_rcg2_recalc_rate(struct clk_hw
*hw
, unsigned long parent_rate
)
155 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
156 u32 cfg
, hid_div
, m
= 0, n
= 0, mode
= 0, mask
;
158 regmap_read(rcg
->clkr
.regmap
, rcg
->cmd_rcgr
+ CFG_REG
, &cfg
);
160 if (rcg
->mnd_width
) {
161 mask
= BIT(rcg
->mnd_width
) - 1;
162 regmap_read(rcg
->clkr
.regmap
, rcg
->cmd_rcgr
+ M_REG
, &m
);
164 regmap_read(rcg
->clkr
.regmap
, rcg
->cmd_rcgr
+ N_REG
, &n
);
168 mode
= cfg
& CFG_MODE_MASK
;
169 mode
>>= CFG_MODE_SHIFT
;
172 mask
= BIT(rcg
->hid_width
) - 1;
173 hid_div
= cfg
>> CFG_SRC_DIV_SHIFT
;
176 return calc_rate(parent_rate
, m
, n
, mode
, hid_div
);
179 static int _freq_tbl_determine_rate(struct clk_hw
*hw
,
180 const struct freq_tbl
*f
, struct clk_rate_request
*req
)
182 unsigned long clk_flags
, rate
= req
->rate
;
184 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
187 f
= qcom_find_freq(f
, rate
);
191 index
= qcom_find_src_index(hw
, rcg
->parent_map
, f
->src
);
195 clk_flags
= clk_hw_get_flags(hw
);
196 p
= clk_hw_get_parent_by_index(hw
, index
);
197 if (clk_flags
& CLK_SET_RATE_PARENT
) {
200 rate
*= f
->pre_div
+ 1;
210 rate
= clk_hw_get_rate(p
);
212 req
->best_parent_hw
= p
;
213 req
->best_parent_rate
= rate
;
219 static int clk_rcg2_determine_rate(struct clk_hw
*hw
,
220 struct clk_rate_request
*req
)
222 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
224 return _freq_tbl_determine_rate(hw
, rcg
->freq_tbl
, req
);
227 static int clk_rcg2_configure(struct clk_rcg2
*rcg
, const struct freq_tbl
*f
)
230 struct clk_hw
*hw
= &rcg
->clkr
.hw
;
231 int ret
, index
= qcom_find_src_index(hw
, rcg
->parent_map
, f
->src
);
236 if (rcg
->mnd_width
&& f
->n
) {
237 mask
= BIT(rcg
->mnd_width
) - 1;
238 ret
= regmap_update_bits(rcg
->clkr
.regmap
,
239 rcg
->cmd_rcgr
+ M_REG
, mask
, f
->m
);
243 ret
= regmap_update_bits(rcg
->clkr
.regmap
,
244 rcg
->cmd_rcgr
+ N_REG
, mask
, ~(f
->n
- f
->m
));
248 ret
= regmap_update_bits(rcg
->clkr
.regmap
,
249 rcg
->cmd_rcgr
+ D_REG
, mask
, ~f
->n
);
254 mask
= BIT(rcg
->hid_width
) - 1;
255 mask
|= CFG_SRC_SEL_MASK
| CFG_MODE_MASK
;
256 cfg
= f
->pre_div
<< CFG_SRC_DIV_SHIFT
;
257 cfg
|= rcg
->parent_map
[index
].cfg
<< CFG_SRC_SEL_SHIFT
;
258 if (rcg
->mnd_width
&& f
->n
&& (f
->m
!= f
->n
))
259 cfg
|= CFG_MODE_DUAL_EDGE
;
260 ret
= regmap_update_bits(rcg
->clkr
.regmap
,
261 rcg
->cmd_rcgr
+ CFG_REG
, mask
, cfg
);
265 return update_config(rcg
);
268 static int __clk_rcg2_set_rate(struct clk_hw
*hw
, unsigned long rate
)
270 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
271 const struct freq_tbl
*f
;
273 f
= qcom_find_freq(rcg
->freq_tbl
, rate
);
277 return clk_rcg2_configure(rcg
, f
);
280 static int clk_rcg2_set_rate(struct clk_hw
*hw
, unsigned long rate
,
281 unsigned long parent_rate
)
283 return __clk_rcg2_set_rate(hw
, rate
);
286 static int clk_rcg2_set_rate_and_parent(struct clk_hw
*hw
,
287 unsigned long rate
, unsigned long parent_rate
, u8 index
)
289 return __clk_rcg2_set_rate(hw
, rate
);
292 const struct clk_ops clk_rcg2_ops
= {
293 .is_enabled
= clk_rcg2_is_enabled
,
294 .get_parent
= clk_rcg2_get_parent
,
295 .set_parent
= clk_rcg2_set_parent
,
296 .recalc_rate
= clk_rcg2_recalc_rate
,
297 .determine_rate
= clk_rcg2_determine_rate
,
298 .set_rate
= clk_rcg2_set_rate
,
299 .set_rate_and_parent
= clk_rcg2_set_rate_and_parent
,
301 EXPORT_SYMBOL_GPL(clk_rcg2_ops
);
303 static int clk_rcg2_shared_force_enable(struct clk_hw
*hw
, unsigned long rate
)
305 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
306 const char *name
= clk_hw_get_name(hw
);
309 /* force enable RCG */
310 ret
= regmap_update_bits(rcg
->clkr
.regmap
, rcg
->cmd_rcgr
+ CMD_REG
,
311 CMD_ROOT_EN
, CMD_ROOT_EN
);
315 /* wait for RCG to turn ON */
316 for (count
= 500; count
> 0; count
--) {
317 ret
= clk_rcg2_is_enabled(hw
);
323 pr_err("%s: RCG did not turn on\n", name
);
326 ret
= __clk_rcg2_set_rate(hw
, rate
);
330 /* clear force enable RCG */
331 return regmap_update_bits(rcg
->clkr
.regmap
, rcg
->cmd_rcgr
+ CMD_REG
,
335 static int clk_rcg2_shared_set_rate(struct clk_hw
*hw
, unsigned long rate
,
336 unsigned long parent_rate
)
338 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
341 rcg
->current_freq
= rate
;
343 if (!__clk_is_enabled(hw
->clk
))
346 return clk_rcg2_shared_force_enable(hw
, rcg
->current_freq
);
350 clk_rcg2_shared_recalc_rate(struct clk_hw
*hw
, unsigned long parent_rate
)
352 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
354 return rcg
->current_freq
= clk_rcg2_recalc_rate(hw
, parent_rate
);
357 static int clk_rcg2_shared_enable(struct clk_hw
*hw
)
359 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
361 return clk_rcg2_shared_force_enable(hw
, rcg
->current_freq
);
364 static void clk_rcg2_shared_disable(struct clk_hw
*hw
)
366 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
368 /* switch to XO, which is the lowest entry in the freq table */
369 clk_rcg2_shared_set_rate(hw
, rcg
->freq_tbl
[0].freq
, 0);
372 const struct clk_ops clk_rcg2_shared_ops
= {
373 .enable
= clk_rcg2_shared_enable
,
374 .disable
= clk_rcg2_shared_disable
,
375 .get_parent
= clk_rcg2_get_parent
,
376 .recalc_rate
= clk_rcg2_shared_recalc_rate
,
377 .determine_rate
= clk_rcg2_determine_rate
,
378 .set_rate
= clk_rcg2_shared_set_rate
,
380 EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops
);
387 static const struct frac_entry frac_table_675m
[] = { /* link rate of 270M */
388 { 52, 295 }, /* 119 M */
389 { 11, 57 }, /* 130.25 M */
390 { 63, 307 }, /* 138.50 M */
391 { 11, 50 }, /* 148.50 M */
392 { 47, 206 }, /* 154 M */
393 { 31, 100 }, /* 205.25 M */
394 { 107, 269 }, /* 268.50 M */
398 static struct frac_entry frac_table_810m
[] = { /* Link rate of 162M */
399 { 31, 211 }, /* 119 M */
400 { 32, 199 }, /* 130.25 M */
401 { 63, 307 }, /* 138.50 M */
402 { 11, 60 }, /* 148.50 M */
403 { 50, 263 }, /* 154 M */
404 { 31, 120 }, /* 205.25 M */
405 { 119, 359 }, /* 268.50 M */
409 static int clk_edp_pixel_set_rate(struct clk_hw
*hw
, unsigned long rate
,
410 unsigned long parent_rate
)
412 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
413 struct freq_tbl f
= *rcg
->freq_tbl
;
414 const struct frac_entry
*frac
;
416 s64 src_rate
= parent_rate
;
418 u32 mask
= BIT(rcg
->hid_width
) - 1;
421 if (src_rate
== 810000000)
422 frac
= frac_table_810m
;
424 frac
= frac_table_675m
;
426 for (; frac
->num
; frac
++) {
428 request
*= frac
->den
;
429 request
= div_s64(request
, frac
->num
);
430 if ((src_rate
< (request
- delta
)) ||
431 (src_rate
> (request
+ delta
)))
434 regmap_read(rcg
->clkr
.regmap
, rcg
->cmd_rcgr
+ CFG_REG
,
437 f
.pre_div
>>= CFG_SRC_DIV_SHIFT
;
442 return clk_rcg2_configure(rcg
, &f
);
448 static int clk_edp_pixel_set_rate_and_parent(struct clk_hw
*hw
,
449 unsigned long rate
, unsigned long parent_rate
, u8 index
)
451 /* Parent index is set statically in frequency table */
452 return clk_edp_pixel_set_rate(hw
, rate
, parent_rate
);
455 static int clk_edp_pixel_determine_rate(struct clk_hw
*hw
,
456 struct clk_rate_request
*req
)
458 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
459 const struct freq_tbl
*f
= rcg
->freq_tbl
;
460 const struct frac_entry
*frac
;
463 u32 mask
= BIT(rcg
->hid_width
) - 1;
465 int index
= qcom_find_src_index(hw
, rcg
->parent_map
, f
->src
);
467 /* Force the correct parent */
468 req
->best_parent_hw
= clk_hw_get_parent_by_index(hw
, index
);
469 req
->best_parent_rate
= clk_hw_get_rate(req
->best_parent_hw
);
471 if (req
->best_parent_rate
== 810000000)
472 frac
= frac_table_810m
;
474 frac
= frac_table_675m
;
476 for (; frac
->num
; frac
++) {
478 request
*= frac
->den
;
479 request
= div_s64(request
, frac
->num
);
480 if ((req
->best_parent_rate
< (request
- delta
)) ||
481 (req
->best_parent_rate
> (request
+ delta
)))
484 regmap_read(rcg
->clkr
.regmap
, rcg
->cmd_rcgr
+ CFG_REG
,
486 hid_div
>>= CFG_SRC_DIV_SHIFT
;
489 req
->rate
= calc_rate(req
->best_parent_rate
,
490 frac
->num
, frac
->den
,
491 !!frac
->den
, hid_div
);
498 const struct clk_ops clk_edp_pixel_ops
= {
499 .is_enabled
= clk_rcg2_is_enabled
,
500 .get_parent
= clk_rcg2_get_parent
,
501 .set_parent
= clk_rcg2_set_parent
,
502 .recalc_rate
= clk_rcg2_recalc_rate
,
503 .set_rate
= clk_edp_pixel_set_rate
,
504 .set_rate_and_parent
= clk_edp_pixel_set_rate_and_parent
,
505 .determine_rate
= clk_edp_pixel_determine_rate
,
507 EXPORT_SYMBOL_GPL(clk_edp_pixel_ops
);
509 static int clk_byte_determine_rate(struct clk_hw
*hw
,
510 struct clk_rate_request
*req
)
512 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
513 const struct freq_tbl
*f
= rcg
->freq_tbl
;
514 int index
= qcom_find_src_index(hw
, rcg
->parent_map
, f
->src
);
515 unsigned long parent_rate
, div
;
516 u32 mask
= BIT(rcg
->hid_width
) - 1;
522 req
->best_parent_hw
= p
= clk_hw_get_parent_by_index(hw
, index
);
523 req
->best_parent_rate
= parent_rate
= clk_hw_round_rate(p
, req
->rate
);
525 div
= DIV_ROUND_UP((2 * parent_rate
), req
->rate
) - 1;
526 div
= min_t(u32
, div
, mask
);
528 req
->rate
= calc_rate(parent_rate
, 0, 0, 0, div
);
533 static int clk_byte_set_rate(struct clk_hw
*hw
, unsigned long rate
,
534 unsigned long parent_rate
)
536 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
537 struct freq_tbl f
= *rcg
->freq_tbl
;
539 u32 mask
= BIT(rcg
->hid_width
) - 1;
541 div
= DIV_ROUND_UP((2 * parent_rate
), rate
) - 1;
542 div
= min_t(u32
, div
, mask
);
546 return clk_rcg2_configure(rcg
, &f
);
549 static int clk_byte_set_rate_and_parent(struct clk_hw
*hw
,
550 unsigned long rate
, unsigned long parent_rate
, u8 index
)
552 /* Parent index is set statically in frequency table */
553 return clk_byte_set_rate(hw
, rate
, parent_rate
);
556 const struct clk_ops clk_byte_ops
= {
557 .is_enabled
= clk_rcg2_is_enabled
,
558 .get_parent
= clk_rcg2_get_parent
,
559 .set_parent
= clk_rcg2_set_parent
,
560 .recalc_rate
= clk_rcg2_recalc_rate
,
561 .set_rate
= clk_byte_set_rate
,
562 .set_rate_and_parent
= clk_byte_set_rate_and_parent
,
563 .determine_rate
= clk_byte_determine_rate
,
565 EXPORT_SYMBOL_GPL(clk_byte_ops
);
567 static int clk_byte2_determine_rate(struct clk_hw
*hw
,
568 struct clk_rate_request
*req
)
570 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
571 unsigned long parent_rate
, div
;
572 u32 mask
= BIT(rcg
->hid_width
) - 1;
574 unsigned long rate
= req
->rate
;
579 p
= req
->best_parent_hw
;
580 req
->best_parent_rate
= parent_rate
= clk_hw_round_rate(p
, rate
);
582 div
= DIV_ROUND_UP((2 * parent_rate
), rate
) - 1;
583 div
= min_t(u32
, div
, mask
);
585 req
->rate
= calc_rate(parent_rate
, 0, 0, 0, div
);
590 static int clk_byte2_set_rate(struct clk_hw
*hw
, unsigned long rate
,
591 unsigned long parent_rate
)
593 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
594 struct freq_tbl f
= { 0 };
596 int i
, num_parents
= clk_hw_get_num_parents(hw
);
597 u32 mask
= BIT(rcg
->hid_width
) - 1;
600 div
= DIV_ROUND_UP((2 * parent_rate
), rate
) - 1;
601 div
= min_t(u32
, div
, mask
);
605 regmap_read(rcg
->clkr
.regmap
, rcg
->cmd_rcgr
+ CFG_REG
, &cfg
);
606 cfg
&= CFG_SRC_SEL_MASK
;
607 cfg
>>= CFG_SRC_SEL_SHIFT
;
609 for (i
= 0; i
< num_parents
; i
++) {
610 if (cfg
== rcg
->parent_map
[i
].cfg
) {
611 f
.src
= rcg
->parent_map
[i
].src
;
612 return clk_rcg2_configure(rcg
, &f
);
619 static int clk_byte2_set_rate_and_parent(struct clk_hw
*hw
,
620 unsigned long rate
, unsigned long parent_rate
, u8 index
)
622 /* Read the hardware to determine parent during set_rate */
623 return clk_byte2_set_rate(hw
, rate
, parent_rate
);
626 const struct clk_ops clk_byte2_ops
= {
627 .is_enabled
= clk_rcg2_is_enabled
,
628 .get_parent
= clk_rcg2_get_parent
,
629 .set_parent
= clk_rcg2_set_parent
,
630 .recalc_rate
= clk_rcg2_recalc_rate
,
631 .set_rate
= clk_byte2_set_rate
,
632 .set_rate_and_parent
= clk_byte2_set_rate_and_parent
,
633 .determine_rate
= clk_byte2_determine_rate
,
635 EXPORT_SYMBOL_GPL(clk_byte2_ops
);
637 static const struct frac_entry frac_table_pixel
[] = {
645 static int clk_pixel_determine_rate(struct clk_hw
*hw
,
646 struct clk_rate_request
*req
)
648 unsigned long request
, src_rate
;
650 const struct frac_entry
*frac
= frac_table_pixel
;
652 for (; frac
->num
; frac
++) {
653 request
= (req
->rate
* frac
->den
) / frac
->num
;
655 src_rate
= clk_hw_round_rate(req
->best_parent_hw
, request
);
656 if ((src_rate
< (request
- delta
)) ||
657 (src_rate
> (request
+ delta
)))
660 req
->best_parent_rate
= src_rate
;
661 req
->rate
= (src_rate
* frac
->num
) / frac
->den
;
668 static int clk_pixel_set_rate(struct clk_hw
*hw
, unsigned long rate
,
669 unsigned long parent_rate
)
671 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
672 struct freq_tbl f
= { 0 };
673 const struct frac_entry
*frac
= frac_table_pixel
;
674 unsigned long request
;
676 u32 mask
= BIT(rcg
->hid_width
) - 1;
678 int i
, num_parents
= clk_hw_get_num_parents(hw
);
680 regmap_read(rcg
->clkr
.regmap
, rcg
->cmd_rcgr
+ CFG_REG
, &cfg
);
681 cfg
&= CFG_SRC_SEL_MASK
;
682 cfg
>>= CFG_SRC_SEL_SHIFT
;
684 for (i
= 0; i
< num_parents
; i
++)
685 if (cfg
== rcg
->parent_map
[i
].cfg
) {
686 f
.src
= rcg
->parent_map
[i
].src
;
690 for (; frac
->num
; frac
++) {
691 request
= (rate
* frac
->den
) / frac
->num
;
693 if ((parent_rate
< (request
- delta
)) ||
694 (parent_rate
> (request
+ delta
)))
697 regmap_read(rcg
->clkr
.regmap
, rcg
->cmd_rcgr
+ CFG_REG
,
700 f
.pre_div
>>= CFG_SRC_DIV_SHIFT
;
705 return clk_rcg2_configure(rcg
, &f
);
710 static int clk_pixel_set_rate_and_parent(struct clk_hw
*hw
, unsigned long rate
,
711 unsigned long parent_rate
, u8 index
)
713 return clk_pixel_set_rate(hw
, rate
, parent_rate
);
716 const struct clk_ops clk_pixel_ops
= {
717 .is_enabled
= clk_rcg2_is_enabled
,
718 .get_parent
= clk_rcg2_get_parent
,
719 .set_parent
= clk_rcg2_set_parent
,
720 .recalc_rate
= clk_rcg2_recalc_rate
,
721 .set_rate
= clk_pixel_set_rate
,
722 .set_rate_and_parent
= clk_pixel_set_rate_and_parent
,
723 .determine_rate
= clk_pixel_determine_rate
,
725 EXPORT_SYMBOL_GPL(clk_pixel_ops
);
727 static int clk_gfx3d_determine_rate(struct clk_hw
*hw
,
728 struct clk_rate_request
*req
)
730 struct clk_rate_request parent_req
= { };
731 struct clk_hw
*p2
, *p8
, *p9
, *xo
;
732 unsigned long p9_rate
;
735 xo
= clk_hw_get_parent_by_index(hw
, 0);
736 if (req
->rate
== clk_hw_get_rate(xo
)) {
737 req
->best_parent_hw
= xo
;
741 p9
= clk_hw_get_parent_by_index(hw
, 2);
742 p2
= clk_hw_get_parent_by_index(hw
, 3);
743 p8
= clk_hw_get_parent_by_index(hw
, 4);
745 /* PLL9 is a fixed rate PLL */
746 p9_rate
= clk_hw_get_rate(p9
);
748 parent_req
.rate
= req
->rate
= min(req
->rate
, p9_rate
);
749 if (req
->rate
== p9_rate
) {
750 req
->rate
= req
->best_parent_rate
= p9_rate
;
751 req
->best_parent_hw
= p9
;
755 if (req
->best_parent_hw
== p9
) {
756 /* Are we going back to a previously used rate? */
757 if (clk_hw_get_rate(p8
) == req
->rate
)
758 req
->best_parent_hw
= p8
;
760 req
->best_parent_hw
= p2
;
761 } else if (req
->best_parent_hw
== p8
) {
762 req
->best_parent_hw
= p2
;
764 req
->best_parent_hw
= p8
;
767 ret
= __clk_determine_rate(req
->best_parent_hw
, &parent_req
);
771 req
->rate
= req
->best_parent_rate
= parent_req
.rate
;
776 static int clk_gfx3d_set_rate_and_parent(struct clk_hw
*hw
, unsigned long rate
,
777 unsigned long parent_rate
, u8 index
)
779 struct clk_rcg2
*rcg
= to_clk_rcg2(hw
);
783 /* Just mux it, we don't use the division or m/n hardware */
784 cfg
= rcg
->parent_map
[index
].cfg
<< CFG_SRC_SEL_SHIFT
;
785 ret
= regmap_write(rcg
->clkr
.regmap
, rcg
->cmd_rcgr
+ CFG_REG
, cfg
);
789 return update_config(rcg
);
792 static int clk_gfx3d_set_rate(struct clk_hw
*hw
, unsigned long rate
,
793 unsigned long parent_rate
)
796 * We should never get here; clk_gfx3d_determine_rate() should always
797 * make us use a different parent than what we're currently using, so
798 * clk_gfx3d_set_rate_and_parent() should always be called.
803 const struct clk_ops clk_gfx3d_ops
= {
804 .is_enabled
= clk_rcg2_is_enabled
,
805 .get_parent
= clk_rcg2_get_parent
,
806 .set_parent
= clk_rcg2_set_parent
,
807 .recalc_rate
= clk_rcg2_recalc_rate
,
808 .set_rate
= clk_gfx3d_set_rate
,
809 .set_rate_and_parent
= clk_gfx3d_set_rate_and_parent
,
810 .determine_rate
= clk_gfx3d_determine_rate
,
812 EXPORT_SYMBOL_GPL(clk_gfx3d_ops
);