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inet: frag: enforce memory limits earlier
[linux/fpc-iii.git] / drivers / crypto / marvell / hash.c
blob662cf4ddb04b8a71a9e98a06990887cfc44b43e9
1 /*
2 * Hash algorithms supported by the CESA: MD5, SHA1 and SHA256.
3 *
4 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
5 * Author: Arnaud Ebalard <arno@natisbad.org>
6 *
7 * This work is based on an initial version written by
8 * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 */
14
15 #include <crypto/md5.h>
16 #include <crypto/sha.h>
17
18 #include "cesa.h"
19
20 struct mv_cesa_ahash_dma_iter {
21 struct mv_cesa_dma_iter base;
22 struct mv_cesa_sg_dma_iter src;
23 };
24
25 static inline void
26 mv_cesa_ahash_req_iter_init(struct mv_cesa_ahash_dma_iter *iter,
27 struct ahash_request *req)
28 {
29 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
30 unsigned int len = req->nbytes + creq->cache_ptr;
31
32 if (!creq->last_req)
33 len &= ~CESA_HASH_BLOCK_SIZE_MSK;
34
35 mv_cesa_req_dma_iter_init(&iter->base, len);
36 mv_cesa_sg_dma_iter_init(&iter->src, req->src, DMA_TO_DEVICE);
37 iter->src.op_offset = creq->cache_ptr;
38 }
39
40 static inline bool
41 mv_cesa_ahash_req_iter_next_op(struct mv_cesa_ahash_dma_iter *iter)
42 {
43 iter->src.op_offset = 0;
44
45 return mv_cesa_req_dma_iter_next_op(&iter->base);
46 }
47
48 static inline int
49 mv_cesa_ahash_dma_alloc_cache(struct mv_cesa_ahash_dma_req *req, gfp_t flags)
50 {
51 req->cache = dma_pool_alloc(cesa_dev->dma->cache_pool, flags,
52 &req->cache_dma);
53 if (!req->cache)
54 return -ENOMEM;
55
56 return 0;
57 }
58
59 static inline void
60 mv_cesa_ahash_dma_free_cache(struct mv_cesa_ahash_dma_req *req)
61 {
62 if (!req->cache)
63 return;
64
65 dma_pool_free(cesa_dev->dma->cache_pool, req->cache,
66 req->cache_dma);
67 }
68
69 static int mv_cesa_ahash_dma_alloc_padding(struct mv_cesa_ahash_dma_req *req,
70 gfp_t flags)
71 {
72 if (req->padding)
73 return 0;
74
75 req->padding = dma_pool_alloc(cesa_dev->dma->padding_pool, flags,
76 &req->padding_dma);
77 if (!req->padding)
78 return -ENOMEM;
79
80 return 0;
81 }
82
83 static void mv_cesa_ahash_dma_free_padding(struct mv_cesa_ahash_dma_req *req)
84 {
85 if (!req->padding)
86 return;
87
88 dma_pool_free(cesa_dev->dma->padding_pool, req->padding,
89 req->padding_dma);
90 req->padding = NULL;
91 }
92
93 static inline void mv_cesa_ahash_dma_last_cleanup(struct ahash_request *req)
94 {
95 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
96
97 mv_cesa_ahash_dma_free_padding(&creq->req.dma);
98 }
99
100 static inline void mv_cesa_ahash_dma_cleanup(struct ahash_request *req)
101 {
102 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
103
104 dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
105 mv_cesa_ahash_dma_free_cache(&creq->req.dma);
106 mv_cesa_dma_cleanup(&creq->base);
107 }
108
109 static inline void mv_cesa_ahash_cleanup(struct ahash_request *req)
110 {
111 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
112
113 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
114 mv_cesa_ahash_dma_cleanup(req);
115 }
116
117 static void mv_cesa_ahash_last_cleanup(struct ahash_request *req)
118 {
119 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
120
121 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
122 mv_cesa_ahash_dma_last_cleanup(req);
123 }
124
125 static int mv_cesa_ahash_pad_len(struct mv_cesa_ahash_req *creq)
126 {
127 unsigned int index, padlen;
128
129 index = creq->len & CESA_HASH_BLOCK_SIZE_MSK;
130 padlen = (index < 56) ? (56 - index) : (64 + 56 - index);
131
132 return padlen;
133 }
134
135 static int mv_cesa_ahash_pad_req(struct mv_cesa_ahash_req *creq, u8 *buf)
136 {
137 unsigned int index, padlen;
138
139 buf[0] = 0x80;
140 /* Pad out to 56 mod 64 */
141 index = creq->len & CESA_HASH_BLOCK_SIZE_MSK;
142 padlen = mv_cesa_ahash_pad_len(creq);
143 memset(buf + 1, 0, padlen - 1);
144
145 if (creq->algo_le) {
146 __le64 bits = cpu_to_le64(creq->len << 3);
147 memcpy(buf + padlen, &bits, sizeof(bits));
148 } else {
149 __be64 bits = cpu_to_be64(creq->len << 3);
150 memcpy(buf + padlen, &bits, sizeof(bits));
151 }
152
153 return padlen + 8;
154 }
155
156 static void mv_cesa_ahash_std_step(struct ahash_request *req)
157 {
158 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
159 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
160 struct mv_cesa_engine *engine = creq->base.engine;
161 struct mv_cesa_op_ctx *op;
162 unsigned int new_cache_ptr = 0;
163 u32 frag_mode;
164 size_t len;
165 unsigned int digsize;
166 int i;
167
168 mv_cesa_adjust_op(engine, &creq->op_tmpl);
169 memcpy_toio(engine->sram, &creq->op_tmpl, sizeof(creq->op_tmpl));
170
171 if (!sreq->offset) {
172 digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(req));
173 for (i = 0; i < digsize / 4; i++)
174 writel_relaxed(creq->state[i], engine->regs + CESA_IVDIG(i));
175 }
176
177 if (creq->cache_ptr)
178 memcpy_toio(engine->sram + CESA_SA_DATA_SRAM_OFFSET,
179 creq->cache, creq->cache_ptr);
180
181 len = min_t(size_t, req->nbytes + creq->cache_ptr - sreq->offset,
182 CESA_SA_SRAM_PAYLOAD_SIZE);
183
184 if (!creq->last_req) {
185 new_cache_ptr = len & CESA_HASH_BLOCK_SIZE_MSK;
186 len &= ~CESA_HASH_BLOCK_SIZE_MSK;
187 }
188
189 if (len - creq->cache_ptr)
190 sreq->offset += sg_pcopy_to_buffer(req->src, creq->src_nents,
191 engine->sram +
192 CESA_SA_DATA_SRAM_OFFSET +
193 creq->cache_ptr,
194 len - creq->cache_ptr,
195 sreq->offset);
196
197 op = &creq->op_tmpl;
198
199 frag_mode = mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK;
200
201 if (creq->last_req && sreq->offset == req->nbytes &&
202 creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
203 if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
204 frag_mode = CESA_SA_DESC_CFG_NOT_FRAG;
205 else if (frag_mode == CESA_SA_DESC_CFG_MID_FRAG)
206 frag_mode = CESA_SA_DESC_CFG_LAST_FRAG;
207 }
208
209 if (frag_mode == CESA_SA_DESC_CFG_NOT_FRAG ||
210 frag_mode == CESA_SA_DESC_CFG_LAST_FRAG) {
211 if (len &&
212 creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
213 mv_cesa_set_mac_op_total_len(op, creq->len);
214 } else {
215 int trailerlen = mv_cesa_ahash_pad_len(creq) + 8;
216
217 if (len + trailerlen > CESA_SA_SRAM_PAYLOAD_SIZE) {
218 len &= CESA_HASH_BLOCK_SIZE_MSK;
219 new_cache_ptr = 64 - trailerlen;
220 memcpy_fromio(creq->cache,
221 engine->sram +
222 CESA_SA_DATA_SRAM_OFFSET + len,
223 new_cache_ptr);
224 } else {
225 len += mv_cesa_ahash_pad_req(creq,
226 engine->sram + len +
227 CESA_SA_DATA_SRAM_OFFSET);
228 }
229
230 if (frag_mode == CESA_SA_DESC_CFG_LAST_FRAG)
231 frag_mode = CESA_SA_DESC_CFG_MID_FRAG;
232 else
233 frag_mode = CESA_SA_DESC_CFG_FIRST_FRAG;
234 }
235 }
236
237 mv_cesa_set_mac_op_frag_len(op, len);
238 mv_cesa_update_op_cfg(op, frag_mode, CESA_SA_DESC_CFG_FRAG_MSK);
239
240 /* FIXME: only update enc_len field */
241 memcpy_toio(engine->sram, op, sizeof(*op));
242
243 if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
244 mv_cesa_update_op_cfg(op, CESA_SA_DESC_CFG_MID_FRAG,
245 CESA_SA_DESC_CFG_FRAG_MSK);
246
247 creq->cache_ptr = new_cache_ptr;
248
249 mv_cesa_set_int_mask(engine, CESA_SA_INT_ACCEL0_DONE);
250 writel_relaxed(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG);
251 BUG_ON(readl(engine->regs + CESA_SA_CMD) &
252 CESA_SA_CMD_EN_CESA_SA_ACCL0);
253 writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
254 }
255
256 static int mv_cesa_ahash_std_process(struct ahash_request *req, u32 status)
257 {
258 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
259 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
260
261 if (sreq->offset < (req->nbytes - creq->cache_ptr))
262 return -EINPROGRESS;
263
264 return 0;
265 }
266
267 static inline void mv_cesa_ahash_dma_prepare(struct ahash_request *req)
268 {
269 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
270 struct mv_cesa_req *basereq = &creq->base;
271
272 mv_cesa_dma_prepare(basereq, basereq->engine);
273 }
274
275 static void mv_cesa_ahash_std_prepare(struct ahash_request *req)
276 {
277 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
278 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
279
280 sreq->offset = 0;
281 }
282
283 static void mv_cesa_ahash_dma_step(struct ahash_request *req)
284 {
285 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
286 struct mv_cesa_req *base = &creq->base;
287
288 /* We must explicitly set the digest state. */
289 if (base->chain.first->flags & CESA_TDMA_SET_STATE) {
290 struct mv_cesa_engine *engine = base->engine;
291 int i;
292
293 /* Set the hash state in the IVDIG regs. */
294 for (i = 0; i < ARRAY_SIZE(creq->state); i++)
295 writel_relaxed(creq->state[i], engine->regs +
296 CESA_IVDIG(i));
297 }
298
299 mv_cesa_dma_step(base);
300 }
301
302 static void mv_cesa_ahash_step(struct crypto_async_request *req)
303 {
304 struct ahash_request *ahashreq = ahash_request_cast(req);
305 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
306
307 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
308 mv_cesa_ahash_dma_step(ahashreq);
309 else
310 mv_cesa_ahash_std_step(ahashreq);
311 }
312
313 static int mv_cesa_ahash_process(struct crypto_async_request *req, u32 status)
314 {
315 struct ahash_request *ahashreq = ahash_request_cast(req);
316 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
317
318 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
319 return mv_cesa_dma_process(&creq->base, status);
320
321 return mv_cesa_ahash_std_process(ahashreq, status);
322 }
323
324 static void mv_cesa_ahash_complete(struct crypto_async_request *req)
325 {
326 struct ahash_request *ahashreq = ahash_request_cast(req);
327 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
328 struct mv_cesa_engine *engine = creq->base.engine;
329 unsigned int digsize;
330 int i;
331
332 digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq));
333 for (i = 0; i < digsize / 4; i++)
334 creq->state[i] = readl_relaxed(engine->regs + CESA_IVDIG(i));
335
336 if (creq->last_req) {
337 /*
338 * Hardware's MD5 digest is in little endian format, but
339 * SHA in big endian format
340 */
341 if (creq->algo_le) {
342 __le32 *result = (void *)ahashreq->result;
343
344 for (i = 0; i < digsize / 4; i++)
345 result[i] = cpu_to_le32(creq->state[i]);
346 } else {
347 __be32 *result = (void *)ahashreq->result;
348
349 for (i = 0; i < digsize / 4; i++)
350 result[i] = cpu_to_be32(creq->state[i]);
351 }
352 }
353
354 atomic_sub(ahashreq->nbytes, &engine->load);
355 }
356
357 static void mv_cesa_ahash_prepare(struct crypto_async_request *req,
358 struct mv_cesa_engine *engine)
359 {
360 struct ahash_request *ahashreq = ahash_request_cast(req);
361 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
362
363 creq->base.engine = engine;
364
365 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
366 mv_cesa_ahash_dma_prepare(ahashreq);
367 else
368 mv_cesa_ahash_std_prepare(ahashreq);
369 }
370
371 static void mv_cesa_ahash_req_cleanup(struct crypto_async_request *req)
372 {
373 struct ahash_request *ahashreq = ahash_request_cast(req);
374 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
375
376 if (creq->last_req)
377 mv_cesa_ahash_last_cleanup(ahashreq);
378
379 mv_cesa_ahash_cleanup(ahashreq);
380
381 if (creq->cache_ptr)
382 sg_pcopy_to_buffer(ahashreq->src, creq->src_nents,
383 creq->cache,
384 creq->cache_ptr,
385 ahashreq->nbytes - creq->cache_ptr);
386 }
387
388 static const struct mv_cesa_req_ops mv_cesa_ahash_req_ops = {
389 .step = mv_cesa_ahash_step,
390 .process = mv_cesa_ahash_process,
391 .cleanup = mv_cesa_ahash_req_cleanup,
392 .complete = mv_cesa_ahash_complete,
393 };
394
395 static void mv_cesa_ahash_init(struct ahash_request *req,
396 struct mv_cesa_op_ctx *tmpl, bool algo_le)
397 {
398 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
399
400 memset(creq, 0, sizeof(*creq));
401 mv_cesa_update_op_cfg(tmpl,
402 CESA_SA_DESC_CFG_OP_MAC_ONLY |
403 CESA_SA_DESC_CFG_FIRST_FRAG,
404 CESA_SA_DESC_CFG_OP_MSK |
405 CESA_SA_DESC_CFG_FRAG_MSK);
406 mv_cesa_set_mac_op_total_len(tmpl, 0);
407 mv_cesa_set_mac_op_frag_len(tmpl, 0);
408 creq->op_tmpl = *tmpl;
409 creq->len = 0;
410 creq->algo_le = algo_le;
411 }
412
413 static inline int mv_cesa_ahash_cra_init(struct crypto_tfm *tfm)
414 {
415 struct mv_cesa_hash_ctx *ctx = crypto_tfm_ctx(tfm);
416
417 ctx->base.ops = &mv_cesa_ahash_req_ops;
418
419 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
420 sizeof(struct mv_cesa_ahash_req));
421 return 0;
422 }
423
424 static bool mv_cesa_ahash_cache_req(struct ahash_request *req)
425 {
426 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
427 bool cached = false;
428
429 if (creq->cache_ptr + req->nbytes < CESA_MAX_HASH_BLOCK_SIZE && !creq->last_req) {
430 cached = true;
431
432 if (!req->nbytes)
433 return cached;
434
435 sg_pcopy_to_buffer(req->src, creq->src_nents,
436 creq->cache + creq->cache_ptr,
437 req->nbytes, 0);
438
439 creq->cache_ptr += req->nbytes;
440 }
441
442 return cached;
443 }
444
445 static struct mv_cesa_op_ctx *
446 mv_cesa_dma_add_frag(struct mv_cesa_tdma_chain *chain,
447 struct mv_cesa_op_ctx *tmpl, unsigned int frag_len,
448 gfp_t flags)
449 {
450 struct mv_cesa_op_ctx *op;
451 int ret;
452
453 op = mv_cesa_dma_add_op(chain, tmpl, false, flags);
454 if (IS_ERR(op))
455 return op;
456
457 /* Set the operation block fragment length. */
458 mv_cesa_set_mac_op_frag_len(op, frag_len);
459
460 /* Append dummy desc to launch operation */
461 ret = mv_cesa_dma_add_dummy_launch(chain, flags);
462 if (ret)
463 return ERR_PTR(ret);
464
465 if (mv_cesa_mac_op_is_first_frag(tmpl))
466 mv_cesa_update_op_cfg(tmpl,
467 CESA_SA_DESC_CFG_MID_FRAG,
468 CESA_SA_DESC_CFG_FRAG_MSK);
469
470 return op;
471 }
472
473 static int
474 mv_cesa_ahash_dma_add_cache(struct mv_cesa_tdma_chain *chain,
475 struct mv_cesa_ahash_req *creq,
476 gfp_t flags)
477 {
478 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
479 int ret;
480
481 if (!creq->cache_ptr)
482 return 0;
483
484 ret = mv_cesa_ahash_dma_alloc_cache(ahashdreq, flags);
485 if (ret)
486 return ret;
487
488 memcpy(ahashdreq->cache, creq->cache, creq->cache_ptr);
489
490 return mv_cesa_dma_add_data_transfer(chain,
491 CESA_SA_DATA_SRAM_OFFSET,
492 ahashdreq->cache_dma,
493 creq->cache_ptr,
494 CESA_TDMA_DST_IN_SRAM,
495 flags);
496 }
497
498 static struct mv_cesa_op_ctx *
499 mv_cesa_ahash_dma_last_req(struct mv_cesa_tdma_chain *chain,
500 struct mv_cesa_ahash_dma_iter *dma_iter,
501 struct mv_cesa_ahash_req *creq,
502 unsigned int frag_len, gfp_t flags)
503 {
504 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
505 unsigned int len, trailerlen, padoff = 0;
506 struct mv_cesa_op_ctx *op;
507 int ret;
508
509 /*
510 * If the transfer is smaller than our maximum length, and we have
511 * some data outstanding, we can ask the engine to finish the hash.
512 */
513 if (creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX && frag_len) {
514 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len,
515 flags);
516 if (IS_ERR(op))
517 return op;
518
519 mv_cesa_set_mac_op_total_len(op, creq->len);
520 mv_cesa_update_op_cfg(op, mv_cesa_mac_op_is_first_frag(op) ?
521 CESA_SA_DESC_CFG_NOT_FRAG :
522 CESA_SA_DESC_CFG_LAST_FRAG,
523 CESA_SA_DESC_CFG_FRAG_MSK);
524
525 return op;
526 }
527
528 /*
529 * The request is longer than the engine can handle, or we have
530 * no data outstanding. Manually generate the padding, adding it
531 * as a "mid" fragment.
532 */
533 ret = mv_cesa_ahash_dma_alloc_padding(ahashdreq, flags);
534 if (ret)
535 return ERR_PTR(ret);
536
537 trailerlen = mv_cesa_ahash_pad_req(creq, ahashdreq->padding);
538
539 len = min(CESA_SA_SRAM_PAYLOAD_SIZE - frag_len, trailerlen);
540 if (len) {
541 ret = mv_cesa_dma_add_data_transfer(chain,
542 CESA_SA_DATA_SRAM_OFFSET +
543 frag_len,
544 ahashdreq->padding_dma,
545 len, CESA_TDMA_DST_IN_SRAM,
546 flags);
547 if (ret)
548 return ERR_PTR(ret);
549
550 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len + len,
551 flags);
552 if (IS_ERR(op))
553 return op;
554
555 if (len == trailerlen)
556 return op;
557
558 padoff += len;
559 }
560
561 ret = mv_cesa_dma_add_data_transfer(chain,
562 CESA_SA_DATA_SRAM_OFFSET,
563 ahashdreq->padding_dma +
564 padoff,
565 trailerlen - padoff,
566 CESA_TDMA_DST_IN_SRAM,
567 flags);
568 if (ret)
569 return ERR_PTR(ret);
570
571 return mv_cesa_dma_add_frag(chain, &creq->op_tmpl, trailerlen - padoff,
572 flags);
573 }
574
575 static int mv_cesa_ahash_dma_req_init(struct ahash_request *req)
576 {
577 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
578 gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
579 GFP_KERNEL : GFP_ATOMIC;
580 struct mv_cesa_req *basereq = &creq->base;
581 struct mv_cesa_ahash_dma_iter iter;
582 struct mv_cesa_op_ctx *op = NULL;
583 unsigned int frag_len;
584 bool set_state = false;
585 int ret;
586
587 basereq->chain.first = NULL;
588 basereq->chain.last = NULL;
589
590 if (!mv_cesa_mac_op_is_first_frag(&creq->op_tmpl))
591 set_state = true;
592
593 if (creq->src_nents) {
594 ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents,
595 DMA_TO_DEVICE);
596 if (!ret) {
597 ret = -ENOMEM;
598 goto err;
599 }
600 }
601
602 mv_cesa_tdma_desc_iter_init(&basereq->chain);
603 mv_cesa_ahash_req_iter_init(&iter, req);
604
605 /*
606 * Add the cache (left-over data from a previous block) first.
607 * This will never overflow the SRAM size.
608 */
609 ret = mv_cesa_ahash_dma_add_cache(&basereq->chain, creq, flags);
610 if (ret)
611 goto err_free_tdma;
612
613 if (iter.src.sg) {
614 /*
615 * Add all the new data, inserting an operation block and
616 * launch command between each full SRAM block-worth of
617 * data. We intentionally do not add the final op block.
618 */
619 while (true) {
620 ret = mv_cesa_dma_add_op_transfers(&basereq->chain,
621 &iter.base,
622 &iter.src, flags);
623 if (ret)
624 goto err_free_tdma;
625
626 frag_len = iter.base.op_len;
627
628 if (!mv_cesa_ahash_req_iter_next_op(&iter))
629 break;
630
631 op = mv_cesa_dma_add_frag(&basereq->chain, &creq->op_tmpl,
632 frag_len, flags);
633 if (IS_ERR(op)) {
634 ret = PTR_ERR(op);
635 goto err_free_tdma;
636 }
637 }
638 } else {
639 /* Account for the data that was in the cache. */
640 frag_len = iter.base.op_len;
641 }
642
643 /*
644 * At this point, frag_len indicates whether we have any data
645 * outstanding which needs an operation. Queue up the final
646 * operation, which depends whether this is the final request.
647 */
648 if (creq->last_req)
649 op = mv_cesa_ahash_dma_last_req(&basereq->chain, &iter, creq,
650 frag_len, flags);
651 else if (frag_len)
652 op = mv_cesa_dma_add_frag(&basereq->chain, &creq->op_tmpl,
653 frag_len, flags);
654
655 if (IS_ERR(op)) {
656 ret = PTR_ERR(op);
657 goto err_free_tdma;
658 }
659
660 if (op) {
661 /* Add dummy desc to wait for crypto operation end */
662 ret = mv_cesa_dma_add_dummy_end(&basereq->chain, flags);
663 if (ret)
664 goto err_free_tdma;
665 }
666
667 if (!creq->last_req)
668 creq->cache_ptr = req->nbytes + creq->cache_ptr -
669 iter.base.len;
670 else
671 creq->cache_ptr = 0;
672
673 basereq->chain.last->flags |= (CESA_TDMA_END_OF_REQ |
674 CESA_TDMA_BREAK_CHAIN);
675
676 if (set_state) {
677 /*
678 * Put the CESA_TDMA_SET_STATE flag on the first tdma desc to
679 * let the step logic know that the IVDIG registers should be
680 * explicitly set before launching a TDMA chain.
681 */
682 basereq->chain.first->flags |= CESA_TDMA_SET_STATE;
683 }
684
685 return 0;
686
687 err_free_tdma:
688 mv_cesa_dma_cleanup(basereq);
689 dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
690
691 err:
692 mv_cesa_ahash_last_cleanup(req);
693
694 return ret;
695 }
696
697 static int mv_cesa_ahash_req_init(struct ahash_request *req, bool *cached)
698 {
699 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
700
701 creq->src_nents = sg_nents_for_len(req->src, req->nbytes);
702 if (creq->src_nents < 0) {
703 dev_err(cesa_dev->dev, "Invalid number of src SG");
704 return creq->src_nents;
705 }
706
707 *cached = mv_cesa_ahash_cache_req(req);
708
709 if (*cached)
710 return 0;
711
712 if (cesa_dev->caps->has_tdma)
713 return mv_cesa_ahash_dma_req_init(req);
714 else
715 return 0;
716 }
717
718 static int mv_cesa_ahash_queue_req(struct ahash_request *req)
719 {
720 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
721 struct mv_cesa_engine *engine;
722 bool cached = false;
723 int ret;
724
725 ret = mv_cesa_ahash_req_init(req, &cached);
726 if (ret)
727 return ret;
728
729 if (cached)
730 return 0;
731
732 engine = mv_cesa_select_engine(req->nbytes);
733 mv_cesa_ahash_prepare(&req->base, engine);
734
735 ret = mv_cesa_queue_req(&req->base, &creq->base);
736
737 if (mv_cesa_req_needs_cleanup(&req->base, ret))
738 mv_cesa_ahash_cleanup(req);
739
740 return ret;
741 }
742
743 static int mv_cesa_ahash_update(struct ahash_request *req)
744 {
745 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
746
747 creq->len += req->nbytes;
748
749 return mv_cesa_ahash_queue_req(req);
750 }
751
752 static int mv_cesa_ahash_final(struct ahash_request *req)
753 {
754 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
755 struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
756
757 mv_cesa_set_mac_op_total_len(tmpl, creq->len);
758 creq->last_req = true;
759 req->nbytes = 0;
760
761 return mv_cesa_ahash_queue_req(req);
762 }
763
764 static int mv_cesa_ahash_finup(struct ahash_request *req)
765 {
766 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
767 struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
768
769 creq->len += req->nbytes;
770 mv_cesa_set_mac_op_total_len(tmpl, creq->len);
771 creq->last_req = true;
772
773 return mv_cesa_ahash_queue_req(req);
774 }
775
776 static int mv_cesa_ahash_export(struct ahash_request *req, void *hash,
777 u64 *len, void *cache)
778 {
779 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
780 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
781 unsigned int digsize = crypto_ahash_digestsize(ahash);
782 unsigned int blocksize;
783
784 blocksize = crypto_ahash_blocksize(ahash);
785
786 *len = creq->len;
787 memcpy(hash, creq->state, digsize);
788 memset(cache, 0, blocksize);
789 memcpy(cache, creq->cache, creq->cache_ptr);
790
791 return 0;
792 }
793
794 static int mv_cesa_ahash_import(struct ahash_request *req, const void *hash,
795 u64 len, const void *cache)
796 {
797 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
798 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
799 unsigned int digsize = crypto_ahash_digestsize(ahash);
800 unsigned int blocksize;
801 unsigned int cache_ptr;
802 int ret;
803
804 ret = crypto_ahash_init(req);
805 if (ret)
806 return ret;
807
808 blocksize = crypto_ahash_blocksize(ahash);
809 if (len >= blocksize)
810 mv_cesa_update_op_cfg(&creq->op_tmpl,
811 CESA_SA_DESC_CFG_MID_FRAG,
812 CESA_SA_DESC_CFG_FRAG_MSK);
813
814 creq->len = len;
815 memcpy(creq->state, hash, digsize);
816 creq->cache_ptr = 0;
817
818 cache_ptr = do_div(len, blocksize);
819 if (!cache_ptr)
820 return 0;
821
822 memcpy(creq->cache, cache, cache_ptr);
823 creq->cache_ptr = cache_ptr;
824
825 return 0;
826 }
827
828 static int mv_cesa_md5_init(struct ahash_request *req)
829 {
830 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
831 struct mv_cesa_op_ctx tmpl = { };
832
833 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_MD5);
834
835 mv_cesa_ahash_init(req, &tmpl, true);
836
837 creq->state[0] = MD5_H0;
838 creq->state[1] = MD5_H1;
839 creq->state[2] = MD5_H2;
840 creq->state[3] = MD5_H3;
841
842 return 0;
843 }
844
845 static int mv_cesa_md5_export(struct ahash_request *req, void *out)
846 {
847 struct md5_state *out_state = out;
848
849 return mv_cesa_ahash_export(req, out_state->hash,
850 &out_state->byte_count, out_state->block);
851 }
852
853 static int mv_cesa_md5_import(struct ahash_request *req, const void *in)
854 {
855 const struct md5_state *in_state = in;
856
857 return mv_cesa_ahash_import(req, in_state->hash, in_state->byte_count,
858 in_state->block);
859 }
860
861 static int mv_cesa_md5_digest(struct ahash_request *req)
862 {
863 int ret;
864
865 ret = mv_cesa_md5_init(req);
866 if (ret)
867 return ret;
868
869 return mv_cesa_ahash_finup(req);
870 }
871
872 struct ahash_alg mv_md5_alg = {
873 .init = mv_cesa_md5_init,
874 .update = mv_cesa_ahash_update,
875 .final = mv_cesa_ahash_final,
876 .finup = mv_cesa_ahash_finup,
877 .digest = mv_cesa_md5_digest,
878 .export = mv_cesa_md5_export,
879 .import = mv_cesa_md5_import,
880 .halg = {
881 .digestsize = MD5_DIGEST_SIZE,
882 .statesize = sizeof(struct md5_state),
883 .base = {
884 .cra_name = "md5",
885 .cra_driver_name = "mv-md5",
886 .cra_priority = 300,
887 .cra_flags = CRYPTO_ALG_ASYNC |
888 CRYPTO_ALG_KERN_DRIVER_ONLY,
889 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
890 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
891 .cra_init = mv_cesa_ahash_cra_init,
892 .cra_module = THIS_MODULE,
893 }
894 }
895 };
896
897 static int mv_cesa_sha1_init(struct ahash_request *req)
898 {
899 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
900 struct mv_cesa_op_ctx tmpl = { };
901
902 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA1);
903
904 mv_cesa_ahash_init(req, &tmpl, false);
905
906 creq->state[0] = SHA1_H0;
907 creq->state[1] = SHA1_H1;
908 creq->state[2] = SHA1_H2;
909 creq->state[3] = SHA1_H3;
910 creq->state[4] = SHA1_H4;
911
912 return 0;
913 }
914
915 static int mv_cesa_sha1_export(struct ahash_request *req, void *out)
916 {
917 struct sha1_state *out_state = out;
918
919 return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
920 out_state->buffer);
921 }
922
923 static int mv_cesa_sha1_import(struct ahash_request *req, const void *in)
924 {
925 const struct sha1_state *in_state = in;
926
927 return mv_cesa_ahash_import(req, in_state->state, in_state->count,
928 in_state->buffer);
929 }
930
931 static int mv_cesa_sha1_digest(struct ahash_request *req)
932 {
933 int ret;
934
935 ret = mv_cesa_sha1_init(req);
936 if (ret)
937 return ret;
938
939 return mv_cesa_ahash_finup(req);
940 }
941
942 struct ahash_alg mv_sha1_alg = {
943 .init = mv_cesa_sha1_init,
944 .update = mv_cesa_ahash_update,
945 .final = mv_cesa_ahash_final,
946 .finup = mv_cesa_ahash_finup,
947 .digest = mv_cesa_sha1_digest,
948 .export = mv_cesa_sha1_export,
949 .import = mv_cesa_sha1_import,
950 .halg = {
951 .digestsize = SHA1_DIGEST_SIZE,
952 .statesize = sizeof(struct sha1_state),
953 .base = {
954 .cra_name = "sha1",
955 .cra_driver_name = "mv-sha1",
956 .cra_priority = 300,
957 .cra_flags = CRYPTO_ALG_ASYNC |
958 CRYPTO_ALG_KERN_DRIVER_ONLY,
959 .cra_blocksize = SHA1_BLOCK_SIZE,
960 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
961 .cra_init = mv_cesa_ahash_cra_init,
962 .cra_module = THIS_MODULE,
963 }
964 }
965 };
966
967 static int mv_cesa_sha256_init(struct ahash_request *req)
968 {
969 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
970 struct mv_cesa_op_ctx tmpl = { };
971
972 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA256);
973
974 mv_cesa_ahash_init(req, &tmpl, false);
975
976 creq->state[0] = SHA256_H0;
977 creq->state[1] = SHA256_H1;
978 creq->state[2] = SHA256_H2;
979 creq->state[3] = SHA256_H3;
980 creq->state[4] = SHA256_H4;
981 creq->state[5] = SHA256_H5;
982 creq->state[6] = SHA256_H6;
983 creq->state[7] = SHA256_H7;
984
985 return 0;
986 }
987
988 static int mv_cesa_sha256_digest(struct ahash_request *req)
989 {
990 int ret;
991
992 ret = mv_cesa_sha256_init(req);
993 if (ret)
994 return ret;
995
996 return mv_cesa_ahash_finup(req);
997 }
998
999 static int mv_cesa_sha256_export(struct ahash_request *req, void *out)
1000 {
1001 struct sha256_state *out_state = out;
1002
1003 return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
1004 out_state->buf);
1005 }
1006
1007 static int mv_cesa_sha256_import(struct ahash_request *req, const void *in)
1008 {
1009 const struct sha256_state *in_state = in;
1010
1011 return mv_cesa_ahash_import(req, in_state->state, in_state->count,
1012 in_state->buf);
1013 }
1014
1015 struct ahash_alg mv_sha256_alg = {
1016 .init = mv_cesa_sha256_init,
1017 .update = mv_cesa_ahash_update,
1018 .final = mv_cesa_ahash_final,
1019 .finup = mv_cesa_ahash_finup,
1020 .digest = mv_cesa_sha256_digest,
1021 .export = mv_cesa_sha256_export,
1022 .import = mv_cesa_sha256_import,
1023 .halg = {
1024 .digestsize = SHA256_DIGEST_SIZE,
1025 .statesize = sizeof(struct sha256_state),
1026 .base = {
1027 .cra_name = "sha256",
1028 .cra_driver_name = "mv-sha256",
1029 .cra_priority = 300,
1030 .cra_flags = CRYPTO_ALG_ASYNC |
1031 CRYPTO_ALG_KERN_DRIVER_ONLY,
1032 .cra_blocksize = SHA256_BLOCK_SIZE,
1033 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
1034 .cra_init = mv_cesa_ahash_cra_init,
1035 .cra_module = THIS_MODULE,
1036 }
1037 }
1038 };
1039
1040 struct mv_cesa_ahash_result {
1041 struct completion completion;
1042 int error;
1043 };
1044
1045 static void mv_cesa_hmac_ahash_complete(struct crypto_async_request *req,
1046 int error)
1047 {
1048 struct mv_cesa_ahash_result *result = req->data;
1049
1050 if (error == -EINPROGRESS)
1051 return;
1052
1053 result->error = error;
1054 complete(&result->completion);
1055 }
1056
1057 static int mv_cesa_ahmac_iv_state_init(struct ahash_request *req, u8 *pad,
1058 void *state, unsigned int blocksize)
1059 {
1060 struct mv_cesa_ahash_result result;
1061 struct scatterlist sg;
1062 int ret;
1063
1064 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1065 mv_cesa_hmac_ahash_complete, &result);
1066 sg_init_one(&sg, pad, blocksize);
1067 ahash_request_set_crypt(req, &sg, pad, blocksize);
1068 init_completion(&result.completion);
1069
1070 ret = crypto_ahash_init(req);
1071 if (ret)
1072 return ret;
1073
1074 ret = crypto_ahash_update(req);
1075 if (ret && ret != -EINPROGRESS)
1076 return ret;
1077
1078 wait_for_completion_interruptible(&result.completion);
1079 if (result.error)
1080 return result.error;
1081
1082 ret = crypto_ahash_export(req, state);
1083 if (ret)
1084 return ret;
1085
1086 return 0;
1087 }
1088
1089 static int mv_cesa_ahmac_pad_init(struct ahash_request *req,
1090 const u8 *key, unsigned int keylen,
1091 u8 *ipad, u8 *opad,
1092 unsigned int blocksize)
1093 {
1094 struct mv_cesa_ahash_result result;
1095 struct scatterlist sg;
1096 int ret;
1097 int i;
1098
1099 if (keylen <= blocksize) {
1100 memcpy(ipad, key, keylen);
1101 } else {
1102 u8 *keydup = kmemdup(key, keylen, GFP_KERNEL);
1103
1104 if (!keydup)
1105 return -ENOMEM;
1106
1107 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1108 mv_cesa_hmac_ahash_complete,
1109 &result);
1110 sg_init_one(&sg, keydup, keylen);
1111 ahash_request_set_crypt(req, &sg, ipad, keylen);
1112 init_completion(&result.completion);
1113
1114 ret = crypto_ahash_digest(req);
1115 if (ret == -EINPROGRESS) {
1116 wait_for_completion_interruptible(&result.completion);
1117 ret = result.error;
1118 }
1119
1120 /* Set the memory region to 0 to avoid any leak. */
1121 memset(keydup, 0, keylen);
1122 kfree(keydup);
1123
1124 if (ret)
1125 return ret;
1126
1127 keylen = crypto_ahash_digestsize(crypto_ahash_reqtfm(req));
1128 }
1129
1130 memset(ipad + keylen, 0, blocksize - keylen);
1131 memcpy(opad, ipad, blocksize);
1132
1133 for (i = 0; i < blocksize; i++) {
1134 ipad[i] ^= 0x36;
1135 opad[i] ^= 0x5c;
1136 }
1137
1138 return 0;
1139 }
1140
1141 static int mv_cesa_ahmac_setkey(const char *hash_alg_name,
1142 const u8 *key, unsigned int keylen,
1143 void *istate, void *ostate)
1144 {
1145 struct ahash_request *req;
1146 struct crypto_ahash *tfm;
1147 unsigned int blocksize;
1148 u8 *ipad = NULL;
1149 u8 *opad;
1150 int ret;
1151
1152 tfm = crypto_alloc_ahash(hash_alg_name, CRYPTO_ALG_TYPE_AHASH,
1153 CRYPTO_ALG_TYPE_AHASH_MASK);
1154 if (IS_ERR(tfm))
1155 return PTR_ERR(tfm);
1156
1157 req = ahash_request_alloc(tfm, GFP_KERNEL);
1158 if (!req) {
1159 ret = -ENOMEM;
1160 goto free_ahash;
1161 }
1162
1163 crypto_ahash_clear_flags(tfm, ~0);
1164
1165 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1166
1167 ipad = kzalloc(2 * blocksize, GFP_KERNEL);
1168 if (!ipad) {
1169 ret = -ENOMEM;
1170 goto free_req;
1171 }
1172
1173 opad = ipad + blocksize;
1174
1175 ret = mv_cesa_ahmac_pad_init(req, key, keylen, ipad, opad, blocksize);
1176 if (ret)
1177 goto free_ipad;
1178
1179 ret = mv_cesa_ahmac_iv_state_init(req, ipad, istate, blocksize);
1180 if (ret)
1181 goto free_ipad;
1182
1183 ret = mv_cesa_ahmac_iv_state_init(req, opad, ostate, blocksize);
1184
1185 free_ipad:
1186 kfree(ipad);
1187 free_req:
1188 ahash_request_free(req);
1189 free_ahash:
1190 crypto_free_ahash(tfm);
1191
1192 return ret;
1193 }
1194
1195 static int mv_cesa_ahmac_cra_init(struct crypto_tfm *tfm)
1196 {
1197 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(tfm);
1198
1199 ctx->base.ops = &mv_cesa_ahash_req_ops;
1200
1201 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1202 sizeof(struct mv_cesa_ahash_req));
1203 return 0;
1204 }
1205
1206 static int mv_cesa_ahmac_md5_init(struct ahash_request *req)
1207 {
1208 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1209 struct mv_cesa_op_ctx tmpl = { };
1210
1211 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_MD5);
1212 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1213
1214 mv_cesa_ahash_init(req, &tmpl, true);
1215
1216 return 0;
1217 }
1218
1219 static int mv_cesa_ahmac_md5_setkey(struct crypto_ahash *tfm, const u8 *key,
1220 unsigned int keylen)
1221 {
1222 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1223 struct md5_state istate, ostate;
1224 int ret, i;
1225
1226 ret = mv_cesa_ahmac_setkey("mv-md5", key, keylen, &istate, &ostate);
1227 if (ret)
1228 return ret;
1229
1230 for (i = 0; i < ARRAY_SIZE(istate.hash); i++)
1231 ctx->iv[i] = be32_to_cpu(istate.hash[i]);
1232
1233 for (i = 0; i < ARRAY_SIZE(ostate.hash); i++)
1234 ctx->iv[i + 8] = be32_to_cpu(ostate.hash[i]);
1235
1236 return 0;
1237 }
1238
1239 static int mv_cesa_ahmac_md5_digest(struct ahash_request *req)
1240 {
1241 int ret;
1242
1243 ret = mv_cesa_ahmac_md5_init(req);
1244 if (ret)
1245 return ret;
1246
1247 return mv_cesa_ahash_finup(req);
1248 }
1249
1250 struct ahash_alg mv_ahmac_md5_alg = {
1251 .init = mv_cesa_ahmac_md5_init,
1252 .update = mv_cesa_ahash_update,
1253 .final = mv_cesa_ahash_final,
1254 .finup = mv_cesa_ahash_finup,
1255 .digest = mv_cesa_ahmac_md5_digest,
1256 .setkey = mv_cesa_ahmac_md5_setkey,
1257 .export = mv_cesa_md5_export,
1258 .import = mv_cesa_md5_import,
1259 .halg = {
1260 .digestsize = MD5_DIGEST_SIZE,
1261 .statesize = sizeof(struct md5_state),
1262 .base = {
1263 .cra_name = "hmac(md5)",
1264 .cra_driver_name = "mv-hmac-md5",
1265 .cra_priority = 300,
1266 .cra_flags = CRYPTO_ALG_ASYNC |
1267 CRYPTO_ALG_KERN_DRIVER_ONLY,
1268 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
1269 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1270 .cra_init = mv_cesa_ahmac_cra_init,
1271 .cra_module = THIS_MODULE,
1272 }
1273 }
1274 };
1275
1276 static int mv_cesa_ahmac_sha1_init(struct ahash_request *req)
1277 {
1278 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1279 struct mv_cesa_op_ctx tmpl = { };
1280
1281 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA1);
1282 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1283
1284 mv_cesa_ahash_init(req, &tmpl, false);
1285
1286 return 0;
1287 }
1288
1289 static int mv_cesa_ahmac_sha1_setkey(struct crypto_ahash *tfm, const u8 *key,
1290 unsigned int keylen)
1291 {
1292 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1293 struct sha1_state istate, ostate;
1294 int ret, i;
1295
1296 ret = mv_cesa_ahmac_setkey("mv-sha1", key, keylen, &istate, &ostate);
1297 if (ret)
1298 return ret;
1299
1300 for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1301 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1302
1303 for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1304 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1305
1306 return 0;
1307 }
1308
1309 static int mv_cesa_ahmac_sha1_digest(struct ahash_request *req)
1310 {
1311 int ret;
1312
1313 ret = mv_cesa_ahmac_sha1_init(req);
1314 if (ret)
1315 return ret;
1316
1317 return mv_cesa_ahash_finup(req);
1318 }
1319
1320 struct ahash_alg mv_ahmac_sha1_alg = {
1321 .init = mv_cesa_ahmac_sha1_init,
1322 .update = mv_cesa_ahash_update,
1323 .final = mv_cesa_ahash_final,
1324 .finup = mv_cesa_ahash_finup,
1325 .digest = mv_cesa_ahmac_sha1_digest,
1326 .setkey = mv_cesa_ahmac_sha1_setkey,
1327 .export = mv_cesa_sha1_export,
1328 .import = mv_cesa_sha1_import,
1329 .halg = {
1330 .digestsize = SHA1_DIGEST_SIZE,
1331 .statesize = sizeof(struct sha1_state),
1332 .base = {
1333 .cra_name = "hmac(sha1)",
1334 .cra_driver_name = "mv-hmac-sha1",
1335 .cra_priority = 300,
1336 .cra_flags = CRYPTO_ALG_ASYNC |
1337 CRYPTO_ALG_KERN_DRIVER_ONLY,
1338 .cra_blocksize = SHA1_BLOCK_SIZE,
1339 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1340 .cra_init = mv_cesa_ahmac_cra_init,
1341 .cra_module = THIS_MODULE,
1342 }
1343 }
1344 };
1345
1346 static int mv_cesa_ahmac_sha256_setkey(struct crypto_ahash *tfm, const u8 *key,
1347 unsigned int keylen)
1348 {
1349 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1350 struct sha256_state istate, ostate;
1351 int ret, i;
1352
1353 ret = mv_cesa_ahmac_setkey("mv-sha256", key, keylen, &istate, &ostate);
1354 if (ret)
1355 return ret;
1356
1357 for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1358 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1359
1360 for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1361 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1362
1363 return 0;
1364 }
1365
1366 static int mv_cesa_ahmac_sha256_init(struct ahash_request *req)
1367 {
1368 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1369 struct mv_cesa_op_ctx tmpl = { };
1370
1371 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA256);
1372 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1373
1374 mv_cesa_ahash_init(req, &tmpl, false);
1375
1376 return 0;
1377 }
1378
1379 static int mv_cesa_ahmac_sha256_digest(struct ahash_request *req)
1380 {
1381 int ret;
1382
1383 ret = mv_cesa_ahmac_sha256_init(req);
1384 if (ret)
1385 return ret;
1386
1387 return mv_cesa_ahash_finup(req);
1388 }
1389
1390 struct ahash_alg mv_ahmac_sha256_alg = {
1391 .init = mv_cesa_ahmac_sha256_init,
1392 .update = mv_cesa_ahash_update,
1393 .final = mv_cesa_ahash_final,
1394 .finup = mv_cesa_ahash_finup,
1395 .digest = mv_cesa_ahmac_sha256_digest,
1396 .setkey = mv_cesa_ahmac_sha256_setkey,
1397 .export = mv_cesa_sha256_export,
1398 .import = mv_cesa_sha256_import,
1399 .halg = {
1400 .digestsize = SHA256_DIGEST_SIZE,
1401 .statesize = sizeof(struct sha256_state),
1402 .base = {
1403 .cra_name = "hmac(sha256)",
1404 .cra_driver_name = "mv-hmac-sha256",
1405 .cra_priority = 300,
1406 .cra_flags = CRYPTO_ALG_ASYNC |
1407 CRYPTO_ALG_KERN_DRIVER_ONLY,
1408 .cra_blocksize = SHA256_BLOCK_SIZE,
1409 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1410 .cra_init = mv_cesa_ahmac_cra_init,
1411 .cra_module = THIS_MODULE,
1412 }
1413 }
1414 };
Linux with added FPC-III support