?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
inet: frag: enforce memory limits earlier
[linux/fpc-iii.git] / drivers / dma / ioat / init.c
blob84eb83eb2efef41eed6daee14f533f9726dc61e0
1 /*
2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2015 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in
15 * the file called "COPYING".
16 *
17 */
18
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/slab.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/dmaengine.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/workqueue.h>
28 #include <linux/prefetch.h>
29 #include <linux/dca.h>
30 #include <linux/aer.h>
31 #include <linux/sizes.h>
32 #include "dma.h"
33 #include "registers.h"
34 #include "hw.h"
35
36 #include "../dmaengine.h"
37
38 MODULE_VERSION(IOAT_DMA_VERSION);
39 MODULE_LICENSE("Dual BSD/GPL");
40 MODULE_AUTHOR("Intel Corporation");
41
42 static struct pci_device_id ioat_pci_tbl[] = {
43 /* I/OAT v3 platforms */
44 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) },
45 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) },
46 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) },
47 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) },
48 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) },
49 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) },
50 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) },
51 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) },
52
53 /* I/OAT v3.2 platforms */
54 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) },
55 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) },
56 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) },
57 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) },
58 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) },
59 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) },
60 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) },
61 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) },
62 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) },
63 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) },
64
65 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) },
66 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) },
67 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) },
68 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) },
69 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) },
70 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) },
71 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) },
72 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) },
73 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) },
74 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) },
75
76 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) },
77 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) },
78 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) },
79 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) },
80 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) },
81 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) },
82 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) },
83 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) },
84 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) },
85 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) },
86
87 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) },
88 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) },
89 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) },
90 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) },
91 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) },
92 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) },
93 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) },
94 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) },
95 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) },
96 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) },
97
98 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX0) },
99 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX1) },
100 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX2) },
101 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX3) },
102 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX4) },
103 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX5) },
104 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX6) },
105 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX7) },
106 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8) },
107 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9) },
108
109 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SKX) },
110
111 /* I/OAT v3.3 platforms */
112 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) },
113 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) },
114 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) },
115 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) },
116
117 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0) },
118 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1) },
119 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2) },
120 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3) },
121
122 { 0, }
123 };
124 MODULE_DEVICE_TABLE(pci, ioat_pci_tbl);
125
126 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
127 static void ioat_remove(struct pci_dev *pdev);
128 static void
129 ioat_init_channel(struct ioatdma_device *ioat_dma,
130 struct ioatdma_chan *ioat_chan, int idx);
131 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma);
132 static int ioat_enumerate_channels(struct ioatdma_device *ioat_dma);
133 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma);
134
135 static int ioat_dca_enabled = 1;
136 module_param(ioat_dca_enabled, int, 0644);
137 MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)");
138 int ioat_pending_level = 4;
139 module_param(ioat_pending_level, int, 0644);
140 MODULE_PARM_DESC(ioat_pending_level,
141 "high-water mark for pushing ioat descriptors (default: 4)");
142 static char ioat_interrupt_style[32] = "msix";
143 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
144 sizeof(ioat_interrupt_style), 0644);
145 MODULE_PARM_DESC(ioat_interrupt_style,
146 "set ioat interrupt style: msix (default), msi, intx");
147
148 struct kmem_cache *ioat_cache;
149 struct kmem_cache *ioat_sed_cache;
150
151 static bool is_jf_ioat(struct pci_dev *pdev)
152 {
153 switch (pdev->device) {
154 case PCI_DEVICE_ID_INTEL_IOAT_JSF0:
155 case PCI_DEVICE_ID_INTEL_IOAT_JSF1:
156 case PCI_DEVICE_ID_INTEL_IOAT_JSF2:
157 case PCI_DEVICE_ID_INTEL_IOAT_JSF3:
158 case PCI_DEVICE_ID_INTEL_IOAT_JSF4:
159 case PCI_DEVICE_ID_INTEL_IOAT_JSF5:
160 case PCI_DEVICE_ID_INTEL_IOAT_JSF6:
161 case PCI_DEVICE_ID_INTEL_IOAT_JSF7:
162 case PCI_DEVICE_ID_INTEL_IOAT_JSF8:
163 case PCI_DEVICE_ID_INTEL_IOAT_JSF9:
164 return true;
165 default:
166 return false;
167 }
168 }
169
170 static bool is_snb_ioat(struct pci_dev *pdev)
171 {
172 switch (pdev->device) {
173 case PCI_DEVICE_ID_INTEL_IOAT_SNB0:
174 case PCI_DEVICE_ID_INTEL_IOAT_SNB1:
175 case PCI_DEVICE_ID_INTEL_IOAT_SNB2:
176 case PCI_DEVICE_ID_INTEL_IOAT_SNB3:
177 case PCI_DEVICE_ID_INTEL_IOAT_SNB4:
178 case PCI_DEVICE_ID_INTEL_IOAT_SNB5:
179 case PCI_DEVICE_ID_INTEL_IOAT_SNB6:
180 case PCI_DEVICE_ID_INTEL_IOAT_SNB7:
181 case PCI_DEVICE_ID_INTEL_IOAT_SNB8:
182 case PCI_DEVICE_ID_INTEL_IOAT_SNB9:
183 return true;
184 default:
185 return false;
186 }
187 }
188
189 static bool is_ivb_ioat(struct pci_dev *pdev)
190 {
191 switch (pdev->device) {
192 case PCI_DEVICE_ID_INTEL_IOAT_IVB0:
193 case PCI_DEVICE_ID_INTEL_IOAT_IVB1:
194 case PCI_DEVICE_ID_INTEL_IOAT_IVB2:
195 case PCI_DEVICE_ID_INTEL_IOAT_IVB3:
196 case PCI_DEVICE_ID_INTEL_IOAT_IVB4:
197 case PCI_DEVICE_ID_INTEL_IOAT_IVB5:
198 case PCI_DEVICE_ID_INTEL_IOAT_IVB6:
199 case PCI_DEVICE_ID_INTEL_IOAT_IVB7:
200 case PCI_DEVICE_ID_INTEL_IOAT_IVB8:
201 case PCI_DEVICE_ID_INTEL_IOAT_IVB9:
202 return true;
203 default:
204 return false;
205 }
206
207 }
208
209 static bool is_hsw_ioat(struct pci_dev *pdev)
210 {
211 switch (pdev->device) {
212 case PCI_DEVICE_ID_INTEL_IOAT_HSW0:
213 case PCI_DEVICE_ID_INTEL_IOAT_HSW1:
214 case PCI_DEVICE_ID_INTEL_IOAT_HSW2:
215 case PCI_DEVICE_ID_INTEL_IOAT_HSW3:
216 case PCI_DEVICE_ID_INTEL_IOAT_HSW4:
217 case PCI_DEVICE_ID_INTEL_IOAT_HSW5:
218 case PCI_DEVICE_ID_INTEL_IOAT_HSW6:
219 case PCI_DEVICE_ID_INTEL_IOAT_HSW7:
220 case PCI_DEVICE_ID_INTEL_IOAT_HSW8:
221 case PCI_DEVICE_ID_INTEL_IOAT_HSW9:
222 return true;
223 default:
224 return false;
225 }
226
227 }
228
229 static bool is_bdx_ioat(struct pci_dev *pdev)
230 {
231 switch (pdev->device) {
232 case PCI_DEVICE_ID_INTEL_IOAT_BDX0:
233 case PCI_DEVICE_ID_INTEL_IOAT_BDX1:
234 case PCI_DEVICE_ID_INTEL_IOAT_BDX2:
235 case PCI_DEVICE_ID_INTEL_IOAT_BDX3:
236 case PCI_DEVICE_ID_INTEL_IOAT_BDX4:
237 case PCI_DEVICE_ID_INTEL_IOAT_BDX5:
238 case PCI_DEVICE_ID_INTEL_IOAT_BDX6:
239 case PCI_DEVICE_ID_INTEL_IOAT_BDX7:
240 case PCI_DEVICE_ID_INTEL_IOAT_BDX8:
241 case PCI_DEVICE_ID_INTEL_IOAT_BDX9:
242 return true;
243 default:
244 return false;
245 }
246 }
247
248 static inline bool is_skx_ioat(struct pci_dev *pdev)
249 {
250 return (pdev->device == PCI_DEVICE_ID_INTEL_IOAT_SKX) ? true : false;
251 }
252
253 static bool is_xeon_cb32(struct pci_dev *pdev)
254 {
255 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) ||
256 is_hsw_ioat(pdev) || is_bdx_ioat(pdev) || is_skx_ioat(pdev);
257 }
258
259 bool is_bwd_ioat(struct pci_dev *pdev)
260 {
261 switch (pdev->device) {
262 case PCI_DEVICE_ID_INTEL_IOAT_BWD0:
263 case PCI_DEVICE_ID_INTEL_IOAT_BWD1:
264 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
265 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
266 /* even though not Atom, BDX-DE has same DMA silicon */
267 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0:
268 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1:
269 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2:
270 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3:
271 return true;
272 default:
273 return false;
274 }
275 }
276
277 static bool is_bwd_noraid(struct pci_dev *pdev)
278 {
279 switch (pdev->device) {
280 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
281 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
282 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0:
283 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1:
284 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2:
285 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3:
286 return true;
287 default:
288 return false;
289 }
290
291 }
292
293 /*
294 * Perform a IOAT transaction to verify the HW works.
295 */
296 #define IOAT_TEST_SIZE 2000
297
298 static void ioat_dma_test_callback(void *dma_async_param)
299 {
300 struct completion *cmp = dma_async_param;
301
302 complete(cmp);
303 }
304
305 /**
306 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
307 * @ioat_dma: dma device to be tested
308 */
309 static int ioat_dma_self_test(struct ioatdma_device *ioat_dma)
310 {
311 int i;
312 u8 *src;
313 u8 *dest;
314 struct dma_device *dma = &ioat_dma->dma_dev;
315 struct device *dev = &ioat_dma->pdev->dev;
316 struct dma_chan *dma_chan;
317 struct dma_async_tx_descriptor *tx;
318 dma_addr_t dma_dest, dma_src;
319 dma_cookie_t cookie;
320 int err = 0;
321 struct completion cmp;
322 unsigned long tmo;
323 unsigned long flags;
324
325 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
326 if (!src)
327 return -ENOMEM;
328 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
329 if (!dest) {
330 kfree(src);
331 return -ENOMEM;
332 }
333
334 /* Fill in src buffer */
335 for (i = 0; i < IOAT_TEST_SIZE; i++)
336 src[i] = (u8)i;
337
338 /* Start copy, using first DMA channel */
339 dma_chan = container_of(dma->channels.next, struct dma_chan,
340 device_node);
341 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
342 dev_err(dev, "selftest cannot allocate chan resource\n");
343 err = -ENODEV;
344 goto out;
345 }
346
347 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
348 if (dma_mapping_error(dev, dma_src)) {
349 dev_err(dev, "mapping src buffer failed\n");
350 goto free_resources;
351 }
352 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
353 if (dma_mapping_error(dev, dma_dest)) {
354 dev_err(dev, "mapping dest buffer failed\n");
355 goto unmap_src;
356 }
357 flags = DMA_PREP_INTERRUPT;
358 tx = ioat_dma->dma_dev.device_prep_dma_memcpy(dma_chan, dma_dest,
359 dma_src, IOAT_TEST_SIZE,
360 flags);
361 if (!tx) {
362 dev_err(dev, "Self-test prep failed, disabling\n");
363 err = -ENODEV;
364 goto unmap_dma;
365 }
366
367 async_tx_ack(tx);
368 init_completion(&cmp);
369 tx->callback = ioat_dma_test_callback;
370 tx->callback_param = &cmp;
371 cookie = tx->tx_submit(tx);
372 if (cookie < 0) {
373 dev_err(dev, "Self-test setup failed, disabling\n");
374 err = -ENODEV;
375 goto unmap_dma;
376 }
377 dma->device_issue_pending(dma_chan);
378
379 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
380
381 if (tmo == 0 ||
382 dma->device_tx_status(dma_chan, cookie, NULL)
383 != DMA_COMPLETE) {
384 dev_err(dev, "Self-test copy timed out, disabling\n");
385 err = -ENODEV;
386 goto unmap_dma;
387 }
388 if (memcmp(src, dest, IOAT_TEST_SIZE)) {
389 dev_err(dev, "Self-test copy failed compare, disabling\n");
390 err = -ENODEV;
391 goto unmap_dma;
392 }
393
394 unmap_dma:
395 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
396 unmap_src:
397 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
398 free_resources:
399 dma->device_free_chan_resources(dma_chan);
400 out:
401 kfree(src);
402 kfree(dest);
403 return err;
404 }
405
406 /**
407 * ioat_dma_setup_interrupts - setup interrupt handler
408 * @ioat_dma: ioat dma device
409 */
410 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma)
411 {
412 struct ioatdma_chan *ioat_chan;
413 struct pci_dev *pdev = ioat_dma->pdev;
414 struct device *dev = &pdev->dev;
415 struct msix_entry *msix;
416 int i, j, msixcnt;
417 int err = -EINVAL;
418 u8 intrctrl = 0;
419
420 if (!strcmp(ioat_interrupt_style, "msix"))
421 goto msix;
422 if (!strcmp(ioat_interrupt_style, "msi"))
423 goto msi;
424 if (!strcmp(ioat_interrupt_style, "intx"))
425 goto intx;
426 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
427 goto err_no_irq;
428
429 msix:
430 /* The number of MSI-X vectors should equal the number of channels */
431 msixcnt = ioat_dma->dma_dev.chancnt;
432 for (i = 0; i < msixcnt; i++)
433 ioat_dma->msix_entries[i].entry = i;
434
435 err = pci_enable_msix_exact(pdev, ioat_dma->msix_entries, msixcnt);
436 if (err)
437 goto msi;
438
439 for (i = 0; i < msixcnt; i++) {
440 msix = &ioat_dma->msix_entries[i];
441 ioat_chan = ioat_chan_by_index(ioat_dma, i);
442 err = devm_request_irq(dev, msix->vector,
443 ioat_dma_do_interrupt_msix, 0,
444 "ioat-msix", ioat_chan);
445 if (err) {
446 for (j = 0; j < i; j++) {
447 msix = &ioat_dma->msix_entries[j];
448 ioat_chan = ioat_chan_by_index(ioat_dma, j);
449 devm_free_irq(dev, msix->vector, ioat_chan);
450 }
451 goto msi;
452 }
453 }
454 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
455 ioat_dma->irq_mode = IOAT_MSIX;
456 goto done;
457
458 msi:
459 err = pci_enable_msi(pdev);
460 if (err)
461 goto intx;
462
463 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
464 "ioat-msi", ioat_dma);
465 if (err) {
466 pci_disable_msi(pdev);
467 goto intx;
468 }
469 ioat_dma->irq_mode = IOAT_MSI;
470 goto done;
471
472 intx:
473 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
474 IRQF_SHARED, "ioat-intx", ioat_dma);
475 if (err)
476 goto err_no_irq;
477
478 ioat_dma->irq_mode = IOAT_INTX;
479 done:
480 if (is_bwd_ioat(pdev))
481 ioat_intr_quirk(ioat_dma);
482 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
483 writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
484 return 0;
485
486 err_no_irq:
487 /* Disable all interrupt generation */
488 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
489 ioat_dma->irq_mode = IOAT_NOIRQ;
490 dev_err(dev, "no usable interrupts\n");
491 return err;
492 }
493
494 static void ioat_disable_interrupts(struct ioatdma_device *ioat_dma)
495 {
496 /* Disable all interrupt generation */
497 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
498 }
499
500 static int ioat_probe(struct ioatdma_device *ioat_dma)
501 {
502 int err = -ENODEV;
503 struct dma_device *dma = &ioat_dma->dma_dev;
504 struct pci_dev *pdev = ioat_dma->pdev;
505 struct device *dev = &pdev->dev;
506
507 ioat_dma->completion_pool = dma_pool_create("completion_pool", dev,
508 sizeof(u64),
509 SMP_CACHE_BYTES,
510 SMP_CACHE_BYTES);
511
512 if (!ioat_dma->completion_pool) {
513 err = -ENOMEM;
514 goto err_out;
515 }
516
517 ioat_enumerate_channels(ioat_dma);
518
519 dma_cap_set(DMA_MEMCPY, dma->cap_mask);
520 dma->dev = &pdev->dev;
521
522 if (!dma->chancnt) {
523 dev_err(dev, "channel enumeration error\n");
524 goto err_setup_interrupts;
525 }
526
527 err = ioat_dma_setup_interrupts(ioat_dma);
528 if (err)
529 goto err_setup_interrupts;
530
531 err = ioat3_dma_self_test(ioat_dma);
532 if (err)
533 goto err_self_test;
534
535 return 0;
536
537 err_self_test:
538 ioat_disable_interrupts(ioat_dma);
539 err_setup_interrupts:
540 dma_pool_destroy(ioat_dma->completion_pool);
541 err_out:
542 return err;
543 }
544
545 static int ioat_register(struct ioatdma_device *ioat_dma)
546 {
547 int err = dma_async_device_register(&ioat_dma->dma_dev);
548
549 if (err) {
550 ioat_disable_interrupts(ioat_dma);
551 dma_pool_destroy(ioat_dma->completion_pool);
552 }
553
554 return err;
555 }
556
557 static void ioat_dma_remove(struct ioatdma_device *ioat_dma)
558 {
559 struct dma_device *dma = &ioat_dma->dma_dev;
560
561 ioat_disable_interrupts(ioat_dma);
562
563 ioat_kobject_del(ioat_dma);
564
565 dma_async_device_unregister(dma);
566
567 dma_pool_destroy(ioat_dma->completion_pool);
568
569 INIT_LIST_HEAD(&dma->channels);
570 }
571
572 /**
573 * ioat_enumerate_channels - find and initialize the device's channels
574 * @ioat_dma: the ioat dma device to be enumerated
575 */
576 static int ioat_enumerate_channels(struct ioatdma_device *ioat_dma)
577 {
578 struct ioatdma_chan *ioat_chan;
579 struct device *dev = &ioat_dma->pdev->dev;
580 struct dma_device *dma = &ioat_dma->dma_dev;
581 u8 xfercap_log;
582 int i;
583
584 INIT_LIST_HEAD(&dma->channels);
585 dma->chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET);
586 dma->chancnt &= 0x1f; /* bits [4:0] valid */
587 if (dma->chancnt > ARRAY_SIZE(ioat_dma->idx)) {
588 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
589 dma->chancnt, ARRAY_SIZE(ioat_dma->idx));
590 dma->chancnt = ARRAY_SIZE(ioat_dma->idx);
591 }
592 xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET);
593 xfercap_log &= 0x1f; /* bits [4:0] valid */
594 if (xfercap_log == 0)
595 return 0;
596 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
597
598 for (i = 0; i < dma->chancnt; i++) {
599 ioat_chan = devm_kzalloc(dev, sizeof(*ioat_chan), GFP_KERNEL);
600 if (!ioat_chan)
601 break;
602
603 ioat_init_channel(ioat_dma, ioat_chan, i);
604 ioat_chan->xfercap_log = xfercap_log;
605 spin_lock_init(&ioat_chan->prep_lock);
606 if (ioat_reset_hw(ioat_chan)) {
607 i = 0;
608 break;
609 }
610 }
611 dma->chancnt = i;
612 return i;
613 }
614
615 /**
616 * ioat_free_chan_resources - release all the descriptors
617 * @chan: the channel to be cleaned
618 */
619 static void ioat_free_chan_resources(struct dma_chan *c)
620 {
621 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
622 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
623 struct ioat_ring_ent *desc;
624 const int total_descs = 1 << ioat_chan->alloc_order;
625 int descs;
626 int i;
627
628 /* Before freeing channel resources first check
629 * if they have been previously allocated for this channel.
630 */
631 if (!ioat_chan->ring)
632 return;
633
634 ioat_stop(ioat_chan);
635 ioat_reset_hw(ioat_chan);
636
637 spin_lock_bh(&ioat_chan->cleanup_lock);
638 spin_lock_bh(&ioat_chan->prep_lock);
639 descs = ioat_ring_space(ioat_chan);
640 dev_dbg(to_dev(ioat_chan), "freeing %d idle descriptors\n", descs);
641 for (i = 0; i < descs; i++) {
642 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head + i);
643 ioat_free_ring_ent(desc, c);
644 }
645
646 if (descs < total_descs)
647 dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n",
648 total_descs - descs);
649
650 for (i = 0; i < total_descs - descs; i++) {
651 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail + i);
652 dump_desc_dbg(ioat_chan, desc);
653 ioat_free_ring_ent(desc, c);
654 }
655
656 for (i = 0; i < ioat_chan->desc_chunks; i++) {
657 dma_free_coherent(to_dev(ioat_chan), SZ_2M,
658 ioat_chan->descs[i].virt,
659 ioat_chan->descs[i].hw);
660 ioat_chan->descs[i].virt = NULL;
661 ioat_chan->descs[i].hw = 0;
662 }
663 ioat_chan->desc_chunks = 0;
664
665 kfree(ioat_chan->ring);
666 ioat_chan->ring = NULL;
667 ioat_chan->alloc_order = 0;
668 dma_pool_free(ioat_dma->completion_pool, ioat_chan->completion,
669 ioat_chan->completion_dma);
670 spin_unlock_bh(&ioat_chan->prep_lock);
671 spin_unlock_bh(&ioat_chan->cleanup_lock);
672
673 ioat_chan->last_completion = 0;
674 ioat_chan->completion_dma = 0;
675 ioat_chan->dmacount = 0;
676 }
677
678 /* ioat_alloc_chan_resources - allocate/initialize ioat descriptor ring
679 * @chan: channel to be initialized
680 */
681 static int ioat_alloc_chan_resources(struct dma_chan *c)
682 {
683 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
684 struct ioat_ring_ent **ring;
685 u64 status;
686 int order;
687 int i = 0;
688 u32 chanerr;
689
690 /* have we already been set up? */
691 if (ioat_chan->ring)
692 return 1 << ioat_chan->alloc_order;
693
694 /* Setup register to interrupt and write completion status on error */
695 writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
696
697 /* allocate a completion writeback area */
698 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
699 ioat_chan->completion =
700 dma_pool_zalloc(ioat_chan->ioat_dma->completion_pool,
701 GFP_NOWAIT, &ioat_chan->completion_dma);
702 if (!ioat_chan->completion)
703 return -ENOMEM;
704
705 writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF,
706 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
707 writel(((u64)ioat_chan->completion_dma) >> 32,
708 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
709
710 order = IOAT_MAX_ORDER;
711 ring = ioat_alloc_ring(c, order, GFP_NOWAIT);
712 if (!ring)
713 return -ENOMEM;
714
715 spin_lock_bh(&ioat_chan->cleanup_lock);
716 spin_lock_bh(&ioat_chan->prep_lock);
717 ioat_chan->ring = ring;
718 ioat_chan->head = 0;
719 ioat_chan->issued = 0;
720 ioat_chan->tail = 0;
721 ioat_chan->alloc_order = order;
722 set_bit(IOAT_RUN, &ioat_chan->state);
723 spin_unlock_bh(&ioat_chan->prep_lock);
724 spin_unlock_bh(&ioat_chan->cleanup_lock);
725
726 ioat_start_null_desc(ioat_chan);
727
728 /* check that we got off the ground */
729 do {
730 udelay(1);
731 status = ioat_chansts(ioat_chan);
732 } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status));
733
734 if (is_ioat_active(status) || is_ioat_idle(status))
735 return 1 << ioat_chan->alloc_order;
736
737 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
738
739 dev_WARN(to_dev(ioat_chan),
740 "failed to start channel chanerr: %#x\n", chanerr);
741 ioat_free_chan_resources(c);
742 return -EFAULT;
743 }
744
745 /* common channel initialization */
746 static void
747 ioat_init_channel(struct ioatdma_device *ioat_dma,
748 struct ioatdma_chan *ioat_chan, int idx)
749 {
750 struct dma_device *dma = &ioat_dma->dma_dev;
751 struct dma_chan *c = &ioat_chan->dma_chan;
752 unsigned long data = (unsigned long) c;
753
754 ioat_chan->ioat_dma = ioat_dma;
755 ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1));
756 spin_lock_init(&ioat_chan->cleanup_lock);
757 ioat_chan->dma_chan.device = dma;
758 dma_cookie_init(&ioat_chan->dma_chan);
759 list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels);
760 ioat_dma->idx[idx] = ioat_chan;
761 init_timer(&ioat_chan->timer);
762 ioat_chan->timer.function = ioat_timer_event;
763 ioat_chan->timer.data = data;
764 tasklet_init(&ioat_chan->cleanup_task, ioat_cleanup_event, data);
765 }
766
767 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */
768 static int ioat_xor_val_self_test(struct ioatdma_device *ioat_dma)
769 {
770 int i, src_idx;
771 struct page *dest;
772 struct page *xor_srcs[IOAT_NUM_SRC_TEST];
773 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1];
774 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1];
775 dma_addr_t dest_dma;
776 struct dma_async_tx_descriptor *tx;
777 struct dma_chan *dma_chan;
778 dma_cookie_t cookie;
779 u8 cmp_byte = 0;
780 u32 cmp_word;
781 u32 xor_val_result;
782 int err = 0;
783 struct completion cmp;
784 unsigned long tmo;
785 struct device *dev = &ioat_dma->pdev->dev;
786 struct dma_device *dma = &ioat_dma->dma_dev;
787 u8 op = 0;
788
789 dev_dbg(dev, "%s\n", __func__);
790
791 if (!dma_has_cap(DMA_XOR, dma->cap_mask))
792 return 0;
793
794 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
795 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
796 if (!xor_srcs[src_idx]) {
797 while (src_idx--)
798 __free_page(xor_srcs[src_idx]);
799 return -ENOMEM;
800 }
801 }
802
803 dest = alloc_page(GFP_KERNEL);
804 if (!dest) {
805 while (src_idx--)
806 __free_page(xor_srcs[src_idx]);
807 return -ENOMEM;
808 }
809
810 /* Fill in src buffers */
811 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
812 u8 *ptr = page_address(xor_srcs[src_idx]);
813
814 for (i = 0; i < PAGE_SIZE; i++)
815 ptr[i] = (1 << src_idx);
816 }
817
818 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++)
819 cmp_byte ^= (u8) (1 << src_idx);
820
821 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
822 (cmp_byte << 8) | cmp_byte;
823
824 memset(page_address(dest), 0, PAGE_SIZE);
825
826 dma_chan = container_of(dma->channels.next, struct dma_chan,
827 device_node);
828 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
829 err = -ENODEV;
830 goto out;
831 }
832
833 /* test xor */
834 op = IOAT_OP_XOR;
835
836 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE);
837 if (dma_mapping_error(dev, dest_dma))
838 goto free_resources;
839
840 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
841 dma_srcs[i] = DMA_ERROR_CODE;
842 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) {
843 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE,
844 DMA_TO_DEVICE);
845 if (dma_mapping_error(dev, dma_srcs[i]))
846 goto dma_unmap;
847 }
848 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
849 IOAT_NUM_SRC_TEST, PAGE_SIZE,
850 DMA_PREP_INTERRUPT);
851
852 if (!tx) {
853 dev_err(dev, "Self-test xor prep failed\n");
854 err = -ENODEV;
855 goto dma_unmap;
856 }
857
858 async_tx_ack(tx);
859 init_completion(&cmp);
860 tx->callback = ioat_dma_test_callback;
861 tx->callback_param = &cmp;
862 cookie = tx->tx_submit(tx);
863 if (cookie < 0) {
864 dev_err(dev, "Self-test xor setup failed\n");
865 err = -ENODEV;
866 goto dma_unmap;
867 }
868 dma->device_issue_pending(dma_chan);
869
870 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
871
872 if (tmo == 0 ||
873 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
874 dev_err(dev, "Self-test xor timed out\n");
875 err = -ENODEV;
876 goto dma_unmap;
877 }
878
879 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
880 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
881
882 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
883 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
884 u32 *ptr = page_address(dest);
885
886 if (ptr[i] != cmp_word) {
887 dev_err(dev, "Self-test xor failed compare\n");
888 err = -ENODEV;
889 goto free_resources;
890 }
891 }
892 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
893
894 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
895
896 /* skip validate if the capability is not present */
897 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
898 goto free_resources;
899
900 op = IOAT_OP_XOR_VAL;
901
902 /* validate the sources with the destintation page */
903 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
904 xor_val_srcs[i] = xor_srcs[i];
905 xor_val_srcs[i] = dest;
906
907 xor_val_result = 1;
908
909 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
910 dma_srcs[i] = DMA_ERROR_CODE;
911 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) {
912 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
913 DMA_TO_DEVICE);
914 if (dma_mapping_error(dev, dma_srcs[i]))
915 goto dma_unmap;
916 }
917 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
918 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
919 &xor_val_result, DMA_PREP_INTERRUPT);
920 if (!tx) {
921 dev_err(dev, "Self-test zero prep failed\n");
922 err = -ENODEV;
923 goto dma_unmap;
924 }
925
926 async_tx_ack(tx);
927 init_completion(&cmp);
928 tx->callback = ioat_dma_test_callback;
929 tx->callback_param = &cmp;
930 cookie = tx->tx_submit(tx);
931 if (cookie < 0) {
932 dev_err(dev, "Self-test zero setup failed\n");
933 err = -ENODEV;
934 goto dma_unmap;
935 }
936 dma->device_issue_pending(dma_chan);
937
938 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
939
940 if (tmo == 0 ||
941 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
942 dev_err(dev, "Self-test validate timed out\n");
943 err = -ENODEV;
944 goto dma_unmap;
945 }
946
947 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
948 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
949
950 if (xor_val_result != 0) {
951 dev_err(dev, "Self-test validate failed compare\n");
952 err = -ENODEV;
953 goto free_resources;
954 }
955
956 memset(page_address(dest), 0, PAGE_SIZE);
957
958 /* test for non-zero parity sum */
959 op = IOAT_OP_XOR_VAL;
960
961 xor_val_result = 0;
962 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
963 dma_srcs[i] = DMA_ERROR_CODE;
964 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) {
965 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
966 DMA_TO_DEVICE);
967 if (dma_mapping_error(dev, dma_srcs[i]))
968 goto dma_unmap;
969 }
970 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
971 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
972 &xor_val_result, DMA_PREP_INTERRUPT);
973 if (!tx) {
974 dev_err(dev, "Self-test 2nd zero prep failed\n");
975 err = -ENODEV;
976 goto dma_unmap;
977 }
978
979 async_tx_ack(tx);
980 init_completion(&cmp);
981 tx->callback = ioat_dma_test_callback;
982 tx->callback_param = &cmp;
983 cookie = tx->tx_submit(tx);
984 if (cookie < 0) {
985 dev_err(dev, "Self-test 2nd zero setup failed\n");
986 err = -ENODEV;
987 goto dma_unmap;
988 }
989 dma->device_issue_pending(dma_chan);
990
991 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
992
993 if (tmo == 0 ||
994 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
995 dev_err(dev, "Self-test 2nd validate timed out\n");
996 err = -ENODEV;
997 goto dma_unmap;
998 }
999
1000 if (xor_val_result != SUM_CHECK_P_RESULT) {
1001 dev_err(dev, "Self-test validate failed compare\n");
1002 err = -ENODEV;
1003 goto dma_unmap;
1004 }
1005
1006 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1007 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
1008
1009 goto free_resources;
1010 dma_unmap:
1011 if (op == IOAT_OP_XOR) {
1012 if (dest_dma != DMA_ERROR_CODE)
1013 dma_unmap_page(dev, dest_dma, PAGE_SIZE,
1014 DMA_FROM_DEVICE);
1015 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
1016 if (dma_srcs[i] != DMA_ERROR_CODE)
1017 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1018 DMA_TO_DEVICE);
1019 } else if (op == IOAT_OP_XOR_VAL) {
1020 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1021 if (dma_srcs[i] != DMA_ERROR_CODE)
1022 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1023 DMA_TO_DEVICE);
1024 }
1025 free_resources:
1026 dma->device_free_chan_resources(dma_chan);
1027 out:
1028 src_idx = IOAT_NUM_SRC_TEST;
1029 while (src_idx--)
1030 __free_page(xor_srcs[src_idx]);
1031 __free_page(dest);
1032 return err;
1033 }
1034
1035 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma)
1036 {
1037 int rc;
1038
1039 rc = ioat_dma_self_test(ioat_dma);
1040 if (rc)
1041 return rc;
1042
1043 rc = ioat_xor_val_self_test(ioat_dma);
1044
1045 return rc;
1046 }
1047
1048 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma)
1049 {
1050 struct dma_device *dma;
1051 struct dma_chan *c;
1052 struct ioatdma_chan *ioat_chan;
1053 u32 errmask;
1054
1055 dma = &ioat_dma->dma_dev;
1056
1057 /*
1058 * if we have descriptor write back error status, we mask the
1059 * error interrupts
1060 */
1061 if (ioat_dma->cap & IOAT_CAP_DWBES) {
1062 list_for_each_entry(c, &dma->channels, device_node) {
1063 ioat_chan = to_ioat_chan(c);
1064 errmask = readl(ioat_chan->reg_base +
1065 IOAT_CHANERR_MASK_OFFSET);
1066 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR |
1067 IOAT_CHANERR_XOR_Q_ERR;
1068 writel(errmask, ioat_chan->reg_base +
1069 IOAT_CHANERR_MASK_OFFSET);
1070 }
1071 }
1072 }
1073
1074 static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca)
1075 {
1076 struct pci_dev *pdev = ioat_dma->pdev;
1077 int dca_en = system_has_dca_enabled(pdev);
1078 struct dma_device *dma;
1079 struct dma_chan *c;
1080 struct ioatdma_chan *ioat_chan;
1081 bool is_raid_device = false;
1082 int err;
1083 u16 val16;
1084
1085 dma = &ioat_dma->dma_dev;
1086 dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock;
1087 dma->device_issue_pending = ioat_issue_pending;
1088 dma->device_alloc_chan_resources = ioat_alloc_chan_resources;
1089 dma->device_free_chan_resources = ioat_free_chan_resources;
1090
1091 dma_cap_set(DMA_INTERRUPT, dma->cap_mask);
1092 dma->device_prep_dma_interrupt = ioat_prep_interrupt_lock;
1093
1094 ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET);
1095
1096 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev))
1097 ioat_dma->cap &=
1098 ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS);
1099
1100 /* dca is incompatible with raid operations */
1101 if (dca_en && (ioat_dma->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ)))
1102 ioat_dma->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ);
1103
1104 if (ioat_dma->cap & IOAT_CAP_XOR) {
1105 is_raid_device = true;
1106 dma->max_xor = 8;
1107
1108 dma_cap_set(DMA_XOR, dma->cap_mask);
1109 dma->device_prep_dma_xor = ioat_prep_xor;
1110
1111 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1112 dma->device_prep_dma_xor_val = ioat_prep_xor_val;
1113 }
1114
1115 if (ioat_dma->cap & IOAT_CAP_PQ) {
1116 is_raid_device = true;
1117
1118 dma->device_prep_dma_pq = ioat_prep_pq;
1119 dma->device_prep_dma_pq_val = ioat_prep_pq_val;
1120 dma_cap_set(DMA_PQ, dma->cap_mask);
1121 dma_cap_set(DMA_PQ_VAL, dma->cap_mask);
1122
1123 if (ioat_dma->cap & IOAT_CAP_RAID16SS)
1124 dma_set_maxpq(dma, 16, 0);
1125 else
1126 dma_set_maxpq(dma, 8, 0);
1127
1128 if (!(ioat_dma->cap & IOAT_CAP_XOR)) {
1129 dma->device_prep_dma_xor = ioat_prep_pqxor;
1130 dma->device_prep_dma_xor_val = ioat_prep_pqxor_val;
1131 dma_cap_set(DMA_XOR, dma->cap_mask);
1132 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1133
1134 if (ioat_dma->cap & IOAT_CAP_RAID16SS)
1135 dma->max_xor = 16;
1136 else
1137 dma->max_xor = 8;
1138 }
1139 }
1140
1141 dma->device_tx_status = ioat_tx_status;
1142
1143 /* starting with CB3.3 super extended descriptors are supported */
1144 if (ioat_dma->cap & IOAT_CAP_RAID16SS) {
1145 char pool_name[14];
1146 int i;
1147
1148 for (i = 0; i < MAX_SED_POOLS; i++) {
1149 snprintf(pool_name, 14, "ioat_hw%d_sed", i);
1150
1151 /* allocate SED DMA pool */
1152 ioat_dma->sed_hw_pool[i] = dmam_pool_create(pool_name,
1153 &pdev->dev,
1154 SED_SIZE * (i + 1), 64, 0);
1155 if (!ioat_dma->sed_hw_pool[i])
1156 return -ENOMEM;
1157
1158 }
1159 }
1160
1161 if (!(ioat_dma->cap & (IOAT_CAP_XOR | IOAT_CAP_PQ)))
1162 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1163
1164 err = ioat_probe(ioat_dma);
1165 if (err)
1166 return err;
1167
1168 list_for_each_entry(c, &dma->channels, device_node) {
1169 ioat_chan = to_ioat_chan(c);
1170 writel(IOAT_DMA_DCA_ANY_CPU,
1171 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
1172 }
1173
1174 err = ioat_register(ioat_dma);
1175 if (err)
1176 return err;
1177
1178 ioat_kobject_add(ioat_dma, &ioat_ktype);
1179
1180 if (dca)
1181 ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base);
1182
1183 /* disable relaxed ordering */
1184 err = pcie_capability_read_word(pdev, IOAT_DEVCTRL_OFFSET, &val16);
1185 if (err)
1186 return err;
1187
1188 /* clear relaxed ordering enable */
1189 val16 &= ~IOAT_DEVCTRL_ROE;
1190 err = pcie_capability_write_word(pdev, IOAT_DEVCTRL_OFFSET, val16);
1191 if (err)
1192 return err;
1193
1194 return 0;
1195 }
1196
1197 static void ioat_shutdown(struct pci_dev *pdev)
1198 {
1199 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev);
1200 struct ioatdma_chan *ioat_chan;
1201 int i;
1202
1203 if (!ioat_dma)
1204 return;
1205
1206 for (i = 0; i < IOAT_MAX_CHANS; i++) {
1207 ioat_chan = ioat_dma->idx[i];
1208 if (!ioat_chan)
1209 continue;
1210
1211 spin_lock_bh(&ioat_chan->prep_lock);
1212 set_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
1213 del_timer_sync(&ioat_chan->timer);
1214 spin_unlock_bh(&ioat_chan->prep_lock);
1215 /* this should quiesce then reset */
1216 ioat_reset_hw(ioat_chan);
1217 }
1218
1219 ioat_disable_interrupts(ioat_dma);
1220 }
1221
1222 static void ioat_resume(struct ioatdma_device *ioat_dma)
1223 {
1224 struct ioatdma_chan *ioat_chan;
1225 u32 chanerr;
1226 int i;
1227
1228 for (i = 0; i < IOAT_MAX_CHANS; i++) {
1229 ioat_chan = ioat_dma->idx[i];
1230 if (!ioat_chan)
1231 continue;
1232
1233 spin_lock_bh(&ioat_chan->prep_lock);
1234 clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
1235 spin_unlock_bh(&ioat_chan->prep_lock);
1236
1237 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
1238 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
1239
1240 /* no need to reset as shutdown already did that */
1241 }
1242 }
1243
1244 #define DRV_NAME "ioatdma"
1245
1246 static pci_ers_result_t ioat_pcie_error_detected(struct pci_dev *pdev,
1247 enum pci_channel_state error)
1248 {
1249 dev_dbg(&pdev->dev, "%s: PCIe AER error %d\n", DRV_NAME, error);
1250
1251 /* quiesce and block I/O */
1252 ioat_shutdown(pdev);
1253
1254 return PCI_ERS_RESULT_NEED_RESET;
1255 }
1256
1257 static pci_ers_result_t ioat_pcie_error_slot_reset(struct pci_dev *pdev)
1258 {
1259 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
1260 int err;
1261
1262 dev_dbg(&pdev->dev, "%s post reset handling\n", DRV_NAME);
1263
1264 if (pci_enable_device_mem(pdev) < 0) {
1265 dev_err(&pdev->dev,
1266 "Failed to enable PCIe device after reset.\n");
1267 result = PCI_ERS_RESULT_DISCONNECT;
1268 } else {
1269 pci_set_master(pdev);
1270 pci_restore_state(pdev);
1271 pci_save_state(pdev);
1272 pci_wake_from_d3(pdev, false);
1273 }
1274
1275 err = pci_cleanup_aer_uncorrect_error_status(pdev);
1276 if (err) {
1277 dev_err(&pdev->dev,
1278 "AER uncorrect error status clear failed: %#x\n", err);
1279 }
1280
1281 return result;
1282 }
1283
1284 static void ioat_pcie_error_resume(struct pci_dev *pdev)
1285 {
1286 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev);
1287
1288 dev_dbg(&pdev->dev, "%s: AER handling resuming\n", DRV_NAME);
1289
1290 /* initialize and bring everything back */
1291 ioat_resume(ioat_dma);
1292 }
1293
1294 static const struct pci_error_handlers ioat_err_handler = {
1295 .error_detected = ioat_pcie_error_detected,
1296 .slot_reset = ioat_pcie_error_slot_reset,
1297 .resume = ioat_pcie_error_resume,
1298 };
1299
1300 static struct pci_driver ioat_pci_driver = {
1301 .name = DRV_NAME,
1302 .id_table = ioat_pci_tbl,
1303 .probe = ioat_pci_probe,
1304 .remove = ioat_remove,
1305 .shutdown = ioat_shutdown,
1306 .err_handler = &ioat_err_handler,
1307 };
1308
1309 static struct ioatdma_device *
1310 alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase)
1311 {
1312 struct device *dev = &pdev->dev;
1313 struct ioatdma_device *d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
1314
1315 if (!d)
1316 return NULL;
1317 d->pdev = pdev;
1318 d->reg_base = iobase;
1319 return d;
1320 }
1321
1322 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1323 {
1324 void __iomem * const *iomap;
1325 struct device *dev = &pdev->dev;
1326 struct ioatdma_device *device;
1327 int err;
1328
1329 err = pcim_enable_device(pdev);
1330 if (err)
1331 return err;
1332
1333 err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME);
1334 if (err)
1335 return err;
1336 iomap = pcim_iomap_table(pdev);
1337 if (!iomap)
1338 return -ENOMEM;
1339
1340 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1341 if (err)
1342 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1343 if (err)
1344 return err;
1345
1346 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1347 if (err)
1348 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1349 if (err)
1350 return err;
1351
1352 device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]);
1353 if (!device)
1354 return -ENOMEM;
1355 pci_set_master(pdev);
1356 pci_set_drvdata(pdev, device);
1357
1358 device->version = readb(device->reg_base + IOAT_VER_OFFSET);
1359 if (device->version >= IOAT_VER_3_0) {
1360 if (is_skx_ioat(pdev))
1361 device->version = IOAT_VER_3_2;
1362 err = ioat3_dma_probe(device, ioat_dca_enabled);
1363
1364 if (device->version >= IOAT_VER_3_3)
1365 pci_enable_pcie_error_reporting(pdev);
1366 } else
1367 return -ENODEV;
1368
1369 if (err) {
1370 dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n");
1371 pci_disable_pcie_error_reporting(pdev);
1372 return -ENODEV;
1373 }
1374
1375 return 0;
1376 }
1377
1378 static void ioat_remove(struct pci_dev *pdev)
1379 {
1380 struct ioatdma_device *device = pci_get_drvdata(pdev);
1381
1382 if (!device)
1383 return;
1384
1385 dev_err(&pdev->dev, "Removing dma and dca services\n");
1386 if (device->dca) {
1387 unregister_dca_provider(device->dca, &pdev->dev);
1388 free_dca_provider(device->dca);
1389 device->dca = NULL;
1390 }
1391
1392 pci_disable_pcie_error_reporting(pdev);
1393 ioat_dma_remove(device);
1394 }
1395
1396 static int __init ioat_init_module(void)
1397 {
1398 int err = -ENOMEM;
1399
1400 pr_info("%s: Intel(R) QuickData Technology Driver %s\n",
1401 DRV_NAME, IOAT_DMA_VERSION);
1402
1403 ioat_cache = kmem_cache_create("ioat", sizeof(struct ioat_ring_ent),
1404 0, SLAB_HWCACHE_ALIGN, NULL);
1405 if (!ioat_cache)
1406 return -ENOMEM;
1407
1408 ioat_sed_cache = KMEM_CACHE(ioat_sed_ent, 0);
1409 if (!ioat_sed_cache)
1410 goto err_ioat_cache;
1411
1412 err = pci_register_driver(&ioat_pci_driver);
1413 if (err)
1414 goto err_ioat3_cache;
1415
1416 return 0;
1417
1418 err_ioat3_cache:
1419 kmem_cache_destroy(ioat_sed_cache);
1420
1421 err_ioat_cache:
1422 kmem_cache_destroy(ioat_cache);
1423
1424 return err;
1425 }
1426 module_init(ioat_init_module);
1427
1428 static void __exit ioat_exit_module(void)
1429 {
1430 pci_unregister_driver(&ioat_pci_driver);
1431 kmem_cache_destroy(ioat_cache);
1432 }
1433 module_exit(ioat_exit_module);
Linux with added FPC-III support